Simulation test file generation method and device, equipment and storage medium

Abstract

The present disclosure relates to the technical field of chip testing, and particularly relates to a simulation test file generation method, device and equipment and a storage medium; a hidden port is identified by comparing port instantiation and connection information of a primitive instance with standard port information; a hierarchical netlist path of the hidden port in a gate-level netlist simulation model is determined according to a primitive type and physical position information of the primitive instance to which the hidden port belongs; and then a corresponding driving statement and observation statement are respectively generated for a hidden input port and a hidden output port. Therefore, in the case that a top-level port of a target test case is incomplete and a netlist path of a primitive instance changes with a layout result, the hidden port inside a gate-level netlist simulation model can be automatically located, and driving content or observation content matched with an actual hierarchical netlist path of the hidden port can be generated, so that the generation efficiency of a simulation test file, path matching accuracy and port test coverage completeness are improved.

Description

Technical Field

[0001] This disclosure relates to the field of chip testing technology, specifically to a method, apparatus, device, and storage medium for generating simulation test files. Background Technology

[0002] Bit-stream testing can be used to verify the configuration results of programmable logic devices and the functionality of corresponding hardware resources. When performing bit-stream testing on input / output (IO) modules, it is usually necessary to write simulation test files based on the design under test (DUT), apply test stimuli to the DUT and obtain the output response to determine whether the corresponding hardware functions meet expectations.

[0003] Different test cases may have different design structures, port configurations, and hardware layouts. Some signals under test may not be directly presented in the top-level interface of the test case, and the positions of related low-level signals may also change with the design, compilation, and layout results. Related test files usually rely on manual analysis and writing, which can easily lead to the omission of signals under test or incorrect signal position matching, affecting the efficiency of test file generation and test coverage. Summary of the Invention

[0004] Based on this, this disclosure provides a method, apparatus, device, and storage medium for generating simulation test files to address the problem of improving the efficiency of test file generation and verification coverage for I / O module bitstream testing.

[0005] Firstly, this disclosure provides a method for generating simulation test files, the method comprising: Obtain the design file and preset primitive description data of the target test case, parse the design file to obtain the primitive instances in the target test case, the primitive type of each primitive instance, and port instantiation and connection information, and obtain the standard port information corresponding to the primitive type of each primitive instance from the primitive description data. The port instantiation and connection information of each primitive instance are compared with the corresponding standard port information to determine the hidden ports that do not form a driver interface or observation interface at the top level of the target test case. Obtain and parse the layout result data corresponding to the target test case, obtain the physical location information of the primitive instance to which the hidden port belongs, and query the preset hardware netlist mapping relationship according to the primitive type and physical location information of the primitive instance to which the hidden port belongs, and determine the hierarchical netlist path of the hidden port in the gate-level netlist simulation model corresponding to the target test case. A simulation test file is generated based on the port direction of the hidden port and the hierarchical netlist path. For the hidden input port, a driving statement is generated to apply test stimuli to the hidden input port through the corresponding hierarchical netlist path. For the hidden output port, an observation statement is generated to obtain the output signal of the hidden output port through the corresponding hierarchical netlist path.

[0006] Secondly, this disclosure also provides a simulation test file generation apparatus, the apparatus comprising: The data parsing module is used to obtain the design file of the target test case and the preset primitive description data, parse the design file to obtain the primitive instances in the target test case, the primitive type of each primitive instance, and the port instantiation and connection information, and obtain the standard port information corresponding to the primitive type of each primitive instance from the primitive description data. The hidden port determination module is used to compare the port instantiation and connection information of each primitive instance with the corresponding standard port information to determine the hidden ports that do not form a driver interface or observation interface at the top level of the target test case. The netlist path determination module is used to acquire and parse the layout result data corresponding to the target test case, obtain the physical location information of the primitive instance to which the hidden port belongs, and query the preset hardware netlist mapping relationship according to the primitive type and physical location information of the primitive instance to which the hidden port belongs, and determine the hierarchical netlist path of the hidden port in the gate-level netlist simulation model corresponding to the target test case. The test file generation module is used to generate simulation test files based on the port direction of the hidden port and the hierarchical netlist path. Specifically, for the hidden input port, it generates driving statements to apply test stimuli to the hidden input port through the corresponding hierarchical netlist path; for the hidden output port, it generates observation statements to obtain the output signal of the hidden output port through the corresponding hierarchical netlist path.

[0007] Thirdly, this disclosure also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the above-described simulation test file generation methods.

[0008] Fourthly, this disclosure also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described simulation test file generation methods.

[0009] Fifthly, this disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described simulation test file generation methods.

[0010] In the simulation test file generation method of the above embodiments of this disclosure, by comparing the port instantiation and connection information of primitive instances with standard port information, hidden ports that do not form a driving interface or observation interface at the top level of the target test case can be identified. Based on the primitive type and physical location information of the primitive instance to which the hidden port belongs, the hierarchical netlist path of the hidden port in the gate-level netlist simulation model can be determined. Then, corresponding driving statements and observation statements are generated for the hidden input port and hidden output port, respectively. Therefore, when the top-level port of the target test case is incomplete and the netlist path of the primitive instance changes with the layout result, the hidden ports inside the gate-level netlist simulation model can be automatically located, and driving content or observation content matching the actual hierarchical netlist path of the hidden port can be generated, improving the generation efficiency, path matching accuracy, and port test coverage completeness of the simulation test file. Attached Figure Description

[0011] To more clearly illustrate the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A flowchart illustrating a method for generating simulation test files according to an embodiment of this disclosure; Figure 2 A flowchart illustrating a hidden port determination process provided in this embodiment of the disclosure; Figure 3 A schematic diagram illustrating the process of determining a hierarchical netlist path for a hidden port and generating a simulation test file, as provided in this embodiment of the disclosure. Figure 4 This is a schematic diagram of the structure of a simulation test file generation device provided in an embodiment of the present disclosure; Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0013] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this disclosure.

[0014] It should be noted that, in the description of this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this disclosure are used to distinguish similar objects and are not used to describe a particular order or sequence.

[0015] To enable those skilled in the art to better understand the present disclosure, the present disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] In one embodiment, please refer to Figure 1 , Figure 1 This is a flowchart illustrating a simulation test file generation method provided in an embodiment of the present disclosure. The method may include the following steps: Step S101: Obtain the design file and preset primitive description data of the target test case, parse the design file, obtain the primitive instances in the target test case, the primitive type of each primitive instance, and the port instantiation and connection information, and obtain the standard port information corresponding to the primitive type of each primitive instance from the primitive description data.

[0017] Specifically, the design document for the target test case is used to describe the logical design of the bitstream to be tested, which may include port declarations of the top-level module, instantiation statements of one or more primitive instances, and port connection relationships of each primitive instance.

[0018] Target test cases can be test cases constructed for the input / output modules and their underlying primitive combinations within a single logic region of a programmable logic device.

[0019] When parsing a design file, the top-level module in the design file can be identified, each primitive instance instantiated in the top-level module can be traversed, and the instance identifier, primitive type, instantiation port, and connection object of each instantiation port can be extracted from the instantiation statement of each primitive instance to form the port instantiation and connection information of the corresponding primitive instance.

[0020] Port instantiation and connection information can be used to characterize whether the corresponding port is listed in the primitive instantiation statement, whether the listed port is connected to a signal, whether the connected signal is a constant signal, whether the connected signal is brought out to the top level of the target test case, and the connection relationship between the port and other primitive instances.

[0021] Primitive description data can record the standard port information of the corresponding primitive according to the primitive type. The standard port information can include the set of standard ports corresponding to the primitive type, as well as the port name and port direction of each standard port.

[0022] In subsequent embodiments, the primitive description data may further include the port mapping name, clock port identifier, and differential attributes of the corresponding primitives for each primitive port.

[0023] In one possible implementation, primitive description data is stored in a pre-established primitive database. The primitive database can be incrementally expanded as needed.

[0024] When it is necessary to adapt to new primitive types, the standard port information and corresponding primitive attributes corresponding to the primitive type can be added to the primitive database. This allows the new primitive type to be integrated into the existing design file parsing, hidden port identification, netlist path determination, and simulation test file generation processes, thereby improving the scalability of the primitive database and the adaptation efficiency of different primitive types.

[0025] Step S102: Compare the port instantiation and connection information of each primitive instance with the corresponding standard port information to determine the hidden ports that have not formed a driver interface or observation interface at the top level of the target test case.

[0026] Specifically, for each primitive instance, based on the standard port information corresponding to that primitive instance, we check whether each standard port appears in the primitive instantiation statement, whether it is connected to the corresponding signal, and whether the connected signal is brought out through the top-level port of the target test case.

[0027] Hidden ports can include hidden input ports and hidden output ports. A hidden input port is a primitive input port that cannot directly receive test stimuli through the top-level input interface of the target test case; a hidden output port is a primitive output port that cannot directly obtain output signals through the top-level output interface of the target test case.

[0028] For input ports that have already formed a driving interface at the top level of the target test case, test stimuli can be applied through the top-level input interface; for output ports that have already formed an observation interface at the top level of the target test case, output signals can be obtained through the top-level output interface.

[0029] For primitive ports that do not have a corresponding interface at the top level of the target test case but still exist in the gate-level netlist simulation model, it is necessary to drive or observe them through the internal netlist node in the gate-level netlist simulation model using the primitive port.

[0030] Step S103: Obtain and parse the layout result data corresponding to the target test case, obtain the physical location information of the primitive instance to which the hidden port belongs, and query the preset hardware netlist mapping relationship according to the primitive type and physical location information of the primitive instance to which the hidden port belongs, and determine the hierarchical netlist path of the hidden port in the gate-level netlist simulation model corresponding to the target test case.

[0031] Specifically, the layout result data can be a layout result file generated by electronic design automation tools after the target test cases have been laid out. The layout result file records the layout information after the primitive instances in the target test cases are placed into the corresponding hardware resource locations of the programmable logic device.

[0032] Based on the instance identifier of the primitive instance to which the hidden port belongs, the layout record corresponding to the primitive instance is searched in the layout result data, and the physical location information of the primitive instance is obtained from the corresponding layout record. The physical location information may include the site location of the primitive instance and the cell position occupied by the primitive instance within that site.

[0033] Hardware netlist mappings are used to record the correspondence between primitive types, physical locations, and gate-level netlist paths.

[0034] Since different primitive types, as well as the same primitive type in different physical locations, may correspond to different netlist levels in the gate-level netlist simulation model, the netlist path information corresponding to the primitive instance can be determined by querying the hardware netlist mapping relationship based on the primitive type and physical location information of the primitive instance to which the hidden port belongs.

[0035] The gate-level netlist simulation model is a gate-level hardware netlist simulation model of the circuit corresponding to the target test case, rather than a physical programmable logic device. The hierarchical netlist path of the hidden ports is used to locate the actual internal netlist node in the gate-level netlist simulation model corresponding to the hidden ports after the target test case has been laid out.

[0036] Step S104: Generate a simulation test file based on the port direction of the hidden port and the hierarchical netlist path. Specifically, for the hidden input port, generate a driving statement to apply test stimuli to the hidden input port through the corresponding hierarchical netlist path; for the hidden output port, generate an observation statement to obtain the output signal of the hidden output port through the corresponding hierarchical netlist path.

[0037] Specifically, the port direction of the hidden port is determined based on the standard port information corresponding to the hidden port. For hidden ports with the port direction being the input direction, a driving statement pointing to the hierarchical netlist path of the hidden input port is generated in the simulation test file, so that the test stimulus can bypass the incomplete top-level port and be directly applied to the corresponding netlist node inside the gate-level netlist simulation model.

[0038] For a hidden port whose port direction is output, an observation statement is generated in the simulation test file to point to the hierarchical netlist path of the hidden output port. The output signal of the hidden output port is brought out to the observation signal in the simulation test file through the observation statement.

[0039] Simulation test files may also include signal declarations, target test case instantiation, top-level port connections, test stimuli for regular input ports, observations for regular output ports, reference models, the correspondence between the reference models and the gate-level netlist simulation models, output comparison statements, and test result output statements.

[0040] The instantiation content of the target test cases is generated based on the top-level module and its port information in the design file.

[0041] For the input ports that are normally brought out at the top level of the target test case, test stimuli are applied to the gate-level netlist simulation model through the top-level port connection; for the output ports that are normally brought out at the top level of the target test case, the output signals are obtained through the top-level port connection.

[0042] For hidden input ports and hidden output ports, driving and observation are accomplished through hierarchical netlist paths, respectively.

[0043] The simulation test file generated in this embodiment can also be called the input vector file from the perspective of excitation data. The input vector file and the simulation test file represent the same file.

[0044] In the simulation test file generation method of the above embodiments of this disclosure, by comparing the port instantiation and connection information of primitive instances with standard port information, hidden ports that do not form a driving interface or observation interface at the top level of the target test case can be identified. Based on the primitive type and physical location information of the primitive instance to which the hidden port belongs, the hierarchical netlist path of the hidden port in the gate-level netlist simulation model can be determined. Then, corresponding driving statements and observation statements are generated for the hidden input port and hidden output port, respectively. Therefore, when the top-level port of the target test case is incomplete and the netlist path of the primitive instance changes with the layout result, the hidden ports inside the gate-level netlist simulation model can be automatically located, and driving content or observation content matching the actual hierarchical netlist path of the hidden port can be generated, improving the generation efficiency, path matching accuracy, and port test coverage completeness of the simulation test file.

[0045] In one possible implementation of step S102 above, such as Figure 2 As shown, Figure 2This is a flowchart illustrating a hidden port determination process provided in an embodiment of the present disclosure. The process compares the port instantiation and connection information of each primitive instance with the corresponding standard port information to determine hidden ports that do not form a driver interface or observation interface at the top level of the target test case. The process includes the following steps: Step S1021: Obtain the standard port set of the primitive instance based on the standard port information corresponding to each primitive instance.

[0046] Specifically, for each primitive instance in the target test case, the primitive description data is queried according to the primitive type of the primitive instance, and all standard ports corresponding to the primitive type are read to form the standard port set of the primitive instance.

[0047] The standard port set is used to fully represent all the ports that the corresponding primitive type has according to the primitive definition, and serves as the port benchmark for verifying the actual instantiated ports in the target test case.

[0048] Here, each standard port in the standard port set can have a corresponding port name and port direction.

[0049] Step S1022: For each primitive instance, based on the port instantiation and connection information of the primitive instance, identify from the standard port set of the primitive instance the ports not listed in the primitive instantiation statement, the ports listed in the primitive instantiation statement but not connected, and the ports connected inside the target test case but not brought out to the top level of the target test case, to obtain candidate hidden ports.

[0050] Specifically, the ports actually listed in the primitive instantiation statement are compared item by item with the standard port set of the corresponding primitive instance.

[0051] If a standard port in the standard port set does not appear in the port list of the primitive instantiation statement, then that standard port is identified as a candidate hidden port that is not listed in the primitive instantiation statement.

[0052] If a standard port has appeared in the primitive instantiation statement, but the standard port is not connected to the corresponding signal, then the standard port is identified as a candidate hidden port that has been listed but not connected.

[0053] If a standard port is already connected to a signal inside the target test case, but the signal is not further connected to the top-level port of the target test case, then the standard port cannot be directly driven or observed through the top-level interface of the target test case. The standard port is identified as a candidate hidden port connected inside the target test case but not brought out to the top level.

[0054] The primitive input port connected to the constant signal is a port that is connected inside the target test case but does not form a top-level driver interface.

[0055] For this type of port, its connection status to constant signals can be recorded in the port instantiation and connection information to determine the corresponding driving statement later.

[0056] Step S1023: Obtain the netlist node information of the gate-level netlist simulation model, and remove ports from the candidate hidden ports that do not have corresponding netlist nodes in the netlist node information to obtain the hidden ports.

[0057] Specifically, when compiling target test cases, electronic design automation tools may optimize ports or corresponding logic that do not participate in actual logical functions, so that the port no longer has a netlist node that can be driven or observed in the gate-level netlist simulation model.

[0058] The primitive instance information and port information corresponding to each candidate hidden port are mapped to the netlist node information in the gate-level netlist simulation model.

[0059] If a netlist node corresponding to a candidate hidden port exists in the gate-level netlist simulation model, the candidate hidden port is retained; if no corresponding netlist node exists, it indicates that the candidate hidden port has been optimized during the compilation process, and the candidate hidden port is removed from the candidate hidden ports.

[0060] In one possible implementation, valid hidden ports can be determined from the hidden ports obtained in step S1023. Specifically, based on the connection relationships of the hidden ports in the target test cases, it is determined whether the hidden port needs to be individually connected to a test stimulus or output an observation. For hidden ports that only serve as internal interconnections between primitive instances, their original internal connections are retained; for hidden ports that need to be individually connected to a test stimulus or used as functional observation signals, they are determined as valid hidden ports. In this implementation, hierarchical netlist paths are subsequently determined for the valid hidden ports, and driving statements or observation statements are generated.

[0061] If the hidden port is not obtained in step S1023, the instantiation, stimulus, observation and output comparison content corresponding to the regular top-level port will be directly generated when generating the simulation test file.

[0062] In the simulation test file generation method of the above embodiments of this disclosure, by using the standard port set of primitives as a benchmark, candidate hidden ports that are not listed, not connected, or not brought out to the top level in the design file can be identified; by corresponding the candidate hidden ports with the netlist node information in the gate-level netlist simulation model, the hidden ports actually retained in the gate-level netlist simulation model can be determined; by further determining the effective hidden ports, the subsequently generated driving statements and observation statements correspond to the test requirements of the corresponding ports.

[0063] In one embodiment, please refer to Figure 3 , Figure 3 This diagram illustrates a process for determining a hierarchical netlist path for a hidden port and generating a simulation test file, as provided in an embodiment of this disclosure.

[0064] like Figure 3 As shown, the design file of the target test case is parsed to obtain the primitive types, port instantiation and connection information in the target test case, and the standard port information corresponding to the corresponding primitive type is obtained from the primitive description data; the port instantiation and connection information is compared with the standard port information to determine the hidden ports that have not formed a driver interface or observation interface at the top level of the target test case, and the port direction of the hidden port is obtained according to the standard port information corresponding to the hidden port.

[0065] Parse the layout result data corresponding to the target test case to obtain the physical location information of the primitive instance to which the hidden port belongs; obtain the port mapping name corresponding to the hidden port from the primitive description data, and query the hardware netlist mapping relationship according to the primitive type and physical location information of the primitive instance to which the hidden port belongs to obtain the corresponding netlist path prefix; combine the netlist path prefix with the port mapping name to obtain the hierarchical netlist path of the hidden port in the gate-level netlist simulation model.

[0066] When the primitive instance to which the hidden port belongs is a differential primitive, the netlist mapping positions corresponding to the first differential port and the second differential port are determined according to the differential attribute and physical location information. For the two netlist mapping positions, the hardware netlist mapping relationship is queried to obtain the corresponding netlist path prefix. Each netlist path prefix is ​​combined with the port mapping name of the corresponding differential port to obtain the hierarchical netlist path corresponding to the first differential port and the second differential port respectively.

[0067] After obtaining the hierarchical netlist path of the hidden port, corresponding statements are generated according to the port direction of the hidden port; for the hidden input port, a driving statement is generated to apply test stimuli to the hidden input port through the corresponding hierarchical netlist path; for the hidden output port, an observation statement is generated to obtain the output signal of the hidden output port through the corresponding hierarchical netlist path.

[0068] The generated driver and observation statements are written into the simulation test file to obtain the simulation test file corresponding to the target test case.

[0069] In one possible implementation of step S103 above, the hidden port is determined by querying a preset hardware netlist mapping relationship based on the primitive type and physical location information of the primitive instance to which the hidden port belongs, and determining the hierarchical netlist path of the hidden port in the gate-level netlist simulation model corresponding to the target test case. This includes the following steps: Step S1031: Obtain the port mapping name corresponding to the hidden port from the primitive description data.

[0070] Specifically, the primitive description data can record the logical port name of each standard port and the port mapping name corresponding to that logical port name for each primitive type.

[0071] The logical port name is used to identify the corresponding port in the design file and primitive definition, and the port mapping name is used to identify the netlist node corresponding to the corresponding port in the gate-level netlist simulation model.

[0072] Based on the primitive type of the primitive instance to which the hidden port belongs and the port name of the hidden port, find the corresponding standard port from the primitive description data and read the port mapping name corresponding to the standard port.

[0073] Step S1032: Query the hardware netlist mapping relationship based on the primitive type and physical location information of the primitive instance to which the hidden port belongs, and obtain the netlist path prefix.

[0074] Specifically, the hardware netlist mapping relationship can be stored in a preset hardware netlist mapping file or hardware netlist mapping database to record the netlist path prefixes corresponding to each primitive type in different physical locations.

[0075] Based on the primitive type of the primitive instance to which the hidden port belongs, determine the netlist mapping entry corresponding to the primitive type from the hardware netlist mapping relationship. Then, based on the physical location information of the primitive instance, determine the netlist mapping entry matching the physical location from the corresponding netlist mapping entries, and read the corresponding netlist path prefix.

[0076] Step S1033: Combine the netlist path prefix with the port mapping name to obtain the hierarchical netlist path.

[0077] Specifically, the netlist path prefix is ​​used to locate the hierarchical position of the primitive instance to which the hidden port belongs in the gate-level netlist simulation model, and the port mapping name is used to locate the specific port node in the primitive instance.

[0078] Based on the hierarchical path organization method of the gate-level netlist simulation model, the netlist path prefix is ​​combined with the port mapping name to obtain the hierarchical netlist path pointing to the netlist node corresponding to the hidden port.

[0079] For different hidden ports of the same primitive instance, the netlist path prefix corresponding to the primitive instance can be reused, and the netlist path prefix can be combined with the port mapping name corresponding to different hidden ports to obtain the hierarchical netlist path corresponding to each hidden port.

[0080] In the simulation test file generation method of the above embodiments of this disclosure, the netlist path prefix corresponding to the primitive instance and the port mapping name corresponding to the port are determined and combined respectively, so that the netlist path prefix can be determined according to the primitive type and layout position, and the specific port node can be determined according to the port mapping name, thereby forming a hierarchical netlist path corresponding to different primitive instances and different hidden ports.

[0081] In one possible implementation of step S1032 above, the hardware netlist mapping relationship is queried based on the primitive type and physical location information of the primitive instance to which the hidden port belongs, to obtain the netlist path prefix, including the following steps: Step A1: Read the site location and unit location from the physical location information.

[0082] Specifically, the layout record corresponding to the primitive instance to which the hidden port belongs in the parsed layout result data is read, and the station position and cell position in the layout record are read.

[0083] Here, the site location can correspond to the SITE location in the programmable logic device layout architecture, used to indicate the hardware site where the primitive instance is located; the cell location can correspond to the ELEM location, used to indicate the specific logic cell occupied by the primitive instance in the corresponding hardware site.

[0084] Step A2: Obtain the netlist mapping entry corresponding to the primitive type of the primitive instance to which the hidden port belongs from the hardware netlist mapping relationship. Each netlist mapping entry records the site range, cell range and the corresponding netlist path prefix.

[0085] Specifically, using the primitive type of the primitive instance to which the hidden port belongs as the query condition, one or more netlist mapping entries pre-established for that primitive type are obtained from the hardware netlist mapping relationship.

[0086] Different netlist mapping entries correspond to different site ranges and cell ranges that can be deployed for the corresponding primitive types, and the netlist path prefixes corresponding to the site ranges and cell ranges in the gate-level netlist simulation model are recorded.

[0087] Step A3: Match the site location and cell location with the site range and cell range recorded in each netlist mapping entry, respectively. Determine the successfully matched netlist mapping entries as target netlist mapping entries, and read the netlist path prefix from the target netlist mapping entries.

[0088] Specifically, for each netlist mapping entry of the corresponding primitive type, it is determined whether the site location of the primitive instance to which the hidden port belongs is within the site range recorded in the netlist mapping entry, and whether the cell location of the primitive instance is within the cell range recorded in the netlist mapping entry.

[0089] The netlist mapping entry that successfully matches both the site location and the cell location is identified as the target netlist mapping entry, and the netlist path prefix recorded in the target netlist mapping entry is read.

[0090] In the simulation test file generation method of the above embodiments of this disclosure, by matching the site position and cell position in the layout result data with the netlist mapping entries established according to the primitive type, the corresponding netlist level can be automatically located according to the primitive type and actual layout position of the primitive instance, and the netlist path prefix can be directly obtained from the matched netlist mapping entries, thereby improving the mapping efficiency and mapping accuracy between the primitive instance and the gate-level netlist level.

[0091] Based on steps A1 to A3 above, when the primitive instance to which the hidden port belongs is a differential primitive, steps S1032 and S1033 can determine the hierarchical netlist path corresponding to the differential primitive in the following manner: Step B1: Obtain the differential attributes of the primitive instance to which the hidden port belongs from the primitive description data.

[0092] Specifically, the primitive description data is queried according to the primitive type of the primitive instance to which the hidden port belongs, and the differential attribute corresponding to the primitive type is read. The differential attribute is used to indicate whether the corresponding primitive is a differential primitive. For differential primitives, the hardware netlist mapping relationship records the netlist mapping positions of the first differential port and the second differential port under the corresponding physical locations.

[0093] Step B2: When the differential attribute indicates that the primitive instance to which the hidden port belongs is a differential primitive, determine the first netlist mapping position occupied by the first differential port and the second netlist mapping position occupied by the second differential port according to the differential attribute and physical location information. The first netlist mapping position includes the first site position and the first cell position, and the second netlist mapping position includes the second site position and the second cell position.

[0094] Specifically, when the primitive instance to which the hidden port belongs, as indicated by the differential attribute, is a differential primitive, it is determined that netlist path mapping needs to be performed on the first differential port and the second differential port respectively. Based on the primitive type and physical location information of the differential primitive, the first netlist mapping position corresponding to the first differential port and the second netlist mapping position corresponding to the second differential port are obtained from the hardware netlist mapping relationship respectively.

[0095] The first differential port and the second differential port can correspond to the T-terminal and C-terminal of the differential primitive, respectively.

[0096] Step B3: Match the first site location and the first unit location with the site range and unit range recorded in each netlist mapping entry to determine the first target netlist mapping entry; and match the second site location and the second unit location with the site range and unit range recorded in each netlist mapping entry to determine the second target netlist mapping entry.

[0097] Specifically, the same position matching method as in step A3 is used to match the netlist mapping positions corresponding to the two differential ports respectively.

[0098] The netlist mapping entries that successfully match both the first site location and the first unit location are determined as the first target netlist mapping entries; the netlist mapping entries that successfully match both the second site location and the second unit location are determined as the second target netlist mapping entries.

[0099] Step B4: Read the first netlist path prefix and the second netlist path prefix from the first target netlist mapping entry and the second target netlist mapping entry respectively, and obtain the port mapping names corresponding to the first differential port and the second differential port from the primitive description data.

[0100] Specifically, the first netlist path prefix is ​​used to locate the hierarchical position of the hardware resources occupied by the first differential port in the gate-level netlist simulation model, and the second netlist path prefix is ​​used to locate the hierarchical position of the hardware resources occupied by the second differential port in the gate-level netlist simulation model.

[0101] Based on the port names of the first differential port and the second differential port, the corresponding port mapping names are read from the primitive description data.

[0102] Step B5: Combine the first netlist path prefix with the port mapping name corresponding to the first differential port to obtain the hierarchical netlist path of the first differential port, and combine the second netlist path prefix with the port mapping name corresponding to the second differential port to obtain the hierarchical netlist path of the second differential port.

[0103] Specifically, two hierarchical netlist paths are formed by using the netlist path prefix and port mapping name corresponding to each of the two differential ports, so that the first differential port and the second differential port can be located in the gate-level netlist simulation model respectively.

[0104] In the simulation test file generation method of the above embodiments of this disclosure, for the differential primitives that occupy two sets of netlist mapping positions, the netlist mapping position, netlist path prefix and port mapping name corresponding to each of the two differential ports are determined respectively, which can form a hierarchical netlist path pointing to the actual netlist nodes of the first differential port and the second differential port respectively, thereby improving the completeness of path derivation and the accuracy of position mapping of the two differential ports of the differential primitive.

[0105] In one possible implementation of step S104 above, generating a simulation test file based on the port direction of the hidden port and the hierarchical netlist path includes the following steps: Step S1041: Determine whether the hidden input port is connected to a constant signal based on the port instantiation and connection information.

[0106] Specifically, read the port instantiation and connection information corresponding to the hidden input port, and determine whether the hidden input port is connected to a constant signal in the design file of the target test case.

[0107] If the hidden input port is connected to a constant signal, then the hidden input port is determined to have the original constant value; if the hidden input port is not connected to a constant signal, then the hidden input port is regarded as a hidden input port that has not been fixed as a constant.

[0108] Step S1042: When the hidden input port is not connected to a constant signal, generate a forced assignment statement or a continuous assignment statement that applies test stimuli to the hidden input port through the corresponding hierarchical netlist path.

[0109] Specifically, based on the hierarchical netlist path corresponding to the hidden input port, a forced assignment statement or a continuous assignment statement is generated in the simulation test file, and the test stimulus to be generated is associated with the corresponding hierarchical netlist path.

[0110] When executing the simulation test file, forced assignment statements or continuous assignment statements act on the hidden input ports inside the gate-level netlist simulation model through the hierarchical netlist path, so that the hidden input ports that do not form a driving interface at the top level of the target test case receive test stimuli.

[0111] Step S1043: When the hidden input port is connected to a constant signal, generate a forced assignment statement that overwrites the original constant value of the hidden input port through the corresponding hierarchical netlist path.

[0112] Specifically, the constant connections in the target test cases are preserved in the gate-level netlist simulation model. To test hidden input ports connected to constant signals, a forced assignment statement is generated to point to the hierarchical netlist path of that hidden input port.

[0113] When executing the corresponding test, a forced assignment statement overrides the original constant value of the hidden input port, causing the hidden input port to receive the corresponding test stimulus. If the forced assignment is not executed, the hidden input port retains its original constant configuration in the target test case.

[0114] Step S1044: For the hidden output port, generate an observation statement that leads the output signal of the hidden output port to the observation signal through the corresponding hierarchical netlist path.

[0115] Specifically, the observation signal corresponding to the hidden output port is declared in the simulation test file, and the observation statement that connects the hierarchical netlist path of the hidden output port to the observation signal is generated.

[0116] When running the simulation test file, the output signal of the hidden output port inside the gate-level netlist simulation model is obtained by observing the signal, and the output signal is provided to the subsequent output comparison statement.

[0117] In the simulation test file generation method of the above embodiments of this disclosure, corresponding assignment statements are generated according to whether the hidden input port is connected to a constant signal, and corresponding observation statements are generated for the hidden output port. This can cover different hidden port states such as uninstantiated, unconnected, internally connected but not brought out to the top layer, and connected to a constant signal.

[0118] In one possible implementation of the above embodiments, the primitive description data further includes a clock port identifier corresponding to each primitive port.

[0119] Specifically, the clock port identifier is used to indicate whether the corresponding primitive port is a clock port used to receive clock signals. Input ports not indicated as clock ports by the clock port identifier can be processed as data ports.

[0120] In one possible implementation of step S104 above, generating the driving statement to apply test stimuli to the hidden input port through the corresponding hierarchical netlist path includes the following steps: Step C1: Determine whether the hidden input port is a clock port or a data port based on the clock port identifier.

[0121] Specifically, based on the primitive type of the primitive instance to which the hidden input port belongs and the port name of the hidden input port, the corresponding clock port identifier is read from the primitive description data.

[0122] If the clock port identifier indicates that the hidden input port is a clock port, then the driving statement is generated according to the excitation method corresponding to the clock port; if the clock port identifier does not indicate that the hidden input port is a clock port, then the driving statement is generated according to the excitation method corresponding to the data port.

[0123] Step C2: With the input port hidden as a clock port, generate a drive statement containing a periodic clock excitation that flips the level according to a preset period.

[0124] Specifically, a clock stimulus is generated in the simulation test file to change the clock signal level according to a preset period, and the clock stimulus is applied to the corresponding clock port through the hierarchical netlist path corresponding to the hidden input port.

[0125] Step C3: With the input port hidden as a data port, generate a driving statement containing data stimuli that dynamically change according to randomly generated data values.

[0126] Specifically, data stimulus content is generated in the simulation test file to generate random data values ​​and make the data stimulus change dynamically with the random data values, and the data stimulus is applied to the corresponding data port through the hierarchical netlist path corresponding to the hidden input port.

[0127] In the simulation test file generation method of the above embodiments of this disclosure, clock ports and data ports are distinguished according to the clock port identifier in the primitive description data, and periodic clock stimuli and dynamic data stimuli are generated respectively, so that hidden input ports of different function types can obtain test stimuli adapted to their port attributes.

[0128] In another possible implementation of step S104 above, generating the simulation test file based on the port direction of the hidden port and the hierarchical netlist path also includes the following steps: Step D1: Determine the interconnection relationship between multiple primitive instances based on port instantiation and connection information, and generate a reference model based on the multiple primitive instances and interconnection relationship.

[0129] Specifically, the design file of the target test case and the mapping result file corresponding to the target test case are parsed to obtain the primitive instances in the target test case and the connection relationships between the primitive instances.

[0130] Based on the primitive type of each primitive instance, the standard port information of the corresponding primitive is obtained from the primitive description data, and the primitive instances are connected according to the interconnection relationship in the target test case to form a reference model corresponding to the target test case.

[0131] The reference model represents the logical functionality that the target test cases should implement according to the design documents. Each primitive instance in the reference model retains the standard port corresponding to the corresponding primitive type, so that both regular ports and hidden ports can have corresponding ports in the reference model.

[0132] Step D2: Establish the port correspondence between the hidden port and the corresponding standard port in the reference model.

[0133] Specifically, based on the primitive instance to which the hidden port belongs, the port name of the hidden port, and the primitive instance and standard port in the reference model, the standard port corresponding to the hidden port in the reference model is determined.

[0134] For a gate-level netlist simulation model, hidden ports are driven or observed through their hierarchical netlist paths; for a reference model, identical ports are connected through primitive instances and standard ports in the reference model. This allows hidden ports in the gate-level netlist simulation model and their corresponding standard ports in the reference model to receive the same test stimuli or form corresponding output signals.

[0135] For the regular ports that are normally brought out at the top level of the target test case, the port correspondence between the gate-level netlist simulation model and the reference model can be established according to the primitive instance and port name.

[0136] Step D3: Determine the working clock from the input port of the target test case based on the clock port identifier.

[0137] Specifically, based on the primitive ports corresponding to each input port in the target test case and the clock port identifier in the primitive description data, the clock input port used to drive the target test case and the reference model is determined, and the clock signal corresponding to the clock input port is determined as the working clock.

[0138] Step D4: Generate stimulus input statements for applying the same test stimuli to the gate-level netlist simulation model and the reference model.

[0139] Specifically, for the corresponding gate-level netlist simulation model input ports and reference model input ports, stimulus input statements that share the same test stimulus are generated in the simulation test file.

[0140] For the normally exposed input ports at the top level, the same test stimulus is applied to the gate-level netlist simulation model and the reference model respectively through the top-level port connection; for the hidden input ports, the same test stimulus is applied to the hidden input ports in the gate-level netlist simulation model through the hierarchical netlist path, and applied to the reference model through the corresponding standard port.

[0141] Step D5 generates an output comparison statement for comparing the corresponding output signals of the gate-level netlist simulation model and the reference model after the effective edge of the working clock has passed through a preset time tolerance window.

[0142] Specifically, the corresponding output signals between the gate-level netlist simulation model and the reference model are determined.

[0143] The output signals of the gate-level netlist simulation model can include regular output signals obtained through the top-level output port and hidden output signals obtained through the hierarchical netlist path; the output signals of the reference model are the output signals of the corresponding standard ports in the reference model.

[0144] Generate output comparison statements triggered by the effective edge of the operating clock in the simulation test file.

[0145] Considering the signal propagation delay in the gate-level netlist simulation model, after the effective edge of the working clock arrives and a preset time tolerance window has elapsed, the corresponding output signals of the gate-level netlist simulation model and the reference model are read and compared.

[0146] Step D6: Generate a first decision branch, a second decision branch, and a third decision branch in the output comparison statement. The first decision branch is used to output a mismatch result when the output signal of the reference model is a definite logic value and the corresponding output signal of the gate-level netlist simulation model is an unknown state. The second decision branch is used to output a matching result when the corresponding output signals of the reference model and the gate-level netlist simulation model are both unknown states. The third decision branch is used to output a matching result or a mismatch result in other cases based on whether the values ​​of the corresponding output signals are consistent.

[0147] Specifically, for each set of corresponding output signals, the signal states of the reference model output signal and the gate-level netlist simulation model output signal are determined.

[0148] When the output signal of the reference model is a definite logic value, while the corresponding output signal of the gate-level netlist simulation model is an unknown state, it indicates that the gate-level netlist simulation model has not produced the definite output expected by the reference model, and the first decision branch outputs a mismatch result.

[0149] When both the output signal of the reference model and the corresponding output signal of the gate-level netlist simulation model are in an unknown state, the second decision branch outputs the matching result.

[0150] In other cases, the third decision branch compares the values ​​of the two corresponding output signals. If the values ​​match, a matching result is output; otherwise, a mismatch result is output.

[0151] Based on the matching results of the corresponding output signals of each group during the simulation process, test conclusions corresponding to the target test cases can be generated.

[0152] If all corresponding output signals meet the corresponding matching conditions, then the bitstream function of the target test case is determined to conform to the reference model; if there are output signals that do not meet the corresponding matching conditions, then the mismatch result of the corresponding output signal is recorded.

[0153] In the simulation test file generation method of the above embodiments of this disclosure, a reference model is generated based on primitive instances and their interconnections in the target test cases. The same test stimulus is applied to both the gate-level netlist simulation model and the reference model. The output signal of the reference model can be used to verify the output signal of the gate-level netlist simulation model. By performing the comparison after the effective edge of the working clock has passed through a time tolerance window, the output comparison timing is adapted to the signal propagation process of the gate-level netlist simulation model, improving the timing correspondence between the output of the gate-level netlist simulation model and the reference model, and the accuracy of the comparison results. By setting decision branches corresponding to determined logic values ​​and unknown states respectively, the output comparison logic can output corresponding matching results according to different signal states.

[0154] In a specific application embodiment, the design file and constraint file of the target test case are input into the electronic design automation tool, which then performs synthesis, placement and corresponding compilation processing on the target test case to generate the placement result file, mapping result file and bitstream file corresponding to the target test case.

[0155] The layout result file is used to determine the physical location information of each primitive instance; the mapping result file is used to assist in determining the primitive instances and their interconnection relationships in the target test case; and the bitstream file is used to configure the gate-level netlist simulation model corresponding to the target test case.

[0156] After generating the simulation test file corresponding to the target test case according to steps S101 to S104 above, import the simulation test file and bit stream file into the gate-level netlist simulation model corresponding to the target test case.

[0157] In the simulation environment, the bitstream configuration information in the bitstream file is loaded into the corresponding configuration register inside the gate-level netlist simulation model, so that the gate-level netlist simulation model forms the circuit configuration corresponding to the bitstream file.

[0158] Then, the simulation test file is run, and test stimuli are applied to the gate-level netlist simulation model through the hierarchical netlist paths of the regular top-level ports and hidden ports of the target test cases, and the same test stimuli are applied to the reference model simultaneously.

[0159] During the simulation, the corresponding output signals of the gate-level netlist simulation model and the reference model are obtained. The output comparison statements in the simulation test file are used to determine whether the corresponding output signals match. The bitstream test conclusion of the target test case is formed based on the matching results of the output signals.

[0160] Therefore, this embodiment can automatically complete primitive instance parsing, hidden port identification, physical location extraction, hierarchical netlist path derivation, signal connection of regular ports and hidden ports, test stimulus generation, reference model generation, output comparison and result determination from the design file of the target test case, primitive description data and layout result data, forming a complete simulation test file for gate-level netlist simulation, realizing the automatic generation of local hardware resource bitstream test files, improving the completeness of test port coverage, the accuracy of netlist path matching and the efficiency of test file generation.

[0161] In one embodiment, a simulation test file generation apparatus is provided, which corresponds one-to-one with the simulation test file generation method in the above embodiments. For example... Figure 4 As shown, the simulation test file generation device includes: The data parsing module 41 is used to obtain the design file of the target test case and the preset primitive description data, parse the design file, obtain the primitive instances in the target test case, the primitive type of each primitive instance, and the port instantiation and connection information, and obtain the standard port information corresponding to the primitive type of each primitive instance from the primitive description data. The hidden port determination module 42 is used to compare the port instantiation and connection information of each primitive instance with the corresponding standard port information to determine the hidden ports that have not formed a driver interface or observation interface at the top level of the target test case. The netlist path determination module 43 is used to acquire and parse the layout result data corresponding to the target test case, obtain the physical location information of the primitive instance to which the hidden port belongs, and query the preset hardware netlist mapping relationship according to the primitive type and physical location information of the primitive instance to which the hidden port belongs, and determine the hierarchical netlist path of the hidden port in the gate-level netlist simulation model corresponding to the target test case. The test file generation module 44 is used to generate simulation test files based on the port direction of the hidden port and the hierarchical netlist path. Specifically, for the hidden input port, it generates driving statements to apply test stimuli to the hidden input port through the corresponding hierarchical netlist path; for the hidden output port, it generates observation statements to obtain the output signal of the hidden output port through the corresponding hierarchical netlist path.

[0162] In one embodiment, the hidden port determination module 42 is specifically used to: obtain the standard port set of the primitive instance based on the standard port information corresponding to each primitive instance; For each primitive instance, based on the port instantiation and connection information of the primitive instance, identify from the standard port set of the primitive instance the ports that are not listed in the primitive instantiation statement, the ports that are listed in the primitive instantiation statement but are not connected, and the ports that are connected inside the target test case but are not brought out to the top level of the target test case, to obtain candidate hidden ports. Obtain the netlist node information of the gate-level netlist simulation model, and remove ports from the candidate hidden ports that do not have corresponding netlist nodes in the netlist node information to obtain the hidden ports.

[0163] In one embodiment, the netlist path determination module 43 is specifically used to: obtain the port mapping name corresponding to the hidden port from the primitive description data; Based on the primitive type and physical location information of the primitive instance to which the hidden port belongs, query the hardware netlist mapping relationship to obtain the netlist path prefix; By combining the netlist path prefix with the port mapping name, a hierarchical netlist path is obtained.

[0164] In one embodiment, the netlist path determination module 43 is specifically used to: read the site location and cell location from the physical location information; Retrieve the netlist mapping entry corresponding to the primitive type of the primitive instance to which the hidden port belongs from the hardware netlist mapping relationship. Each netlist mapping entry records the site range, cell range and the corresponding netlist path prefix. The site location and cell location are matched with the site range and cell range recorded in each netlist mapping entry, respectively. The successfully matched netlist mapping entries are identified as target netlist mapping entries, and the netlist path prefix is ​​read from the target netlist mapping entries.

[0165] In one embodiment, the netlist path determination module 43 is specifically used to: obtain the differential attribute of the primitive instance to which the hidden port belongs from the primitive description data; When the differential attribute indicates that the primitive instance to which the hidden port belongs is a differential primitive, the first netlist mapping position occupied by the first differential port and the second netlist mapping position occupied by the second differential port of the differential primitive are determined according to the differential attribute and physical location information. The first netlist mapping position includes the first site position and the first cell position, and the second netlist mapping position includes the second site position and the second cell position. The first site location and the first unit location are matched with the site range and unit range recorded in each netlist mapping entry to determine the first target netlist mapping entry. The second site location and the second unit location are matched with the site range and unit range recorded in each netlist mapping entry to determine the second target netlist mapping entry. Read the first netlist path prefix and the second netlist path prefix from the first target netlist mapping entry and the second target netlist mapping entry respectively, and obtain the port mapping names corresponding to the first differential port and the second differential port from the primitive description data; The hierarchical netlist path of the first differential port is obtained by combining the first netlist path prefix with the port mapping name corresponding to the first differential port, and the hierarchical netlist path of the second differential port is obtained by combining the second netlist path prefix with the port mapping name corresponding to the second differential port.

[0166] In one embodiment, the test file generation module 44 is specifically used for: Determine whether the hidden input port is connected to a constant signal based on the port instantiation and connection information; When the hidden input port is not connected to a constant signal, generate a forced assignment statement or a continuous assignment statement that applies test stimuli to the hidden input port through the corresponding hierarchical netlist path. When a hidden input port is connected to a constant signal, a forced assignment statement is generated that overwrites the original constant value of the hidden input port through the corresponding hierarchical netlist path. For hidden output ports, generate observation statements that lead the output signal of the hidden output port to the observation signal through the corresponding hierarchical netlist path.

[0167] In one embodiment, the primitive description data further includes a clock port identifier corresponding to each primitive port; Test file generation module 44 is specifically used for: Based on the clock port identifier, determine whether the hidden input port is a clock port or a data port; With the input port hidden as a clock port, a drive statement containing a periodic clock excitation that flips the level according to a preset period is generated. With the input port hidden as a data port, generate a driving statement containing data stimuli that dynamically change according to randomly generated data values.

[0168] In one embodiment, the test file generation module 44 is further specifically used for: The interconnection relationship between multiple primitive instances is determined based on port instantiation and connection information, and a reference model is generated based on the multiple primitive instances and interconnection relationship. Establish the port correspondence between the hidden ports and the corresponding standard ports in the reference model; Determine the operating clock from the input port of the target test case based on the clock port identifier; Generate stimulus input statements for applying the same test stimuli to the gate-level netlist simulation model and the reference model; Generate an output comparison statement to compare the corresponding output signals of the gate-level netlist simulation model and the reference model after the effective edge of the working clock has passed through a preset time tolerance window; The output comparison statement generates a first decision branch, a second decision branch, and a third decision branch. The first decision branch is used to output a mismatch result when the output signal of the reference model is a definite logic value and the corresponding output signal of the gate-level netlist simulation model is an unknown state. The second decision branch is used to output a matching result when the corresponding output signals of the reference model and the gate-level netlist simulation model are both unknown states. The third decision branch is used to output a matching result or a mismatch result in other cases based on whether the values ​​of the corresponding output signals are consistent.

[0169] It should be noted that the simulation test file generation device provided in the above embodiments is only illustrated by the division of the above functional modules when implementing the corresponding simulation test file generation method. In practical applications, the above processing can be assigned to different functional modules as needed to complete all or part of the processing described above. In addition, the above simulation test file generation device embodiments and simulation test file generation method embodiments belong to the same concept, and their specific implementation process can be found in the corresponding method embodiments, which will not be repeated here.

[0170] This disclosure also provides an electronic device for executing the simulation test file generation method of the above embodiments.

[0171] Figure 5 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure.

[0172] The following is a detailed reference. Figure 5 The diagram illustrates a structural schematic suitable for implementing an electronic device according to embodiments of the present disclosure. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 501, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 502 or a program loaded from memory 508 into random access memory (RAM) 503. The RAM 503 also stores various programs and data required for the operation of the electronic device. The processor 501, ROM 502, and RAM 503 are interconnected via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0173] Typically, the following devices can be connected to I / O interface 505: input devices 506 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 507 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 508 including, for example, magnetic tapes, hard disks, etc.; and communication devices 509. Communication device 509 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 5 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0174] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 509, or installed from a memory 508, or installed from a ROM 502. When the computer program is executed by the processor 501, it performs the functions defined in the simulation test file generation method of embodiments of this disclosure.

[0175] Figure 5 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0176] This disclosure also provides a computer-readable storage medium in which the methods described in this disclosure can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium after being downloaded over a network. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium may also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the simulation test file generation method shown in the above embodiments.

[0177] A portion of this disclosure can be applied to computer program products, such as computer program instructions, which, when executed by a computer, can invoke or provide methods and / or technical solutions according to this disclosure through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, and installation package files. Accordingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions; the computer compiling the instructions and then executing the corresponding compiled program; the computer reading and executing the instructions; or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0178] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for generating simulation test files, characterized in that, The method includes: Obtain the design file and preset primitive description data of the target test case, parse the design file to obtain the primitive instances in the target test case, the primitive type of each primitive instance, and port instantiation and connection information, and obtain the standard port information corresponding to the primitive type of each primitive instance from the primitive description data. The port instantiation and connection information of each primitive instance are compared with the corresponding standard port information to determine the hidden ports that do not form a driver interface or observation interface at the top level of the target test case. Obtain and parse the layout result data corresponding to the target test case, obtain the physical location information of the primitive instance to which the hidden port belongs, and query the preset hardware netlist mapping relationship according to the primitive type and physical location information of the primitive instance to which the hidden port belongs, and determine the hierarchical netlist path of the hidden port in the gate-level netlist simulation model corresponding to the target test case. A simulation test file is generated based on the port direction of the hidden port and the hierarchical netlist path. For the hidden input port, a driving statement is generated to apply test stimuli to the hidden input port through the corresponding hierarchical netlist path. For the hidden output port, an observation statement is generated to obtain the output signal of the hidden output port through the corresponding hierarchical netlist path.

2. The method according to claim 1, characterized in that, The step of comparing the port instantiation and connection information of each primitive instance with the corresponding standard port information to determine hidden ports that do not form a driver interface or observation interface at the top level of the target test case includes: Based on the standard port information corresponding to each primitive instance, obtain the standard port set of that primitive instance; For each primitive instance, based on the port instantiation and connection information of the primitive instance, identify from the standard port set of the primitive instance the ports not listed in the primitive instantiation statement, the ports listed in the primitive instantiation statement but not connected, and the ports connected inside the target test case but not brought out to the top level of the target test case, to obtain candidate hidden ports. Obtain the netlist node information of the gate-level netlist simulation model, and remove ports from the candidate hidden ports that do not have corresponding netlist nodes in the netlist node information to obtain the hidden ports.

3. The method according to claim 2, characterized in that, The step of querying a preset hardware netlist mapping relationship based on the primitive type and physical location information of the primitive instance to which the hidden port belongs, and determining the hierarchical netlist path of the hidden port in the gate-level netlist simulation model corresponding to the target test case, includes: Obtain the port mapping name corresponding to the hidden port from the primitive description data; Based on the primitive type and physical location information of the primitive instance to which the hidden port belongs, the hardware netlist mapping relationship is queried to obtain the netlist path prefix; The hierarchical netlist path is obtained by combining the netlist path prefix with the port mapping name.

4. The method according to claim 3, characterized in that, The step of querying the hardware netlist mapping relationship based on the primitive type and physical location information of the primitive instance to which the hidden port belongs, to obtain the netlist path prefix, includes: Read the site location and unit location from the physical location information; Obtain from the hardware netlist mapping relationship the netlist mapping entry corresponding to the primitive type of the primitive instance to which the hidden port belongs, and each netlist mapping entry records the site range, cell range and corresponding netlist path prefix; The site location and the unit location are matched with the site range and unit range recorded in each of the netlist mapping entries, respectively. The successfully matched netlist mapping entries are determined as target netlist mapping entries, and the netlist path prefix is ​​read from the target netlist mapping entries.

5. The method according to claim 4, characterized in that, The step of querying a preset hardware netlist mapping relationship based on the primitive type and physical location information of the primitive instance to which the hidden port belongs, and determining the hierarchical netlist path of the hidden port in the gate-level netlist simulation model corresponding to the target test case, includes: Obtain the differential attribute of the primitive instance to which the hidden port belongs from the primitive description data; When the differential attribute indicates that the primitive instance to which the hidden port belongs is a differential primitive, the first netlist mapping position occupied by the first differential port and the second netlist mapping position occupied by the second differential port of the differential primitive are determined according to the differential attribute and the physical location information. The first netlist mapping position includes a first site position and a first cell position, and the second netlist mapping position includes a second site position and a second cell position. The first site location and the first unit location are matched with the site range and unit range recorded in each of the netlist mapping entries to determine the first target netlist mapping entry. The second site location and the second unit location are matched with the site range and unit range recorded in each of the netlist mapping entries to determine the second target netlist mapping entry. Read the first netlist path prefix and the second netlist path prefix from the first target netlist mapping entry and the second target netlist mapping entry respectively, and obtain the port mapping names corresponding to the first differential port and the second differential port from the primitive description data; The hierarchical netlist path of the first differential port is obtained by combining the first netlist path prefix with the port mapping name corresponding to the first differential port, and the hierarchical netlist path of the second differential port is obtained by combining the second netlist path prefix with the port mapping name corresponding to the second differential port.

6. The method according to claim 4, characterized in that, The step of generating simulation test files based on the port direction of the hidden port and the hierarchical netlist path includes: Determine whether the hidden input port is connected to a constant signal based on the port instantiation and connection information. When the hidden input port is not connected to a constant signal, generate a forced assignment statement or a continuous assignment statement that applies test stimuli to the hidden input port through the corresponding hierarchical netlist path. When the hidden input port is connected to a constant signal, a forced assignment statement is generated that overwrites the original constant value of the hidden input port through the corresponding hierarchical netlist path. For the hidden output port, an observation statement is generated that leads the output signal of the hidden output port to the observation signal through the corresponding hierarchical netlist path.

7. The method according to claim 6, characterized in that, The primitive description data also includes clock port identifiers corresponding to each primitive port. The generation of the driving statement that applies test stimuli to the hidden input port through the corresponding hierarchical netlist path includes: Based on the clock port identifier, the hidden input port is determined to be either a clock port or a data port; When the hidden input port is a clock port, a drive statement containing a periodic clock excitation that flips the level according to a preset period is generated. When the hidden input port is a data port, a driving statement containing data stimuli that dynamically change according to randomly generated data values ​​is generated.

8. The method according to claim 7, characterized in that, The step of generating the simulation test file based on the port direction of the hidden port and the hierarchical netlist path also includes: The interconnection relationship between multiple primitive instances is determined based on the port instantiation and connection information, and a reference model is generated based on the multiple primitive instances and the interconnection relationship; Establish a port correspondence between the hidden port and the corresponding standard port in the reference model; The operating clock is determined from the input port of the target test case based on the clock port identifier. Generate stimulus input statements for applying the same test stimuli to the gate-level netlist simulation model and the reference model; Generate an output comparison statement to compare the corresponding output signals of the gate-level netlist simulation model and the reference model after the effective edge of the working clock has passed through a preset time tolerance window; The output comparison statement generates a first decision branch, a second decision branch, and a third decision branch. The first decision branch is used to output a mismatch result when the output signal of the reference model is a determined logic value and the corresponding output signal of the gate-level netlist simulation model is an unknown state. The second decision branch is used to output a matching result when the corresponding output signals of the reference model and the gate-level netlist simulation model are both unknown states. The third decision branch is used to output a matching result or a mismatch result in other cases based on whether the values ​​of the corresponding output signals are consistent.

9. A simulation test file generation device, characterized in that, The device includes: The data parsing module is used to obtain the design file of the target test case and the preset primitive description data, parse the design file to obtain the primitive instances in the target test case, the primitive type of each primitive instance, and the port instantiation and connection information, and obtain the standard port information corresponding to the primitive type of each primitive instance from the primitive description data. The hidden port determination module is used to compare the port instantiation and connection information of each primitive instance with the corresponding standard port information to determine the hidden ports that do not form a driver interface or observation interface at the top level of the target test case. The netlist path determination module is used to acquire and parse the layout result data corresponding to the target test case, obtain the physical location information of the primitive instance to which the hidden port belongs, and query the preset hardware netlist mapping relationship according to the primitive type and physical location information of the primitive instance to which the hidden port belongs, and determine the hierarchical netlist path of the hidden port in the gate-level netlist simulation model corresponding to the target test case. The test file generation module is used to generate simulation test files based on the port direction of the hidden port and the hierarchical netlist path. Specifically, for the hidden input port, it generates driving statements to apply test stimuli to the hidden input port through the corresponding hierarchical netlist path; for the hidden output port, it generates observation statements to obtain the output signal of the hidden output port through the corresponding hierarchical netlist path.

10. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the simulation test file generation method as described in any one of claims 1 to 8 when executing the computer program.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the simulation test file generation method as described in any one of claims 1 to 8.

Images