Cache verification method, electronic device, storage medium and program product

Abstract

The present disclosure relates to a cache verification method, an electronic device, a storage medium and a program product, comprising: performing electronic system level (ESL) function modeling on a cache structure to be verified to obtain a cache function model, the cache function model being a non-timing function model that processes instructions without simulating timing behavior at a clock cycle level; and verifying a cache coherence protocol using the cache function model. Thus, modeling and verification can be performed quickly and efficiently.

Description

Technical Field

[0001] This disclosure relates to the field of chip verification technology, and in particular to a cache verification method, electronic device, storage medium, and program product. Background Technology

[0002] Cache memory is a crucial component of a computer system, and improving its performance is essential for the entire system. Current technologies utilize cache timing models to explore the structure and verify the performance of cache memory; however, these models are often difficult to apply outside the broader computer architecture.

[0003] Furthermore, the cache timing model itself has numerous consistency protocols and a complex hierarchical architecture (ranging from L1 to L3 caches). Therefore, the cache timing model is difficult to model, the verification environment is complex, and its upstream and downstream paths involve many modules. Building a cache timing model in a traditional Register Transfer Level (RTL) environment is difficult and time-consuming. Summary of the Invention

[0004] In view of this, this disclosure proposes a cache verification method, electronic device, storage medium, and program product that enables rapid and efficient modeling and verification.

[0005] According to a first aspect of this disclosure, a cache verification method is provided, comprising: performing electronic system-level ESL functional modeling on the cache structure to be verified to obtain a cache functional model, wherein the cache functional model is a non-timing functional model that processes instructions without simulating clock cycle-level timing behavior; and using the cache functional model to verify a cache coherence protocol.

[0006] According to a second aspect of this disclosure, a cache verification apparatus is provided, comprising: a modeling module for performing electronic system-level ESL functional modeling on the cache structure to be verified to obtain a cache functional model, wherein the cache functional model is a non-timing functional model that processes instructions without simulating clock cycle-level timing behavior; and a verification module for verifying a cache coherence protocol using the cache functional model.

[0007] According to a third aspect of this disclosure, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the cache verification method described above.

[0008] According to a fourth aspect of this disclosure, a non-volatile computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of the cache verification method described above.

[0009] According to a fifth aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the steps of the cache verification method described above.

[0010] This disclosure enables pure functional modeling of cache hierarchy and coherence protocols, free from constraints on the overall computer architecture and clock cycle-level timing, thereby reducing the difficulty of building cache models.

[0011] Since the constructed cache functional model is a non-time-sequential functional model, its execution is driven by function calls rather than triggered by the simulation clock. Therefore, compared with RTL simulation with precise clock cycles, the execution speed of the non-time-sequential functional model is greatly improved, which can improve the verification efficiency of the cache coherence protocol, reduce the verification complexity, and shorten the verification cycle.

[0012] Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0013] The accompanying drawings, which are included in and form part of this specification, illustrate exemplary embodiments, features, and aspects of this disclosure together with the specification and serve to explain the principles of this disclosure.

[0014] Figure 1 A flowchart illustrating a cache verification method according to an embodiment of the present disclosure is shown.

[0015] Figure 2 A flowchart illustrating a cache verification method according to an embodiment of the present disclosure is shown.

[0016] Figure 3 A schematic diagram of a cache function model according to an embodiment of the present disclosure is shown.

[0017] Figure 4 A schematic diagram of a cache function model according to an embodiment of the present disclosure is shown.

[0018] Figure 5 A schematic diagram of a cache function model according to an embodiment of the present disclosure is shown.

[0019] Figure 6 A schematic diagram of the internal architecture of a functional cache memory according to an embodiment of the present disclosure is shown.

[0020] Figure 7A schematic diagram of the internal architecture of a host interconnect listening table according to an embodiment of the present disclosure is shown.

[0021] Figure 8 A schematic diagram of a simulation input acquisition architecture according to an embodiment of the present disclosure is shown.

[0022] Figure 9 This diagram illustrates the execution flow of an instruction in a cache functional model according to an embodiment of the present disclosure.

[0023] Figure 10 A block diagram of a cache verification apparatus according to an embodiment of the present disclosure is shown.

[0024] Figure 11 This is a block diagram illustrating an apparatus 1100 for cache verification according to an exemplary embodiment. Detailed Implementation

[0025] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0026] As used herein, the terms “comprising,” “including,” “having,” or variations thereof are open-ended and include one or more of the stated features, integrals, elements, steps, components, or functions, but do not exclude the presence or addition of one or more other features, integrals, elements, steps, components, functions, or groups thereof.

[0027] When an element is referred to as “connected,” “coupled,” “responding,” or a variation thereof relative to another element, it may be directly connected, coupled, or responding to another element, or there may be an intermediate element present.

[0028] Although the terms first, second, third, etc., may be used herein to describe various elements / operations, these elements / operations should not be limited by these terms. These terms are only used to distinguish one element / operation from another. Therefore, without departing from the teachings of the inventive concept, a first element / operation in some embodiments may be referred to as a second element / operation in other embodiments.

[0029] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0030] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0031] Figure 1 A flowchart illustrating a cache verification method according to an embodiment of the present disclosure is shown. This cache verification method can be executed by a computer. Figure 1 As shown, the cache verification method may include the following steps:

[0032] In step S110, electronic system-level (ESL) functional modeling is performed on the cache structure to be verified to obtain a cache functional model. The cache functional model is a non-timing functional model that processes instructions without simulating clock cycle-level timing behavior.

[0033] A cache architecture includes a hierarchical structure, which is a multi-level cache system divided according to storage access speed, capacity, and physical distance from the processor core. For example, this hierarchical structure includes, but is not limited to, Level 1 cache, Level 2 cache, and Level 3 cache.

[0034] The L1 cache is the cache level closest to the processor core and is usually integrated inside the processor core. It can be further divided into the L1 Instruction Cache (L1I) and the L1 Data Cache (L1D), which are used to cache the instruction stream that the processor is about to execute and the data stream that the processor is currently operating on, respectively.

[0035] The L2 cache is located between the L1 cache and lower-level memory. It can be a private L2 cache for a single processor core or a shared L2 cache shared by multiple cores within the same physical package. The L2 cache has a larger storage capacity than the L1 cache and is used to cache instructions and data blocks that are replaced due to the capacity limitations of the L1 cache, thereby reducing the frequency of accesses to lower-level memory.

[0036] Level 3 cache is typically deployed on the processor chip as the Last Level Cache (LLC) and is shared by multiple processor cores or processing clusters. Level 3 cache has larger storage capacity and relatively higher access latency, and is used to aggregate shared data across multiple cores at the chip level.

[0037] Considering that the RTL timing model of cache in the existing technology is deeply coupled with the underlying hardware implementation, it is necessary to rely on the entire computer architecture and simulate the timing behavior at the clock cycle level, which leads to high modeling difficulty and long simulation cycle. This embodiment proposes to perform ESL functional modeling on the cache structure at an abstraction level higher than RTL, extract the functional characteristics of the cache hierarchical architecture, and construct a non-timing functional model to obtain the cache functional model. Thus, the functional behavior description of the cache can be constructed independently of the underlying hardware timing constraints without relying on the entire computer architecture.

[0038] Unlike RTL modeling, which focuses on register state transitions and gate-level signal propagation within each clock cycle, ESL functional modeling in this embodiment is at the functional level of abstraction. It uses transaction requests and function calls as the basic units of interaction between modules, rather than clock edge-triggered signal toggling as the driving mechanism.

[0039] Therefore, the cache functional model does not require instantiating complex RTL circuits for processor cores, main memory controllers, interconnect networks, and numerous upstream and downstream functional modules. It only needs to interact with the abstracted upstream and downstream modules through standardized transaction interfaces to describe the functional characteristics of the cache's hierarchical architecture, independent of the overall computer architecture. These functional characteristics may include, but are not limited to, hit detection logic, cache replacement policy logic, and cache coherence protocol state machines.

[0040] The hit detection logic compares the tag field with the tag information within the cache group, and uses the valid bits to determine whether a cache hit or a cache miss occurs. The cache replacement strategy logic selects a cache line to replace when a cache miss occurs and there are no free cache lines in the target group, using strategies such as Least Recently Used (LRU), First-In-First-Out (FIFO), or Random Replacement. The cache consistency protocol state machine maintains the consistency state of cache lines in multi-level caching or multi-core shared cache scenarios, and handles corresponding state transitions and listener responses.

[0041] The constructed cache functional model is a non-timing functional model, which does not simulate clock cycle-level hardware timing behavior. Specifically, the execution of the cache functional model is not triggered by the simulation clock, but is driven by function calls.

[0042] For example, the cache functional model reads transaction requests one by one from the memory access transaction sequence provided by the input source through interface functions (i.e., reads instructions one by one from the instruction sequence), and completes the functional operations of address resolution, tag comparison, hit determination, and data return during the corresponding transaction processing. For cache hit scenarios, this functional operation is completed within a single function call; for cache miss scenarios, the model triggers the response of the lower storage level and the cache line replacement / write-back process through the function call chain. Thus, without being constrained by the overall computer architecture and clock cycle-level timing constraints, timing-independent functional modeling is performed for the cache hierarchy architecture and its cache coherence protocol.

[0043] In step S130, the cache coherency protocol is verified using the cache function model.

[0044] Cache consensus protocols can include, but are not limited to, MESI, MOSI, or MESIF protocols. Different consensus protocols correspond to different state transition logics in the cache line state machine. During the modeling phase, the functional logic of one or more consensus protocols can be implemented in advance in the cache functional model, and corresponding conditional compilation macros or configuration parameters can be defined as protocol selection switches. During the simulation phase, the consensus protocol type to be verified can be dynamically switched according to verification requirements without recompiling or refactoring the model.

[0045] Taking the MESI protocol as an example, each cache line has four consistency states, which can be represented by 2 bits: M (Modified), E (Exclusive), S (Shared), and I (Invalid). The M state indicates that the cache line data is valid, has been modified but not written back to main memory, and exists only in the current cache. The E state indicates that the cache line data is valid and consistent with the main memory data, and exists only in the current cache. The S state indicates that the cache line data is valid and consistent with the main memory data; the cache line data can exist in multiple caches simultaneously. The I state indicates that the cache line data is invalid.

[0046] Compared to the MESI protocol, the MOSI protocol adds an O (Owned) state. The O state indicates that the cache line data is valid and has been modified to be inconsistent with the main memory data, but cache line data can exist in multiple caches simultaneously. A cache line in the O state acts as a data provider; that is, when it receives a read listener request from another cache, it forwards the latest data to the requester without accessing main memory. Simultaneously, a cache line in the O state needs to write dirty data back to main memory.

[0047] Compared to the MESI protocol, the MESIF protocol adds an F (Forward) state. The F state is a special form of the S state. When multiple caches simultaneously hold a copy of the same valid cache line, one cache line copy is designated as being in the F state, and the cache in the F state acts as the sole source of data forwarding. When other caches initiate a read request for that address, the cache in the F state provides the data copy, rather than the main memory or other caches in the S state responding.

[0048] The cache functional model is used to simulate the behavior of the cache hierarchy architecture under the constraints of the cache coherence protocol. During verification, the cache functional model obtains instructions one by one from the instruction sequence provided by the input source. The model outputs the consistency state transitions, data responses, and expected results of the monitored transactions for each level of cache. The expected results are compared with the actual response of the design to be verified, and / or, based on the protocol assertion check results during the model's operation, the cache coherence protocol is verified to have any functional defects in the corresponding verification scenario.

[0049] For example, the cache functional model reads and executes instructions one by one from the instruction sequence provided by the input source through interface functions. During instruction execution, the running status of the cache functional model is monitored, which may include, but is not limited to: the consistency status of cache lines at all levels, the data visibility of each core to the same address, and the compliance of listening requests and responses.

[0050] If the instruction sequence completes execution and at least one of the following abnormal runtime states—data inconsistency anomaly, state transition anomaly, or listener response anomaly—is detected during monitoring, then the cache consistency protocol is verified to have a functional defect. If the instruction sequence completes execution and no of the aforementioned abnormal runtime states is detected during monitoring, then the cache consistency protocol is verified to be functionally correct.

[0051] Data consistency anomaly refers to the failure of each core to obtain data values ​​that conform to the consistency protocol when accessing the same physical address. For example, after a core modifies a cache line, other cores' non-expired replicas still return the old data.

[0052] State transition anomalies refer to cache line consistency state transitions that do not conform to the path specified by the cache consistency protocol state machine. For example, a cache line in the S state does not transition to the I state after receiving an exclusive write listener request.

[0053] An abnormal listener response refers to a response to a listener request that does not match the response type specified by the cache consistency protocol. For example, a kernel holding a valid copy of the data may not return data or may return an incorrect consistency status indication when the listener hits.

[0054] According to this embodiment, it is possible to perform pure functional modeling only on the hierarchical architecture and consistency protocol of the cache, without being subject to the constraints of the entire computer architecture and clock cycle-level timing, thereby reducing the difficulty of building the cache model.

[0055] Since the constructed cache functional model is a non-time-sequential functional model, its execution is driven by function calls rather than triggered by the simulation clock. Therefore, compared with RTL simulation with precise clock cycles, the execution speed of the non-time-sequential functional model is greatly improved, which can improve the verification efficiency of the cache coherence protocol, reduce the verification complexity, and shorten the verification cycle.

[0056] Because ESL functional modeling is detached from the overall computer architecture and timing constraints, it allows for flexible, convenient, and rapid adjustment of cache hierarchy configurations, such as the number of cache levels and cores. Furthermore, the cache functional model enables real-time verification of the correctness of the adjusted cache hierarchy architecture and consistency protocol. This allows for multi-round, low-cost architecture exploration and functional verification.

[0057] In some embodiments, the architecture parameters of the cache function model are configured by reading a configuration file through an interface function, thereby changing the cache structure corresponding to the cache function model. The architecture parameters include at least one of the following: the number of cache groups at each level of cache, the number of cache paths, the number of cores, the number of effective cores, the number of cache groups for the listener table, the number of cache paths / operating modes, and the number of core composite die CCDs.

[0058] The number of cache sets and cache paths together determine the capacity and set associativity of each cache level. For example, the number of cache sets in the first-level cache can be adjusted to 64 and the number of cache paths to 4, or the number of cache sets in the second-level cache can be adjusted to 512 and the number of cache paths to 8, by reading the configuration file through an interface function. Upon receiving parameter changes, the cache functional model dynamically reallocates the storage array size and the number of entries in the functional cache list, thereby simulating cache structures with different capacity and associativity configurations in real time without recompiling or refactoring the model.

[0059] The core count defines the total number of processor cores simulated by the cache functionality model. For example, the core count can be configured to 1, 2, 4, or 8 to support validation of different processor architectures from single-core to multi-core. The cache functionality model instantiates a corresponding private cache hierarchy (such as L1I, L1D, and PL2) and core ID for each core based on the core count, and maintains consistent state interactions between cores in multi-core scenarios.

[0060] The effective cores parameter specifies a subset of cores that actually participate in the current simulation, within the configured core count. For example, with a core count of 8, the effective cores parameter can be used to enable only 4 cores for consistency protocol verification, while the remaining cores are disabled. This allows for flexible simulation of the impact of different core activation strategies on cache consistency behavior within the same model instance without modifying the underlying model code.

[0061] The listener table is used to record and manage the status information of each core cache line during multi-core consistency verification to support listener filtering or directory functions. The number of cache groups and cache paths in the listener table determines its capacity and conflict characteristics. The working mode defines how the listener table is organized and its query strategy, such as inclusive mode, non-inclusive mode, exclusive mode, or directory-based consistency maintenance mode. For example, the listener table can be configured to inclusive mode through interface functions, enabling it to accurately record the tags and status information of all valid cache lines in its next-level cache, thereby quickly determining the target core set during listener broadcasting and reducing unnecessary listener request distribution.

[0062] The number of CCDs defines the number of core complex dies in the processor chip simulated by the cache functional model. In a multi-chip module or die architecture, each CCD can contain multiple processor cores and corresponding cache levels. By configuring the number of CCDs, the cache functional model can simulate cache coherence interactions across CCDs, such as local coherence access between cores within the same CCD and remote coherence access between cores across CCDs, thereby supporting cache coherence protocol verification for die-level architectures.

[0063] According to this embodiment, during simulation startup or operation, the cache functional model reads the configuration values ​​of the aforementioned architecture parameters by calling an interface function to read the configuration file, thereby adjusting the cache structure of the cache functional model. This allows for rapid, flexible, and low-cost exploration of the cache structure through simple interface function calls.

[0064] Figure 2 A flowchart illustrating a cache verification method according to an embodiment of the present disclosure is shown. This cache verification method can be executed by a computer. Figure 2 As shown, the cache verification method may include the following steps:

[0065] In step S210, electronic system-level ESL functional modeling is performed on the cache structure to be verified to obtain a cache functional model. The cache functional model is a non-timing functional model that processes instructions without simulating clock cycle-level timing behavior.

[0066] For step S210, please refer to the detailed description of step S110 above, which will not be repeated here.

[0067] In step S220, the cache function model is used to serially iterate the instruction sequence. The cache function model reads only one instruction from the instruction sequence each time, and actively reads the next instruction after the instruction is executed. This process is repeated until the entire instruction sequence is executed.

[0068] The cache functional model reads instructions one by one from the instruction sequence provided by the input source through standardized interface functions, and executes the read instructions on the cache functional model in a serial iterative manner. The transaction object corresponding to each instruction in the instruction sequence includes the operation type, which may include, but is not limited to, read request, write request, load request, loadinvalidate request, snoop request, and snoop invalidate request.

[0069] The cache functional model actively reads and executes only one instruction from the instruction sequence at a time. In each iteration, the cache functional model completes the full functional processing of the instruction within a single function call. This functional processing includes: address resolution, decomposing the target address into a tag field, an index field, and an intra-block offset field, and locating the target cache group in the functional cache memory based on the index field; tag comparison and hit detection, comparing the tag field with the tag information of each path in the target cache group, and determining a cache hit or cache miss based on the valid bits; consistency state query and update, determining the consistency state of the current cache line and the allowed state transition paths based on the cache consistency protocol state machine; data read and write operations, reading target data from the functional cache memory or writing requested data by byte mask in a hit scenario, and triggering a cache filling process or generating a write-back transaction in a miss scenario; and listener transaction generation, where the query transaction processing module generates listener requests and processes listener responses in cross-core consistency interaction scenarios.

[0070] After processing is complete, the cache function model actively reads the next instruction from the instruction sequence again through its internal logic, and so on, until all instructions in the instruction sequence have been executed.

[0071] In multi-core verification scenarios, the instruction sequence contains interleaved instructions from multiple cores or CCDs. The cache functional model routes instructions to the corresponding core private cache level (e.g., L1I, L1D, or PL2) or shared cache level (e.g., LLC) for processing based on the initiating node identifier of each instruction. When the processing of an instruction involves cross-core consistency interaction, such as a core initiating an exclusive write request to a shared cache line, the cache functional model synchronously generates listener requests for other core caches within a single function call. Based on the consistency status of each core recorded in the functional cache memory and the listener response status recorded in the functional linked list, it updates the consistency status, thereby simulating the functional semantics of multi-core concurrent access without relying on clock cycle-level synchronization mechanisms.

[0072] Compared to methods that rely on external clock signals to input instructions into the cache timing model, this embodiment allows the cache functional model to actively read instructions one by one. After the current instruction is executed, its internal logic actively retrieves the next instruction from the instruction sequence for processing, without the need for an external clock driver. This simplifies the setup of the verification environment, avoids providing the model with complex external clock and synchronization drive circuits, and eliminates pipeline pauses and signal propagation waits caused by clock edge triggering due to serial instruction processing, thereby improving simulation execution speed.

[0073] In step S230, the cache coherence protocol is verified based on the running state of the cache function model during the execution of the instruction sequence.

[0074] For step S230, please refer to the previous description of step S130, which will not be repeated here.

[0075] In step S240, the cache miss index is output by the cache function model as an auxiliary parameter for verifying the performance of the cache.

[0076] During the execution of the instruction sequence, the cache functional model statistically analyzes and outputs cache miss metrics. After verifying the functional correctness of the cache consistency protocol, the cache miss metrics output by the cache functional model can be used as auxiliary parameters, combined with system-level performance metrics such as average storage access latency, consistent transaction completion time, interconnect bandwidth utilization, and the number of consistent messages, to comprehensively verify the performance of the cache.

[0077] In some embodiments, while maintaining consistency in cache capacity, associativity, and replacement algorithm, the system-level performance metrics of the current cache architecture configuration can be compared with the system-level performance metrics of a known effective benchmark cache architecture under the same instruction sequence. If the system-level performance metrics of both are within a preset deviation threshold, and the cache miss metric of the last-level cache does not show significant degradation, then the cache performance is verified to be as expected; if the cache miss metric of the last-level cache shows significant optimization, then the cache performance is verified to be efficient; if the cache miss metric of the last-level cache shows significant degradation, then the cache performance is verified to be as expected.

[0078] For example, the difference between the cache miss metric of the last-level cache under the current cache structure configuration and the cache miss metric of the last-level cache under the baseline cache structure configuration can be calculated. If the difference is greater than a first threshold, it is determined that the cache miss metric of the last-level cache has significantly deteriorated; if the difference is less than the negative of the first threshold, it is determined that the cache miss metric of the last-level cache has significantly improved; if the difference is greater than or equal to the negative of the first threshold and less than or equal to the first threshold, it is determined that the cache miss metric of the last-level cache has not significantly deteriorated.

[0079] According to this embodiment, the cache coherence protocol can be quickly verified, thereby enabling low-cost and high-efficiency architectural exploration of cache structures and verification of the effectiveness of the cache coherence protocol.

[0080] The traditional cache timing model uses a parallel input of multiple requests. Multiple requests may simultaneously compete for the same cache group, cache line, or miss handling register resource, leading to requests conflicting, deadlocks, or complex arbitration scheduling problems, increasing the difficulty of setting up the verification environment and the complexity of debugging. In this embodiment, the cache functional model actively reads and executes instructions sequentially, processing only a single transaction request at any given time. This fundamentally avoids resource contention and conflicts caused by concurrent access from multiple requests, eliminating the need for complex request arbitration, pipeline conflict detection, and out-of-order scheduling logic. This significantly reduces the internal complexity of the cache functional model and the difficulty of setting up the verification environment.

[0081] Because the cache functional model executes instructions serially and iteratively, with each instruction processed within a single function call, the model's execution is independent of external clock signals and does not require simulating clock cycle-level signal synchronization and state propagation. Therefore, freed from the constraints of the overall computer architecture and clock cycle-level timing, we only perform pure functional modeling and verification of the cache's hierarchical architecture and consistency protocol.

[0082] Existing parallel request processing technologies are limited by clock cycle driving, with each cycle only able to advance a limited number of operation steps, and requiring waiting for arbitration, synchronization, and conflict resolution. In this embodiment, serial execution is directly driven by function calls. After the current instruction is completed, the model's internal logic actively reads the next instruction, eliminating clock edge waiting, pipeline bubbles, and synchronization overhead. This significantly improves simulation execution speed, enabling rapid verification of the cache coherency protocol and shortening the verification cycle.

[0083] The traditional cache timing model requires an external clock driver, complex request dispatch logic, and a parallel stimulus generator. In this embodiment, the cache functional model actively reads instructions one by one, without requiring an external clock driver or a parallel request injection and conflict management module. The verification environment only needs to provide a serial transaction sequence input to run, thus simplifying the setup of the verification environment and reducing manpower and resource investment.

[0084] Because ESL functional modeling is free from timing constraints and the serial execution mechanism avoids coupling with parallel scheduling logic, it allows for flexible and convenient adjustment of cache hierarchy configurations (such as the number of cache levels, core count, and CCD count), and enables real-time verification of the adjusted hierarchy architecture and consistency protocol using the cache functional model. This allows for multi-round, low-cost functional verification and architecture exploration.

[0085] In some embodiments, the instruction sequence can be divided into multiple segments; during the execution of the instruction sequence, for each level of the cache functional model, the hit / miss status of each request in each segment on that level of cache is recorded one by one; after the entire instruction sequence has been executed, for each level of cache, based on the number of miss requests in each segment on that level of cache, the total number of requests in each segment, the weight of each segment, and the total weight, the cache miss index of each level of cache is calculated; the cache miss index of each level of cache is output as the auxiliary parameter.

[0086] The instruction sequence can be divided into multiple segments in any suitable way, and each segment can be configured with a corresponding weight coefficient to reflect the degree of impact of different execution stages on cache performance. During the execution of the instruction sequence, for each level of the cache functional model, the hit or miss status of each instruction in each segment on that level of cache is recorded one by one.

[0087] Each level of cache is configured with independent hit and miss counters to count the number of hits and misses in the current level of cache. The hit or miss status of each instruction is recorded individually. For example, whenever an instruction is processed in this level of cache, the cache functional model updates the hit or miss counter of the corresponding level of cache according to the result of the hit detection logic, and records the hit / miss status of that instruction in the corresponding segment.

[0088] After the entire instruction sequence has been executed, for each level of cache, a cache miss metric is calculated using a preset formula based on the number of miss requests for each segment in that cache level, the total number of requests for each segment, the weight coefficient of each segment, and the total weight. For example, the cache miss metric is Misses Per KiloInstructions (MPKI).

[0089] In some embodiments, the number of missed requests for each segment is divided by the total number of requests to obtain a first quotient; the weight of each segment is divided by the total weight to obtain a second quotient; the product of the first and second quotients for each segment is calculated, and the sum of the products of each segment is calculated as the cache miss index for each level of cache. The cache miss index for each segment can be calculated using the following formula 1:

[0090] Formula 1

[0091] MPKI represents the cache miss index for each slice. count This represents the number of missed requests for each slice. total count The total number of requests for the current segment is represented by the value "total". weight Represents the total weight, slice weight This indicates the weight of the current segment.

[0092] Figure 3 A schematic diagram of a cache function model with one CCD according to an embodiment of the present disclosure is shown. Figure 3As shown, the cache functional model includes one CCD, which comprises N cores. Each core includes an L1 cache and a PL2 cache. The L1 cache is divided into an L1D cache and an L1I cache, and the L1D and L1I caches share a PL2 cache. The N cores share one LLC. The Host Interconnect Fabric Snoop Table (HIF SNT) is located below the LLC and is used to provide snoop transaction management and routing forwarding functions in the host interconnect architecture. The HIF SNT receives access requests or snoop requests from the LLC in the form of a transaction-level interface and passes them to lower-level storage layers or external devices. It should be noted that in real processor systems, different vendors may use different names for the interconnect snoop functional module, but they all undertake cross-module transaction routing and snoop response forwarding functions.

[0093] In traditional RTL implementations, PL2 and LLC (usually divided into multiple slices) are connected via a complex mesh interconnection structure. PL2 needs to route through the mesh network to determine the target LLC slice. In this embodiment, the cache function model abstracts the functionality of the mesh interconnection network into a routing table, integrated into the interface logic of PL2 or LLC. When processing instructions, PL2 quickly obtains the LLC slice identifier to which the instruction should reach by looking up the routing table, thereby achieving correct instruction transmission without simulating the physical topology, arbitration logic, and signal propagation delay of the mesh network.

[0094] In real computer systems, the kernel domain (including L1 and PL2) and the non-kernel domain (including LLC and HIF SNT) typically operate at different clock frequencies, requiring cross-clock domain conversion for correct communication. Since the cache function model in this embodiment is a non-timing function model, L1, PL2, LLC, and HIF SNT do not rely on clock edge triggering but interact at the transaction level through function calls. Therefore, this model eliminates the need to implement complex cross-clock domain synchronization logic, clock frequency conversion circuits, and corresponding timing convergence constraints, significantly simplifying model complexity and improving simulation execution efficiency.

[0095] It should be noted that the architectural parameters of the cache functionality model can be adjusted by reading configuration files. For example, assuming a configuration file is read to change the configuration from including both L1 and PL2 caches per core to including only L1 cache and excluding PL2 cache per core, the adjusted cache functionality model will be more efficient than... Figure 3 The change in the cache functionality model is the removal of the PL2 cache from each core.

[0096] For example, assuming a configuration file is read to adjust each L1 cache (including L1D and L1I) to include only L1I and exclude L1D per core, then the adjusted cache functional model compared to... Figure 3 The change in the cache functionality model is the removal of L1D from each L1 cache.

[0097] Figure 4 This diagram illustrates the structure of a cache functional model with two CCDs according to an embodiment of the present disclosure. Figure 3 Compared to the single CCD structure shown, Figure 4 The difference lies in the fact that the cache function model is expanded to include two CCDs (CCD_0 to CCD_1), and each CCD still maintains a three-level hierarchical structure of L1 Cache, PL2, and LLC. The LLCs in each CCD are connected to the corresponding host interconnection listener tables (HIF SNT_0 to HIF SNT_1).

[0098] The HIF SNTs of different CCDs are interconnected via an interconnection channel to achieve cross-CCD transaction routing. That is, when the cache in CCD_0 is missing and needs to access the data cached in CCD_1, or needs to broadcast a listen request to CCD_1, the request is forwarded to the HIF SNT_1 of CCD_1 via the cross-CCD interconnection channel through HIF SNT_0 of CCD_0, thereby achieving cache consistency transaction transmission and listen response interaction between the two CCDs.

[0099] Therefore, while retaining the simplified characteristics of single CCD internal function call driving and no need for clock frequency conversion, HIF SNT's cross-CCD interconnect abstraction supports functional verification of cross-crystal cache coherency protocols under multi-CCD architecture.

[0100] It should be understood that, compared to Figure 3 The configuration file corresponding to the cache function model in the middle. Figure 4 In the configuration file corresponding to the high-speed cache function model, the number of CCDs is configured from 1 to 2.

[0101] Figure 5 This diagram illustrates the structure of a cache functional model with four CCDs according to an embodiment of the present disclosure. Figure 4 Compared to the multi-CCD structure shown, Figure 5The difference lies in the cache functional model: it is expanded to include four CCDs (CCD_0 to CCD_3), and each CCD still maintains a three-level hierarchical structure of L1 Cache, PL2, and LLC. The HIF SNTs of each CCD adopt a fully cross-connected topology, meaning that the HIF SNTs of each CCD are directly connected to the HIF SNTs of other CCDs through interconnect channels, rather than... Figure 4 The diagram shows only the pairwise interconnections between two CCDs.

[0102] This enables functional verification of cross-crystal cache coherency protocols under more CCDs and more complex interconnect topologies.

[0103] It should be understood that, compared to Figure 3 The configuration file corresponding to the cache function model in the middle. Figure 5 In the configuration file corresponding to the high-speed cache function model, the number of CCDs is configured from 1 to 4.

[0104] According to this embodiment, the cache function model can be expanded into a multi-CCD structure. Different CCDs are interconnected through a host interconnection listener table, and the number of CCDs can be flexibly configured according to simulation and architecture exploration needs.

[0105] Compared to single-CCD structures, multi-CCD structures not only support the exploration of LLC and HIF SNT architectures, but also support the verification of data consistency between different levels of caches across multiple CCDs and HIF SNT. HIF SNT functions as a fourth-level cache, and it also has internal storage units. The specific storage location of a request is located through the cache group number and cache path number, and the replacement of cache paths within each cache group follows the least recently used replacement algorithm.

[0106] Figure 6 A schematic diagram of the internal architecture of a functional cache memory according to an embodiment of the present disclosure is shown. Figure 6 As shown, the functional cache memory includes a set-associative cache line storage array and a function linked list (FuncLinkList). The set-associative cache line storage array adopts a set-associative mapping structure, containing N+1 cache sets from Set 0 to Set N, and each set contains N+1 cache paths from way 0 to way N. Each storage unit corresponds to a functional map of a cache line, used to store the tag field, data field, consistency status bits (such as M state, E state, S state, and I state in the MESI protocol), valid bit, and dirty bit of that cache line.

[0107] The function list is used to manage the replacement order of cache lines or the status of missing transactions, and contains N+1 entries from Entry 0 to Entry N. Each Entry can correspond to a cache line or a cache group, and records the most recent use order of the cache line, the status of the missing handling register, the listener response status, or the replacement candidate flag.

[0108] Each level of cache is configured with this storage unit, which locates the storage location corresponding to the target request through the cache set number and cache way number. The smallest unit of each storage unit stores the request set, way, label, address, and consistency status. The replacement of the way in each set follows the least recently used (LRU) replacement algorithm.

[0109] The cache functionality model uses linked lists to implement the LRU replacement algorithm for each level of the cache. The head of the linked list corresponds to the least recently used cache path within the cache group. Whenever a cache miss occurs and replacement is required, the cache path at the head of the linked list is selected as the replacement candidate row, and the latest cache path is moved to the tail of the linked list.

[0110] Each level of cache independently maintains the consistency state of its local cache lines. Additionally, the next level of cache maintains the consistency state of the previous level cache and its associated kernel identifier. For example, using... Figure 3 For example, PL2 records the consistency status of each cache line in L1I and L1D within its corresponding core, and LLC records the consistency status of all cores sharing this LLC and the corresponding core identifier.

[0111] For each cache level, upon receiving a load request or load invalidate request from the parent cache level, the following processing is performed: If the request hits the current cache level, the current cache level queries the consistency status of the corresponding cache line in the parent cache level. If another cache in the parent cache level holds a valid copy of the cache line, a snoop request or snoop invalidate request is sent to the parent cache level based on the consistency status and request type. If the parent cache level returns a data copy in the M state, the current cache level first writes the data back to the corresponding cache line and then returns the latest data to the request initiator. If the request does not hit the current cache level, a load request or load invalidate request is sent to the next lower cache level.

[0112] When there are no free cache paths in the target cache group and replacement is required, the tag information is updated according to the LRU replacement algorithm, an eviction transaction is generated, and sent to the next-level cache. Simultaneously, the current-level cache receives listener requests or listener invalidation requests from the next-level cache and returns the corresponding listener response.

[0113] Because the caching model is a time-free model, transaction requests are processed sequentially. Figure 3 The cache functionality model shown is suitable for quickly verifying changes in data consistency protocols and architecture configurations of the first-level or second-level cache, such as setting whether the cache functionality simulation model has a second-level cache and whether the first-level cache has L1D.

[0114] Figure 7 A schematic diagram of the internal architecture of a host interconnect listening table according to an embodiment of the present disclosure is shown. Figure 7 As shown, HIF SNT comprises a storage array and a HIF SNT chain (HIFSntChain). The storage array and... Figure 6 Similarly, a set-associative mapping structure is adopted, containing N+1 cache sets from Set 0 to Set N, and each set contains N+1 cache paths from way 0 to way N. Each storage unit corresponds to a functional image of a listener table entry, used to store the tag field, data field, consistency status bit, valid bit, and dirty bit of the listener address. The HIF SNT chain contains N+1 entries from Entry 0 to Entry N, used to manage the replacement order of listener table entries, the listener hit chain, or the transaction processing status.

[0115] HIF SNT receives load requests and load invalidation requests from LLC, sends listener requests and listener invalidation requests to LLC and other CCD HIF SNTs, and receives corresponding listener responses. Through cross-CCD transaction routing and listener forwarding by HIF SNT, data consistency between different levels of cache in a multi-CCD system is maintained.

[0116] Furthermore, in a multi-CCD architecture, configuration files can be read via interface functions to flexibly adjust architectural parameters such as the number of cache groups and cache paths of LLC and HIF SNT, thereby enabling architectural exploration and functional verification of the capacity scale, associativity configuration, and listening filtering efficiency of LLC and HIF SNT.

[0117] Figure 8This diagram illustrates a simulation input acquisition architecture according to an embodiment of the present disclosure. The input source is generated based on the dynamic binary instrumentation tool Pin and its derivatives. Pin provides a rich set of application programming interfaces (APIs) for monitoring program execution status and simulating instructions not supported by existing processors. Pintool refers to specific tools developed based on the Pin framework, which can be used to perform program analysis and simulation verification; PinPlay can be understood as a simulator framework that supports the recording and playback of program execution trajectories.

[0118] For example, for a benchmark program, Pintool is used to capture all executed instructions during program execution, generating a trace file, i.e., a Pinball file, containing memory access address sequences, operation types, and thread / core identifier information. The Pinball files (PinBall_0, PinBall_1, ..., PinBall_N) correspond to the instruction execution traces of each processor core or each CCD.

[0119] The simulation input scheduler employs a pinball replay mechanism, polling each pinball file to obtain instructions to be executed. The simulation input scheduler checks pinball_0 to pinball_N sequentially in a preset order (e.g., fixed-priority polling, cyclic polling, or timestamp-based event-driven polling), reading one instruction from the currently ready pinball file.

[0120] The output ports of the simulation input scheduler are connected to the corresponding L1 cache interfaces of each core, for example... Figures 3-5 L1I_0, L1D_0, L1I_N, and L1D_N. After reading the instruction from a Pinball file, the simulation input scheduler provides the address sequence to the corresponding core cache interface through the core application programming interface, based on the core identifier and operation type in the instruction.

[0121] Leveraging the serial iterative execution characteristics of the aforementioned cache functional model, the simulation input scheduler actively reads only one instruction from the currently selected pinball file at a time and sends it to the corresponding core cache interface via the core application programming interface. After this instruction completes all functional processing within the cache functional model (including cache hit detection at each level, consistency state updates, and monitoring transaction generation), the simulation input scheduler initiates another polling to read the next instruction from the pinball file. This process repeats until all trajectory data in all pinball files has been replayed, thus achieving full simulation of the instruction sequence.

[0122] Since the simulation input scheduler actively polls for input based on the Pinball Replay mechanism, it does not require external clock driving and strict clock synchronization between core trajectories, thus further simplifying the construction of the verification environment in multi-core and multi-CCD scenarios and ensuring the consistency of the serial execution mechanism.

[0123] Figure 9 This diagram illustrates the execution flow of an instruction in a cache functional model according to an embodiment of the present disclosure. After receiving an instruction (memory access transaction request), the L1D, the first-level data cache of the CCD's core X, performs address resolution and tag comparison. If the request hits L1D, L1D processes the request based on the request type and the consistency status of the current cache line, including returning the target data and determining, according to the cache consistency protocol, whether to initiate a query request or a query invalidation request to the L1I, the first-level instruction cache within the core X. After L1I returns a response based on the query request, L1D and L1I update their respective consistency statuses based on the response results.

[0124] If the request misses L1D, L1D forwards the request to the private second-level cache PL2 of core X. PL2 performs a hit check. If a hit occurs, it processes the request based on the request type and consistency status, and determines whether a query or invalidation request needs to be sent to L1I. If a miss occurs, the request is forwarded to the last-level cache LLC. LLC determines, based on the request type and consistency status, whether a listener request or invalidation request needs to be sent to the PL2 of other cores within this CCD, such as core Y, to check whether other cores hold a valid copy of the cache line.

[0125] If the request involves cross-CCD consistency interaction, the LLC or HIF SNT sends a listening request to the HIF SNT of other CCDs through an interface function call. The caches at all levels of other CCDs then perform the query and return the listening response.

[0126] Throughout the entire request processing process, every cache module accessed (including L1D, L1I, PL2, LLC, and all levels of cache across CCDs) provides corresponding feedback and modifies its own consistency state based on the request type, the state transition rules of the cache consistency protocol, and the received query / listening response.

[0127] Figure 10 A block diagram of a cache verification apparatus according to an embodiment of the present disclosure is shown. Figure 10As shown, the cache verification device 1000 includes a modeling module 1010 and a verification module 1030. The modeling module 1010 performs electronic system-level ESL functional modeling on the cache structure to be verified, obtaining a cache functional model. This cache functional model is a non-timing functional model, processing instructions without simulating clock cycle-level timing behavior. The verification module 1030 uses the cache functional model to verify the cache coherence protocol.

[0128] In one possible implementation, the verification module 1030 is used to serially iteratively execute a sequence of instructions using the cache functional model; and to verify the cache coherence protocol based on the running state of the cache functional model during the execution of the instruction sequence.

[0129] In one possible implementation, the cache function model reads only one instruction from the instruction sequence at a time, and actively reads the next instruction after the instruction is executed, repeating this process until the entire instruction sequence is executed.

[0130] In one possible implementation, the verification module 1030 is used to verify that the cache coherence protocol has a functional defect if at least one of the following anomalies is detected during the execution of the instruction sequence: inconsistent data read by each core from the same physical address; cache line state transitions violate the state machine specifications of the coherence protocol; and the listener response type does not conform to the protocol specifications.

[0131] In one possible implementation, the cache verification device 1000 further includes a control module (not shown) for outputting a cache miss index based on the cache functional model as an auxiliary parameter for verifying the performance of the cache.

[0132] In one possible implementation, the control module is configured to: divide the instruction sequence into multiple segments; during the execution of the instruction sequence, record the hit / miss status of each request in each segment on the cache level of the cache functional model; after all instructions in the sequence have been executed, calculate the cache miss index of each cache level based on the number of miss requests in each segment on the cache level, the total number of requests in each segment, the weight of each segment, and the total weight; and output the cache miss index of each cache level as the auxiliary parameter.

[0133] In one possible implementation, the control module is configured to: divide the number of missed requests for each segment by the total number of requests to obtain a first quotient; divide the weight of each segment by the total weight to obtain a second quotient; calculate the product of the first quotient and the second quotient for each segment, and calculate the sum of the products of each segment as the cache miss index for each level of cache.

[0134] In one possible implementation, whenever a cache miss occurs and a replacement needs to be performed, the cache path corresponding to the head of the linked list is selected as a replacement candidate row, wherein the head of the linked list corresponds to the least recently used cache path in the cache group.

[0135] In one possible implementation, the architecture parameters of the cache function model are configured by reading a configuration file to change the cache structure corresponding to the cache function model.

[0136] In one possible implementation, the architecture parameters include at least one of the following: the number of cache groups, the number of cache paths, the number of cores, the number of active cores, the number of cache groups, the number of cache paths and operating modes of the listener table, and the number of core complex die CCDs.

[0137] In one possible implementation, the cache functional model has one or more core complex dies, each core complex die includes N cores, each core includes a level 1 cache, each level 1 cache includes an instruction cache, the N cores share a level 3 cache, and the lower level of the level 3 cache is provided with an interconnect listening function module.

[0138] In one possible implementation, each core also includes a second-level cache, with each first-level cache sharing a second-level cache.

[0139] In one possible implementation, each level 1 cache also includes a data cache, and the instruction cache and data cache of each level 1 cache share a level 2 cache.

[0140] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0141] This disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the above-described cache verification method.

[0142] This disclosure also provides a non-volatile computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the steps of the above-described cache verification method.

[0143] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of the above-described cache verification method.

[0144] Figure 11 This is a block diagram illustrating an apparatus 1100 for cache verification according to an exemplary embodiment. For example, apparatus 1100 may be provided as a server. (Refer to...) Figure 11 The apparatus 1100 includes a processing component 1122, which further includes one or more processors, and memory resources represented by memory 1132 for storing instructions, such as application programs, that can be executed by the processing component 1122. The application programs stored in memory 1132 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 1122 is configured to execute instructions to perform the aforementioned cache verification method.

[0145] Device 1100 may also include a power supply component 1126 configured to perform power management of device 1100, a wired or wireless network interface 1150 configured to connect device 1100 to a network, and an input / output interface 1158 (I / O interface). Device 1100 can operate on an operating system, such as Windows Server, stored in memory 1132. TM macOS X TM Unix TM Linux TM FreeBSD TM Or similar.

[0146] In an exemplary embodiment, a non-volatile computer-readable storage medium is also provided, such as a memory 1132 including computer program instructions, which can be executed by the processing component 1122 of the device 1100 to complete the cache verification method described above.

[0147] Computer-readable storage media can be tangible devices capable of holding and storing programs / instructions used by instruction execution devices. Computer-readable storage media can be, for example—but not limited to—electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination of the foregoing. The computer-readable storage media used herein are not to be construed as transient signals themselves, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through waveguides or other transmission media (e.g., light pulses through fiber optic cables), or electrical signals transmitted through wires.

[0148] The computer program (or computer-readable program instructions) described herein can be downloaded from a computer-readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them to the computer-readable storage medium in the respective computing / processing device.

[0149] The computer program (or computer program instructions) used to perform the operations of this disclosure may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or may be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuitry, such as programmable logic circuitry, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), is personalized by utilizing state information from the computer-readable program instructions to implement various aspects of this disclosure.

[0150] Various aspects of this disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0151] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart and / or block diagram. These computer-readable program instructions can also be stored in a computer-readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the computer-readable medium storing the instructions comprises an article of manufacture that includes instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart and / or block diagram.

[0152] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0153] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of an instruction containing one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0154] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A cache verification method, characterized in that, include: Electronic system-level ESL functional modeling is performed on the cache structure to be verified to obtain a cache functional model. The cache functional model is a non-timing functional model that processes instructions without simulating clock cycle-level timing behavior. The cache coherence protocol was validated using the aforementioned cache functionality model.

2. The cache verification method according to claim 1, characterized in that, The cache coherence protocol is validated using the aforementioned cache functionality model, including: The cache function model is used to serially iteratively execute instruction sequences; The cache coherence protocol is verified based on the operating state of the cache function model during the execution of the instruction sequence.

3. The cache verification method according to claim 2, characterized in that, The cache function model reads only one instruction from the instruction sequence at a time, and actively reads the next instruction after the instruction is executed, repeating this process until the entire instruction sequence is executed.

4. The cache verification method according to claim 2, characterized in that, Based on the operational state of the cache functional model during the execution of the instruction sequence, the cache coherence protocol is verified, including: If at least one of the following anomalies is detected during the execution of the instruction sequence, it is verified that the cache consistency protocol has a functional defect: inconsistent data read by each core from the same physical address; cache line state transitions violate the consistency protocol state machine specifications; and the listener response type does not conform to the protocol specifications.

5. The cache verification method according to claim 1, characterized in that, Also includes: The cache miss index is output by the cache functional model as an auxiliary parameter to verify the performance of the cache.

6. The cache verification method according to claim 5, characterized in that, The cache miss index output by the aforementioned cache functional model serves as an auxiliary parameter for verifying the performance of the cache, including: Divide the instruction sequence into multiple segments; During the execution of the instruction sequence, for each level of cache in the cache function model, the hit / miss status of each request in each segment on that level of cache is recorded one by one; After all the instructions in the sequence have been executed, for each level of cache, the cache miss index is calculated based on the number of miss requests for each segment in that level of cache, the total number of requests for each segment, the weight of each segment, and the total weight. Output the cache miss index of each level of cache as the auxiliary parameter.

7. The cache verification method according to claim 6, characterized in that, Based on the number of cache misses for each segment in that cache level, the total number of requests for each segment, the weight of each segment, and the total weight, the cache miss metrics for each cache level are calculated, including: Divide the number of missed requests for each segment by the total number of requests to obtain the first quotient; Divide the weight of each segment by the total weight to obtain the second quotient; Calculate the product of the first and second quotients of each segment, and use the sum of the products of each segment as the cache miss index for each level of cache.

8. The cache verification method according to any one of claims 1 to 7, characterized in that, Whenever a cache miss occurs and a replacement is required, the cache path corresponding to the head of the linked list is selected as the replacement candidate row. The head of the linked list corresponds to the least recently used cache path in the cache group.

9. The cache verification method according to any one of claims 1 to 7, characterized in that, The architecture parameters of the cache function model are configured by reading the configuration file, thereby changing the cache structure corresponding to the cache function model.

10. The cache verification method according to claim 9, characterized in that, The architecture parameters include at least one of the following: the number of cache groups, the number of cache paths, the number of cores, the number of active cores, the number of cache groups, the number of cache paths and operating modes of the listener table, and the number of core complex die CCDs.

11. The cache verification method according to any one of claims 1 to 7, characterized in that, The cache functional model has one or more core complex dies, each core complex die includes N cores, each core includes a level 1 cache, each level 1 cache includes an instruction cache, the N cores share a level 3 cache, and the lower level of the level 3 cache is provided with an interconnect listening function module.

12. The cache verification method according to claim 11, characterized in that, Each core also includes a secondary cache, and each primary cache shares a secondary cache.

13. The cache verification method according to claim 12, characterized in that, Each level 1 cache also includes a data cache, and the instruction cache and data cache of each level 1 cache share a level 2 cache.

14. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the steps of the cache verification method according to any one of claims 1 to 13.

15. A non-volatile computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the cache verification method according to any one of claims 1 to 13.

16. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the cache verification method according to any one of claims 1 to 13.

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