An adaptive fractal memory management method for a memory-computing integrated embedded system

Abstract

The application discloses a kind of self-adapting fractal memory management methods for memory-computing integrated embedded system, comprising: by parsing the computing semantic primitive in memory allocation request, generate the memory object with the memory-computing affinity label carried;The memory-computing potential field of physical storage array is constructed, the memory object is abstracted as particle and diffusion-competition dynamics equation is solved, and self-organizing layout decision is realized;When local computing potential intensity exceeds phase transition critical threshold, execute fluctuation reconfiguration from storage mode to computing mode and update computing topology addressing mapping;While periodically collecting storage unit wear data and feeding back to potential field, realize zero additional cost adaptive wear leveling by potential penalty.The application drives storage and computing dynamic cooperation with unified model, improves the resource utilization and hardware life of memory-computing integrated embedded system.

Description

Technical Field

[0001] This invention relates to the field of embedded system memory management technology, and in particular to an adaptive fractal memory management method for in-memory computing embedded systems. Background Technology

[0002] Memory management technology in embedded systems has long evolved around the core issue of dynamic allocation and reclamation of limited physical resources. From the static memory pools initially used in real-time operating system kernels to the widely deployed buddy system allocators, Slab allocators, and the TLSF algorithm for real-time applications, these classic solutions share a common technical premise: they all treat physical memory units as homogeneous resources with only a single "data container" attribute. The memory address space is flat, and storage and computation have clear physical boundaries at the hardware level. The manager's entire responsibility is limited to maintaining free blocks, responding to allocation requests, handling fragmentation, and performing reclamation and merging. This technical paradigm has effectively supported various embedded applications for decades, but its fundamental limitation lies in its inability to perceive and manage the extended dimension of "what else can memory units do besides storing data."

[0003] In recent years, with the explosive growth of IoT terminal intelligence and edge AI inference demands, in-memory computing architectures based on novel non-volatile storage media (such as Resistive Random Access Memory (ReRAM) and Magnetic Random Access Memory (STT-MRAM)) have gradually moved from the laboratory to chip-level implementation. The disruptive feature of this type of hardware is that the same physical storage crossbar array can be dynamically configured into two distinct operating modes at runtime. In storage mode, the array connects to a data buffer via row / column decoders, functioning as a conventional high-density non-volatile random access memory. In computing mode, the internal crossbar connections are reconfigured: the row terminals connect to a digital-to-analog converter to apply input voltage, and the column terminals connect to a transimpedance amplifier and an analog-to-digital converter to acquire output current. This allows the use of Kirchhoff's current law to directly perform matrix-vector multiplication—the core computational primitive in AI inference—in the analog domain. Thus, the same set of physical storage units is endowed with "in-memory duality": the "identity" of a physical memory is no longer a fixed attribute during manufacturing, but a dynamic variable that can theoretically flow and switch between the two modes as needed.

[0004] However, existing memory management technologies are fundamentally mismatched with this new hardware paradigm. Traditional methods such as buddy systems and slab allocators completely assume that storage and computation are physically separated, and therefore cannot make any decision on whether a region should currently be used for storage or computation. Even in the initial exploration of software support for in-memory computing hardware, most existing work simplifies the problem to static partitioning, that is, during initialization, a portion of the array is permanently or semi-permanently designated as a computation area, and another portion as a storage area, managed by two separate sets of management logic. This static partitioning completely eliminates the potential for dynamic reconfigurability of the hardware. A few more advanced studies have attempted to introduce dynamic switching, but their decision-making is usually limited to simple request queue length or operator type judgments, lacking a unified underlying management model that can simultaneously balance multiple antagonistic factors such as "storage layout efficiency," "computation topology optimality," "data affinity," and "hardware durability" at runtime. Most importantly, existing methods cannot simultaneously treat a single data object as both "data that needs storage space" and "an operator that will become part of the computational logic" and process them as a unified whole at the moment of memory allocation and layout.

[0005] In summary, with in-memory computing duality hardware becoming a visible technological trend, there is a gap in the current field of embedded memory management that urgently needs to be filled: the lack of a new management method that can fundamentally treat the in-memory computing identity of memory units as dynamically manageable variables and drive the collaborative adaptation of storage layout and computing topology through a unified model. Summary of the Invention

[0006] The purpose of this invention is to provide an adaptive fractal memory management method for in-memory computing embedded systems, in order to solve at least some of the problems existing in the prior art.

[0007] Technical solution: An adaptive fractal memory management method for in-memory computing embedded systems, comprising the following steps:

[0008] Based on the computational semantic primitives carried in the memory allocation requests initiated by the application, memory-computation affinity analysis is performed on each request to generate memory objects carrying memory-computation affinity tags and estimated lifecycles.

[0009] Construct a computing potential energy field for a physical storage array, and determine the target layout position of the memory objects in the array by solving the diffusion-competition dynamics equations between memory objects in the computing potential energy field;

[0010] When the computational potential intensity of the target layout region exceeds the preset storage-computation phase transition critical threshold, a fluctuation reconfiguration from storage mode to computation mode is performed on the region, and the computation topology addressing mapping is updated.

[0011] Wear data of the storage unit is periodically collected and fed back to the storage potential energy field to achieve adaptive equilibrium of wear perception through the diffusion-competition dynamic equation.

[0012] According to a further improvement of the present invention, generating a memory object carrying a memory affinity tag and an estimated lifespan includes:

[0013] Collect computational semantic primitive data attached to memory allocation requests initiated by the application;

[0014] The computational semantic primitive data is subjected to memory-computation affinity analysis to obtain the memory-computation affinity tag and estimated lifecycle of the request;

[0015] The memory affinity tag, along with the estimated lifecycle, the requested virtual address, and the size, are encapsulated to construct the memory object.

[0016] According to a further improvement of the present invention, determining the target layout position of the memory object in the array includes:

[0017] Collect current mode status data, historical access frequency data, and wear cycle count data of each basic unit of the physical storage array;

[0018] The collected mode state data, access frequency data, and wear cycle count data are normalized and weighted to calculate the global memory potential energy function value of the array, thereby generating a memory potential energy map.

[0019] The memory objects to be laid out and the existing memory objects in the array are all abstracted as particles. Based on their respective memory affinity labels and data dependencies, the memory affinity forces between the particles are calculated.

[0020] Using the memory potential energy map as the external potential field and the memory affinity force as the internal interaction, the multi-particle Langevin dynamics equations, including the memory object to be laid out, are solved. Through a preset number of iterative relaxations, the energy minimum equilibrium position of the memory object in the potential field is determined.

[0021] The energy minimum equilibrium position is mapped to the target tile address in the physical array, which is used as the target layout position.

[0022] According to a further improvement of the present invention, updating the computational topology addressing mapping includes:

[0023] Collect calculated potential intensity data within the target layout area, wherein the calculated potential intensity data is the integral value within the area;

[0024] The calculated potential intensity data is compared with a preset storage-computation phase transition critical threshold.

[0025] When it is determined that the calculated potential intensity data exceeds the critical threshold of the storage-computation phase transition, a bus freeze command is sent to the target tile to stop the data transmission and computation pipeline of that tile, while keeping the other tiles in the array working normally, thus completing the wavefront freezing.

[0026] For the frozen target tile, write a mode switching sequence to its control register to control the internal cross switch to switch from the state connected to the storage buffer to the state connected to the analog computing peripheral circuit, so that the target tile switches from the storage mode to the computing mode in place, while keeping the original stored data unchanged, thus completing the state transition.

[0027] Based on the mode switching result, the system's memory mapping table is updated, and the original linear address space mapping relationship is reconstructed into a computational topology addressing mapping from logical addresses to physical computing unit row and column channels.

[0028] According to a further improvement of the present invention, the wave reconfiguration further includes a wavefront propagation step: after the target tile completes the mode switching, the potential energy change is propagated to the neighboring tiles in the form of a wavefront based on the potential energy value automatically updated at its boundary due to the sudden change in mode state, driving the particles in the neighboring storage area to diffuse outward, thereby expanding the continuous space of the computing area.

[0029] According to a further improvement of the present invention, wear-sensing adaptive equilibrium is achieved through the diffusion-competition kinetic equation, including:

[0030] The number of SET / RESET operations is periodically collected from the endurance monitoring circuit of each physical storage cell;

[0031] The count data is normalized to obtain the real-time wear normalized value for each unit;

[0032] The wear normalization value is used as a penalty term and substituted into the storage potential energy function to recalculate the potential energy value, so as to increase the potential energy of the high wear area.

[0033] When solving the diffusion-competition dynamics equations for subsequent memory objects, all particles will automatically avoid regions with increased potential energy, allowing memory objects with high write frequencies to be placed in low-wear regions.

[0034] Beneficial effects: By constructing a storage computing potential energy field and utilizing diffusion-competition dynamics to achieve self-organized layout of memory objects, this invention dynamically coordinates storage and computing mode switching, data layout optimization, and wear leveling with zero additional overhead within a unified framework, thereby improving the resource utilization and hardware lifespan of the in-memory computing embedded system. Attached Figure Description

[0035] Figure 1 This is a flowchart of the overall solution of the present invention.

[0036] Figure 2 This is a flowchart illustrating the process of generating a memory object carrying a storage affinity tag and an estimated lifespan, as described in this invention.

[0037] Figure 3 This is a flowchart illustrating how the present invention determines the distribution of target layout positions of memory objects in an array.

[0038] Figure 4 This is a flowchart of the updated computational topology addressing mapping of the present invention.

[0039] Figure 5 This is a flowchart of the adaptive equilibrium of wear sensing achieved by the present invention through diffusion-competition dynamics equations. Detailed Implementation

[0040] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0041] like Figures 1-5 As shown, this embodiment describes in detail the data processing flow of an adaptive fractal memory management method for in-memory computing embedded systems, specifically including:

[0042] Step S1: Based on the computational semantic primitives carried in the memory allocation requests initiated by the application, perform memory-computation affinity analysis on each request and generate memory objects carrying memory-computation affinity tags and estimated lifecycles.

[0043] The core problem addressed by this solution—the dynamic management of storage and computing modes in in-memory computing hardware—begins with a deep analysis and attribute reshaping of upper-layer application memory requests. In traditional methods, all memory allocation requests are merely abstracted as needs for contiguous storage space of a specific size; this solution, however, upgrades these requests into memory objects carrying computational intent.

[0044] S1-1: Collect computational semantic primitive data attached to the memory allocation request initiated by the application.

[0045] Specifically, when software running on an embedded system, such as a neural network inference runtime, initiates a memory allocation request, its calling interface has been extended to include a "computational semantic primitive" field. In this embodiment, this primitive is not a simple data type marker, but rather structured data describing the type of computation to be performed in this memory region. For example, a request to allocate memory for the weight matrix of a fully connected layer would include primitives containing rich semantic information such as "operator type: matrix-vector multiplication (GEMM)," "data role: non-volatile weights," and "expected access mode: high-concurrency read." The task of this step is to intercept and parse these primitives, providing the initial basis for subsequent affinity quantification.

[0046] S1-2: Perform memory-computation affinity analysis on the computational semantic primitive data to obtain the memory-computation affinity label and estimated lifecycle of the request.

[0047] In this embodiment, this analysis is performed by a lightweight affinity analyzer, which maps complex semantic primitives to two key numerical attributes through a pre-defined lookup operation or a lightweight classifier. The first attribute is the memory-computation affinity label α, whose value range is normalized to the interval [0.0, 1.0]. The closer α is to 1.0, the more suitable the data is to be placed in a memory array in a computational mode and directly participate in in-memory computation to achieve maximum energy efficiency; conversely, an α of 0.0 indicates that this is a standard variable buffer that only needs to be stored. In a preferred embodiment, the weight matrix in the previous example, because it will be repeatedly used in matrix multiplication calculations, will have its α value directly marked by the analyzer as 0.95 or higher. At the same time, the second attribute, the estimated lifetime τ, is also calculated, which predicts the approximate time span from allocation to release of the data block, for example, in milliseconds, based on prior knowledge of operator execution latency or runtime scheduling information.

[0048] S1-3: Encapsulate the memory affinity tag, estimated lifecycle, requested virtual address, and size to construct the memory object. Based on the numerical attributes obtained in the preceding steps, this step reconstructs the traditional "memory allocation request" into a higher-level, self-describing entity, namely, the "memory object" (m-object). In this embodiment, the data structure of the m-object not only includes the requested virtual address and required space size, but also embeds an α tag and a τ value in its header. This encapsulation operation marks a key shift from traditional memory management centered on "space" to resource management centered on "data intent and characteristics." Each basic unit subsequently handed over to the memory manager for scheduling is no longer a passive data block waiting to be placed, but an active object carrying its own memory attributes and capable of actively influencing layout decisions.

[0049] Step S2: Construct the computing potential energy field of the physical storage array, and determine the target layout position of the memory objects in the array by solving the diffusion-competition dynamics equations between memory objects in the computing potential energy field.

[0050] This solution abandons the deterministic search logic of "finding a sufficiently large free partition" and instead constructs a unified physical field model, allowing memory objects to self-organize and emerge with an optimal layout through simulated physical dynamics processes within this field.

[0051] S2-1: Collect current mode status data, historical access frequency data, and wear cycle count data of each basic unit of the physical storage array.

[0052] In this embodiment, the physical storage array, such as a crossbar switch array composed of resistive random access memory (ReRAM), is abstracted as a two-dimensional grid. For each independently addressable or controllable storage cell (or a coarser-grained storage "pixel") in this grid, the underlying microcontroller or hardware monitoring module managing its operating state continuously collects three types of data. The first is the mode state C(x,y), which is a continuous value between [0,1], indicating whether the region is currently configured as a pure storage mode (0), a pure computing mode (1), or a transitional state between the two. The second is the historical access frequency, which records the number of times the cell is read or written per unit time. The third is the wear cycle count, which is continuously recorded by a non-resettable hardware counter, showing the total number of SET / RESET operations experienced by the cell. These data together constitute the raw input characterizing the current state and health of the physical array.

[0053] S2-2: Normalize and weight the collected mode state data, access frequency data, and wear cycle count data to calculate the global memory potential energy function value of the array, thereby generating the memory potential energy map.

[0054] Furthermore, the aforementioned heterogeneous raw data is transformed into dimensionless values ​​using a preset normalization formula. Subsequently, a storage potential energy field controller performs a weighted synthesis of these normalized values. In a typical implementation, the storage potential energy function is defined as Ψ(x,y) = λc * C(x,y) + λs * (1 - C(x,y)) + Ω(x,y) + W(x,y). Here, λc and λs are system-level global policy parameters. When the workload is biased towards AI inference, λc is dynamically increased to reduce the potential energy of the computing region and attract more objects. Ω(x,y) represents the local spatial density potential, which is proportional to the density of memory objects in the surrounding neighborhood of that point, and its function is to prevent excessive spatial congestion. W(x,y) is the wear normalization penalty term. All calculations are completed within each control cycle, ultimately generating a potential energy scalar field corresponding to each point of the physical array, namely the memory potential energy map. It is like a topographic map in the real world, where the "valleys" represent the current optimal layout candidate positions.

[0055] S2-3: Abstract the memory objects to be laid out and the existing memory objects in the array into particles, and calculate the memory affinity force between the particles based on their respective memory affinity labels and data dependencies.

[0056] In a preferred embodiment, the memory potential map constructs the external environment, while this step defines the internal behavioral rules between particles. Each memory object in this model is assigned a charged "particle" identity, its charge determined by its α value. Objects with high affinity (α close to 1) exhibit a mutual attraction with objects also possessing high computational affinity, tending to cluster together to form computational clusters. Conversely, storage objects with an affinity of 0 exhibit a repulsive force with computational objects of high α, naturally "squeezing" the storage objects out of computational hotspots. Furthermore, data dependencies are also mapped as another kind of attraction; for example, a feature map object and its corresponding convolution kernel object, if having a direct consumer-production dependency in the computational pipeline, will have an exceptionally strong attraction, ensuring they are physically adjacent to each other to minimize data transport overhead.

[0057] S2-4: Using the memory potential energy map as the external potential field and the memory affinity force as the internal interaction, solve the multi-particle Langevin dynamics equations that include the memory object to be laid out. Through a preset number of iterative relaxations, determine the energy minimum equilibrium position of the memory object in the potential field.

[0058] In this embodiment, after placing the newly allocated m-object particle into the aforementioned potential field model, the particle will experience the "slope" (external force) from the potential energy diagram and the attraction / repulsion (internal force) from other particles. Its motion behavior is described by a simplified, discretized Langevin equation. In a specific microcontroller execution process, this is not a real physical simulation, but a set of computationally inefficient numerical iterations. In each iteration, the resultant force vector acting on the current particle is calculated, and its virtual position is updated accordingly. The equation typically also includes a damping term and a small random noise term; the former ensures that the particle eventually converges to a certain equilibrium point, while the latter helps the particle escape local pseudo-minimums. After dozens of iterations of relaxation, the particle's position will stabilize at a minimum point on the potential energy diagram, which is the logically optimal habitat for the memory object under all current constraints.

[0059] S2-5: Map the energy minimum equilibrium position to the target tile address in the physical array, as the target layout position.

[0060] Finally, after completing the dynamics solution, the memory manager directly converts the final converged two-dimensional logical coordinates into the starting address and boundary of a rectangular region (i.e., the target tile) on the physical array through a linear mapping function. This address is the final physical location of this memory allocation request. The entire process does not require traversing any free lists; the layout decision is automatically completed simply by solving the dynamics equations.

[0061] Step S3: When the computational potential intensity of the target layout region exceeds the preset storage-computation phase transition critical threshold, perform a fluctuation reconfiguration from storage mode to computation mode for the region and update the computational topology addressing mapping.

[0062] When memory objects continuously gather within a region under the influence of the storage-computing potential energy field, a localized and controllable physical mode transition—a "phase transition" from storage mode to computing mode—is eventually triggered. This process is a key manifestation of the dynamic hardware reconfiguration capability of this solution.

[0063] S3-1: Collect the calculated potential intensity data within the target layout area, wherein the calculated potential intensity data is the integral value within the area.

[0064] Specifically, a reconfiguration monitoring logic continuously scans each tile. For the target layout area determined in step S2, or any array partition already occupied by objects, this logic calculates a scalar index called "computational potential strength" on a cycle-by-cycle basis. This strength is defined as the spatial integral of the product of the storage potential function Ψ and the mode state C over the target area. This integral value is not a simple density statistic; it comprehensively reflects the degree of clustering of computationally compatible objects in the area (represented by Ψ) and the current computing hardware tendency in the area (represented by C). Therefore, it is a composite index that simultaneously considers "demand" and "current situation".

[0065] S3-2: Compare the calculated potential intensity data with a preset storage-computation phase transition critical threshold.

[0066] In an optional implementation, the storage-computation phase transition critical threshold Θ_c is a constant calibrated during the chip design phase using search algorithms such as simulated annealing, and can be adjusted by the operating system at runtime. Once the real-time intensity value acquired in step S3-1 exceeds this critical point Θ_c, it indicates that the "computational demand" of this region has exceeded the minimum energy allowed by the "storage container," and the system is thermodynamically in a metastable state. It must release potential energy through a phase transition to enter a new steady state.

[0067] S3-3: When it is determined that the calculated potential intensity data exceeds the critical threshold of storage-computation phase transition, a bus freeze command is sent to the target tile to stop the data transmission and computation pipeline of that tile, while keeping the other tiles in the array working normally, thus completing the wavefront freezing.

[0068] At the moment the threshold is crossed, a hardware state machine is immediately triggered. First, the reconfiguration controller precisely selects the rectangular subarray (tile) that triggered the phase transition condition and issues a highest-priority "freeze" command to its local bus arbiter. Within nanoseconds, direct memory access (DMA) operations and any scheduled in-memory computation pipelines within that tile are safely suspended and paused. The atomicity and extremely short latency of this operation ensure that the phase transition process does not result in data races or inconsistencies. A highly innovative aspect is that this freeze operation is completely isolated; all other tiles in the array and their running computation tasks and input / output operations are unaffected and continue operating at full speed, guaranteeing the real-time performance and throughput of the entire system.

[0069] S3-4: For the frozen target tile, write a mode switching sequence to its control register to control the internal cross switch to switch from the state connected to the storage buffer to the state connected to the analog computing peripheral circuit, so that the target tile switches from the storage mode to the computing mode in place, while keeping the original stored data unchanged, thus completing the state transition.

[0070] After successful wavefront establishment, the crucial mode transition is executed. Each tile in the array has a dedicated set of control registers. The controller writes a specific "magic sequence" into these registers, which directly affects the cross-switch network within the tile. In storage mode, the cross-switch connects the row / column decoders of storage cells (such as ReRAM cells) to the SRAM data buffer and address bus. After writing the mode-switching sequence, the cross-switch connections are physically reconfigured. The row decoders are then connected to the input of an external digital-to-analog converter (DAC) to apply the analog voltage required for computation; the column decoders are switched to the outputs of the transimpedance amplifier and analog-to-digital converter (ADC) to acquire the current of the computation result. In a preferred embodiment, this switching action occurs at the pure circuit level, taking on the order of microseconds. Most importantly, since the data is stored in the storage cells as resistors, the switching connection does not change the resistance of the storage cells themselves. Therefore, before and after the mode switch, the data stored in the tile is completely and in situ preserved without any time-consuming data migration.

[0071] S3-5: Based on the mode switching result, update the system's memory mapping table and reconstruct the original linear address space mapping relationship into a computational topology addressing mapping from logical addresses to physical computing unit row and column channels.

[0072] After the hardware mode transition is complete, the management model must be updated accordingly. The memory mapping table in the Memory Management Unit (MMU), responsible for address translation, will be updated in real time. Before the phase transition, the physical address of the tile was mapped to a contiguous logical address space, just like a regular RAM block. After the phase transition, this contiguous address space mapping is replaced by a "computation topology address" mapping. Here, the high-order bits of a logical address may represent the row index of a matrix, and the low-order bits represent the column index. These two indices no longer correspond to decoder addresses but directly to the numbers of the DAC input channel and ADC sampling channel. This step allows upper-level in-memory computation library functions to program this phase-transformed array directly and naturally, just like accessing a regular two-dimensional array, achieving computation scheduling with zero software overhead.

[0073] S3-6: After the target tile completes the mode switch, based on the potential energy value automatically updated at its boundary due to the sudden change in mode state, the potential energy change is propagated to neighboring tiles in the form of a wavefront, driving the particles in the neighboring storage area to diffuse outward, thus expanding the continuous space of the computing area.

[0074] As a further optimization, the effects of phase transitions are not limited to the tile's interior. When a tile abruptly changes from a storage state (C close to 0) to a computation state (C=1), the storage potential energy Ψ at its boundary experiences a sharp drop. This change, like a pebble thrown into calm water, propagates a potential energy gradient in the form of a wavefront to neighboring tiles still in storage mode, according to the equation. This newly generated gradient exerts a strong repulsive force on the storage particles in neighboring tiles, accelerating their diffusion to more distant regions. Thus, a local phase transition can trigger a chain of beneficial self-organizing reactions, automatically cleaning and converging a continuous computational region for computational tasks, achieving on-demand dynamic expansion of computational resources. When the computational density decreases and the intensity falls below another low threshold, the reverse phase transition process is triggered, the relevant region reverts to storage mode, and the data is stored according to the latest layout; the entire process is reversible and bidirectional.

[0075] Step S4: Periodically collect wear data of the storage unit and feed the wear data back to the storage potential energy field to achieve adaptive equilibrium of wear perception through the diffusion-competition dynamic equation.

[0076] Another important feature of this invention is that it elevates wear management from a passive, reactive approach to a proactive, pre-emptive avoidance strategy integrated with layout decisions. Wear leveling is no longer a separate module that adds extra write amplification overhead, but rather an intrinsic property of the storage potential field.

[0077] S4-1: Periodically collect the count data of the number of SET / RESET operations from the endurance monitoring circuit of each physical memory cell.

[0078] For non-volatile memory, each cell has a physical lifetime limit, i.e., a limited number of write tolerances. In the improved hardware design according to this embodiment, each memory cell or block is equipped with a durability monitoring circuit, the core of which is a reliable hardware counter that increments with each SET or RESET operation. A low-priority background task periodically, for example, every few seconds, iterates through all these counters, collecting their raw count values ​​into a temporary data buffer. This data is the only true physical basis for calculating the wear resistance potential.

[0079] S4-2: Normalize the count data to obtain the real-time wear normalized value for each unit.

[0080] After data collection, all raw counts are normalized. In a preferred embodiment, the denominator of the normalization is not a uniform value for all cells, but a preset "target lifespan" or a dynamically maintained global average wear value for the array, determined based on the device's physical characteristics and design margins. The output of this step is a three-dimensional map that perfectly matches the physical array dimensions, with values ​​continuously varying between [0, 1]—a real-time wear normalization value map. A value of 0 represents a nearly brand-new cell, while a value closer to 1 indicates that the cell is nearing the end of its lifespan.

[0081] S4-3: The wear normalization value is used as a penalty term and substituted into the stored potential energy function to recalculate the potential energy value, so as to increase the potential energy of the high wear area.

[0082] After obtaining the latest W(x,y) map, the in-memory potential energy field controller will directly incorporate this value as a penalty term when updating the potential energy function Ψ(x,y) in the next control cycle, replacing the old wear parameter. This update operation is smooth and non-disruptive. As a certain region is continuously written to and worn, its W value will gradually approach 1 from 0, which will directly cause the in-memory potential energy value Ψ of that point and the surrounding area to be gradually but continuously increased. A continuously rising potential energy is directly equivalent to the formation of a continuously rising "hill" in the physical model.

[0083] S4-4: When the diffusion-competition dynamics equations are solved for subsequent memory objects, all particles will automatically avoid regions with increased potential energy, allowing memory objects with high write frequencies to be placed in low-wear regions.

[0084] In the layout decision-making process described in step S2, all memory objects, acting as "particles," are inherently driven by the tendency to slide towards areas of lower potential energy. Therefore, when certain regions become high-potential-energy "hills" due to wear, all particles naturally avoid these regions without any additional decision-making overhead during their diffusion-competitive random walk or gradient descent pathfinding process. Furthermore, objects with high write frequency characteristics, due to their dynamic behavior (frequent creation and destruction, equivalent to frequent rearrangement of particles in the potential field), are most sensitive to this potential energy barrier and will be most effectively diverted to the least worn "plains" or "basins." This mechanism does not add additional data migration operations; instead, it uses the global state of physical wear as a primary constraint when allocating a location for each new write, achieving fine-grained adaptive wear leveling with zero additional write amplification overhead, coexisting with storage allocation decisions.

[0085] This invention breaks through the fundamental paradigm of traditional memory management, which treats storage units as static data containers. By constructing a unified storage-computation potential energy field model, it enables the storage allocation and computation scheduling problems, which originally required two separate sets of logic, to be solved simultaneously within the same mathematical framework, eliminating optimization conflicts between storage layout and computation topology. In its specific implementation, this solution abandons the deterministic search mechanism of traversing the free list. Instead, it utilizes diffusion-competition dynamics equations to allow memory objects to self-organize and emerge globally optimal layout configurations based on their storage-computation affinity labels, data dependencies, and the real-time wear status of the array. This physics-like spontaneous process naturally adapts to load statistics and has extremely low computational complexity, making it particularly suitable for resource-intensive deeply embedded environments. Simultaneously, this solution elevates wear leveling from a traditional post-hoc migration strategy to an intrinsic attribute coexisting with allocation decisions. By continuously injecting a normalized wear penalty term into the potential energy function, high-wear areas automatically generate a repulsive effect on subsequent writes, achieving fine-grained lifetime management while completely avoiding any additional data migration overhead. The naturally triggered fluctuation reconfiguration mechanism accompanying the layout further ensures that the switching between storage and computing modes propagates in an orderly manner, much like a phase transition. This guarantees the predictability of real-time tasks and enables the dynamic expansion and contraction of computing resources on demand. In summary, this invention, with a highly self-consistent original method, simultaneously overcomes the key technical challenges in four dimensions—cooperative optimization, adaptive layout, dynamic reconfiguration, and lifespan management—of in-memory computing embedded systems, providing solid underlying management support for the high energy efficiency and long-term reliable operation of intelligent edge devices.

[0086] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and all such equivalent transformations fall within the protection scope of the present invention.

Claims

1. An adaptive fractal memory management method for in-memory computing embedded systems, characterized in that, include: Based on the computational semantic primitives carried in the memory allocation requests initiated by the application, memory-computation affinity analysis is performed on each request to generate memory objects carrying memory-computation affinity tags and estimated lifecycles. Construct a computing potential energy field for a physical storage array, and determine the target layout position of the memory objects in the array by solving the diffusion-competition dynamics equations between memory objects in the computing potential energy field; When the computational potential intensity of the target layout region exceeds the preset storage-computation phase transition critical threshold, a fluctuation reconfiguration from storage mode to computation mode is performed on the region, and the computation topology addressing mapping is updated. Wear data of the storage unit is periodically collected and fed back to the storage potential energy field to achieve adaptive equilibrium of wear perception through the diffusion-competition dynamic equation.

2. The method according to claim 1, characterized in that, Generate memory objects carrying memory affinity tags and estimated lifecycles, including: Collect computational semantic primitive data attached to memory allocation requests initiated by the application; The computational semantic primitive data is subjected to memory-computation affinity analysis to obtain the memory-computation affinity tag and estimated lifecycle of the request; The memory affinity tag, along with the estimated lifecycle, the requested virtual address, and the size, are encapsulated to construct the memory object.

3. The method according to claim 1, characterized in that, Determining the target layout location of the memory object in the array includes: Collect current mode status data, historical access frequency data, and wear cycle count data of each basic unit of the physical storage array; The collected mode state data, access frequency data, and wear cycle count data are normalized and weighted to calculate the global memory potential energy function value of the array, thereby generating a memory potential energy map. The memory objects to be laid out and the existing memory objects in the array are all abstracted as particles. Based on their respective memory affinity labels and data dependencies, the memory affinity forces between the particles are calculated. Using the memory potential energy map as the external potential field and the memory affinity force as the internal interaction, the multi-particle Langevin dynamics equations, including the memory object to be laid out, are solved. Through a preset number of iterative relaxations, the energy minimum equilibrium position of the memory object in the potential field is determined. The energy minimum equilibrium position is mapped to the target tile address in the physical array, which is used as the target layout position.

4. The method according to claim 1, characterized in that, Update the computation topology addressing mapping, including: Collect calculated potential intensity data within the target layout area, wherein the calculated potential intensity data is the integral value within the area; The calculated potential intensity data is compared with a preset storage-computation phase transition critical threshold. When it is determined that the calculated potential intensity data exceeds the critical threshold of the storage-computation phase transition, a bus freeze command is sent to the target tile to stop the data transmission and computation pipeline of that tile, while keeping the other tiles in the array working normally, thus completing the wavefront freezing. For the frozen target tile, write a mode switching sequence to its control register to control the internal cross switch to switch from the state connected to the storage buffer to the state connected to the analog computing peripheral circuit, so that the target tile switches from the storage mode to the computing mode in place, while keeping the original stored data unchanged, thus completing the state transition. Based on the mode switching result, the system's memory mapping table is updated, and the original linear address space mapping relationship is reconstructed into a computational topology addressing mapping from logical addresses to physical computing unit row and column channels.

5. The method according to claim 4, characterized in that, The wave reconfiguration also includes a wavefront propagation step: After the target tile completes the mode switch, based on the potential energy value automatically updated at its boundary due to the sudden change in mode state, the potential energy change is propagated to neighboring tiles in the form of a wavefront, driving the particles in the neighboring storage area to diffuse outward, thus expanding the continuous space of the computing area.

6. The method according to claim 1, characterized in that, Achieving adaptive equilibrium for wear sensing through the diffusion-competition dynamics equation includes: The number of SET / RESET operations is periodically collected from the endurance monitoring circuit of each physical storage cell; The count data is normalized to obtain the real-time wear normalized value for each unit; The wear normalization value is used as a penalty term and substituted into the storage potential energy function to recalculate the potential energy value, so as to increase the potential energy of the high wear area. When the diffusion-competition dynamics equations are solved for subsequent memory objects, all particles will automatically avoid regions with increased potential energy, allowing memory objects with high write frequencies to be placed in low-wear regions.

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