Spaceborne dual DDR data cache system and method based on time interleaving and dynamic reconstruction

Abstract

The application discloses a kind of based on timing stagger and dynamic reconstruction's satellite-borne double DDR data cache system and method, belong to spaceflight electronics technology and computer storage technology field.System includes: storage execution unit, the storage execution unit includes two independent DDR storage channels, for providing data cache physical medium;Data scheduling unit, the data scheduling unit is connected to the storage execution unit, for managing the routing and scheduling of internal data flow of system, the data scheduling unit supports the reconfigurable configuration of two working states of normal mode and degraded mode;Intelligent control unit, intelligent control unit is connected to the storage execution unit and the data scheduling unit respectively, for generating two phase difference adjustable clock signals to control the read-write operation of timing stagger of the two DDR storage channels, and real-time monitoring is carried out to system health state, and according to monitoring result, the reconfigurable switching of working mode is carried out to the data scheduling unit.

Description

Technical Field

[0001] This invention belongs to the fields of aerospace electronic technology and computer storage technology, and relates to a spaceborne dual DDR data cache system and method based on timing interleaving and dynamic reconstruction. Background Technology

[0002] With the rapid development of space missions such as high-resolution Earth observation, satellite internet, and deep space exploration, the data acquisition rate and total volume of spaceborne payloads are growing exponentially. Taking high-resolution optical remote sensing satellites as an example, the raw data rates generated by their multispectral and panchromatic cameras can reach several Gbps or even tens of Gbps; synthetic aperture radar (SAR) payloads also generate massive amounts of real-time data in strip or scan modes. Meanwhile, with the accelerated deployment of artificial intelligence technology in the spaceborne field, payload data needs to undergo preprocessing tasks such as target detection, image segmentation, and compression encoding in orbit. This places far higher demands on the read / write bandwidth and real-time response capabilities of data caching systems than on traditional storage systems. DDR SDRAM, due to its high bandwidth density, large capacity, and relatively mature aerospace application experience, has become the preferred physical medium for data caching in current spaceborne solid-state storage systems. Existing DDR cache architectures in spaceborne storage systems typically adopt the following two design schemes: The first type is the single DDR cache architecture. In this architecture, the system is configured with only a single DDR storage channel, and all read and write operations share the same data bus and control interface. This architecture can basically meet the requirements in simple sequential recording or sequential playback scenarios. However, when the system needs to perform data recording and playback tasks simultaneously, the single DDR architecture, limited by the exclusivity of the physical interface, must switch between read and write operations in a time-sharing manner, resulting in a sharp drop in effective bandwidth. Furthermore, the single DDR architecture lacks redundancy; if the storage channel malfunctions due to single-event effects or cumulative radiation damage, the entire data caching service will be completely interrupted, making it difficult to meet the requirements of long-life, high-reliability aerospace missions. The second type is the conventional dual DDR cache architecture. To compensate for the shortcomings of the single DDR architecture, some existing solutions use two DDR storage channels to build the cache system. However, existing dual DDR solutions typically employ a macroscopic ping-pong operation: at the same time, the two DDR controllers are configured to operate in the same direction—that is, both channels simultaneously perform write operations, or both channels simultaneously perform read operations. While this synchronous working mode simplifies the control logic design, it is essentially still a half-duplex working mode. In typical hybrid service scenarios on spaceborne systems (e.g., recording payload data while simultaneously replaying historical data to the data transmission channel), the read ports are completely idle during simultaneous write operations by both DDR memory modules, and vice versa. This results in the system's effective bandwidth only reaching about half of its theoretical peak. As spaceborne data rates continue to rise, this bandwidth bottleneck has become a key factor restricting system performance. In particular, for image preprocessing algorithms that require continuous data streams, such as convolution and fast Fourier transform, the discontinuous memory access mode further exacerbates the "memory wall" problem.

[0003] In terms of adaptability to the space environment, existing DDR caching solutions also have significant shortcomings. In the space environment, radiation effects such as single-event upsets, single-event function interruptions, and total dose effects caused by high-energy particles and cosmic rays can lead to DDR controller state machine jump errors, DDR memory cell data flips, and PLL lockouts. Existing solutions mostly employ cold backup or software-level reset recovery strategies to handle these faults. That is, when an anomaly is detected in the primary channel, the onboard computer controls the system to switch to the backup channel or performs a reset operation through software instructions. This type of solution has two inherent drawbacks: First, the interruption response and mode switching time involving software is usually in the milliseconds or even seconds. During this period, the data caching service is interrupted, which may lead to the loss of high-speed payload data. Second, the cold backup channel is in an inactive state for a long time before the switch, and its own health status cannot be verified in real time, posing a risk of "backup but not working". There is no system-level solution in the existing technology that deeply integrates high-bandwidth data scheduling with hardware-level intelligent fault tolerance mechanisms.

[0004] In summary, existing spaceborne DDR caching solutions have significant technical shortcomings in both bandwidth utilization and space environment reliability, making it difficult to meet the high-performance, high-reliability, and high-availability requirements of data caching systems for future high-resolution Earth observation, on-orbit artificial intelligence computing, and deep space exploration missions. Summary of the Invention

[0005] The purpose of this invention is to solve the technical problems of existing spaceborne DDR caching schemes having significant shortcomings in both bandwidth utilization and space environment reliability, and to provide a spaceborne dual DDR data caching system and method based on timing interleaving and dynamic reconstruction.

[0006] To achieve the above objectives, the present invention employs the following technical solution: In a first aspect, the present invention discloses a spaceborne dual DDR data cache system based on timing interleaving and dynamic reconstruction, comprising: The storage execution unit includes two independent DDR storage channels for providing physical media for data caching; A data scheduling unit, connected to the storage execution unit, is used to manage the routing and scheduling of data flows within the system. The data scheduling unit supports reconfigurable configuration of two working states: normal mode and degraded mode. The intelligent control unit is connected to the storage execution unit and the data scheduling unit respectively. It is used to generate two clock signals with adjustable phase difference to control the two DDR storage channels to perform time-interleaved read and write operations, monitor the system health status in real time, and control the data scheduling unit to perform reconfigurable switching of working modes according to the monitoring results.

[0007] Further improvements are made in the following aspects: The data scheduling unit includes: A reconfigurable write data distributor has its input connected to an external data source and its output connected to the write ports of the two DDR storage channels respectively. In normal mode, the reconfigurable write data distributor routes the input data to one of the DDR storage channels, and in degraded mode, it broadcasts the input data to both DDR storage channels simultaneously. The reconfigurable read data synthesizer has its input terminals connected to the read ports of the two DDR memory channels respectively, and its output terminal connected to an external data receiver. In normal mode, the reconfigurable read data synthesizer selects one channel from the two DDR memory channels for data output, and in degraded mode, it only selects the healthy channel for data output.

[0008] The intelligent control unit includes: The radiation-resistant clock generation module is used to generate two clock signals with the same frequency and a dynamically adjustable phase difference, which are then supplied to the two DDR memory channels respectively. A control state machine module is connected to the radiation-resistant clock generation module and the two DDR memory channels, and is used to control the two DDR memory channels to alternately perform burst read operations and burst write operations according to the clock signal; The health status monitoring module is connected to the data path and control path of the two DDR storage channels respectively, and is used to collect system health status parameters in real time. The dynamic reconfiguration controller is connected to the health status monitoring module, the control state machine module, and the data scheduling unit, respectively, and is used to determine the fault based on the health status parameters and control the data scheduling unit to perform working mode switching.

[0009] The phase difference between the two clock signals output by the radiation-resistant clock generation module can be dynamically adjusted within the range of 120° to 180°. Under stable radiation environment conditions, the phase difference is configured to 180° to achieve complete parallelization of the read and write operations of the two DDR memory channels. When the radiation environment deteriorates, the phase difference is automatically reduced to 120° to increase the timing fault tolerance margin. The control state machine module adopts a triple-modular redundancy architecture, including three physically isolated state machine instances and a majority voting circuit connected to the output of the three state machine instances. The three state machine instances use Gray code encoding to ensure that only one bit of the codeword changes during state transition. The control state machine module defines a first operating state and a second operating state. In the first operating state, the first DDR memory channel performs a burst write operation and the second DDR memory channel performs a burst read operation. In the second operating state, the first DDR memory channel performs a burst read operation and the second DDR memory channel performs a burst write operation. The switching between the first operating state and the second operating state is triggered by the DDR burst transmission completion signal.

[0010] The health status monitoring module includes: The CRC check submodule is connected to the data write path and data read path of the two DDR storage channels. It is used to calculate the CRC check code before data writing and compare the check code when data is read to achieve end-to-end data integrity verification. The command timeout detection submodule is connected to the control command path of the two DDR memory channels and is used to set an independent timeout counter for each DDR access command and monitor the command response time. The environmental monitoring submodule is used to collect radiation dose rate and temperature environmental parameters.

[0011] After receiving a switching request from the health status monitoring module, the dynamic reconfiguration controller waits for the current DDR burst transmission cycle to end naturally and triggers a mode switch at the burst transmission boundary. The mode switch includes two levels: control system reconfiguration and data path reconfiguration. The control system reconfiguration switches the operating modes of the two DDR controllers from a time-interleaved mode to a synchronous operation mode. The data path reconfiguration configures the write data allocator of the data scheduling unit to broadcast mode and the read data synthesizer to a health channel selection mode. The entire switching process is completed autonomously by the hardware logic within 10 microseconds.

[0012] The dynamic reconfiguration controller dynamically adjusts the DDR refresh frequency based on the radiation dose rate collected in real time by the health status monitoring module, and / or optimizes the IO drive intensity and timing parameters based on temperature parameters, and / or reconfigures the system into a single-channel degrade mode under extreme fault conditions.

[0013] The intelligent control unit controls the two DDR storage channels to operate in a time-interleaved manner under normal working mode to achieve full-duplex communication at the system level; when a channel failure is detected, the system is controlled to switch to synchronous redundancy mode, where the two DDR storage channels perform write operations synchronously, and read operations are performed only from the healthy channel.

[0014] Each DDR memory channel of the memory execution unit integrates an ECC check circuit to detect and correct memory errors caused by single-event effects; the data scheduling unit also includes an anti-SEU asynchronous FIFO, which adopts Gray code addressing mechanism and triple-modular redundancy hardening design and is set on the cross-clock domain data path; the two DDR memory channels are aerospace-grade DDR3 SDRAM or DDR4 SDRAM.

[0015] Secondly, this invention discloses a spaceborne dual DDR data caching method based on timing interleaving and dynamic reconstruction, and based on the above-mentioned spaceborne dual DDR data caching system based on timing interleaving and dynamic reconstruction, comprising: System initialization: After the system is powered on, clock locking, DDR memory initialization and redundant logic self-test are completed, and the system enters normal working mode; Interleaved read / write: In the normal operating mode, two clock signals with adjustable phase difference are used to drive the two DDR storage channels respectively, and control the two DDR storage channels to alternately perform burst read and burst write operations. When one DDR storage channel performs a burst write operation, the other DDR storage channel performs a burst read operation, and the read and write roles are switched in the next burst transmission cycle to achieve full-duplex data caching at the system level. Real-time health status monitoring: During the execution of the time-interleaved read and write steps, the data integrity and command response status of the two DDR storage channels are monitored in parallel in real time, and system health status parameters are collected; Fault determination and mode switching: Based on the health status parameters, determine whether a channel fault has occurred. When a fault is determined to have occurred in a certain DDR storage channel, wait for the current DDR burst transmission cycle to end naturally, and trigger mode switching at the burst transmission boundary to switch the system from time-interleaved mode to synchronous redundancy mode. Synchronous Redundancy Operation: In the synchronous redundancy mode, the two DDR storage channels perform write operations synchronously, and read operations are only performed from the healthy channel, maintaining the continuous operation of the data caching service.

[0016] Compared with the prior art, the present invention has the following beneficial effects: This invention discloses a spaceborne dual-DDR data caching system based on time-interleaved and dynamic reconfiguration. Firstly, this invention fundamentally solves the bandwidth bottleneck problem of traditional dual-DDR caching systems in mixed read / write scenarios through a three-level collaborative architecture of a storage execution unit, a data scheduling unit, and an intelligent control unit. In traditional dual-DDR architectures, the two controllers execute operations in the same direction synchronously, resulting in alternating idle read / write ports and an effective bandwidth utilization rate of less than 50%. This invention generates two clock signals with adjustable phase difference through the intelligent control unit, driving the two DDR storage channels to perform time-interleaved read / write operations. This ensures that while one DDR storage channel performs a burst write operation, the other channel performs a burst read operation, and the read / write roles are switched in the next burst cycle. This breaks through the inherent limitation of "half-duplex" at the system level, achieving true full-duplex data caching and bringing the effective bandwidth utilization rate close to the theoretical peak. Secondly, this invention establishes a hardware implementation mechanism for dynamically balancing performance and reliability through the reconfigurable normal and degraded modes of the data scheduling unit, combined with the real-time health monitoring and mode switching decisions of the intelligent control unit. The intelligent control unit continuously collects health parameters such as data integrity and command response status during system operation. Once a channel fault is detected, it immediately controls the data scheduling unit to complete a reconfigurable switch of the working mode. This architecture design allows the system to fully leverage the bandwidth advantage of staggered timing under normal operating conditions, and automatically switch to synchronous redundancy mode to ensure data security under fault conditions, achieving a leap from "optimal single performance" to "optimal performance throughout the entire lifecycle." Furthermore, through the integrated design of the intelligent control unit, this invention achieves fully hardware-based autonomous execution of fault detection, judgment, and mode switching, significantly improving the system's service continuity. All monitoring and switching logic is completed at the hardware level without relying on software intervention. When the health status monitoring module determines that a certain DDR storage channel has failed, the dynamic reconfiguration controller triggers a mode switch at the current burst transmission boundary, and the entire process is completed within microseconds. Compared with traditional solutions that rely on software response and cold backup switching, this invention shortens the fault tolerance response time by more than three orders of magnitude, ensuring that data caching services are not interrupted and data is not lost when a single point of failure occurs. Finally, this invention generates two clock signals with adjustable phase difference through an intelligent control unit, enabling the system to dynamically adjust the timing interleaving degree according to environmental conditions. Under stable radiation environments, a large phase difference configuration achieves fully parallel read and write operations, maximizing bandwidth utilization. When a deterioration in the radiation environment is detected, the phase difference is automatically adjusted to increase timing fault tolerance margin. This finds a dynamic optimal balance between performance and reliability, avoiding excessive conservatism leading to performance waste in favorable environments and excessive aggressiveness leading to reliability degradation in harsh environments, significantly improving the system's overall performance under various orbital conditions.

[0017] This invention discloses a spaceborne dual DDR data caching method based on time-interleaved and dynamic reconstruction. Firstly, by implementing time-interleaved read / write steps, this invention achieves complete parallelization of read / write operations at the burst transmission granularity of the two DDR storage channels at the method level, fundamentally breaking through the bandwidth bottleneck of traditional dual DDR caching methods. In traditional methods, two controllers execute operations in the same direction synchronously, with read / write ports alternately idle, resulting in an effective bandwidth utilization of less than 50%. This invention drives the two DDR storage channels separately using two clock signals with adjustable phase difference, controlling the two channels to alternately execute burst read and burst write operations. While one channel is performing a burst write, the other channel is performing a burst read, and they switch roles in the next burst cycle, ensuring the system is in an effective read / write concurrent state throughout the entire time period, achieving true full-duplex data caching with an effective bandwidth utilization approaching the theoretical peak. Secondly, through the coordinated operation of real-time health status monitoring, fault diagnosis, and mode switching steps, this invention constructs a complete "monitoring-determination-switching-recovery" fault-tolerant method flow, enabling the system to have closed-loop processing capabilities from fault detection to autonomous recovery. During the interleaved read / write operation, the system continuously monitors the data integrity and command response status of the two DDR storage channels in parallel. If a failure is detected in one channel, a mode switch is immediately triggered at the boundary where the current burst transmission cycle naturally ends, switching the system from interleaved mode to synchronous redundancy mode. This process design, which deeply couples health monitoring and mode switching in terms of timing, allows the system to prioritize bandwidth performance under normal operating conditions and automatically switch to redundancy mode to ensure data security in the event of a failure, achieving a dynamic balance between performance and reliability throughout the system's lifecycle. Furthermore, by selecting the mode switch timing at the burst transmission boundary and combining it with the subsequent synchronous redundancy operation steps, this invention ensures the integrity of data transmission and the continuity of service throughout the fault tolerance process. The switching operation is triggered only after the current burst transmission cycle naturally ends, avoiding data loss or corruption caused by forced switching during data transmission. After the switch is completed, the system immediately enters synchronous redundancy operation mode, with both DDR storage channels synchronously performing write operations and read operations only performed from the healthy channel, ensuring uninterrupted operation of the data caching service. The entire process chain of "fault determination - boundary waiting - mode switching - redundant operation" is completed autonomously at the hardware level without relying on software intervention. The switching latency is within microseconds, which reduces the fault tolerance response time by more than three orders of magnitude compared to traditional fault tolerance methods that rely on software responses. Finally, this invention enables the entire method to incorporate reliability design from the startup stage and adaptively adjust during operation by executing clock locking and redundant logic self-checks in the system initialization step, and by dynamically adjusting the phase difference according to environmental conditions in the timing interleaved read / write step.After power-on, the system first performs clock locking and redundant logic self-tests to ensure that each module is in a known state and fully functional before entering normal operating mode. During staggered read / write operations, the phase difference between the two clock signals can be dynamically adjusted within a certain range. When the radiation environment is stable, a large phase difference configuration is used to achieve maximum bandwidth utilization; when the radiation environment deteriorates, the phase difference is automatically reduced to increase timing fault tolerance margin. This end-to-end adaptive design, from initialization to normal operation, allows the method to flexibly and dynamically adapt to changes in the space radiation environment, avoiding performance waste or insufficient reliability of fixed configurations in complex environments. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is an architecture diagram of a spaceborne dual DDR data cache system based on timing interleaving and dynamic reconstruction in an embodiment of the present invention; Figure 2 This is a timing diagram of timing interleaving and mode switching waveforms in a spaceborne dual DDR data cache system based on timing interleaving and dynamic reconstruction in an embodiment of the present invention; Figure 3 This is a flowchart illustrating the interaction between the control state machine and health monitoring in a spaceborne dual DDR data cache system based on time-series interleaving and dynamic reconstruction, as described in an embodiment of the present invention. Figure 4 This is a detailed timing diagram of seamless switching in a spaceborne dual DDR data cache system based on timing interleaving and dynamic reconstruction, according to an embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0023] In the description of the embodiments of the present invention, it should be noted that if terms such as "upper," "lower," "horizontal," or "inner" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, terms such as "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] Furthermore, the use of the term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0025] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0026] The present invention will now be described in further detail with reference to the accompanying drawings: See Figure 1 This invention discloses a spaceborne dual DDR data cache system based on timing interleaving and dynamic reconstruction, comprising: The storage execution unit includes two independent DDR storage channels for providing physical media for data caching; A data scheduling unit, connected to the storage execution unit, is used for routing and scheduling data flows within the system. The data scheduling unit supports reconfigurable configurations for both normal and degraded operating modes. The data scheduling unit includes: A reconfigurable write data distributor has its input connected to an external data source and its output connected to the write ports of the two DDR storage channels respectively. In normal mode, the reconfigurable write data distributor routes the input data to one of the DDR storage channels, and in degraded mode, it broadcasts the input data to both DDR storage channels simultaneously. The reconfigurable read data synthesizer has its input terminals connected to the read ports of the two DDR memory channels respectively, and its output terminal connected to an external data receiver. In normal mode, the reconfigurable read data synthesizer selects one channel from the two DDR memory channels for data output, and in degraded mode, it only selects the healthy channel for data output.

[0027] An intelligent control unit, connected to both the storage execution unit and the data scheduling unit, generates two clock signals with adjustable phase difference to control the two DDR storage channels to perform time-interleaved read and write operations. It also monitors the system health status in real time and controls the data scheduling unit to reconfigure its operating mode based on the monitoring results. The intelligent control unit controls the two DDR storage channels to operate in a time-interleaved manner under normal operating conditions, achieving full-duplex communication at the system level. When a channel fault is detected, it controls the system to switch to synchronous redundancy mode, where both DDR storage channels synchronously perform write operations, and read operations are performed only from the healthy channel. Each DDR storage channel in the storage execution unit integrates an ECC check circuit to detect and correct storage errors caused by single-event effects. The data scheduling unit also includes an anti-SEU asynchronous FIFO, which employs Gray code addressing and a triple-modulus redundancy hardening design and is located on the cross-clock domain data path. The two DDR storage channels are aerospace-grade DDR3 SDRAM or DDR4 SDRAM.

[0028] The intelligent control unit includes: The radiation-resistant clock generation module is used to generate two clock signals with the same frequency and a dynamically adjustable phase difference, which are then supplied to the two DDR memory channels respectively. A control state machine module is connected to the radiation-resistant clock generation module and the two DDR memory channels, and is used to control the two DDR memory channels to alternately perform burst read operations and burst write operations according to the clock signal; The health status monitoring module is connected to the data path and control path of the two DDR storage channels respectively, and is used to collect system health status parameters in real time. The dynamic reconfiguration controller is connected to the health status monitoring module, the control state machine module, and the data scheduling unit, respectively, and is used to determine the fault based on the health status parameters and control the data scheduling unit to perform working mode switching.

[0029] See Figure 2 The phase difference between the two clock signals output by the radiation-resistant clock generation module can be dynamically adjusted within the range of 120° to 180°; under stable radiation environment conditions, the phase difference is configured to 180° to achieve complete parallelization of the read and write operations of the two DDR memory channels; when a deterioration in the radiation environment is detected, the phase difference automatically decreases to 120° to increase timing fault tolerance margin; such as Figure 2 The diagram illustrates the system's operating timing and mode switching mechanism. It fully demonstrates the transition from the normal operating timing interleaved mode to the degraded synchronous redundancy mode: initially, the dual DDRs use a 180° phase difference clock to achieve full-duplex data transmission; during the fault detection phase, the health monitoring unit identifies channel anomalies and triggers switching conditions; critical switching occurs at the boundary of a sudden transmission event, ensuring uninterrupted data flow. The entire timing process reflects the seamless fault-tolerance technology at the hardware level.

[0030] The control state machine module adopts a triple-modular redundancy architecture, including three physically isolated state machine instances and a majority voting circuit connected to the output of the three state machine instances. The three state machine instances use Gray code encoding to ensure that only one bit of the codeword changes during state transition. The control state machine module defines a first operating state and a second operating state. In the first operating state, the first DDR memory channel performs a burst write operation and the second DDR memory channel performs a burst read operation. In the second operating state, the first DDR memory channel performs a burst read operation and the second DDR memory channel performs a burst write operation. The switching between the first operating state and the second operating state is triggered by the DDR burst transmission completion signal.

[0031] See Figure 3 The health status monitoring module includes: a CRC checksum submodule, connected to the data write and read paths of the two DDR storage channels, used to calculate the CRC checksum before data writing and compare the checksum during data reading to achieve end-to-end data integrity verification; a command timeout detection submodule, connected to the control command path of the two DDR storage channels, used to set an independent timeout counter for each DDR access command and monitor the command response time; and an environmental monitoring submodule, used to collect radiation dose rate and temperature environmental parameters. Figure 3 The diagram illustrates the interaction between the control state machine and the health monitoring system. The process begins with system initialization and self-test, implementing staggered timing control through a dual-state loop in normal mode, while the health monitoring unit performs real-time diagnostics in parallel. When a channel fault is detected, the system triggers a three-level switching mechanism based on sudden boundary conditions—clock synchronization, path reconstruction, and mode switching—ultimately entering a degraded operating mode while maintaining service continuity. This demonstrates a complete fault-tolerant lifecycle from fault detection to autonomous recovery.

[0032] See Figure 4 After receiving a switching request from the health status monitoring module, the dynamic reconfiguration controller waits for the current DDR burst transmission cycle to end naturally and triggers a mode switch at the burst transmission boundary. The mode switch includes two levels: control system reconfiguration and data path reconfiguration. The control system reconfiguration switches the operating modes of the two DDR controllers from interleaved timing mode to synchronous operation mode. The data path reconfiguration configures the write data allocator of the data scheduling unit to broadcast mode and the read data synthesizer to healthy channel selection mode. The entire switching process is completed autonomously by the hardware logic within 10 microseconds. Figure 4 The diagram illustrates the detailed timing relationships of the seamless switching process. The timing diagram details the relative timing of key events such as fault flag setting, burst termination pulse, and mode switching activation, with particular emphasis on the stable read / write data validity signal at the switching moment of clock cycle 16. This switching mechanism based on precise time synchronization ensures the continuity of data flow during mode transitions, achieving truly seamless fault-tolerant switching.

[0033] The dynamic reconfiguration controller dynamically adjusts the DDR refresh frequency based on the radiation dose rate collected in real time by the health status monitoring module, and / or optimizes the IO drive intensity and timing parameters based on temperature parameters, and / or reconfigures the system into a single-channel degraded mode under extreme fault conditions. Figure 1 As shown, the system adopts a three-level modular design: the intelligent data routing module is responsible for data flow scheduling and buffering; the core control module integrates radiation-resistant clock generation, TMR control state machine, health monitoring, and dynamic reconfiguration controller to realize system status monitoring and fault-tolerant decision-making; the bottom DDR storage unit contains dual-channel memory, supporting both timing interleaving and synchronous redundancy operating modes. The modules cooperate with each other through data flow, control flow, and status feedback signals to form a complete fault-tolerant storage system.

[0034] This invention discloses a spaceborne dual-DDR data caching system based on time-interleaved and dynamic reconfiguration. Firstly, this invention fundamentally solves the bandwidth bottleneck problem of traditional dual-DDR caching systems in mixed read / write scenarios through a three-level collaborative architecture of a storage execution unit, a data scheduling unit, and an intelligent control unit. In traditional dual-DDR architectures, the two controllers execute operations in the same direction synchronously, resulting in alternating idle read / write ports and an effective bandwidth utilization rate of less than 50%. This invention generates two clock signals with adjustable phase difference through the intelligent control unit, driving the two DDR storage channels to perform time-interleaved read / write operations. This ensures that while one DDR storage channel performs a burst write operation, the other channel performs a burst read operation, and the read / write roles are switched in the next burst cycle. This breaks through the inherent limitation of "half-duplex" at the system level, achieving true full-duplex data caching and bringing the effective bandwidth utilization rate close to the theoretical peak. Secondly, this invention establishes a hardware implementation mechanism for dynamically balancing performance and reliability through the reconfigurable normal and degraded modes of the data scheduling unit, combined with the real-time health monitoring and mode switching decisions of the intelligent control unit. The intelligent control unit continuously collects health parameters such as data integrity and command response status during system operation. Once a channel fault is detected, it immediately controls the data scheduling unit to complete a reconfigurable switch of the working mode. This architecture design allows the system to fully leverage the bandwidth advantage of staggered timing under normal operating conditions, and automatically switch to synchronous redundancy mode to ensure data security under fault conditions, achieving a leap from "optimal single performance" to "optimal performance throughout the entire lifecycle." Furthermore, through the integrated design of the intelligent control unit, this invention achieves fully hardware-based autonomous execution of fault detection, judgment, and mode switching, significantly improving the system's service continuity. All monitoring and switching logic is completed at the hardware level without relying on software intervention. When the health status monitoring module determines that a certain DDR storage channel has failed, the dynamic reconfiguration controller triggers a mode switch at the current burst transmission boundary, and the entire process is completed within microseconds. Compared with traditional solutions that rely on software response and cold backup switching, this invention shortens the fault tolerance response time by more than three orders of magnitude, ensuring that data caching services are not interrupted and data is not lost when a single point of failure occurs. Finally, this invention generates two clock signals with adjustable phase difference through an intelligent control unit, enabling the system to dynamically adjust the timing interleaving degree according to environmental conditions. Under stable radiation environments, a large phase difference configuration achieves fully parallel read and write operations, maximizing bandwidth utilization. When a deterioration in the radiation environment is detected, the phase difference is automatically adjusted to increase timing fault tolerance margin. This finds a dynamic optimal balance between performance and reliability, avoiding excessive conservatism leading to performance waste in favorable environments and excessive aggressiveness leading to reliability degradation in harsh environments, significantly improving the system's overall performance under various orbital conditions.

[0035] See Figure 2 , Figure 3and Figure 4 This invention also discloses a spaceborne dual DDR data caching method based on timing interleaving and dynamic reconstruction, which, based on the above-mentioned spaceborne dual DDR data caching system based on timing interleaving and dynamic reconstruction, includes: System initialization: After the system is powered on, clock locking, DDR memory initialization and redundant logic self-test are completed, and the system enters normal working mode; Interleaved read / write: In the normal operating mode, two clock signals with adjustable phase difference are used to drive the two DDR storage channels respectively, and control the two DDR storage channels to alternately perform burst read and burst write operations. When one DDR storage channel performs a burst write operation, the other DDR storage channel performs a burst read operation, and the read and write roles are switched in the next burst transmission cycle to achieve full-duplex data caching at the system level. Real-time health status monitoring: During the execution of the time-interleaved read and write steps, the data integrity and command response status of the two DDR storage channels are monitored in parallel in real time, and system health status parameters are collected; Fault determination and mode switching: Based on the health status parameters, determine whether a channel fault has occurred. When a fault is determined to have occurred in a certain DDR storage channel, wait for the current DDR burst transmission cycle to end naturally, and trigger mode switching at the burst transmission boundary to switch the system from time-interleaved mode to synchronous redundancy mode. Synchronous Redundancy Operation: In the synchronous redundancy mode, the two DDR storage channels perform write operations synchronously, and read operations are only performed from the healthy channel, maintaining the continuous operation of the data caching service.

[0036] This invention discloses a spaceborne dual DDR data caching method based on time-interleaved and dynamic reconstruction. Firstly, by implementing time-interleaved read / write steps, this invention achieves complete parallelization of read / write operations at the burst transmission granularity of the two DDR storage channels at the method level, fundamentally breaking through the bandwidth bottleneck of traditional dual DDR caching methods. In traditional methods, two controllers execute operations in the same direction synchronously, with read / write ports alternately idle, resulting in an effective bandwidth utilization of less than 50%. This invention drives the two DDR storage channels separately using two clock signals with adjustable phase difference, controlling the two channels to alternately execute burst read and burst write operations. While one channel is performing a burst write, the other channel is performing a burst read, and they switch roles in the next burst cycle, ensuring the system is in an effective read / write concurrent state throughout the entire time period, achieving true full-duplex data caching with an effective bandwidth utilization approaching the theoretical peak. Secondly, through the coordinated operation of real-time health status monitoring, fault diagnosis, and mode switching steps, this invention constructs a complete "monitoring-determination-switching-recovery" fault-tolerant method flow, enabling the system to have closed-loop processing capabilities from fault detection to autonomous recovery. During the interleaved read / write operation, the system continuously monitors the data integrity and command response status of the two DDR storage channels in parallel. If a failure is detected in one channel, a mode switch is immediately triggered at the boundary where the current burst transmission cycle naturally ends, switching the system from interleaved mode to synchronous redundancy mode. This process design, which deeply couples health monitoring and mode switching in terms of timing, allows the system to prioritize bandwidth performance under normal operating conditions and automatically switch to redundancy mode to ensure data security in the event of a failure, achieving a dynamic balance between performance and reliability throughout the system's lifecycle. Furthermore, by selecting the mode switch timing at the burst transmission boundary and combining it with the subsequent synchronous redundancy operation steps, this invention ensures the integrity of data transmission and the continuity of service throughout the fault tolerance process. The switching operation is triggered only after the current burst transmission cycle naturally ends, avoiding data loss or corruption caused by forced switching during data transmission. After the switch is completed, the system immediately enters synchronous redundancy operation mode, with both DDR storage channels synchronously performing write operations and read operations only performed from the healthy channel, ensuring uninterrupted operation of the data caching service. The entire process chain of "fault determination - boundary waiting - mode switching - redundant operation" is completed autonomously at the hardware level without relying on software intervention. The switching latency is within microseconds, which reduces the fault tolerance response time by more than three orders of magnitude compared to traditional fault tolerance methods that rely on software responses. Finally, this invention enables the entire method to incorporate reliability design from the startup stage and adaptively adjust during operation by executing clock locking and redundant logic self-checks in the system initialization step, and by dynamically adjusting the phase difference according to environmental conditions in the timing interleaved read / write step.After power-on, the system first performs clock locking and redundant logic self-tests to ensure that each module is in a known state and fully functional before entering normal operating mode. During staggered read / write operations, the phase difference between the two clock signals can be dynamically adjusted within a certain range. When the radiation environment is stable, a large phase difference configuration is used to achieve maximum bandwidth utilization; when the radiation environment deteriorates, the phase difference is automatically reduced to increase timing fault tolerance margin. This end-to-end adaptive design, from initialization to normal operation, allows the method to flexibly and dynamically adapt to changes in the space radiation environment, avoiding performance waste or insufficient reliability of fixed configurations in complex environments.

[0037] Example 1 This embodiment is implemented based on the Xilinx Virtex-7 series FPGA (model XC7VX690T) platform. This FPGA provides abundant programmable logic resources and a high-performance memory controller, laying the hardware foundation for building a highly reliable onboard data caching system. The system is equipped with two aerospace-grade DDR3 SDRAM chips manufactured by Shenzhen Guowei Electronics Co., Ltd., each with a capacity of 4Gb, which together constitute the system's physical cache medium.

[0038] In the implementation, the core timing and control modules were developed using the Vivado design suite. The clock generation unit utilizes the PLL IP core within the FPGA, outputting two 166MHz clock signals with a precisely configured 180-degree phase difference. The triple-modulus redundant control state machine is implemented using a hardware description language. The three state machine instances are distributed across different clock regions of the FPGA through layout constraints, ensuring physical isolation. The majority voter employs a real-time arbitration mechanism to make decisions on the outputs of the three instances. The health status monitoring unit is designed independently, with the CRC-32 checksum calculation completed before the data is written to DDR via the AXI4 interconnect architecture. The checksum and corresponding physical address are stored in protected distributed RAM.

[0039] After system startup, a strict initialization process is executed. Following FPGA configuration, PLL locking, DDR3 memory initialization, and redundant logic self-testing are performed sequentially. Upon successful initialization, the system enters a timing-interleaved full-duplex operating mode. Data from the onboard payload is input via a high-speed serial interface. When the health monitoring unit detects consecutive command response timeouts accompanied by CRC check errors on a DDR channel, it determines that the channel is faulty and immediately sends a switching request to the dynamic reconfiguration controller.

[0040] Upon receiving a request, the dynamic reconfiguration controller maintains the current data transmission, awaiting the completion of the ongoing burst operation. At the next burst boundary, the controller leverages the parallel processing capabilities of the Virtex-7 FPGA to complete all reconfiguration operations within four clock cycles: adjusting the clocks of the two DDR controllers to synchronous mode, switching the write data distributor to broadcast mode, and configuring the read data synthesizer to healthy channel strobe mode. The entire switching process is completed within 24 nanoseconds at a 166MHz clock speed, remaining completely transparent to the continuously transmitting data stream.

[0041] After entering synchronous redundancy mode, the system maintains full data caching functionality. All written data is simultaneously stored on both DDR channels, and read operations are performed only from the healthy channel. Simultaneously, the system reports fault diagnosis information, including error type, timestamp, and recovery actions, to the onboard main processor via the system bus.

[0042] This embodiment verifies the technical effectiveness through ground testing. Under normal operating timing interleaved mode, the system's measured bandwidth utilization reached 94.5%, a significant improvement over traditional solutions. In fault injection testing, the system completed fault-tolerant switching within 24 nanoseconds, and the continuously transmitted high-speed data stream remained undamaged during the switching process. Radiation environment simulation testing showed that the system maintained stable operation after accumulating a certain dose of radiation, demonstrating the effectiveness of the radiation-resistant design. This implementation fully demonstrates the practical value and technical advantages of this invention in a spaceborne environment.

[0043] This embodiment has the following specific effects: (1) Significant improvement in performance indicators: This invention achieves a fundamental breakthrough in bandwidth utilization through a time-interleaved architecture. In standard operating mode, the system can achieve a bandwidth utilization rate of nearly 100%, which is a fundamental improvement over the less than 50% of the traditional dual-DDR solution. Actual test data shows that, under the same hardware configuration, the effective data transmission rate is increased by more than 100%, which can meet the stringent requirements of spaceborne systems for high-speed data caching.

[0044] (2) Order-of-magnitude enhancement of system reliability: By constructing a multi-layered protection system at the device, circuit, and system levels, the system's radiation resistance is significantly enhanced. Specifically, the key control logic employing a triple-modular redundancy design improves single-event upset tolerance by two orders of magnitude; the integrated ECC-checked storage subsystem enables single-error correction and double-error detection; and the online diagnostic system can monitor and handle transient faults in real time. Reliability analysis shows that the system's mean time between failures (MTBF) is more than three times higher than traditional solutions, making it suitable for various orbital environments.

[0045] (3) Technical assurance of service continuity. A seamless switching mechanism based on hardware logic ensures the continuous availability of system services. This mechanism has the following technical characteristics: the switching latency is less than 10 microseconds, which is far superior to the millisecond latency of software control schemes; the switching timing selection based on burst transmission boundaries ensures the integrity of data transmission; the mode switching process is transparent to the system software and requires no intervention from upper-layer applications. Experimental verification shows that in single-point failure scenarios, the system can maintain a state of zero data loss and zero service interruption.

[0046] (4) Breakthrough progress in environmental adaptability. The system has achieved environmental adaptability through intelligent monitoring and dynamic reconfiguration: it supports dynamic adjustment of working parameters based on real-time radiation levels; it has the ability to predict faults and preventive maintenance based on historical data; it can automatically optimize system configuration for different orbital environments; this adaptive feature significantly reduces the system's dependence on ground operation and maintenance and enhances its on-orbit autonomous operation capability.

[0047] (5) Optimization of cost-effectiveness. The technical solution of this invention achieves cost optimization while ensuring system performance: the core technological innovation is mainly realized through FPGA logic design, reducing the dependence on aerospace-grade components throughout the system; the intelligent hardening scheme using commercial components significantly reduces hardware costs while ensuring reliability; the modular design concept supports flexible system configuration and rapid deployment. Cost analysis shows that, under the same performance indicators, the overall system cost is reduced by more than 40% compared to the traditional all-aerospace-grade solution.

[0048] In summary, through technological innovation and system optimization, this invention has achieved significant improvements in multiple dimensions such as performance, reliability, continuity, adaptability, and cost-effectiveness, providing an advanced technical solution for spaceborne data caching systems.

[0049] The working principle of this invention is as follows: This invention provides a highly reliable dual-DDR data caching system for spaceborne applications. The system employs a hierarchical and modular design, achieving a balance between high performance and high reliability through architectural innovation. The core of the system consists of three functionally coupled subsystems: a storage execution unit, a data scheduling unit, and an intelligent control unit.

[0050] The storage execution unit consists of two independent DDR storage channels. Each channel preferentially uses aerospace-grade or high-grade industrial-grade DDR3 / 4 SDRAM devices as the physical storage medium. To ensure data storage integrity, each storage channel integrates ECC or EDAC error correction circuitry, which can automatically detect and correct storage errors caused by single-event events.

[0051] The data scheduling unit is responsible for the management and scheduling of data flows within the system, employing a reconfigurable architecture. The reconfigurable write data allocator supports two operating modes: in normal mode, it implements a 2-to-1 data routing function; in degraded mode, it converts to a 1-to-2 data broadcast function. The reconfigurable read data synthesizer correspondingly supports two modes: in normal mode, it implements a 1-to-2 data selection function; in degraded mode, it converts to a healthy channel gating function. The anti-SEU asynchronous FIFO employs Gray code addressing and a triple-modulus redundancy hardening design to ensure the reliability of cross-clock domain data buffers. The intelligent control unit, serving as the system's control core, integrates multiple dedicated processing engines: the radiation-hardened phase generation unit, based on radiation-hardened PLL technology, provides two system clocks with the same frequency and precisely adjustable phase difference. The tri-modal redundant control state machine employs a physically isolated layout, coupled with majority voting circuitry, to ensure the fault tolerance of the control logic. The intelligent health status monitoring unit integrates multi-dimensional diagnostic functions such as CRC check, timeout detection, SEU counting, and radiation dose monitoring. The dynamic reconfiguration controller seamlessly switches operating modes and adaptively adjusts parameters based on system status. The AXI4 bus interface controller provides a standardized system interconnection interface.

[0052] The specific design is as follows: (1) Deep integration design of temporal staggered state machine and radiation-resistant state machine The core of this invention lies in the deep integration of timing optimization technology and reliability design at the architectural level. In terms of timing control, the system employs a configurable phase difference clock scheme. The phase generation module outputs two clock signals with the same frequency, and their phase difference can be dynamically adjusted within the range of 120° to 180°. Under stable radiation conditions, the system uses a 180° phase difference configuration to achieve complete parallelization of read and write operations on the two DDR channels, maximizing bandwidth utilization. When a deterioration in the radiation environment is detected, the system automatically reduces the phase difference to 120°, increasing the timing margin to improve the system's anti-interference capability.

[0053] In terms of control logic reliability, a triple-modal-redundant state machine architecture is adopted. Three identical state machine instances are physically isolated, significantly reducing the risk of common-mode failure. The state machine uses Gray code encoding to ensure that only one bit changes during state transitions, effectively preventing state machine failure caused by multiple bit flips. The state machine output is arbitrated via a majority voting circuit to guarantee the correctness of the control signals.

[0054] The state machine employs a deterministic scheduling mechanism, with state transitions strictly synchronized with the DDR burst transfer cycle. The system defines two basic operating states: State A (DDR_A performs a burst write operation, DDR_B performs a burst read operation) and State B (DDR_A performs a burst read operation, DDR_B performs a burst write operation). State transitions are triggered by the DDR burst transfer completion signal, ensuring the accuracy and predictability of the scheduling timing.

[0055] (2) Intelligent health status monitoring and predictive maintenance The system constructs a multi-dimensional health status monitoring system, realizing a shift from passive fault tolerance to proactive early warning. The online diagnostic system comprises three core modules: The CRC check module calculates the CRC-32 checksum before writing data to DDR and stores the mapping relationship between the checksum and the physical address in a protected BRAM. During data reading, the checksum is recalculated and compared, achieving end-to-end data integrity verification.

[0056] The command timeout detection module sets an independent timeout counter for each DDR access command and judges the interface status by monitoring the command response time.

[0057] The environmental monitoring module collects environmental parameters such as radiation dose rate and temperature through a dedicated interface, providing environmental context for system decision-making.

[0058] The predictive maintenance mechanism based on historical data establishes a channel reliability assessment model by analyzing the temporal distribution characteristics of SEU events. When the error count per unit time of a channel exceeds a dynamic threshold, the system triggers the maintenance process in advance, realizing the transformation from fault repair to fault prevention.

[0059] (3) Hardware-level autonomous seamless fault-tolerant switching mechanism The system implements hardware-level fault self-healing capabilities to ensure service continuity. Fault determination employs a multi-condition fusion decision-making mechanism. When the health monitoring unit detects persistent fault characteristics in a DDR channel or that the SEU frequency exceeds a safety threshold, it immediately sends a mode switching request to the dynamic reconfiguration controller. The switching process uses a non-interruptible scheme based on burst boundary triggering. After receiving the switching request, the dynamic reconfiguration controller waits for the current DDR burst transmission cycle to end naturally and completes the mode switching during the transmission gap. This natural boundary-based switching mechanism ensures that ongoing data transmission is not interrupted. The mode switching involves two levels: control system reconfiguration and data path reconfiguration. Control system reconfiguration changes the operating mode of the two DDR controllers from staggered to synchronous operation; data path reconfiguration configures the write data distributor to broadcast mode to achieve dual data writing; and configures the read data synthesizer to strobe mode, reading data only from the healthy channel. The entire switching process is completed autonomously by the hardware logic within 10µs, completely transparent to the system software and data processing flow.

[0060] (4) Adaptive parameter adjustment and dynamic reconstruction The system possesses adaptive dynamic reconfiguration capabilities, achieving an optimal balance between performance and reliability. The dynamic reconfiguration controller automatically adjusts the system configuration based on real-time environmental parameters. 1) Dynamically adjust the DDR refresh frequency according to the radiation dose rate, and increase the refresh rate in strong radiation environments to suppress error accumulation; 2) Optimize I / O drive strength and timing parameters based on temperature and environmental parameters to compensate for device performance drift; 3) In extreme failure scenarios, the system can be reconfigured into a single-channel degradation mode, ensuring the continued operation of basic functions by shutting down the faulty channel.

[0061] This adaptive dynamic reconfiguration mechanism enables the system to intelligently respond to dynamic changes in the space environment, significantly improving the reliability and lifespan of on-orbit services.

[0062] The specific objectives of this invention are explained below: (1) Breaking through performance bottlenecks and achieving maximum bandwidth utilization: Addressing the low bandwidth utilization caused by synchronous operation or macroscopic ping-pong operation in traditional dual-DDR architectures, the primary objective of this invention is to achieve a fundamental breakthrough at the micro-timing level through a burst-transmission-level timing interleaving and ping-pong fusion architecture. Furthermore, it aims to achieve complete parallelism and complementarity of read and write operations on the time axis through precise phase control. That is, when one DDR performs a burst write operation, the other DDR must be performing a burst read operation, and their roles will be swapped in the next cycle. This simultaneous write and put operation within each clock cycle fundamentally solves the bandwidth waste problem of traditional architectures, achieving full-duplex communication at the system level, thereby approaching theoretical bandwidth utilization and meeting the extreme data throughput requirements of high-speed spaceborne payloads.

[0063] (2) Constructing a deep defense system to enhance inherent environmental robustness: In response to threats to electronic systems from space irradiation environments such as single-event effects (SEU), single-event function interruptions (SEFI), and total dose effects (TID), and the shortcomings of existing radiation-resistant designs that are mostly limited to device selection or local redundancy, the second objective of this invention is to construct a multi-layered, collaborative radiation-resistant hardening system. The aim is to provide comprehensive deep protection for key components such as the core control unit (using TMR and majority voting), data path (using anti-SEU FIFO and cyclic redundancy check (CRC), storage interface (integrated ECC), and clock network (using radiation-resistant PLL), forming an organic defense whole, significantly improving the inherent robustness of the system in the space irradiation environment, enabling it to withstand long-term, cumulative radiation damage and random transient interference.

[0064] (3) Achieving hardware-level intelligent autonomous fault tolerance to ensure mission continuity: Addressing the pain points of slow response and service interruptions caused by switching processes in existing fault tolerance mechanisms, the third objective of this invention is to establish a hardware-level intelligent health monitoring and seamless fault-tolerant switching mechanism. This objective achieves rapid self-sensing, accurate self-diagnosis, and autonomous self-recovery of faults. Through online CRC verification, command timeout monitoring, and SEU event counting integrated into the hardware logic, the system status is monitored and diagnosed in real-time and continuously. When transient or permanent faults such as single-event effects are detected, seamless switching is triggered within microseconds by pure hardware logic at the natural boundary of the current data burst transmission completion, automatically transitioning from a high-performance "time-interleaved mode" to a highly reliable "synchronous redundancy mode." The ultimate goal is to ensure that data caching and forwarding services are not interrupted or lost in any form when any single point of failure occurs, thereby ensuring the absolute continuity of the aerospace mission.

[0065] (4) Introducing intelligent adaptability to pursue dynamic optimal balance: Addressing the limitations of existing systems with fixed operating modes and inability to adapt to complex and changing spatial environments, another objective of this invention is to introduce adaptive reconfiguration technology based on environmental perception. This transforms the system from a static, passive design into a dynamic, proactive intelligent system. Specifically, by real-time acquisition of environmental and health parameters such as radiation dose rate, chip temperature, and cell error rate, the system can dynamically adjust its operating mode and strategy. For example, in orbital regions with high radiation intensity, it automatically reduces the degree of timing interleaving to obtain a higher timing fault tolerance margin. Based on the SEU occurrence rate, it dynamically adjusts the memory refresh frequency or internal retry strategy. The ultimate goal is to enable the system to autonomously and dynamically find and maintain the optimal balance between performance and reliability in complex and changing spatial environments, extending effective service life and improving the intelligence and success rate of task completion.

[0066] In summary, through the above four progressively different objectives, this invention constructs a dual-DDR onboard data caching system, providing key underlying technical support for future high-performance, long-life, and highly autonomous spacecraft.

[0067] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A spaceborne dual-DDR data cache system based on time-interleaved and dynamic reconstruction, characterized in that, include: The storage execution unit includes two independent DDR storage channels for providing physical media for data caching; A data scheduling unit, connected to the storage execution unit, is used to manage the routing and scheduling of data flows within the system. The data scheduling unit supports reconfigurable configuration of two working states: normal mode and degraded mode. The intelligent control unit is connected to the storage execution unit and the data scheduling unit respectively. It is used to generate two clock signals with adjustable phase difference to control the two DDR storage channels to perform time-interleaved read and write operations, monitor the system health status in real time, and control the data scheduling unit to perform reconfigurable switching of working modes according to the monitoring results.

2. The spaceborne dual DDR data cache system based on timing interleaving and dynamic reconstruction according to claim 1, characterized in that, The data scheduling unit includes: A reconfigurable write data distributor has its input connected to an external data source and its output connected to the write ports of the two DDR storage channels respectively. In normal mode, the reconfigurable write data distributor routes the input data to one of the DDR storage channels, and in degraded mode, it broadcasts the input data to both DDR storage channels simultaneously. The reconfigurable read data synthesizer has its input terminals connected to the read ports of the two DDR memory channels respectively, and its output terminal connected to an external data receiver. In normal mode, the reconfigurable read data synthesizer selects one channel from the two DDR memory channels for data output, and in degraded mode, it only selects the healthy channel for data output.

3. The spaceborne dual DDR data cache system based on timing interleaving and dynamic reconstruction according to claim 1, characterized in that, The intelligent control unit includes: The radiation-resistant clock generation module is used to generate two clock signals with the same frequency and a dynamically adjustable phase difference, which are then supplied to the two DDR memory channels respectively. A control state machine module is connected to the radiation-resistant clock generation module and the two DDR memory channels, and is used to control the two DDR memory channels to alternately perform burst read operations and burst write operations according to the clock signal; The health status monitoring module is connected to the data path and control path of the two DDR storage channels respectively, and is used to collect system health status parameters in real time. The dynamic reconfiguration controller is connected to the health status monitoring module, the control state machine module, and the data scheduling unit, respectively, and is used to determine the fault based on the health status parameters and control the data scheduling unit to perform working mode switching.

4. The spaceborne dual DDR data cache system based on timing interleaving and dynamic reconstruction according to claim 3, characterized in that, The phase difference between the two clock signals output by the radiation-resistant clock generation module can be dynamically adjusted within the range of 120° to 180°. Under stable radiation environment conditions, the phase difference is configured to 180° to achieve complete parallelization of the read and write operations of the two DDR memory channels. When the radiation environment deteriorates, the phase difference is automatically reduced to 120° to increase the timing fault tolerance margin. The control state machine module adopts a triple-modular redundancy architecture, including three physically isolated state machine instances and a majority voting circuit connected to the output of the three state machine instances. The three state machine instances use Gray code encoding to ensure that only one bit of the codeword changes during state transition. The control state machine module defines a first operating state and a second operating state. In the first operating state, the first DDR memory channel performs a burst write operation and the second DDR memory channel performs a burst read operation. In the second operating state, the first DDR memory channel performs a burst read operation and the second DDR memory channel performs a burst write operation. The switching between the first operating state and the second operating state is triggered by the DDR burst transmission completion signal.

5. The spaceborne dual DDR data cache system based on timing interleaving and dynamic reconstruction according to claim 3, characterized in that, The health status monitoring module includes: The CRC check submodule is connected to the data write path and data read path of the two DDR storage channels. It is used to calculate the CRC check code before data writing and compare the check code when data is read to achieve end-to-end data integrity verification. The command timeout detection submodule is connected to the control command path of the two DDR memory channels and is used to set an independent timeout counter for each DDR access command and monitor the command response time. The environmental monitoring submodule is used to collect radiation dose rate and temperature environmental parameters.

6. The spaceborne dual DDR data cache system based on timing interleaving and dynamic reconstruction according to claim 3, characterized in that, After receiving a switching request from the health status monitoring module, the dynamic reconfiguration controller waits for the current DDR burst transmission cycle to end naturally and triggers a mode switch at the burst transmission boundary. The mode switch includes two levels: control system reconfiguration and data path reconfiguration. The control system reconfiguration switches the operating modes of the two DDR controllers from a time-interleaved mode to a synchronous operation mode. The data path reconfiguration configures the write data allocator of the data scheduling unit to broadcast mode and the read data synthesizer to a health channel selection mode. The entire switching process is completed autonomously by the hardware logic within 10 microseconds.

7. The spaceborne dual DDR data cache system based on timing interleaving and dynamic reconstruction according to claim 3, characterized in that, The dynamic reconfiguration controller dynamically adjusts the DDR refresh frequency based on the radiation dose rate collected in real time by the health status monitoring module, and / or optimizes the IO drive intensity and timing parameters based on temperature parameters, and / or reconfigures the system into a single-channel degrade mode under extreme fault conditions.

8. The spaceborne dual DDR data cache system based on timing interleaving and dynamic reconstruction according to claim 1, characterized in that, The intelligent control unit controls the two DDR storage channels to operate in a time-interleaved manner under normal working mode to achieve full-duplex communication at the system level; when a channel failure is detected, the system is controlled to switch to synchronous redundancy mode, where the two DDR storage channels perform write operations synchronously, and read operations are performed only from the healthy channel.

9. The spaceborne dual DDR data cache system based on timing interleaving and dynamic reconstruction according to claim 1, characterized in that, Each DDR memory channel of the memory execution unit integrates an ECC check circuit to detect and correct memory errors caused by single-event effects; the data scheduling unit also includes an anti-SEU asynchronous FIFO, which adopts Gray code addressing mechanism and triple-modular redundancy hardening design and is set on the cross-clock domain data path; the two DDR memory channels are aerospace-grade DDR3 SDRAM or DDR4 SDRAM.

10. A spaceborne dual DDR data caching method based on time-interleaved and dynamic reconstruction, characterized in that, The spaceborne dual DDR data cache system based on timing interleaving and dynamic reconstruction as described in any one of claims 1-9 includes: System initialization: After the system is powered on, clock locking, DDR memory initialization and redundant logic self-test are completed, and the system enters normal working mode; Interleaved read / write: In the normal operating mode, two clock signals with adjustable phase difference are used to drive the two DDR storage channels respectively, and control the two DDR storage channels to alternately perform burst read and burst write operations. When one DDR storage channel performs a burst write operation, the other DDR storage channel performs a burst read operation, and the read and write roles are switched in the next burst transmission cycle to achieve full-duplex data caching at the system level. Real-time health status monitoring: During the execution of the time-interleaved read and write steps, the data integrity and command response status of the two DDR storage channels are monitored in parallel in real time, and system health status parameters are collected; Fault determination and mode switching: Based on the health status parameters, determine whether a channel fault has occurred. When a fault is determined to have occurred in a certain DDR storage channel, wait for the current DDR burst transmission cycle to end naturally, and trigger mode switching at the burst transmission boundary to switch the system from time-interleaved mode to synchronous redundancy mode. Synchronous Redundancy Operation: In the synchronous redundancy mode, the two DDR storage channels perform write operations synchronously, and read operations are only performed from the healthy channel, maintaining the continuous operation of the data caching service.

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