Task processing method, chip, device, equipment, storage medium and program product

Abstract

The application provides a task processing method, a chip, an apparatus, a device, a storage medium and a program product. The method is applied to a multi-core particle combined sealing chip, the multi-core particle combined sealing chip comprises a plurality of core particles and a communication unit connected with the plurality of core particles, and the method comprises the following steps: receiving a plurality of parallel core particle computing tasks, each core particle computing task is bound with a target core particle; determining a source core particle where target data required for executing each core particle computing task is located; if the target task involves cross-core particle data access, a target communication primitive is determined, and a target communication algorithm is determined; a primitive call request is issued to the communication unit, so that the communication unit responds to the primitive call request, and the target data is transferred from the source core particle to a local storage unit of each target core particle by executing the target communication algorithm; and if the target data transfer is completed, the target core particle executes the core particle computing task based on the target data in the local storage unit. Through the application, the cross-core particle data transmission bottleneck can be relieved, and the development difficulty is reduced.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a task processing method, chip, device, equipment, storage medium, and program product. Background Technology

[0002] With the continuous development of semiconductor technology, multi-chip co-packaging architectures, which integrate multiple chips through advanced packaging technology, have been widely used. In task processing for multi-chip co-packaging architectures, unified device management or distributed system management are typically employed. When multiple chips are treated as a unified device, the differences in memory access caused by their underlying physical location are often overlooked. Frequent cross-chip data access is easily limited by the interconnect bandwidth between chips, leading to data transmission bottlenecks and system performance degradation. When multiple chips are treated as a distributed system, data flow usually needs to be manually orchestrated to control the computation and memory access behavior of each chip, resulting in tight coupling between the software development process and the underlying hardware architecture, increasing the complexity and time cost of software development. Summary of the Invention

[0003] This application provides a task processing method, a multi-chip packaged chip, an apparatus, an electronic device, a computer-readable storage medium, and a computer program product, which can alleviate the bottleneck of cross-chip hardware data transmission and decouple software and hardware to reduce development difficulty.

[0004] The technical solution of this application embodiment is implemented as follows: This application provides a task processing method applied to a multi-chip packaged chip, wherein the multi-chip packaged chip includes multiple chips and a communication unit connecting the multiple chips, including: Receive a target task for the multi-chip packaged chip, the target task includes at least a plurality of parallel chip computing tasks, each chip computing task is bound to a target chip that executes the chip computing task, and the plurality of chips include each target chip. Based on the target data address included in the target task, the source core containing the target data required to execute each core computing task is determined from the plurality of cores; If the target task involves cross-core data access, determine the target communication primitive for transporting the target data, and determine the target communication algorithm that implements the target communication primitive and adapts to the core connection relationship between the multiple cores; A primitive call request for the target communication primitive is sent to the communication unit so that the communication unit responds to the primitive call request and executes the target communication algorithm that implements the target communication primitive to transfer the target data from the source core to the local storage unit of each target core. For each target chip, if the target data transfer is completed, the target chip is controlled to perform the chip calculation task based on the target data in the local storage unit.

[0005] This application also provides a multi-chip packaged chip, which includes: Multiple chips are packaged on the same packaging substrate, and each chip includes a local memory cell; A communication unit is used to provide a hardware link between the plurality of cores; The scheduling and management unit is connected to the plurality of cores and the communication unit; The scheduling management unit is configured to: receive a target task for the multi-chip packaged chip, wherein the target task includes at least a plurality of parallel chip computing tasks, each chip computing task is bound to a target chip for executing the chip computing task, and the plurality of chips include each target chip; based on the target data address included in the target task, determine the source chip where the target data required to execute each chip computing task is located from the plurality of chips; if the target task involves cross-chip data access, determine a target communication primitive for transporting the target data, and determine a target communication algorithm that implements the target communication primitive and adapts to the chip connection relationship between the plurality of chips; send a primitive call request for the target communication primitive to the communication unit, so that the communication unit responds to the primitive call request and, by executing the target communication algorithm that implements the target communication primitive, transports the target data from the source chip to the local storage unit of each target chip; and for each target chip, if the target data transport is completed, control the target chip to execute the chip computing task based on the target data in the local storage unit.

[0006] This application also provides a task processing device applied to a multi-chip packaged chip, the multi-chip packaged chip including multiple chips and a communication unit connecting the multiple chips, including: A receiving module is configured to receive a target task for the multi-chip packaged chip, wherein the target task includes at least a plurality of parallel chip computing tasks, each chip computing task is respectively bound to a target chip that executes the chip computing task, and the plurality of chips includes each target chip. The first determining module is used to determine, based on the target data address included in the target task, the source core containing the target data required to execute each core computing task from the plurality of cores; The second determining module is used to determine, if the target task involves cross-core data access, a target communication primitive for transporting the target data, and a target communication algorithm that implements the target communication primitive and is adapted to the core connection relationship between the multiple cores. The calling module is used to send a primitive calling request for the target communication primitive to the communication unit, so that the communication unit responds to the primitive calling request and, by executing the target communication algorithm that implements the target communication primitive, moves the target data from the source core to the local storage unit of each target core; The control module is used to control each target chip to perform the chip computing task based on the target data in the local storage unit, once the target data transfer is completed.

[0007] This application also provides an electronic device, including: Memory is used to store executable instructions for a computer; The multi-chip package is used to execute computer-executable instructions stored in the memory to implement the task processing method provided in the embodiments of this application.

[0008] This application also provides a computer-readable storage medium storing computer-executable instructions or computer programs, which, when executed by a multi-chip packaged chip, implement the task processing method provided in this application.

[0009] This application also provides a computer program product, including computer-executable instructions or a computer program, which, when executed by a multi-chip packaged chip, implements the task processing method provided in this application.

[0010] The embodiments of this application have the following beneficial effects: (1) By determining the source core and uniformly transporting the target data to the local storage unit of each target core through the communication unit before computation, each target core can directly execute core computation tasks based on the data in the local storage unit. This mechanism avoids frequent and random cross-core memory access during the execution of computation tasks, significantly reduces the communication traffic and bandwidth occupation of the interconnection links between cores, and effectively alleviates the hardware data transmission bottleneck under the multi-core encapsulation architecture. (2) When facing cross-core data access, by determining the target communication primitive and the target communication algorithm that adapts to the core connection relationship between multiple cores, the data transport process executed by the communication unit can automatically adapt to the underlying hardware interconnection topology. This not only improves the utilization rate of the hardware communication link, but also achieves effective decoupling between task computation and underlying hardware data transport, eliminating the need to manually control the underlying hardware memory access behavior and reducing the management and development difficulty of the multi-core architecture. Attached Figure Description

[0011] Figure 1 This is a first flowchart illustrating the task processing method provided in the embodiments of this application; Figure 2 This is a schematic diagram of the microstructure of the core provided in the embodiments of this application; Figure 3 This is a schematic diagram of the communication path between multi-chip packaged chips provided in the embodiments of this application; Figure 4 This is a schematic diagram of the set communication primitives provided in the embodiments of this application; Figure 5 This is a schematic diagram of the data flow communication primitives provided in the embodiments of this application; Figure 6 This is a second flowchart illustrating the task processing method provided in the embodiments of this application; Figure 7 This is a third flowchart illustrating the task processing method provided in the embodiments of this application; Figure 8 This is a fourth flowchart illustrating the task processing method provided in the embodiments of this application; Figure 9 This is a first example diagram of the task processing flow provided in the embodiments of this application; Figure 10 This is a second example diagram of the task processing flow provided in the embodiments of this application; Figure 11 This is a third example diagram of the task processing flow provided in the embodiments of this application; Figure 12 This is a schematic diagram illustrating the data dependencies between tasks provided in an embodiment of this application; Figure 13 This is a fifth flowchart illustrating the task processing method provided in the embodiments of this application; Figure 14 This is a schematic diagram of the structure of the multi-chip packaged chip provided in the embodiments of this application; Figure 15 This is a schematic diagram of the structure of the task processing device provided in the embodiments of this application.

[0012] It should be noted that the terms "first" and "second" mentioned above are only used to distinguish between different options and do not represent the degree of superiority or inferiority of the options or their priority in the implementation process. Detailed Implementation

[0013] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0014] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0015] In the following description, the terms "first, second, third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0016] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of a larger module or unit that includes the functionality of the module or unit.

[0017] Unless otherwise defined, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the embodiments of this application is for the purpose of describing the embodiments of this application only and is not intended to limit this application.

[0018] In the implementation of this application, the collection and processing of relevant data should strictly comply with the requirements of relevant laws and regulations, obtain the informed consent or separate consent of the personal information subject, and carry out subsequent data use and processing within the scope of laws and regulations and the authorization of the personal information subject.

[0019] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0020] 1) A chiplet refers to an unpackaged die with a specific function. In the embodiments of this application, the chiplet is not used as a separate packaged chip, but as a modular physical unit, integrated with other chipslet within the same package structure through advanced packaging processes. The chiplet is the basic physical execution unit constituting a multi-chip package, and its internal components include at least a computing unit and a storage unit. Compared to the traditional monolithic architecture that manufactures a single large-area die to achieve the same computing power, the multi-chip package reduces the manufacturing area of ​​a single dielet, thereby alleviating the problem of the area of ​​a single dielet being limited by the photolithography layout, reducing the probability of a single dielet failing due to manufacturing defects, and improving wafer yield.

[0021] 2) Multi-die integrated packaging chips are based on multi-die integrated packaging technology and serve as the underlying hardware physical carrier for the embodiments of this application. Utilizing 2.5D or 3D interconnect structures, multiple physically independent dies are densely integrated onto the same packaging substrate, resulting in a complex data processing system in terms of overall electrical performance—that is, multi-die integrated packaging chips (hereinafter also referred to as multi-die integrated packaging architecture). In related technologies, limited by the physical interconnect medium and link scale, the data transmission bandwidth and data transmission latency of the interconnect network between dies have physical upper limits, and the communication performance between dies is usually lower than the performance of the internal bus within the die, thus easily forming cross-die communication bottlenecks.

[0022] 3) In this embodiment, a distributed system refers to a software-level logic control model established for multi-chip co-packaged chips. Under this logic control model, although multiple chips reside within the same physical package, each chip is abstracted as an independently controllable distributed node at the software management and task scheduling level. Based on this logical abstraction, tasks can be divided into computational tasks executed on a single chip (i.e., chip computation tasks) and communication tasks executed between multiple chips (i.e., communication tasks), and distributed separately. By allocating the data required for computation to the local storage unit of the target chip before computation execution, explicit memory access control based on data locality is achieved, thus distinguishing it from the processing method that treats all physical storage resources as a unified shared storage unit and allows ignoring physical boundaries for unified addressing during computation.

[0023] 4) Network on Chip (NoC) refers to a physical communication network and data transmission channel set configured inside a multi-chip packaged chip to carry out data interaction between the chips. The data management method and communication primitives in the embodiments of this application are all executed through the physical links of this network on chip. By controlling the data flow and transmission timing in the network on chip, the total traffic for cross-chip data access can be reduced, thereby alleviating network congestion and reducing end-to-end communication latency.

[0024] 5) Group communication primitives are a type of parallel communication method used to achieve group data exchange between multiple nodes within a communication group, rather than simple one-to-one communication. This application introduces these primitives into multi-chip co-packaged chips as the first type of communication primitives, used to schedule data interaction between multiple chips. For regular computational tasks such as matrix multiplication, these primitives encapsulate the data transmission process in the underlying cross-chip interconnect, shielding the upper-layer applications from the physical transmission details, thereby decoupling the computational logic from the cross-chip communication process.

[0025] 6) Dataflow primitives represent a token-based dataflow control method used to optimize the sequential execution pattern of "completing all communication before starting computation" that might occur when only set communication primitives are used. Specifically, before executing communication-type and computation-type tasks, send and receive token queues are pre-registered, and the overall dataset to be transmitted is divided into multiple data blocks. When a data block is transmitted across chips to the local storage unit of the target chip, the underlying communication logic responsible for receiving generates a corresponding ready token. Upon detecting this ready token, the target chip triggers local computation for that data block; simultaneously, the on-chip network continues to execute cross-chip transmission of subsequent data blocks. This achieves pipelined overlap between data transport and computation tasks in the time dimension, reducing the impact of cross-chip transmission latency on the computation process and improving the utilization of computing units.

[0026] This application provides a task processing method, a multi-chip co-packaged chip, an apparatus, an electronic device, a computer-readable storage medium, and a computer program product, which can alleviate the bottleneck of cross-chip hardware data transmission and decouple software and hardware to reduce development difficulty. The following is a detailed description of the embodiments of this application based on the above explanation of the terms and terminology used.

[0027] The following describes the task processing method provided in the embodiments of this application. The task processing method provided in the embodiments of this application is applied to a multi-chip packaged chip, which includes multiple chips and a communication unit connecting the multiple chips. See [link to relevant documentation]. Figure 1 , Figure 1 This is a first flowchart illustrating the task processing method provided in this application embodiment. The task processing method provided in this application embodiment includes: Step 101: Receive the target task for the multi-chip co-packaged chip.

[0028] The target task includes at least multiple parallel particle computing tasks, each particle computing task is bound to a target particle that executes the particle computing task, and the multiple particles include each target particle.

[0029] Here, a multi-chip packaged chip is a chip formed by interconnecting multiple chips through packaging. Each chip can perform chip computing tasks as an independent execution unit. The target task is a computing task configured for the multi-chip packaged chip, which consists of at least multiple chip computing tasks that can be executed in parallel. The target chip is a chip that establishes a binding relationship with a chip computing task and is used to execute that chip computing task.

[0030] In the specific implementation process, during the software programming phase, each chip computation task is configured with information such as task identifier, target chip identifier, computation parameters, data address, and data volume. A binding relationship is established between the chip computation task and the target chip based on the target chip identifier. After compilation, each chip computation task forms a chip executable task that can be executed on its corresponding target chip. When receiving a target task, multiple chip computation tasks and their binding relationships are received simultaneously, and the chip participating in execution is determined based on multiple target chip identifiers. These multiple chip tasks include all target chips, thus enabling multiple chip computation tasks to be configured to their corresponding target chips in parallel.

[0031] As an example, we set up three cores, denoted as core 0, core 1, and core 2, and the target task is matrix multiplication. ,in, The left matrix, The right matrix, The result is a matrix. The matrix... The data is divided into three blocks by row. , and , matrix The data is divided into three blocks according to columns. , and and the resulting matrix Divide the data into three blocks according to columns. , and The subscripts 0, 1, and 2 correspond to the aforementioned core particle numbers. That is, in the initial state, the data block... and Located in core 0, and Located in core 1, and Located in core 2. This objective task consists of three core computation tasks, which are respectively bound to core 0, core 1, and core 2 for execution. Specifically, the core computation task bound to core 0 is based on a complete matrix. (Including information collected and supplemented through communication) and ) and local data blocks Multiply to obtain the result data block The core computation task bound to core 1 is based on a complete matrix. (Including information collected and supplemented through communication) and ) and local data blocks Multiply to obtain the result data block The core computation task bound to core 2 is based on a complete matrix. (Including information collected and supplemented through communication) and ) and local data blocks Multiply to obtain the result data block .

[0032] Step 102: Based on the target data address included in the target task, determine the source core containing the target data required to execute each core computation task from multiple cores.

[0033] Here, the target data address is a global address used to identify the data storage location required for the execution of the kernel computing task; the source kernel is the kernel that actually stores the target data. When multiple kernels use a global addressing method, the storage space of different kernels corresponds to different address ranges, and the target data address can be used to determine the source kernel corresponding to the target data.

[0034] In the specific implementation process, for each kernel computation task, the target data address and target data volume are obtained. Based on the global address range to which the target data address belongs, the kernel identifier where the target data is located is determined, and the kernel with that kernel identifier is identified as the source kernel. When the target data consists of multiple data fragments, the address range and corresponding source kernel of each data fragment are determined, and a correspondence between kernel computation tasks, target data addresses, and source kernels is established. When the target data is located locally in the execution kernel, the execution kernel is identified as the source kernel; when the target data is located in other kernels, the other kernels storing the target data are identified as source kernels. For target data spanning multiple address ranges, it is divided into multiple target data fragments according to the address range, and the source kernel of each target data fragment is identified.

[0035] As an example, we set up three cores: core 0, core 1, and core 2, with the target task being matrix multiplication. ,in The left matrix, The right matrix, This is the resulting matrix. Divided by row , and ,Will Divided by column , and The subscript indicates the core number. Core computation task , and They are respectively bound to core 0, core 1, and core 2, among which... Indicates the first Individual chip computing tasks. implement Data is needed. , , and The corresponding source cores are core 0, core 1, core 2 and core 0, respectively; and Corresponding to and The source core particles are determined in the same way.

[0036] Step 103: If the target task involves cross-core data access, determine the target communication primitive used to transport the target data, and determine the target communication algorithm that implements the target communication primitive and adapts to the core connection relationship between multiple cores.

[0037] Here, the target communication primitive is a communication interface used to realize the transmission, copying or reduction of target data between the source core and the target core; the target communication algorithm is the data transmission process of the target communication primitive and the algorithm that determines the data transmission path based on the core connection relationship between multiple cores.

[0038] In the specific implementation process, based on the source kernel, target kernel, data address, and data volume of the target data, it is determined whether the target task involves cross-kernel data access. If multiple target kernels need to obtain the same target data, the target communication primitive is determined to be Broadcast; if each target kernel needs to obtain all target data from other kernels, it is determined to be All-Gather; if data from multiple source kernels needs to be merged into a single target kernel according to a specified reduction operation, it is determined to be Reduce; if the reduction result needs to be distributed to all target kernels, it is determined to be All-Reduce; if the reduction result needs to be distributed in fragments, it is determined to be Reduce-Scatter; for data transmission from a single source kernel to a single target kernel, the target communication primitives are determined to be Send and Recv for the source kernel and target kernel respectively. The parameters of the target communication primitive include the set of participating kernels, source data address, target data address, data volume, reduction operation, and fragmentation method. Furthermore, during the communication domain initialization phase, the core connection relationships between multiple cores are obtained, and a target communication algorithm that matches the core connection relationship is selected from the pre-configured correspondence between communication primitives and communication algorithms. The ring connection relationship adopts the Ring algorithm, which transmits adjacent cores sequentially, and the mesh connection relationship adopts the Mesh algorithm based on XY routing or the shortest path.

[0039] In some embodiments, "determining a target communication algorithm that implements the target communication primitive and adapts to the chip connection relationship between multiple chips" can be achieved by performing the following steps: obtaining the chip connection relationship between multiple chips in a multi-chip package; obtaining the correspondence between multiple pre-configured candidate chip connection relationships and multiple communication algorithms, wherein the multiple candidate chip connection relationships include chip connection relationships; and determining the communication algorithm corresponding to the chip connection relationship from the multiple communication algorithms based on the correspondence, so as to use it as the target communication algorithm.

[0040] Here, the core-granule connection relationship (i.e., hardware topology) is used to represent the connection status between multiple core granules, including core granule identifier, directly connected core granules, connection direction, and the topology type formed by the connection; the communication algorithm is the execution flow that organizes the data transmission order, transmission path, and data fragmentation method according to a specific core-granule connection relationship.

[0041] In the specific implementation process, during the communication domain initialization phase, the chip identifiers and direct connection information between multiple chips in the multi-chip package are obtained through the runtime interface, and the current chip connection relationship is determined based on the direct connection information. Further, the correspondence between multiple pre-configured candidate chip connection relationships and multiple communication algorithms in the communication library is obtained. Each correspondence includes at least the topology type of the candidate chip connection relationship, the set of participating chips, and the matching communication algorithm. The current chip connection relationship is matched with each candidate chip connection relationship; the matching content may include the number of participating chips, chip identifiers, direct connection relationships, and topology type. When the current chip connection relationship matches a candidate chip connection relationship, the communication algorithm corresponding to that candidate chip connection relationship is determined as the target communication algorithm. The target communication algorithm is used to implement target communication primitives such as All-Gather, Reduce-Scatter, Broadcast, or All-Reduce, and maps the logical data transmission path to the actual chip connection relationship.

[0042] As an example, setting the core , and The current core-particle connection relationship is a ring connection, and the direct connection relationships are as follows: connect , connect , connect The correspondence between ring candidate core particle connections and Ring communication algorithms is pre-configured. During All-Gather execution, the target communication algorithm causes each core particle to transmit local data to neighboring core particles and receive data transmitted by another neighboring core particle. After multiple rounds of transmission, each core particle obtains all the target data. If the acquired core particle connection is a grid connection, the grid candidate core particle connection is matched, and a communication algorithm based on XY routing or shortest path transmission is determined.

[0043] By applying the above embodiments, by obtaining the core-to-core connection relationship and selecting a suitable communication algorithm according to the preset correspondence, the communication process is matched with the physical interconnection structure between cores, which helps to reduce unnecessary link detours and link occupation, and improve the bandwidth utilization and data transfer efficiency of the hardware link between cores.

[0044] In some embodiments, "obtaining the chip connection relationship between multiple chips in a multi-chip package" can be achieved by performing the following steps: dividing the source chip and target chip participating in cross-chip data access into a communication domain, and assigning corresponding communication domain internal numbers to the source chip and target chip in the communication domain; initializing the communication domain, and obtaining the chip connection relationship during the communication domain initialization stage; "transferring target data from the source chip to the local storage unit of each target chip" can be achieved by performing the following steps: if multiple source chips provide their respective target data, according to the sorting rule of the communication domain internal number corresponding to the source chip in the communication domain, sequentially splicing and combining the received multiple target data in the local storage unit of the target chip.

[0045] Here, the communication domain is a set of source and target kernels participating in the same cross-kernel data access process, used to limit the scope of participation of the target communication primitive; the communication domain internal number is a unique number of kernels within the communication domain, used to determine the data arrangement order when multiple source kernels provide target data; kernel connection relationship is the direct connection relationship between kernels within the communication domain and the topology type formed therefrom.

[0046] In the specific implementation process, based on the source kernel, target kernel, target data address, and target data volume recorded in the target task, the source kernel and target kernel participating in cross-kernel data access are assigned to the same communication domain. Each kernel within the communication domain is assigned a unique internal communication domain number, which can be assigned in a preset order. The process begins with continuous allocation and establishes a correspondence between communication domain internal numbers and kernel identifiers. During communication domain initialization, the kernel connection relationships within the communication domain are obtained, including directly connected kernels, connection directions, and topology types. The correspondence between kernel connection relationships and communication domain internal numbers is then saved. After initialization, the arrangement order, write location, and data length of the target data are determined based on the communication domain internal number corresponding to the source kernel. Upon receiving target data from each source kernel, it is written to the local storage unit of the target kernel according to the communication domain internal number sorting rules, ensuring that the target data in different target kernels maintains the same arrangement order.

[0047] As an example, setting the core , , and ,in Indicates the first Four core particles are divided into a communication domain, and the internal numbers 0, 1, 2, and 3 are assigned sequentially within the communication domain. Source core particle. , , and Provide target data respectively , , and ,in Indicates the number is The target data is provided by the source core. During All-Gather, each target core receives and writes the target data in ascending order of its number, and the combined result is represented as... ,in This represents the combined target data. This indicates that the cores are assembled in sequence; even if the core connection relationship is Ring, the final result of the combination of each target core will still be saved in this order.

[0048] By applying the above embodiments, a stable core communication identifier and topology configuration can be formed by establishing a communication domain, assigning internal numbers within the communication domain, and obtaining core connection relationships during the initialization phase. Sequentially splicing multi-source data according to internal numbers can ensure that the data is arranged in an orderly manner in the target core's local storage unit, reducing additional data rearrangement operations.

[0049] In some embodiments, candidate core-particle connectivity relationships include ring connectivity relationships and mesh connectivity relationships. Ring connectivity relationships correspond to ring communication algorithms, and mesh connectivity relationships correspond to mesh communication algorithms. Multiple communication algorithms include both ring communication algorithms and mesh communication algorithms. Based on this, "determining the communication algorithm corresponding to the core-particle connectivity relationship from among multiple communication algorithms, based on the correspondence, as the target communication algorithm" can be achieved by performing the following steps: If the core-particle connectivity relationship is a ring connectivity relationship, the ring communication algorithm corresponding to the ring connectivity relationship is selected as the target communication algorithm based on the correspondence; if the core-particle connectivity relationship is a mesh connectivity relationship, the mesh communication algorithm corresponding to the mesh connectivity relationship is selected as the target communication algorithm based on the correspondence.

[0050] Here, a ring connection refers to a connection where multiple cores are connected in a closed sequence, with each core directly connected to at least two adjacent cores; a grid connection refers to a connection where multiple cores are arranged in rows and columns and connected directly between adjacent positions. The correspondence is used to record the matching relationship between candidate core connection relationships and communication algorithms. The target communication algorithm is the communication algorithm that matches the current core connection relationship and is used to implement the target communication primitive.

[0051] In the specific implementation process, during the initialization of the communication domain, the core identifiers of each core within the communication domain and the direct connection information between cores are obtained, and the topology type of the current core connection relationship is determined based on the direct connection information. If each core has an adjacent preceding and succeeding core, and all direct connections form a closed path, the core connection relationship is determined to be a ring connection relationship; if the cores are arranged according to row and column positions, and the direct connections mainly exist between adjacent rows or adjacent columns, the core connection relationship is determined to be a mesh connection relationship. Further, the current core connection relationship is matched with pre-configured candidate core connection relationships; when a ring connection relationship is matched, the corresponding ring communication algorithm (i.e., the Ring algorithm) is invoked; when a mesh connection relationship is matched, the corresponding mesh communication algorithm (i.e., the Mesh algorithm) is invoked. The ring communication algorithm transmits and forwards data according to the circumferential order of adjacent cores, while the mesh communication algorithm determines the data transmission path according to the row and column positions of the cores, prioritizing transmission paths based on XY routing or the shortest path.

[0052] As an example, setting the core , , and When the direct connection is - , - , - and - When the core particle connection is determined to be a ring connection, the ring communication algorithm is used as the target communication algorithm. During All-Gather execution, each core particle transmits its local target data along adjacent connections and continues to forward the received data, ultimately enabling each core particle to obtain all the target data. When the core particles follow... When connecting rows and columns, the core-particle connection relationship is determined to be a grid connection relationship, and the grid communication algorithm is used as the target communication algorithm. The grid communication algorithm selects the transmission path according to the row and column directions to reduce unnecessary data transmission.

[0053] By applying the above embodiments, by selecting the corresponding ring communication algorithm and grid communication algorithm for ring connection and grid connection respectively, the data transmission method can be adapted to the actual hardware interconnection structure. This is beneficial to make full use of the available links in the ring or grid topology and reduce link idleness or transmission detours caused by algorithm and topology mismatch.

[0054] Step 104: Send a primitive call request for the target communication primitive to the communication unit so that the communication unit responds to the primitive call request and executes the target communication algorithm that implements the target communication primitive to transfer the target data from the source core to the local storage unit of each target core.

[0055] Here, the primitive call request is the request information used to describe the target communication primitive and its execution parameters, including at least the type of the target communication primitive, the source chip identifier, the target chip identifier, the source data address, the target data address, and the data volume; the communication unit (i.e., the interconnection network between multiple chips in a multi-chip package) is a functional unit used to execute the target communication algorithm and complete the data transmission between chips; the local storage unit is the storage area inside the target chip used to store the target data.

[0056] In the specific implementation process, a primitive call request is generated based on the target communication primitive and sent to the communication unit. The communication unit parses the primitive call request to obtain parameters such as the source kernel, target kernel, data address, data volume, and target communication algorithm. It determines the data transmission order and path according to the target communication algorithm, reads the target data from the local storage unit of the source kernel, and transmits the target data to the corresponding target kernel through the kernel connection relationships between multiple kernels. After receiving the target data, the target kernel writes the target data to the local storage area corresponding to the target data address. For target data transmitted in fragments, read, transmit, and write operations are performed according to the order of data fragmentation to ensure that each target kernel obtains the target data required to perform its kernel computing task.

[0057] As an example, setting the core , and The target task is matrix multiplication. ,in The left matrix, The right matrix, This is the resulting matrix. Divided by row , , ,Will Divided by column , , The subscript indicates the data fragment number, and and Initially, all are stored in the core. Because each target core chip requires the use of, including , and The complete matrix The target communication primitive is determined to be All-Gather, and a core identifier including three core identifiers and each The primitive call request specifies the source data address, target data address, and data volume. If the core-particle connection is a ring connection, the target communication algorithm adopts a ring communication algorithm, which is executed according to the sequential transmission of adjacent core-particles: each core-particle first sends its local data fragments and receives data fragments sent by adjacent core-particles, and then continues to transmit the received data fragments in subsequent rounds; after multiple rounds of transmission, the core-particle... , and Local storage units all contain including , and The complete matrix .

[0058] In some embodiments, after "determining the target communication algorithm that implements the target communication primitive and adapts to the connection relationship between multiple cores", the following steps may also be performed: mapping the logical transmission path of the target communication algorithm to the hardware link between multiple cores; "issuing a primitive call request for the target communication primitive to the communication unit, so that the communication unit responds to the primitive call request and executes the target communication algorithm that implements the target communication primitive to move the target data from the source core to the local storage unit of each target core" can be achieved by performing the following steps: issuing a primitive call request including the hardware link to the communication unit, so that the communication unit responds to the primitive call request and executes the target communication algorithm that implements the target communication primitive based on the hardware link to move the target data from the source core to the local storage unit of each target core.

[0059] Here, the logical transmission path is the data transmission order between cores determined by the target communication algorithm according to the target communication primitives; the hardware link is the physical connection between multiple cores that can actually be used to transmit target data; the path mapping is to establish the correspondence between the logical transmission path and the hardware link, so that the transmission operation generated by the target communication algorithm is executed along the actually available hardware link.

[0060] In the specific implementation process, the logical transmission paths, source and target kernels involved in the transmission, as well as the transmission direction and data fragmentation information of each logical transmission path, are obtained from the target communication algorithm. Hardware links between multiple kernels are obtained based on their connection relationships, and each logical transmission path is mapped to its corresponding hardware link according to the kernel order, transmission direction, and path connectivity, forming a hardware link sequence. For ring connections, mapping is performed according to the ring-shaped order of adjacent kernels; for grid connections, hardware links based on XY routing or the shortest path are determined according to the row and column directions of the kernels. Furthermore, a primitive call request, including the target communication primitive, source kernel, target kernel, target data address, target data volume, and hardware link sequence, is generated and sent to the communication unit so that the communication unit can read, transmit, and write target data according to the hardware link sequence.

[0061] As an example, setting the core , and The target task is matrix multiplication. ,in The left matrix, The right matrix, The result matrix; Divided by row , , ,Will Divided by column , , The subscript indicates the core number, i.e., the data block in the initial state. and Located in the core , and Located in the core , and Located in the core Each target core chip must obtain , , Therefore, the target communication primitive is determined to be All-Gather. The ring connection relationship includes hardware links. , and ,in Indicates core To the core Hardware link; logical transmission path , and Mapped to respectively , and ,in Indicates from to The logical transmission path. Communication units transmit in rounds based on the mapping results. , , This ensures that the local storage units of each target chip obtain complete... .

[0062] By applying the above embodiments, by mapping the logical transmission path to the inter-core hardware link and including the hardware link in the primitive call request, the communication unit can directly perform data transfer based on the determined physical path, clarify the data transmission path in the interconnect hardware, reduce path configuration overhead, and improve the hardware execution determinism of the communication task.

[0063] In some embodiments, "mapping the logical transmission path of the target communication algorithm onto the hardware link between multiple cores" can be achieved by performing the following steps: if the core connection relationship is a ring connection relationship and the target communication algorithm is a ring communication algorithm, the logical transmission path of the target communication algorithm is allocated hop by hop to the hardware link between two adjacent cores that are directly connected in physical location; if the core connection relationship is a mesh connection relationship and the target communication algorithm is a mesh communication algorithm, the logical transmission path of the target communication algorithm is mapped to the hardware link that is sequentially connected in the first coordinate axis direction and the second coordinate axis direction, or mapped to the hardware link with the smallest physical hop count.

[0064] Here, the logical transmission path is the data transmission order between cores determined by the target communication algorithm; the hardware link is the actual direct connection channel between multiple cores; hop-by-hop allocation is to split the logical transmission path into multiple transmission hops between adjacent cores and match the corresponding hardware link for each transmission hop; the first coordinate axis and the second coordinate axis represent the row direction and column direction in the mesh connection relationship, respectively.

[0065] In the specific implementation process, the logical transmission paths in the target communication algorithm and the identifiers of the cores involved in each logical transmission path are obtained, and the direct connection status between cores is determined according to the core connection relationship. If the core connection relationship is a ring connection relationship and the target communication algorithm is a ring communication algorithm, then according to the arrangement order of the cores in the logical transmission path, it is determined whether adjacent cores are directly connected in physical location; if the determination result is yes, the corresponding logical transmission path is assigned to the hardware link between the adjacent cores; if the determination result is no, the transmission order is adjusted or the transmission path is split according to the ring connection relationship. If the core connection relationship is a mesh connection relationship and the target communication algorithm is a mesh communication algorithm, then the coordinates of each core on the first coordinate axis and the second coordinate axis are obtained, and transmission is prioritized along the direction of the first coordinate axis, and then along the direction of the second coordinate axis; or the physical hop count of different transmission paths is calculated, and the hardware link combination with the smallest physical hop count is selected.

[0066] Applying the above embodiments, in a ring topology, logical transmission paths are allocated hop-by-hop to links between adjacent cores, allowing continuous use of direct interconnect links; in a mesh topology, links in the coordinate axis direction or links with the minimum number of physical hops are used, which can reduce data detours and transmission hops, and reduce link occupancy time and inter-core transmission delay.

[0067] Step 105: For each target kernel, if the target data transfer is complete, control the target kernel to execute kernel calculation tasks based on the target data in the local storage unit.

[0068] Here, "target data transfer complete" means that each target kernel has received all the target data required to execute the kernel computing task and has written the target data to the target data address of the corresponding local storage unit. "Executing kernel computing tasks based on local storage units" means that the kernel computing task directly reads the target data from the local storage to complete the calculation, without needing to access the storage data of other kernels during the calculation process.

[0069] In the specific implementation process, for each target kernel, the data transfer status is obtained, and based on the target data address, data volume, and preset data fragmentation information, it is determined whether the target data written to the local storage unit is complete. When the received data volume of the target data reaches the preset data volume, and all target data fragments have been written, the target data transfer is considered complete; otherwise, the kernel computing task remains in a waiting state. After determining that the target data transfer is complete, based on the binding relationship between the target kernel and the kernel computing task, the kernel computing task is configured as the pending task of the target kernel, and the target kernel reads the target data from the local storage unit to perform the calculation. The calculation result is written to the local storage unit of the target kernel.

[0070] In some embodiments, the target data includes N data blocks, where N is an integer greater than 1. Moving the target data from the source kernel to the local storage unit of each target kernel is the target communication task. The target communication task includes local communication tasks for each data block, and the kernel computation task includes local computation tasks for each data block. Based on this, "issuing a primitive call request for the target communication primitive to the communication unit, so that the communication unit responds to the primitive call request and moves the target data from the source kernel to the local storage unit of each target kernel by executing the target communication algorithm that implements the target communication primitive" can be achieved by performing the following steps: A primitive call request for the target communication primitive is sent to the communication unit so that the communication unit responds to the primitive call request and executes the target communication algorithm that implements the target communication primitive. The following processing is performed: by executing the local communication task of the nth data block in N data blocks, the nth data block is moved from the source core to the local storage unit of each target core, so that the target core generates the nth token inside the target core based on the ready state of the nth data block, so as to trigger the input token of the target core to be updated to the nth token, where n is an integer starting from 1 and incrementing by 1, and n is less than or equal to N; Accordingly, "controlling the target kernel to execute kernel computation tasks based on target data in the local storage unit" can be achieved by performing the following steps: controlling the target kernel to perform the following processing: if the input token is detected to be updated to the nth token, execute the local computation task of the nth data block that is ready as indicated by the nth token; wherein, during the execution of the local computation task of the nth data block that is ready as indicated by the nth token by the target kernel, if n is less than N, the communication unit executes the local communication task of the (n+1)th data block, so that the target kernel generates the (n+1)th token based on the ready state of the (n+1)th data block, thereby triggering the input token of the target kernel to be updated to the (n+1)th token; this is repeated until the local communication task of the Nth data block is completed, and the input token of the target kernel is triggered to be updated to the Nth token; generate an end token inside the target kernel to update the input token of the target kernel to the end token; if the target kernel detects that the input token has been updated to the end token, it determines that the kernel computation task has been completed.

[0071] Here, the target data includes One data block, For integers greater than 1, the first... The data blocks are denoted as ,in Starting from 1 and increasing in increments of 1, and not exceeding 1 / 2... Integers. The target communication task is to transfer various... The task of moving data from the source memory chip to the local storage units of each target memory chip includes communication with each target memory chip. Corresponding local communication tasks; chip computing tasks include communication with various The corresponding local computation task. Each token is denoted as , used to indicate The transfer has been completed and the corresponding local computation task can be executed. The end token is recorded as follows: This is used to indicate the completion of all local communication tasks and local computing tasks.

[0072] In the specific implementation process, a primitive call request, including the target communication primitive and its parameters, is sent to the communication unit. The communication unit then processes each data block sequentially according to the target communication algorithm. For the first... The data block is executed. Local communication tasks for each data block will The process involves transferring the source memory chip to the local storage unit of each target memory chip; once the target memory chip has been confirmed to be complete... After receiving and writing, a process is generated inside the target chip. To update the input token of the target core to The target core detected that the input token was updated to... Then, read from the local storage unit. Execute the first A local computation task for each data block. During the execution of this local computation task, if... The communication unit continues to execute the first... Local communication tasks for each data block, and in After transportation is completed, it is generated inside the target core. This allows communication tasks and chip computing tasks to proceed in parallel on different data blocks. The local communication task triggers the input token to be updated. Then, it is generated inside the target core. Target core particles were detected. Afterwards, it was confirmed that the chip computing task had been completed.

[0073] As an example, the matrix sum matrix The computational data is divided into ,in Indicates the first The target communication task uses All-Gather, moving each data block sequentially according to the Ring communication algorithm. (Completed) Generated after transport The target chip is based on local storage. Execute a local computation task; during the execution of this local computation task, continue data transfer. After completion, generate Execute again The local computational task; then processed in the same way. and send Therefore, the target kernel can perform kernel computation tasks block by block without waiting for all target data to be transferred.

[0074] By applying the above embodiments, by dividing the data into multiple data blocks and using tokens to trigger corresponding local computations after the data blocks are ready, the computation of the current data block and the communication of the next data block can be performed in parallel on the hardware, reducing the idle time of the computing unit waiting for data and improving the parallel utilization of the communication link between the computing unit and the chip.

[0075] In some embodiments, "controlling the target kernel to execute kernel computation tasks based on target data in the local storage unit" can be achieved by performing the following steps: For each target kernel, control the target kernel to only access the target data in the local storage unit to execute the kernel computation task, and during the execution of the kernel computation task, restrict the target kernel from initiating memory access requests for other kernels, which are kernels different from the target kernel among multiple kernels. Based on this, the following steps can also be performed: After each target kernel completes its corresponding kernel computation task, generate the local computation results of each target kernel for the corresponding computation task; control the communication unit to call the data output communication primitive, perform a data aggregation operation on the local computation results generated by each target kernel, and obtain the total computation result of the target task.

[0076] Here, the local storage unit is the storage area inside the target kernel used to store target data and computation results; local computation is the process by which the target kernel performs kernel computation tasks based solely on the target data in the local storage unit; local computation results are partial computation results formed after each target kernel independently performs its kernel computation task; data aggregation is the process of splicing, copying, or reducing multiple local computation results through data output communication primitives to form the total computation result of the target task.

[0077] In the specific implementation process, for each target kernel, the target data that has been moved and passed integrity checks is read from the local storage unit, and the input data range and output data range of the kernel computing task are configured. During the execution of the kernel computing task, the target kernel is restricted from initiating memory access requests to other kernels, so that the target kernel does not obtain computing data through cross-kernel memory access; when the local storage unit lacks the target data required to execute the kernel computing task, the kernel computing task remains in a waiting state. After each target kernel completes its kernel computing task, it generates corresponding local computing results according to the output data range, and determines the data output communication primitives based on the data correspondence between multiple local computing results; for different data fragments, All-Gather or splicing operations are used, and for multiple local computing results at the same data location, Reduce, All-Reduce, or Reduce-Scatter are used for reduction to obtain the total computing result of the target task.

[0078] As an example, setting the core , and The target task is matrix multiplication. ,in The left matrix, The right matrix, This is the final calculation result. Divided by row , , ,Will Divided by column , , ,in and Indicates the number is Data fragmentation. Through input data communication, each target core's local storage unit stores the complete matrix. (Include , , ), and make the core save Core Access only the complete matrix in the local storage unit and It also restricts memory access requests to other cores during the computation process, thereby generating local computation results. Subsequently, the control communication unit invokes data output communication primitives (such as All-Gather) to... , , By collecting the data, we can obtain the following results: ,in To partition the columns of the resulting matrix, This indicates that the columns are assembled sequentially.

[0079] By applying the above embodiments, by restricting the target chip to access only local storage units and prohibiting it from initiating cross-chip memory access, random memory access traffic and link contention on the interconnect links between chips can be reduced; after local computation is completed, the local computation results are collected in a unified manner, which is conducive to the centralized organization of output communication and improves the effective data transmission ratio of the interconnect links.

[0080] In some embodiments, the following steps may also be performed: if other kernel computing tasks subsequently executed by the target kernel require the use of target data, control the target kernel to directly execute other kernel computing tasks based on the target data in the local storage unit, so as to achieve the reuse of target data in the target kernel.

[0081] Here, target data reuse refers to the continued use of target data in subsequent chip computing tasks after the target data has been transferred and stored in the local storage unit of the target chip, without retrieving the target data from other chips. The target data reuse status is used to indicate whether the target data is still used by subsequent chip computing tasks.

[0082] In the specific implementation process, based on the input data address of subsequent kernel computing tasks, it is determined whether the input data address matches the address of the target data in the local storage unit. If they match and the target data has not been released or overwritten, the target kernel is controlled to directly read the target data in the local storage unit to execute other kernel computing tasks, and the target data is maintained in a valid state across multiple kernel computing tasks. After all kernel computing tasks that require the target data are completed, the local storage space occupied by the target data is released, thereby reducing the repeated handling of the target data between multiple kernels.

[0083] By applying the above embodiments, the target data that has been moved to the local storage unit of the target chip can be directly used for subsequent chip computing tasks, which can avoid the same data being repeatedly moved to the target chip, reduce the transmission traffic and bandwidth occupation of the hardware link between chips, and reduce the waiting time for subsequent computing tasks to obtain data.

[0084] Applying the above embodiments of this application, (1) by determining the source kernel and uniformly transporting the target data to the local storage unit of each target kernel through the communication unit before computation, each target kernel can directly execute kernel computation tasks based on the data in the local storage unit. This mechanism avoids frequent and random cross-kernel memory access during the execution of computation tasks by the computing unit, significantly reducing the communication traffic and bandwidth occupation of the interconnection links between kernels, and effectively alleviating the hardware data transmission bottleneck under the multi-kernel co-packed architecture. (2) When facing cross-kernel data access, by determining the target communication primitive and the target communication algorithm that adapts to the kernel connection relationship between multiple kernels, the data transport process executed by the communication unit can automatically adapt to the underlying hardware interconnection topology. This not only improves the utilization rate of the hardware communication link, but also achieves effective decoupling between task computation and underlying hardware data transport, eliminating the need to manually control the underlying hardware memory access behavior, and reducing the management and development difficulty of the multi-kernel architecture.

[0085] The following describes an exemplary application of the embodiments of this application in a real-world application scenario.

[0086] As semiconductor processes approach their physical limits, monolithic architectures face the following technical constraints: First, due to limitations in photolithography and quantum tunneling, transistor feature sizes cannot be continuously reduced, limiting the improvement in computing power per unit area. Second, constrained by the upper limit of photolithography area and wafer yield, the physical area of ​​a single chip cannot be further increased. Based on this, multi-chip packaging technology divides large monolithic integrated circuits into multiple independent chips and establishes physical and electrical interconnections through 2.5D or 3D packaging processes to improve the overall scalability of the system. For multi-chip packaging architectures, related technologies typically include the following two schemes: Scheme 1 treats all chips within the package as computing entities with a unified shared memory unit. From a programming perspective, accessing the memory resources of each chip is assumed to have approximately consistent memory access performance. However, the memory resources of chips in different physical locations exhibit objective heterogeneity in terms of memory access latency and communication bandwidth. A uniform management approach that ignores this physical communication cost leads to high-frequency cross-chip random memory accesses, making the limited interconnect bandwidth between chips a data transmission bottleneck, thereby reducing overall computing performance. Option 2 abstracts multiple cores into independent distributed nodes, allowing users to manually orchestrate data flow paths at the application layer and directly control the allocation of computational tasks and memory access interactions of each core. This approach deeply couples the upper-layer software logic with the underlying core interconnection topology, requiring developers to understand the physical interconnection structure and routing mechanisms of the underlying multi-core structure, thus increasing the difficulty of adapting the underlying logic and extending the application development cycle.

[0087] To address these issues, this application proposes a task processing method to at least alleviate the aforementioned problems. Specifically, it includes: (1) introducing a distributed communication semantic management multi-core cluster architecture. In terms of hardware packaging, multiple cores together constitute the same multi-core cluster architecture; at the communication link and task resource management level, multiple cores are abstracted into mutually independent distributed nodes, rather than using the overall addressing logic of a unified shared storage unit. Based on this management method, task execution is organized according to the principles of data locality and local data reuse, so that the target data required for computation resides in the local storage unit of the corresponding core before the computation begins, and the reuse frequency of the target data in the local storage unit is increased, thereby reducing the dependence on cross-core data access during the computation process, reducing cross-core access traffic, and avoiding the bottleneck formed by limited interconnection link bandwidth. This processing method avoids treating the multi-core cluster architecture as a unified shared storage unit computing entity and ignoring the memory access heterogeneity between different cores, and also avoids the upper-layer application directly handling the communication details between the lower-layer cores.

[0088] (2) Construct a distributed programming model to decouple data transport from computation execution. Under the distributed programming model, based on the pre-defined task binding relationship, task execution order, target data address parameters, and data volume parameters, determine the data dependency relationship, target data location, and target communication primitives to be called; then, the underlying execution environment completes cross-core data transport based on the target communication primitive; once the relevant data is transported to the local storage unit of the target core and is in an available state, the target core is triggered to execute the corresponding local computation. For scenarios using only set communication primitives, this task organization method is "communication first, computation later"; for scenarios using a token-based data flow control method, it is "data blocks are ready, then the corresponding local computation is triggered". This reduces the number of cross-core random memory accesses during the computation process and eliminates the need for upper-layer applications to directly handle the details of the underlying hardware topology and physical interconnect ports.

[0089] (3) Two types of abstract communication mechanisms are provided to support different types of distributed computing tasks. The first type is a set communication primitive, which is used to perform global data interaction operations involving multiple granules. Specifically, it can include reduction, full reduction, full collection, reduction dissemination, broadcasting, sending, and receiving. The second type is a token-based data flow control method, which is used to handle dependency-driven fine-grained data transport tasks. This mechanism does not require waiting for all data transmission to be completed. Instead, it divides the data to be processed into multiple data blocks and performs cross-granule scheduling according to the data blocks. Whenever a data block is partially in place, a corresponding data flow token is generated to trigger the local computation of the ready data block, so that the communication transmission of subsequent data blocks and the local computation of the current data block overlap in time. By encapsulating the underlying data transport process in the aforementioned communication mechanism, upper-layer software developers do not need to directly intervene in the underlying physical data flow.

[0090] (4) Supports adaptation to heterogeneous hardware topologies among multi-core components. After acquiring the hardware topology among multi-core components during runtime, a communication algorithm adapted to the current hardware topology is selected based on the pre-configured correspondence between topology types and communication algorithms. The logical path corresponding to the selected communication algorithm is then mapped to the physical transmission link of the hardware topology. When using a token-based data flow control method, the segmented communication process corresponding to data blocks is executed using the aforementioned topology adaptation and link mapping results. Through this topology adaptation process, the abstract communication semantics obtain the corresponding underlying transmission implementation under different hardware topologies.

[0091] Specifically, (i) the data management process in this application embodiment may include: Step 1: Receive the computation task and generate the core executable task.

[0092] The runtime management unit receives computational tasks based on a distributed programming model from the upper-layer software. These computational tasks can contain multiple subtasks, each typically corresponding to a different data block or a different data processing range. During the software programming phase, the task binding relationship between the task identifier of each subtask and the corresponding kernel identifier is pre-defined; after compilation, each subtask is transformed into a kernel-executable task carrying this binding relationship. Kernel-executable tasks include communication-type tasks and computation-type tasks.

[0093] Step 2: parse the task binding relationship, data dependency relationship and target data location (i.e. data locality).

[0094] Before the executable tasks are distributed, the runtime management unit reads the task binding relationship between the task identifier and the core identifier carried in the executable tasks to determine the target core corresponding to each executable task. Subsequently, according to the task execution order pre-arranged by the user or upper-layer software, the runtime management unit identifies the sequential constraints between communication type tasks and computing type tasks to determine data dependencies; and extracts the target data address parameters and data volume parameters, decodes the target data address according to the preset globally unified addressing rules to identify the source core to which the target data currently belongs, thereby determining whether the target data is located in the local storage unit of the target core or in the storage unit of another core.

[0095] Step 3: Determine the communication processing method and complete the data transfer.

[0096] When the parsing results indicate that the target data resides in the local storage unit of the pre-bound target kernel, the runtime management unit does not need to trigger cross-kernel communication. Instead, it directly sends the corresponding computation type task to the target kernel, which then reads the target data from the local storage unit to perform local computation.

[0097] When the parsing results indicate that the target data is located in a non-local kernel or scattered across multiple different source kernels, the runtime management unit determines the target communication primitive to be invoked based on data dependencies and the location of the target data, and issues the corresponding primitive invocation request. The communication library obtains the hardware topology between each kernel through the runtime interface; for the determined target communication primitive, the communication library selects the appropriate underlying communication algorithm based on the hardware topology. For example, when the hardware topology is ring-shaped, a ring communication algorithm is selected; when the hardware topology is mesh-shaped, a mesh communication algorithm is selected. Subsequently, the underlying communication execution logic completes data transfer between the source kernel and the target kernel according to the primitive invocation request.

[0098] Once the target data is moved to the local storage unit of the target chip, subsequent computations can directly read the target data from that local storage unit, thus avoiding repeated cross-chip access to the same data. The residence, overwriting, and release of target data in the local storage unit can be managed according to the lifecycle of the current task chain.

[0099] Step 4: Control each chip to perform computational tasks.

[0100] After completing the necessary data transfer, the runtime management unit controls each core to execute computational tasks. Each core reads data from its local storage unit and independently performs corresponding calculations, ultimately completing the entire computational task through the parallel collaboration of multiple cores.

[0101] Taking matrix multiplication as an example, suppose the left matrix A is divided into rows into A0, A1, and A2, and stored in cores 0, 1, and 2 respectively; the right matrix B is divided into columns into B0, B1, and B2, and stored in cores 0, 1, and 2 respectively; the result matrix C is divided into columns into C0, C1, and C2, and output to cores 0, 1, and 2 respectively. Since each core needs the complete matrix A when calculating the corresponding result block, but only needs to use the corresponding matrix B block stored locally, the full collection primitive is triggered for matrix A. If the hardware topology between cores is ring-shaped, a ring communication algorithm is matched, specifically: core 0 sends A0, core 1 sends A1, core 2 sends A2, and receives and forwards data blocks sent by other cores sequentially along the ring link; after multiple rounds of transmission, each core obtains the complete matrix A. Since the result matrix C, after being divided into columns, directly corresponds to the local output position of each core, output data communication is not required in this embodiment.

[0102] (ii) The data communication process of this application embodiment may include: First, providing a set of communication primitives independent of hardware topology; Second, obtaining the current hardware topology between multiple cores during the communication domain initialization phase, and selecting a communication algorithm that is compatible with the current hardware topology based on the pre-configured correspondence between topology type and communication algorithm for different functional communication primitives, so as to complete the corresponding data transmission; Third, when adopting a data flow control method based on a token mechanism, before executing communication type tasks and computation type tasks, pre-registering a sending token queue and a receiving token queue, and dividing the data to be transmitted into multiple data blocks; Whenever a data block is transmitted to the local storage unit of the target core, a corresponding ready token is generated to trigger local computation for that data block; At the same time, subsequent data blocks continue to perform cross-core transmission, thereby achieving time overlap between the computation process and the communication process.

[0103] (III) This application also provides a multi-core package architecture. This architecture includes multiple cores, an interconnect structure, and a runtime management unit. The runtime management unit and the scheduler can be the same functional entity and can be integrated into one of the cores or distributed across multiple cores. It is used to implement distributed communication semantics, manage data flow, provide set communication primitives and token-based data flow control methods, manage distributed task distribution, and execute the aforementioned data management methods. The communication primitive set can be used to define the set communication primitives, their interface formats, and corresponding functions, and to define the registration items, token formats, or trigger semantics in the token-based data flow control method. The compiler or scheduling logic can be used to implement a task organization method that decouples computation and data handling, or to compile high-level tasks into core executable tasks that trigger communication-type tasks and computation-type tasks respectively. Based on the above configuration, this architecture can be applied to scenarios such as artificial intelligence training and inference, large-scale data processing, and graphics rendering, and supports the combined use of set communication primitives and token-based data flow control methods to construct complex computational tasks.

[0104] The complete technical solution of the embodiments of this application will be described below.

[0105] First: For multi-core packaging architectures, where inter-core communication bandwidth becomes a performance bottleneck, distributed semantics is used for management. Specifically: (1) The multi-core package architecture includes multiple cores, each of which includes a computing unit and a storage unit. The cores interact with each other through 2.5D interconnect links or 3D interconnect links, thereby forming a computing carrier with cross-core data transmission capability. For example Figure 2 As shown, Figure 2The middle section (1) shows the organization of computing units (Processing Elements, PEs) and storage units (Memory) from a logical (software) perspective. Figure 2 The middle part (2) shows the physical implementation from a physical perspective (chip perspective), that is, the computing unit (PE) and the storage unit (Memory) are distributed in multiple chips. Each chip contains one or more computing units and storage units, and the chips exchange data through interconnection links.

[0106] (2) Scenarios where inter-chip communication bandwidth becomes a performance bottleneck can be determined through theoretical analysis or practical testing. When the overhead of cross-chip data transmission during task execution leads to a decrease in the computing power utilization of the computing unit, or when the bandwidth utilization of the storage unit cannot be fully released, it can be determined that inter-chip communication has become a bottleneck factor restricting overall performance. For example Figure 3 As shown, path 1 represents the path for the computing unit to access the local storage unit, and path 2 represents the data transmission path between different cores. When data exchange occurs frequently along path 2 during task execution, the interconnect bandwidth between cores will reach saturation before the local computing resources, thus limiting the overall computing performance.

[0107] (3) Distributed semantics refers to treating each core as an independently controllable execution node at the software management and task scheduling level. Based on this semantics, each core can receive different instructions and execute corresponding tasks independently, and the tasks executed by different cores are distinguished from each other; at the same time, data communication paths are maintained between cores to support data exchange between multiple cores. After adopting this semantics, local computing behavior and cross-core communication behavior can be clearly distinguished in the task orchestration stage, providing a basis for subsequent organization of data movement and computing execution according to data locality.

[0108] Second: For the data interaction process between cores in a multi-core co-packaging architecture, software encapsulation is performed using set communication primitive interfaces or data flow primitive interfaces. Specifically: (1) The set communication primitive interface can include seven interfaces: All-Reduce, Reduce-Scatter, All-Gather, Reduce, Broadcast, Send, and Recv. For example... Figure 4 As shown, Figure 4Taking rank0 to rank3 as examples, this paper illustrates the data organization and result distribution methods of five aggregate communication primitives: All-Reduce, Reduce-Scatter, All-Gather, Reduce, and Broadcast. Send and Recv are point-to-point communication interfaces, which will be supplemented with textual explanations. Specifically, a) Broadcast(src_chip, src_addr, dst_chips, dst_addr, size) is used to broadcast data from a source chip to one or more target chips, with data distribution satisfying the operation logic out[i]=in[i]; b) Reduce(src_chips, src_addrs, dst_chips, dst_addr, size, op) is used to reduce data on multiple chips and output the complete reduction result to the target chip, with the reduction result satisfying the operation logic out[i]=sum(inX[i]); c) All-Reduce(chips, src_addrs, dst_addrs, size, op) is used to reduce data on multiple chips and distribute the complete reduction result to all participating chips, with the reduction result satisfying out[i]=s The operation logic of um(inX[i]); It should be noted that the underlying data element aggregation calculation logic of the above-mentioned Reduce and All-Reduce is essentially the same, both of which are manifested as performing reduction operations such as summation on the data at the same index position of each participating chip. Therefore, the two correspond to the same operation logic expression in the attached figure; The essential difference between the two is that the distribution target range of the calculation result is different. Reduce only outputs the result to a single target chip, while All-Reduce distributes the result to all participating chips; d) Reduce-Scatter(chips, src_addrs, dst_addrs, size, op, partition) is used to first reduce the data of multiple chips, then divide the data according to the reduction result sharding method, and then distribute the reduction result shards to different target chips. The distribution result satisfies outY[i]=sum(inX[Y The operation logic of count+i]); e) All-Gather(chips, src_addrs, dst_addrs, size) is used to collect the data of all participating chips and make each participating chip obtain a complete or specified set result, whose set result satisfies out[Y] The operation logic of count+i]=inY[i]; Send(src_chip, src_addr, dst_chip, dst_addr, size) is used to send data from a source chip to a target chip point-to-point; Recv(dst_chip, dst_addr, src_chip, size) is used to receive data from a specified source chip in the target chip and work with Send to complete point-to-point communication.

[0109] It should be noted that the input parameters of each set communication primitive interface include the participating kernel set or source kernel identifier, target kernel identifier, source address, target address, data length, reduction operation, and fragmentation method. These input parameters and their naming can be adjusted according to specific implementation requirements. Specifically, the participating kernel set is an ordered set of kernel identifiers participating in the same call; the source address is the starting address of the data to be read from the local storage unit of the source kernel; the target address is the starting address of the result to be written from the local storage unit of the target kernel; the data length is the amount of data processed in this communication; reduction performs summation, maximum / minimum calculations, or logical operations on data units at the same offset; and the fragmentation method is used to limit the number and length of the reduction result fragments and their correspondence with the target kernel.

[0110] (2) The aggregate communication primitive interface maps the logical path of the aggregate communication algorithm to the physical transmission link between multiple cores through hardware topology analysis, thereby improving the bandwidth utilization of the interconnection between cores. Specifically, before aggregate communication, the communication domain participating in this communication is defined. This communication domain includes a group of cores participating in aggregate communication and the internal number of each core in the communication domain. After multiple cores are added to the communication domain, the aggregate communication primitive determines the data distribution order, data collection order, or reduction order according to the number in the communication domain. For example, cores 0, 4, 8, and 12 can be divided into the same communication domain and numbered 0, 1, 2, and 3 respectively in the communication domain. When All-Gather is executed, if the four cores provide input data A, B, C, and D respectively, the aggregate results received by each core are combined into ABCD according to the order corresponding to the internal number in the communication domain. During the communication domain initialization phase, the hardware topology between multiple cores is first read. Then, based on the pre-configured correspondence between the hardware topology and the communication algorithm, a target communication algorithm suitable for the current hardware topology is selected from the preset aggregated communication algorithms. Subsequently, the logical path corresponding to the target communication algorithm is mapped to the physical transmission link, and data transmission is executed according to the mapping result. When the hardware topology is ring-shaped, a ring communication algorithm is selected, that is, the logical path of the aggregated communication algorithm is mapped sequentially to the physical transmission link between adjacent cores according to the pre-configured core order in the communication domain. When the hardware topology is mesh-shaped, a mesh communication algorithm is selected, that is, the logical path of the aggregated communication algorithm is preferentially mapped to the physical transmission link based on XY routing or the shortest path.

[0111] (3) Data Flow Primitive Interface. Input tokens and output tokens are added to the set communication primitives to share progress states between communication-computation and / or communication-communication. The data flow primitive interface is not a separate set of interfaces independent of the set communication primitive interface, but rather an extension of the token mechanism introduced during the execution of communication and computation tasks. Before execution, an input token queue and an output token queue are registered. The input token queue represents the start condition of the current task, and the output token queue records the stage states formed during the execution of the current task. Tokens output by the preceding task are written into the input token queue of the subsequent task to form the input tokens for the subsequent task. During execution, the data to be transmitted is divided into multiple data blocks. When a data block is transmitted to the local storage unit of the target chip, an output token representing that the data block is ready is generated and written into the output token queue. Subsequent computation tasks or subsequent communication tasks that depend on the data block, upon detecting that the input token associated with the data block in their input token queue is ready, execute the corresponding computation or continue subsequent communication.

[0112] like Figure 5As shown, after completing a certain stage of processing, the preceding computation / communication task updates the output token representing the processing status of the corresponding target data block and writes the output token into the output token queue. Subsequent computation / communication tasks are in a waiting state until they detect that there is an input token in their input token queue that represents that the target data block is ready. When they detect that the input token has been updated to the ready state, they perform the corresponding operation. Taking matrix multiplication as an example, in the circular All-Gather process, if core C0 sequentially receives data blocks B1 and B2 from other cores, after receiving B1 in the first round, the communication task generates and outputs an output token Token_B1_arrived indicating that data block B1 has arrived, and updates the state of the input tokens associated with data block B1 in the input token queue of subsequent computation tasks to the ready state, thereby triggering the local computation of A0×B1. After receiving B2 in the second round, the communication task generates and outputs an output token Token_B2_arrived indicating that data block B2 has arrived, and updates the state of the input tokens associated with data block B2 in the input token queue of subsequent computation tasks to the ready state. After detecting that the input token is ready, subsequent computation tasks trigger the local computation of A0×B2 simultaneously with or after executing A0×B1. Thus, the computation process does not need to wait for all data blocks to be transmitted before starting uniformly, but rather progresses step by step as the input tokens corresponding to each data block turn to the ready state.

[0113] (4) The token mechanism transmits tokens within the core to reduce control overhead. Specifically, after a communication task completes the reception of a data block within the current core, an output token indicating that the data block is ready is generated within that core, and the output token is written to the output token queue. The computation task or subsequent communication task that depends on the data block checks whether the input tokens associated with that data block in its input token queue have been updated to the ready state within the same core, and performs corresponding operations when the input tokens meet the start conditions. The tokens output by the preceding task are written to the input token queue of the subsequent task to constitute the input tokens of the subsequent task. Since the generation, writing, detection, and consumption of tokens are all limited to within the same core, there is no need to perform cross-core control information transmission for state changes of each data block, thereby reducing the additional communication overhead introduced by state synchronization. Figure 6 As shown, the specific process includes: 1. Task start; 2. Check if the input token associated with the current processing stage has been updated to the ready state. If yes, proceed to step 3; otherwise, maintain the waiting state and return to step 2; 3. Determine if the input token is the end token. If no, proceed to step 4; if yes, proceed to step 6; 4. Execute the corresponding computation or communication operation based on the data block ready state represented by the input token; 5. Update the output token corresponding to the next processing stage after completing the current processing stage; 6. Task end.

[0114] Third: For distributed systems composed of multiple cores, a global communication-local computation programming model is adopted to orchestrate computational tasks using distributed algorithms, avoiding redundant data transfer between cores and thus reducing the need for cross-core data access. Specifically: (1) A distributed system consisting of multiple cores refers to a system that uses the aforementioned multi-core architecture as its physical carrier and abstracts each core into an independent execution unit at the software management level. Each execution unit corresponds to one core and can interact with other execution units during operation. Each execution unit can receive tasks assigned to it and perform corresponding processing based on the data in its local storage unit.

[0115] (2) Distributed algorithm orchestration refers to breaking down a complete computational task into multiple parallel subtasks (i.e., the aforementioned kernel-executable tasks) and distributing them to multiple execution units for execution. Each subtask processes the data portion or data range associated with its corresponding execution unit, and the computational result obtained after the collaborative completion of multiple subtasks is consistent with the result when the complete computational task is executed as a single whole. Distributed algorithm orchestration can predetermine the binding relationship between task identifiers and kernel identifiers during the software programming stage, and distribute the corresponding subtasks to the corresponding execution units based on this binding relationship during the runtime stage.

[0116] (3) The global communication-local computing programming model includes an input data communication stage, an execution unit computing stage, and an output data communication stage. The input data communication stage is used to move or copy the target data to the local storage unit of the corresponding execution unit's core according to the data dependencies required for subsequent computing before execution. The execution unit computing stage is used for each execution unit to execute its corresponding subtask, provided the required data already resides in the local storage unit. The output data communication stage is used to move, copy, and / or reduce the output results of each execution unit to form the target output result. For example... Figure 7 As shown, under the basic process, each execution unit completes its corresponding processing in the order of input data communication, execution unit calculation, and output data communication.

[0117] (4) The input data communication stage refers to the process of calling the aforementioned set communication primitives or data flow primitives to move the target data required for the subsequent computation stage to the local storage unit of the corresponding execution unit, so that each execution unit can obtain the required input data before executing the corresponding subtask. For subtasks that only rely on local data, there is no need to perform cross-core data transfer; for subtasks that rely on data from other cores, the corresponding data transfer is performed through the set communication primitive interface or data flow primitive interface.

[0118] (5) The execution unit computation phase refers to the process in which each execution unit reads the data required to execute the corresponding subtask from the local storage unit and no longer performs cross-execution unit storage unit access during the computation process. By pre-organizing the data required for computation into the local storage unit, the computation phase can mainly utilize local memory access bandwidth and local computing resources to complete the processing, thereby reducing the performance loss caused by cross-chip random memory access.

[0119] (6) The output data communication stage refers to the process of transferring, copying, and / or reducing the local calculation results according to the target output format after each execution unit has completed its local calculation, thereby completing the data output of the complete calculation task. When the target output results have been stored in the corresponding cores in a predetermined manner, no additional output data communication is required; when the target output results need to be centralized, broadcast, or reduced, the corresponding set communication primitive or data stream primitive is called to complete the processing.

[0120] (7) Both the input data communication stage and the output data communication stage can be completed by directly calling the set communication primitive or the data stream primitive, so as to isolate the details of distributed algorithm orchestration from the underlying communication implementation. The upper-level task orchestration only needs to determine the task allocation relationship of each execution unit, the required input data and the target output format, without directly specifying the underlying physical link, hop-by-hop routing process or specific data transport timing.

[0121] (8) The global communication-local computation programming model can include a single processing flow consisting of one input data communication, one execution unit computation, and one output data communication, or a combined processing flow consisting of multiple fine-grained input data communication, execution unit computation, and output data communication segments. For example... Figure 8 As shown, in a fine-grained processing flow, the input data communication stage can be divided into multiple input data communication parts. Each execution unit performs its corresponding computation between each input data communication part, and performs output data communication after completing all stage processing. When using dataflow primitives, multiple processing flows can be further subdivided into multiple stages that proceed step by step according to data blocks, so that the data communication of one stage overlaps with the local computation of another stage in time, thereby improving the overall processing efficiency.

[0122] The following example illustrates a matrix multiplication task using a multi-core architecture with three cores. In this application scenario, the physical interconnect bandwidth between the three cores is relatively limited, posing a risk of becoming a data transmission bottleneck in subsequent matrix multiplication tasks.

[0123] like Figure 9 As shown, the target application task is clearly defined as matrix multiplication C=AB. Wherein, as... Figure 9As shown in the input and output partitioning diagram, the left matrix A is partitioned into three independent data blocks A0, A1, and A2 along the row dimension; the right matrix B is partitioned into three independent data blocks B0, B1, and B2 along the column dimension. Initially, data blocks A0 and B0 are stored in the local storage unit of core 0, data blocks A1 and B1 are stored in the local storage unit of core 1, and data blocks A2 and B2 are stored in the local storage unit of core 2. For the result matrix C, the final goal is to output it in a column-partitioned form, meaning that result data block C0 is stored in core 0, result data block C1 is stored in core 1, and result data block C2 is stored in core 2. At the software execution level, by pre-writing driver logic and firmware instructions, these three cores can independently execute the computational or communication tasks sent to their local storage.

[0124] When performing matrix multiplication tasks using the set communication primitive interface, such as Figure 10 As shown, the execution flow is divided into three stages: the All-Gather input data communication stage, the independent computation stage for each core, and the output data stage. First, the All-Gather set communication primitive interface is called to perform input data communication. In this stage, cores 0, 1, and 2 send their data blocks A0, A1, and A2 from their local storage units to the other cores, respectively. After the All-Gather operation, each core has completely acquired all three data blocks A0, A1, and A2 of the left matrix A in its local storage unit. Then, the independent computation stage for each core begins. Core 0 reads the complete matrix A from its local storage unit and performs matrix multiplication with data block B0 to obtain the result data block C0; core 1 reads the complete matrix A and performs computation with data block B1 to obtain the result data block C1; core 2 reads the complete matrix A and performs computation with data block B2 to obtain the result data block C2. Since all the input data required for the computation has already been transferred to their respective local storage units in the previous stage, no cross-core data interaction occurs during this computation process. After the calculation is completed, since the resulting data blocks C0, C1, and C2 have been stored in the corresponding target cores as required, the current output result is taken as the final result, and there is no need to initiate additional output data communication operations (no communication required).

[0125] When performing matrix multiplication tasks using the dataflow primitive interface, such as Figure 11As shown, the entire distributed algorithm is decomposed and arranged into multiple fine-grained segments that alternate between global communication and local computation. The local computation tasks executed by each core are numbered as [1], [2], and [3], and the cross-core input data communication tasks (using point-to-point communication) are numbered as (1) and (2). In the local computation task [1] stage, each core performs local computation using the data initially residing locally, i.e., core 0 executes A0×B0, core 1 executes A1×B1, and core 2 executes A2×B2, and obtains the initial accumulated values ​​of the result blocks C0, C1, and C2 respectively. In the input data communication task (1) stage, core 0 sends A0 to core 2, core 1 sends A1 to core 0, and core 2 sends A2 to core 1. In the local computation task [2] stage, each core continues to perform local computation using the newly received data blocks, i.e., core 0 performs A1×B0, core 1 performs A2×B1, and core 2 performs A0×B2, and the computation results are accumulated into C0, C1, and C2 respectively. In the input data communication task (2) stage, each core continues to pass the data blocks received in the previous round to the next core, i.e., core 0 sends A1 to core 2, core 1 sends A2 to core 0, and core 2 sends A0 to core 1. In the local computation task [3] stage, each core completes the remaining computation using the data blocks received in the last round, i.e., core 0 performs A2×B0, core 1 performs A0×B1, and core 2 performs A1×B2. At this point, the full multiplication and addition operation is completed, and the target results C0, C1, and C2 have all been calculated and stored in the corresponding cores, and there is no need to perform subsequent output data communication.

[0126] like Figure 12 As shown, by analyzing the data dependencies of the above fine-grained alternation process, it can be seen that the local computing task [2] must utilize the new data chunks transmitted by the communication task (1) to be executed. Therefore, the local computing task [2] is strictly dependent on the completion of the communication task (1); similarly, the local computing task [3] is strictly dependent on the completion of the communication task (2). Based on this causal dependency, corresponding token semantics are designed to trigger the local computing task. Figure 13As shown, the specific process includes: 1. Task start; 2. Check whether the input token associated with the current processing stage has been updated to the ready state. If yes, proceed to 3; otherwise, maintain the waiting state; 3. Determine whether the input token is the end token. If no, proceed to 4; if yes, proceed to 5; 4. If the received input token indicates that the input data communication task (1) has been completed, then the execution of the local computation task is triggered [2]; if the received input token indicates that the input data communication task (2) has been completed, then the execution of the local computation task is triggered [3]; and so on. If the received input token indicates that the input data communication task (m) has been completed, then the execution of the local computation task [m+1] is triggered; 5. Task end. Through this token mechanism that strongly binds the data arrival status with the triggering condition, the pipeline overlap of data transmission time and computation time in the distributed matrix multiplication task under the multi-core granular encapsulation architecture is realized.

[0127] The following describes the multi-chip packaged chip provided in the embodiments of this application. See also... Figure 14 , Figure 14 This is a schematic diagram of the structure of a multi-chip packaged chip provided in an embodiment of this application. Here, the multi-chip packaged chip 1400 provided in this embodiment includes: multiple chips (including chips 1401-1 to 1401-M, where M is an integer greater than 1), packaged on the same packaging substrate, each chip including a local storage unit 14011; a communication unit 1402 for providing a hardware link between the multiple chips; and a scheduling management unit 1403 connected to the multiple chips and the communication unit; wherein, the scheduling management unit is configured to: receive a target task for the multi-chip packaged chip, the target task including at least multiple parallel chip computing tasks, each chip computing task being bound to a target chip executing the chip computing task, the multiple chips including each target chip; and, based on the target data address included in the target task, retrieve data from the target chip... Among the multiple cores, the source core containing the target data required to execute each core computation task is determined; if the target task involves cross-core data access, a target communication primitive for transporting the target data is determined, and a target communication algorithm that implements the target communication primitive and adapts to the core connection relationship between the multiple cores is determined; a primitive call request for the target communication primitive is sent to the communication unit, so that the communication unit responds to the primitive call request and, by executing the target communication algorithm that implements the target communication primitive, transports the target data from the source core to the local storage unit of each target core; for each target core, if the target data transport is completed, the target core is controlled to execute the core computation task based on the target data in the local storage unit.

[0128] In some embodiments, each of the chips further includes a local computing unit 14012, which is used to perform the chip computing task based on the target data of the local storage unit.

[0129] The following describes an exemplary structure of the task processing apparatus provided in the embodiments of this application. The task processing apparatus provided in the embodiments of this application is applied to a multi-chip packaged chip, which includes multiple chips and a communication unit connecting the multiple chips. In some embodiments, such as Figure 15 As shown, the software modules in the task processing device 1500 may include: a receiving module 1501, configured to receive a target task for the multi-chip packaged chip, the target task including at least a plurality of parallel chip computing tasks, each chip computing task being bound to a target chip for executing the chip computing task, the plurality of chips including each target chip; a first determining module 1502, configured to determine, based on the target data address included in the target task, the source chip containing the target data required to execute each chip computing task from the plurality of chips; and a second determining module 1503, configured to, if the target task involves cross-chip data access, determine the chip used to transfer the target data. The system identifies the target communication primitive and determines a target communication algorithm that implements the target communication primitive and adapts to the connection relationships between the multiple cores. A calling module 1504 sends a primitive call request to the communication unit for the target communication primitive, so that the communication unit responds to the primitive call request by executing the target communication algorithm that implements the target communication primitive, thereby transferring the target data from the source core to the local storage unit of each target core. A control module 1505, for each target core, if the target data transfer is complete, controls the target core to execute the core computation task based on the target data in the local storage unit.

[0130] In some embodiments, the second determining module 1503 is further configured to obtain the chip connection relationship between the plurality of chips in the multi-chip packaged chip; obtain the correspondence between a plurality of pre-configured candidate chip connection relationships and a plurality of communication algorithms, wherein the plurality of candidate chip connection relationships include the chip connection relationship; and, based on the correspondence, determine the communication algorithm corresponding to the chip connection relationship from the plurality of communication algorithms as the target communication algorithm.

[0131] In some embodiments, the second determining module 1503 is further configured to divide the source core and the target core participating in the cross-core data access into a communication domain, and assign corresponding communication domain internal numbers to the source core and the target core within the communication domain; initialize the communication domain, and obtain the core connection relationship during the initialization phase of the communication domain; wherein, the calling module 1504 is further configured to, if multiple source cores provide their respective target data, sequentially concatenate and combine the received multiple target data in the local storage unit of the target core according to the sorting rule of the communication domain internal number corresponding to the source core in the communication domain.

[0132] In some embodiments, the candidate core-particle connectivity includes ring connectivity and mesh connectivity, the ring connectivity has a correspondence with a ring communication algorithm, the mesh connectivity has a correspondence with a mesh communication algorithm, and the plurality of communication algorithms includes the ring communication algorithm and the mesh communication algorithm; the second determining module 1503 is further configured to, if the core-particle connectivity is the ring connectivity, use the ring communication algorithm corresponding to the ring connectivity as the target communication algorithm based on the correspondence; if the core-particle connectivity is the mesh connectivity, use the mesh communication algorithm corresponding to the mesh connectivity as the target communication algorithm based on the correspondence.

[0133] In some embodiments, the second determining module 1503 is further configured to, after determining the target communication algorithm that implements the target communication primitive and adapts to the connection relationship between the multiple cores, map the logical transmission path of the target communication algorithm onto the hardware link between the multiple cores; the calling module 1504 is further configured to send a primitive calling request including the hardware link to the communication unit, so that the communication unit responds to the primitive calling request, executes the target communication algorithm that implements the target communication primitive based on the hardware link, and moves the target data from the source core to the local storage unit of each target core.

[0134] In some embodiments, the second determining module 1503 is further configured to, if the core connection relationship is a ring connection relationship and the target communication algorithm is a ring communication algorithm, allocate the logical transmission path of the target communication algorithm hop-by-hop to the hardware link between two adjacent cores that are directly connected in physical location; if the core connection relationship is a mesh connection relationship and the target communication algorithm is a mesh communication algorithm, map the logical transmission path of the target communication algorithm to the hardware link that is sequentially connected in the first coordinate axis direction and the second coordinate axis direction, or map it to the hardware link with the smallest physical hop count.

[0135] In some embodiments, the target data includes N data blocks, where N is an integer greater than 1. The process of moving the target data from the source kernel to the local storage unit of each target kernel is a target communication task. The target communication task includes local communication tasks for each data block, and the kernel computation task includes local computation tasks for each data block. The calling module 1504 is further configured to issue a primitive call request for the target communication primitive to the communication unit, so that the communication unit responds to the primitive call request by executing the target communication algorithm that implements the target communication primitive, and performs the following processing: by executing the local communication task of the nth data block among the N data blocks, the nth data block is moved from the source kernel to the local storage unit of each target kernel, so that the target kernel generates an nth token based on the ready state of the nth data block, triggering the input token of the target kernel to be updated to the nth token, where n starts from 1 and increments by 1. The integer n is less than or equal to N; the control module 1505 is further configured to control the target core to perform the following processing: if the input token is detected to be updated to the nth token, execute the local computation task of the nth data block indicated by the nth token; wherein, during the execution of the local computation task of the nth data block indicated by the nth token by the target core, if n is less than N, the communication unit executes the local communication task of the (n+1)th data block, so that the target core generates the (n+1)th token based on the ready state of the (n+1)th data block, thereby triggering the input token of the target core to be updated to the (n+1)th token; this is repeated until the local communication task of the Nth data block is completed, and the input token of the target core is triggered to be updated to the Nth token; generate an end token inside the target core to update the input token of the target core to the end token; if the target core detects that the input token has been updated to the end token, it determines that the core computation task has been completed.

[0136] In some embodiments, the control module 1505 is further configured to, for each target chip, control the target chip to only access the target data in the local storage unit to execute the chip computation task, and during the execution of the chip computation task, restrict the target chip from initiating memory access requests for other chips, wherein the other chips are chips different from the target chip among the plurality of chips; the control module 1505 is further configured to, after each target chip has completed the corresponding chip computation task, generate local computation results for each target chip for the corresponding chip computation task; control the communication unit to call the data output communication primitive to perform a data aggregation operation on the local computation results generated by each target chip to obtain the total computation result of the target task.

[0137] In some embodiments, the control module 1505 is further configured to control the target chip to directly execute the other chip computing tasks based on the target data in the local storage unit if other chip computing tasks subsequently executed by the target chip need to use the target data, so as to realize the reuse of the target data in the target chip.

[0138] It should be noted that the description of the device embodiments in this application is similar to the description of the method embodiments described above, and has similar beneficial effects as the method embodiments, so it will not be repeated here. Any technical details not covered in the task processing device provided in the embodiments of this application can be understood based on the description of the technical details in the above method embodiments.

[0139] This application also provides an electronic device, which includes: a memory for storing computer-executable instructions; and a multi-chip packaged chip for implementing the task processing method provided in this application when executing the computer-executable instructions stored in the memory.

[0140] This application also provides a computer program product, which includes computer-executable instructions or a computer program stored in a computer-readable storage medium. When the computer-executable instructions or the computer program are executed by a multi-chip packaged chip, they implement the task processing method provided in this application.

[0141] This application also provides a computer-readable storage medium storing computer-executable instructions or computer programs. When the computer-executable instructions or computer programs are executed by a multi-chip packaged chip, the task processing method provided in this application is implemented.

[0142] In some embodiments, the computer-readable storage medium may be a memory such as RAM, ROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a variety of devices including one or any combination of the above-mentioned memories.

[0143] In some embodiments, computer-executable instructions may take the form of programs, software, software modules, scripts, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as stand-alone programs or as modules, components, subroutines, or other units suitable for use in a computing environment.

[0144] As an example, computer-executable instructions may, but do not necessarily, correspond to files in a file system. They may be part of a file of other programs or data, such as in one or more scripts stored in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple co-located files (e.g., files storing one or more modules, subroutines, or code sections).

[0145] As an example, computer-executable instructions can be deployed to execute on a single electronic device, or on multiple electronic devices located at one location, or on multiple electronic devices distributed across multiple locations and interconnected via a communication network.

[0146] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, and improvements made within the spirit and scope of this application are included within the scope of protection of this application.

Claims

1. A task processing method, characterized in that, The method, applied to multi-chip co-packaged chips, wherein the multi-chip co-packaged chip includes multiple chips and a communication unit connecting the multiple chips, includes: Receive a target task for the multi-chip packaged chip, the target task includes at least a plurality of parallel chip computing tasks, each chip computing task is bound to a target chip that executes the chip computing task, and the plurality of chips include each target chip. Based on the target data address included in the target task, the source core containing the target data required to execute each core computing task is determined from the plurality of cores; If the target task involves cross-core data access, determine the target communication primitive for transporting the target data, and determine the target communication algorithm that implements the target communication primitive and adapts to the core connection relationship between the multiple cores; A primitive call request for the target communication primitive is sent to the communication unit so that the communication unit responds to the primitive call request and executes the target communication algorithm that implements the target communication primitive to transfer the target data from the source core to the local storage unit of each target core. For each target chip, if the target data transfer is completed, the target chip is controlled to perform the chip calculation task based on the target data in the local storage unit.

2. The method as described in claim 1, characterized in that, The determination of the target communication algorithm that implements the target communication primitive and adapts to the core-core connection relationships among the multiple cores includes: Obtain the chip connection relationship between the multiple chips of the multi-chip packaged chip; Obtain the pre-configured correspondence between multiple candidate core connection relationships and multiple communication algorithms, wherein the multiple candidate core connection relationships include the core connection relationships; Based on the correspondence, a communication algorithm corresponding to the core-particle connection relationship is determined from the plurality of communication algorithms to serve as the target communication algorithm.

3. The method as described in claim 2, characterized in that, The step of obtaining the chip connection relationship between the multiple chips of the multi-chip packaged chip includes: The source and target particles participating in the cross-particle data access are divided into a communication domain, and corresponding internal communication domain numbers are assigned to the source and target particles within the communication domain. Initialize the communication domain, and during the initialization phase of the communication domain, obtain the core connection relationship; The step of transferring the target data from the source chip to the local storage unit of each target chip includes: If multiple source chips provide their respective target data, the received target data are sequentially concatenated and combined in the local storage unit of the target chip according to the sorting rules of the internal number of the source chip in the communication domain.

4. The method as described in claim 2, characterized in that, The candidate core particle connection relationships include ring connection relationships and grid connection relationships. The ring connection relationship has the corresponding relationship with the ring communication algorithm, and the grid connection relationship has the corresponding relationship with the grid communication algorithm. The multiple communication algorithms include the ring communication algorithm and the grid communication algorithm. The step of determining the communication algorithm corresponding to the core-particle connection relationship from the plurality of communication algorithms based on the correspondence relationship, and using it as the target communication algorithm, includes: If the core-particle connection relationship is the ring connection relationship, based on the correspondence, the ring communication algorithm corresponding to the ring connection relationship is used as the target communication algorithm; If the core-particle connection relationship is the same as the grid connection relationship, then based on the correspondence, the grid communication algorithm corresponding to the grid connection relationship is used as the target communication algorithm.

5. The method as described in claim 1, characterized in that, After determining the target communication algorithm that implements the target communication primitive and adapts to the core-to-core connection relationships among the multiple cores, the method further includes: The logical transmission path of the target communication algorithm is mapped to the hardware link between the multiple cores; The step of sending a primitive call request for the target communication primitive to the communication unit, so that the communication unit responds to the primitive call request by executing the target communication algorithm that implements the target communication primitive, and transferring the target data from the source chip to the local storage unit of each target chip, includes: The communication unit sends a primitive call request, which includes the hardware link, to the communication unit so that, in response to the primitive call request, the communication unit executes the target communication algorithm that implements the target communication primitive based on the hardware link, and moves the target data from the source chip to the local storage unit of each target chip.

6. The method as described in claim 5, characterized in that, The step of mapping the logical transmission path of the target communication algorithm to the hardware link between the multiple cores includes: If the core connection relationship is a ring connection relationship and the target communication algorithm is a ring communication algorithm, the logical transmission path of the target communication algorithm is allocated hop by hop to the hardware link between two adjacent cores that are directly connected in physical location; If the core-particle connection relationship is a mesh connection relationship and the target communication algorithm is a mesh communication algorithm, the logical transmission path of the target communication algorithm is mapped to a hardware link that is sequentially connected in the first coordinate axis direction and the second coordinate axis direction, or mapped to a hardware link with the smallest physical hop count.

7. The method according to any one of claims 1-6, characterized in that, The target data includes N data blocks, where N is an integer greater than 1. The step of moving the target data from the source chip to the local storage unit of each target chip is a target communication task. The target communication task includes local communication tasks for each data block. The chip computing task includes local computing tasks for each data block. The step of sending a primitive call request for the target communication primitive to the communication unit, so that the communication unit responds to the primitive call request by executing the target communication algorithm that implements the target communication primitive, and transferring the target data from the source chip to the local storage unit of each target chip, includes: A primitive call request for the target communication primitive is sent to the communication unit, so that the communication unit responds to the primitive call request by executing the target communication algorithm that implements the target communication primitive and performs the following processing: By executing the local communication task of the nth data block among the N data blocks, the nth data block is moved from the source core to the local storage unit of each target core, so that the target core generates the nth token based on the ready state of the nth data block, thereby triggering the input token of the target core to be updated to the nth token, where n is an integer starting from 1 and incrementing by 1, and n is less than or equal to N; The control of the target kernel to execute the kernel computing task based on the target data in the local storage unit includes: The target core is controlled to perform the following process: if the input token is detected to be updated to the nth token, the local computation task of the nth data block that is ready as indicated by the nth token is executed; Specifically, during the local computation task of the target core with the nth data block indicated by the nth token, if n is less than N, the communication unit executes the local communication task of the (n+1)th data block, so that the target core generates the (n+1)th token based on the ready state of the (n+1)th data block, thereby triggering the input token of the target core to be updated to the (n+1)th token; this process is repeated until the local communication task of the Nth data block is completed, and the input token of the target core is triggered to be updated to the Nth token; an end token is generated inside the target core to update the input token of the target core to the end token; If the target chip detects that the input token has been updated to the end token, it determines that the chip computing task has been completed.

8. The method according to any one of claims 1-6, characterized in that, The control of the target kernel to execute the kernel computing task based on the target data in the local storage unit includes: For each target core, the target core is controlled to access only the target data in the local storage unit to execute the core computing task, and during the execution of the core computing task, the target core is restricted from initiating memory access requests for other cores, wherein the other cores are cores that are different from the target core among the plurality of cores; The method further includes: After each target particle completes its corresponding particle calculation task, a local calculation result for each target particle for the corresponding particle calculation task is generated. The communication unit is controlled to call the data output communication primitive to perform a data aggregation operation on the local calculation results generated by each of the target core particles, so as to obtain the total calculation result of the target task.

9. The method according to any one of claims 1-6, characterized in that, The method further includes: If other kernel computing tasks subsequently executed by the target kernel require the use of the target data, the target kernel is controlled to directly execute the other kernel computing tasks based on the target data in the local storage unit, so as to realize the reuse of the target data in the target kernel.

10. A multi-chip packaged chip, characterized in that, The multi-chip packaged chip includes: Multiple chips are packaged on the same packaging substrate, and each chip includes a local memory cell; A communication unit is used to provide a hardware link between the plurality of cores; The scheduling and management unit is connected to the plurality of cores and the communication unit; The scheduling management unit is configured to: receive a target task for the multi-chip packaged chip, wherein the target task includes at least a plurality of parallel chip computing tasks, each chip computing task is bound to a target chip for executing the chip computing task, and the plurality of chips include each target chip; based on the target data address included in the target task, determine the source chip where the target data required to execute each chip computing task is located from the plurality of chips; if the target task involves cross-chip data access, determine a target communication primitive for transporting the target data, and determine a target communication algorithm that implements the target communication primitive and adapts to the chip connection relationship between the plurality of chips; send a primitive call request for the target communication primitive to the communication unit, so that the communication unit responds to the primitive call request and, by executing the target communication algorithm that implements the target communication primitive, transports the target data from the source chip to the local storage unit of each target chip; and for each target chip, if the target data transport is completed, control the target chip to execute the chip computing task based on the target data in the local storage unit.

11. A task processing device, characterized in that, An apparatus for use in multi-chip co-packaged chips, wherein the multi-chip co-packaged chip includes multiple chips and a communication unit connecting the multiple chips, the apparatus comprising: A receiving module is configured to receive a target task for the multi-chip packaged chip, wherein the target task includes at least a plurality of parallel chip computing tasks, each chip computing task is respectively bound to a target chip that executes the chip computing task, and the plurality of chips includes each target chip. The first determining module is used to determine, based on the target data address included in the target task, the source core containing the target data required to execute each core computing task from the plurality of cores; The second determining module is used to determine, if the target task involves cross-core data access, a target communication primitive for transporting the target data, and a target communication algorithm that implements the target communication primitive and is adapted to the core connection relationship between the multiple cores. The calling module is used to send a primitive calling request for the target communication primitive to the communication unit, so that the communication unit responds to the primitive calling request and, by executing the target communication algorithm that implements the target communication primitive, moves the target data from the source core to the local storage unit of each target core; The control module is used to control each target chip to perform the chip computing task based on the target data in the local storage unit, once the target data transfer is completed.

12. An electronic device, characterized in that, The electronic device includes: Memory is used to store executable instructions for a computer; A multi-chip packaged chip, when executing computer-executable instructions stored in the memory, implements the task processing method according to any one of claims 1 to 9.

13. A computer-readable storage medium storing computer-executable instructions or a computer program, characterized in that, When the computer-executable instructions or computer program are executed by the multi-chip packaged chip, the task processing method described in any one of claims 1 to 9 is implemented.

14. A computer program product comprising computer-executable instructions or a computer program, characterized in that, When the computer-executable instructions or computer program are executed by the multi-chip packaged chip, the task processing method described in any one of claims 1 to 9 is implemented.

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