A processing method of a DMA transfer unit

Abstract

The application relates to the chip technical field, in particular to a processing method of a DMA (Direct Memory Access) carrying unit. The method comprises the following steps: issuing a first data packet to a candidate DMA carrying unit; obtaining the number of in-flight requests of a first buffer in each clock cycle during carrying the first data packet, and determining the ratio of the total number of requests to the number of requests of the first data packet as an average delay time; if the number of requests of a second data packet and the number of clock cycles included in the average delay time are both greater than the maximum number of unfinished transactions of a single DMA carrying unit, determining the number N of DMAs to which the second data packet is allocated according to the number of requests of the second data packet, the number of clock cycles included in the average delay time and the maximum number of unfinished transactions; if N is greater than or equal to 2 and less than or equal to the number of idle DMA carrying units, splitting the second data packet and allocating the second data packet to N idle DMA carrying units for carrying respectively. The application can improve the bandwidth utilization.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a processing method for a DMA transport unit. Background Technology

[0002] The data transfer capacity of a single Direct Memory Access (DMA) transfer unit is limited. To improve this capacity, existing technologies have developed schemes that use multiple DMA transfer units. However, these schemes allocate DMA transfer units based solely on packet size, assigning more units to larger packets and fewer to smaller packets. However, the data transfer process of a DMA transfer unit is limited by the maximum number of outstanding transactions it can support. Therefore, the scheme that determines the number of DMA transfer units solely based on packet size may encounter the following problems:

[0003] When the data packets are small, the number of DMA transfer units allocated is small, for example, only one DMA transfer unit is allocated. If the data transfer process of the DMA transfer unit has a long delay time, the DMA transfer unit may be forced to stop sending new requests after sending the maximum number of requests for uncompleted transactions, until the response to the sent requests is returned. During this period, the high-speed bus is in an idle waiting state, and the bandwidth utilization is low.

[0004] When the data packets are large, a large number of DMA transfer units are allocated. However, when the data transfer process of the DMA transfer units has a short delay time, a small number of DMA transfer units can send a sufficient number of requests continuously within that delay time by virtue of their maximum number of outstanding transactions, thereby saturating the bus bandwidth. In this case, even if more DMA transfer units are allocated, the bandwidth will not increase. Instead, it will occupy a large number of DMA transfer units, resulting in waste of resources and additional data packet splitting overhead. Summary of the Invention

[0005] The purpose of this invention is to provide a processing method for a DMA transfer unit to solve the aforementioned problems existing in the current DMA allocation scheme.

[0006] According to the present invention, a processing method for a DMA transport unit is provided, the method comprising the following steps:

[0007] S100, the first data packet is sent to the candidate DMA transfer unit; the candidate DMA transfer unit is any idle DMA transfer unit; DMA is direct memory access.

[0008] S200, obtain the number of in-flight requests in the first buffer during each clock cycle in the process of the candidate DMA transfer unit transferring the first data packet, and determine the ratio of the sum of the number of in-flight requests in the first buffer during each clock cycle to the number of requests for the first data packet as the average delay time in the process of the candidate DMA unit transfer; the in-flight request is a request that has been sent but has not received a response.

[0009] S300, if the number of requests for the second data packet and the number of clock cycles included in the average latency are both greater than the maximum number of uncompleted transactions in a single DMA transfer unit, then proceed to S400.

[0010] S400, determine the number N of DMAs to be allocated to the second data packet based on the number of requests for the second data packet, the number of clock cycles included in the average latency time, and the maximum number of uncompleted transactions in a single DMA transport unit.

[0011] S500, if N≥2 and N is less than or equal to the number of idle DMA transport units, then the second data packet is split into N sub-data packets and assigned to N idle DMA transport units for transport respectively.

[0012] Compared with the prior art, the present invention has at least the following beneficial effects:

[0013] In this invention, a first data packet is sent to a candidate DMA transport unit (any idle DMA transport unit). The average latency during the transport process of the candidate DMA unit is obtained by counting the number of in-flight requests in the first buffer during each clock cycle. When a second data packet exists, if the number of requests for the second data packet and the number of clock cycles included in the average latency are both greater than the maximum number of uncompleted transactions for a single DMA transport unit, then the number N of DMAs to be allocated to the second data packet is determined based on the number of requests for the second data packet, the number of clock cycles included in the average latency, and the maximum number of uncompleted transactions for a single DMA transport unit. If N ≥ 2 and N is less than or equal to the number of idle DMA transport units, then the second data packet is split into N sub-data packets and allocated to N idle DMA transport units for transport. Therefore, this invention can comprehensively determine the number of DMA transport units allocated to a data packet based on the average latency during the data packet transport process of the DMA transport unit, the maximum number of uncompleted transactions in a single DMA transport unit, and the number of data packet requests. This ensures that the number of DMA transport units allocated to the data packet matches the latency during the DMA transport process and the maximum number of uncompleted transactions in the DMA transport unit. This invention is applicable to scenarios with different transport latency and different maximum number of uncompleted transactions. It can solve the problems of low bandwidth utilization, resource waste, and additional data packet splitting overhead that exist in the prior art scheme that determines the number of DMA transport units allocated to a data packet only based on the size of the data packet. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a flowchart of the processing method of the DMA transport unit provided in Embodiment 1 of the present invention;

[0016] Figure 2 This is a schematic diagram of the interaction between the DMA transport unit and the address translation unit provided in Embodiment 2 of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Example 1:

[0019] According to this embodiment, a processing method for a DMA transport unit is provided, the method including the following steps, such as... Figure 1 As shown:

[0020] S100, the first data packet is sent to the candidate DMA transfer unit; the candidate DMA transfer unit is any idle DMA transfer unit; DMA is direct memory access.

[0021] In this embodiment, multiple DMA transport units are provided, and the data packets are distributed through the DMA distribution module.

[0022] In this embodiment, an idle DMA transfer unit refers to a DMA transfer unit that has not been assigned a data transfer task.

[0023] In this embodiment, the first data packet is used to determine the average delay time during the transfer of candidate DMA units.

[0024] S200, obtain the number of in-flight requests in the first buffer during each clock cycle in the process of the candidate DMA transfer unit transferring the first data packet, and determine the ratio of the sum of the number of in-flight requests in the first buffer during each clock cycle to the number of requests for the first data packet as the average delay time in the process of the candidate DMA unit transfer; the in-flight request is a request that has been sent but has not received a response.

[0025] In this embodiment, the data packet request is a request sent to the target memory by the DMA transfer unit during the data packet transfer process.

[0026] In this embodiment, the first buffer is used to temporarily store requests for data packets in flight. The depth of the first buffer is greater than or equal to the maximum number of uncompleted transactions in a single DMA transfer unit to prevent the first buffer from running out of space to record requests for data packets in flight, thus preventing data overflow / loss.

[0027] In one specific implementation, the process of the candidate DMA transfer unit transferring the first data packet includes a total of Q clock cycles, where the number of in-flight requests in the first buffer during the q-th clock cycle is p. q The value of q ranges from 1 to Q; the number of requests for the first data packet is R, then the number of clock cycles included in the average delay time during the candidate DMA unit transfer process is: ∑ Q q=1 p q / R.

[0028] In this embodiment, a larger average delay time during the transfer by the candidate DMA unit indicates a longer time interval from when the candidate DMA transfer unit sends a data packet request to the target memory to when a response is received. In this case, the problem that the maximum number of outstanding transactions of the candidate DMA transfer unit cannot cover the average delay time during the transfer by the candidate DMA unit is prone to occur, which leaves the high-speed bus in an idle state and results in low bandwidth utilization. For example: the maximum number of outstanding transactions of the candidate DMA transfer unit is N1. Before the number of in-flight requests of the candidate DMA transfer unit reaches N1, the candidate DMA transfer unit sends one request per clock cycle; the average delay time during the transfer by the candidate DMA unit is N2 clock cycles. If N2>N1, when the number of in-flight requests of the candidate DMA transfer unit reaches N1, the candidate DMA transfer unit still needs to wait for N2-N1 clock cycles before receiving a response, and then can issue a new request for a data packet; thus, the high-speed bus will be in an idle waiting state for N2-N1 clock cycles, which reduces bandwidth utilization.

[0029] In this embodiment, a smaller average delay time during the transfer by the candidate DMA unit indicates a shorter time interval from when the candidate DMA transfer unit sends a data packet request to the target memory to when a response is received. In this case, the maximum number of outstanding transactions of the candidate DMA transfer unit can cover the average delay time during the transfer by the candidate DMA unit, the high-speed bus will not be in an idle state, and bandwidth utilization can be improved. For example: the maximum number of outstanding transactions of the candidate DMA transfer unit is N1. Before the number of in-flight requests of the candidate DMA transfer unit reaches N1, the candidate DMA transfer unit sends one request per clock cycle; the average delay time during the transfer by the candidate DMA unit is N2 clock cycles. If N2<N1, the candidate DMA transfer unit has already received the response returned by the previous request before the number of in-flight requests of the candidate DMA transfer unit reaches N1, which enables the candidate DMA transfer unit to continuously issue data packet requests; thus, the high-speed bus will not be in an idle waiting state, and bandwidth utilization is relatively high.

[0030] In this embodiment, when different DMA transfer units perform data transfer, they share the same path, and it is determined that the average delay time during transfer of the candidate DMA transfer unit is also the average delay time during transfer of other DMA transfer units.

[0031] S300, if both the number of requests of the second data packet and the number of clock cycles included in the average delay time are greater than the maximum number of outstanding transactions of a single DMA transfer unit, proceed to S400.

[0032] In this embodiment, the second data packet is any data packet to be transferred.

[0033] Those skilled in the art will know that the number of requests for the second data packet can be determined based on the size of the second data packet and the amount of data that a single request can carry. For example, if the size of the second data packet is 2KB and the amount of data that a single request can carry is 256 bytes, then the number of requests for the second data packet is 2KB / 256 bytes = 8.

[0034] In this embodiment, S300 further includes: if the number of requests for the second data packet is less than or equal to the maximum number of uncompleted transactions for a single DMA transfer unit, or if the number of clock cycles included in the average latency is less than or equal to the maximum number of uncompleted transactions for a single DMA transfer unit, then the second data packet is not split, and the second data packet is sent to any idle DMA transfer unit for transfer. It should be understood that if both the number of requests for the second data packet and the number of clock cycles included in the average latency are less than or equal to the maximum number of uncompleted transactions for a single DMA transfer unit, the second data packet is also not split, and the second data packet is sent to any idle DMA transfer unit for transfer.

[0035] S400, determine the number N of DMAs to be allocated to the second data packet based on the number of requests for the second data packet, the number of clock cycles included in the average latency time, and the maximum number of uncompleted transactions in a single DMA transport unit.

[0036] As an optional implementation, N = ceil(min(a / c, b / c)), where ceil is rounded up, a is the number of requests for the second data packet, b is the number of clock cycles included in the average latency, and c is the maximum number of uncompleted transactions in a single DMA transfer unit. This implementation prioritizes bandwidth utilization and is suitable for scenarios with a relatively large number of idle DMA transfer units.

[0037] As another optional implementation, if min(a / c,b / c) - floor(min(a / c,b / c)) is greater than a preset difference threshold, then floor(min(a / c,b / c)) + 1 is determined as N; otherwise, max(1,floor(min(a / c,b / c))) is determined as N; 0 ≤ preset difference threshold < 0.5, min is the minimum value, max is the maximum value, a is the number of requests for the second data packet, b is the number of clock cycles included in the average latency time, and c is the maximum number of uncompleted transactions in a single DMA transfer unit. It should be understood that when the preset difference threshold is large, it means that an additional DMA transfer unit is allocated only when the fractional part of min(a / c,b / c) is large; when the preset difference threshold is small, it means that an additional DMA transfer unit can be allocated when the fractional part of min(a / c,b / c) is small. In practical applications, the preset difference threshold can be set according to requirements, for example, the preset difference threshold is 0.1 or 0.2, etc. This specific implementation takes into account both bandwidth utilization and the number of DMA transport units allocated to data packets, making it suitable for scenarios with a relatively small number of idle DMA transport units.

[0038] S500, if N≥2 and N is less than or equal to the number of idle DMA transport units, then the second data packet is split into N sub-data packets and assigned to N idle DMA transport units for transport respectively.

[0039] In this embodiment, after the data packet is split, the resulting sub-data packets are of equal size, meaning that the number of requests in the resulting sub-data packets is the same.

[0040] In this embodiment, S500 further includes: if N=1, then the second data packet is not split, and the second data packet is sent to any idle DMA transport unit for transport.

[0041] In this embodiment, S500 further includes: if N is greater than the number of idle DMA transport units Q and Q≥2, then the second data packet is split into Q sub-data packets and allocated to the Q idle DMA transport units for transport respectively.

[0042] In this embodiment, S500 further includes: if N is greater than the number of idle DMA transfer units Q and Q=1, then the second data packet is not split, and the second data packet is sent to any idle DMA transfer unit for transfer.

[0043] In one specific implementation, data packets are split and distributed to multiple idle DMA transport units for transport. These multiple DMA transport units issue requests in a time-sharing manner through arbitration during the transport process. For example, the maximum number of incomplete transactions for a single DMA transport unit is 10, and the average latency during the transport process of a DMA transport unit is 15 clock cycles. After the data packets are split, they are allocated to the first DMA transport unit and the second DMA transport unit. The first DMA transport unit issues 10 requests (occupying 10 clock cycles), and after switching to the second DMA transport unit, the second DMA transport unit also issues 10 requests (also occupying 10 clock cycles). When switching back to the first DMA transport unit, the first DMA transport unit can still issue 10 requests (because the requests issued by the first DMA transport unit have returned responses after a 15-clock-cycle delay). When switching back to the second DMA transport unit, the second DMA transport unit can also issue 10 requests (because the requests issued by the second DMA transport unit have returned responses after a 15-clock-cycle delay), and so on. This can achieve high bandwidth utilization.

[0044] In this embodiment, the first data packet is sent to the candidate DMA transport unit (any idle DMA transport unit). The average latency during the transport process of the candidate DMA unit is obtained by the number of in-flight requests in the first buffer during each clock cycle. When a second data packet exists, if the number of requests for the second data packet and the number of clock cycles included in the average latency are both greater than the maximum number of uncompleted transactions of a single DMA transport unit, then the number N of DMAs to be allocated to the second data packet is determined according to the number of requests for the second data packet, the number of clock cycles included in the average latency, and the maximum number of uncompleted transactions of a single DMA transport unit. If N≥2 and N is less than or equal to the number of idle DMA transport units, then the second data packet is split into N sub-data packets and allocated to N idle DMA transport units for transport respectively. Therefore, this embodiment can comprehensively determine the number of DMA transport units allocated to a data packet based on the average latency during the data packet transport process of the DMA transport unit, the maximum number of uncompleted transactions of a single DMA transport unit, and the number of data packet requests. This ensures that the number of DMA transport units allocated to the data packet matches the latency during the DMA transport process and the maximum number of uncompleted transactions of the DMA transport unit. It can be applied to scenarios with different transport latency and different maximum number of uncompleted transactions, and can solve the problems of low bandwidth utilization, resource waste, and additional data packet splitting overhead that exist in the prior art scheme that determines the number of DMA transport units allocated to a data packet only based on the size of the data packet.

[0045] Example 2:

[0046] For any DMA transport unit, during the data packet writing process, it needs to obtain the physical address corresponding to the virtual address in the request of the received data packet. To mask the high latency (memory access latency) of obtaining the physical address, existing DMA transport units use a prefetch page table approach, requiring a large number of page tables to be prefetched. Correspondingly, the DMA transport unit also needs to allocate significant resources to store the prefetched page tables (e.g., using a FIFO queue with a depth equal to the maximum number of incomplete transactions or deeper). This results in a significant time required for the DMA transport unit to consume the prefetched page table data if an anomaly occurs (e.g., an upstream instruction to terminate data packet transport). This leads to a prolonged anomaly handling time, impacting anomaly handling efficiency. To address this issue, this embodiment, based on Embodiment 1, further includes a data packet writing process corresponding to each allocated data packet DMA transport unit. This process includes:

[0047] S510, page table mapping entries covering the entire virtual address range of the target data packet to be written are preloaded and locked in the internal cache of the address translation unit; the virtual address range corresponding to the target data packet is continuous.

[0048] In this embodiment, the virtual address range corresponding to the target data packet is represented continuously: the virtual address corresponding to the target data packet increases byte by byte without interruption; for example, from 0x100 to 0x2FF, or from 0x0000_1000 to 0x0000_3FFF, etc. It should be understood that the target data packet is the data packet that the DMA transport unit needs to transport.

[0049] In this embodiment, the page table entry (PTE) covering the entire virtual address range of the target data packet to be written is preloaded and locked in the internal cache (Translation Lookaside Buffer, TLB) of the Memory Management Unit (MMU). Thus, after the DMA transfer unit sends the virtual address (VA) corresponding to the target data packet to the address transfer unit, the address transfer unit can quickly return the physical address (PA) corresponding to the virtual address to the DMA transfer unit.

[0050] In one specific implementation, page table mapping entries covering the entire virtual address range of the target data packet to be written are pre-loaded into the internal cache of the address translation unit through a warm-up process. For example, performing a virtual read of all virtual addresses covered by the target data packet in steps of page size can trigger the address translation unit to pre-load all necessary page table mapping entries into its internal cache.

[0051] S520 extracts virtual addresses starting from the virtual start address corresponding to the target data packet with the first granularity as the step size, and writes the first m extracted virtual addresses into the virtual address FIFO in sequence; m is the number of entries included in the virtual address FIFO, and m is less than the maximum number of uncompleted transactions of the DMA transfer unit.

[0052] In this embodiment, the first granularity is the granularity at which the target data packet is split and sent according to requests. For example, if the first granularity is 256 bytes and the data packet is 2KB, then the number of requests corresponding to the target data packet is 8, and the data volume corresponding to each request is 256 bytes. Accordingly, the virtual addresses extracted starting from the virtual start address corresponding to the target data packet with the first granularity as the step size are: addr0, addr0+256Byte, addr0+512Byte, addr0+768Byte, addr0+1024Byte, addr0+1280Byte, addr0+1536Byte, and addr0+1792Byte, where addr0 is the virtual start address corresponding to the target data packet. When m=4, the first m extracted virtual addresses are written into the virtual address FIFO in sequence, meaning that addr0, addr0+256Byte, addr0+512Byte, and addr0+768Byte are written into the virtual address FIFO in sequence.

[0053] In this embodiment, the maximum number of incomplete transactions for the DMA transfer unit indicates the maximum number of transactions that the DMA transfer unit can have incomplete at the same time. For example, a maximum number of incomplete transactions of 8 means that the DMA transfer unit can continuously send a maximum of 8 address translation requests to the address translation unit without waiting for the first address translation request to complete; and the 9th address translation request can only be sent after the first address translation request has been completed. In this embodiment, the order in which the address translation requests sent by the DMA transfer unit to the address translation unit is consistent with the order in which the addresses returned by the address translation unit are received.

[0054] In this embodiment, m is less than the maximum number of incomplete transactions in the DMA transfer unit. As a specific implementation, the process of obtaining m includes:

[0055] S521 preloads and locks page table mapping entries covering the entire virtual address range of the test data packet into the internal cache of the address translation unit.

[0056] In this embodiment, the test data packet is a data packet used to obtain the average delay time of address translation during DMA unit handling.

[0057] S522, obtain the number of in-flight requests in the second buffer during each clock cycle in the process of the DMA transfer unit sending the address translation request corresponding to the test data packet to the address translation unit, and determine the ratio of the sum of the number of in-flight requests in the second buffer in each clock cycle to the number of address translation requests corresponding to the test data packet as the average delay time for the DMA unit to perform address translation; the depth of the second buffer is greater than or equal to the maximum number of uncompleted transactions of the DMA transfer unit.

[0058] In this embodiment, the second buffer is used to cache address translation requests in flight. The depth of the second buffer is greater than or equal to the maximum number of uncompleted transactions in a single DMA transfer unit to prevent the second buffer from running out of space to record address translation requests in flight, thus preventing data overflow / loss.

[0059] S523, obtains m based on the number of clock cycles included in the average delay time for address translation during DMA unit handling.

[0060] As a specific implementation, the average delay time for address translation during DMA unit handling is determined by rounding up to the nearest clock cycle, which is m.

[0061] In this embodiment, after the page table mapping entries covering the entire virtual address range of the data packet are pre-loaded and locked in the internal cache of the address translation unit, during the process of the DMA transport unit sending the address translation request corresponding to the data packet to the address translation unit, the virtual addresses in the address translation request can all be hit in the internal cache of the address translation unit. Therefore, the delay of the address translation unit returning the physical address is small, and the number of clock cycles included in the average delay time of the DMA unit for address translation is also small. If the number of clock cycles included in the average delay time of the DMA unit for address translation is rounded up to m, then m is also small compared to the maximum number of uncompleted transactions of the DMA transport unit. Compared to setting m as the maximum number of uncompleted transactions of the DMA transport unit, the number of entries included in the virtual address FIFO in this embodiment is small.

[0062] S530, the DMA transfer unit pops m virtual addresses from the virtual address FIFO in sequence and sends them to the address translation unit for conversion from virtual address to physical address. The physical address returned by the address translation unit is then written into the physical address FIFO in sequence. Each time the virtual address FIFO is popped, other extracted virtual addresses are written into it in sequence until there are no more virtual addresses among the extracted virtual addresses that have not been written into the virtual address FIFO.

[0063] In this embodiment, the number of entries in the virtual address FIFO is equal to the number of entries in the physical address FIFO.

[0064] It should be understood that after popping the earliest written virtual start address from the virtual address FIFO, there will be one unwritten entry remaining in the virtual address FIFO. If there are still virtual addresses among the extracted virtual addresses that have not been written to the virtual address FIFO, then the virtual address closest to the virtual start address corresponding to the target data packet among the extracted virtual addresses that have not been written to the virtual address FIFO will be written to the virtual address FIFO. For example, if the virtual address FIFO contains 4 entries, the virtual addresses extracted starting from the virtual start address corresponding to the target data packet with the first granularity as the step size are: addr0, addr0+256Byte, addr0+512Byte, addr0+768Byte, addr0+1024Byte, addr0+1280Byte, addr0+1536Byte, and addr0+1792Byte. Then, addr0, addr0+256Byte, addr0+512Byte, and addr0+768Byte are sequentially stored in the virtual address FIFO. When addr0 is popped, addr0+1024Byte is written into the virtual address FIFO; when addr0+256Byte is popped, addr0+1280Byte is written into the virtual address FIFO, and so on.

[0065] S540, if the DMA transfer unit receives the write request of the target data packet, it pops the physical address with the earliest write time from the physical address FIFO and uses it as the physical address corresponding to the virtual address in the write request of the received target data packet, and sends the generated write request with the physical address to the target memory; wherein, each time a physical address is popped from the physical address FIFO, a virtual address is popped from the virtual address FIFO, until the virtual address FIFO is empty; the write request of the target data packet is generated by segmenting the target data packet with the first granularity and sent to the DMA transfer unit in sequence.

[0066] In this embodiment, the write request for the target data packet is sent from the upstream to the DMA transfer unit. The write request for the target data packet received by the DMA transfer unit carries a virtual address. The DMA transfer unit needs to convert the virtual address carried in the write request of the received target data packet into the corresponding physical address before sending the write request carrying the physical address to the target memory. Figure 2 As shown. Here, "target storage" refers to the object to which data in the target data packet is written, such as memory.

[0067] In this embodiment, the write request for the target data packet is generated by segmenting the target data packet at the first granularity and sent sequentially to the DMA transfer unit. Therefore, the physical addresses in the physical address FIFO correspond to the virtual addresses in the write requests of the target data packet received by the DMA transfer unit. For example, the virtual starting address of the first write request of the target data packet received by the DMA transfer unit is addr0, and the first physical address written to and popped from the physical address FIFO is the physical address corresponding to addr0; the virtual starting address of the second write request of the target data packet received by the DMA transfer unit is addr0+256Byte, and the second physical address written to and popped from the physical address FIFO is the physical address corresponding to addr0+256Byte; and so on.

[0068] In this embodiment, a physical address prefetch state machine is designed in conjunction with a virtual address FIFO and a physical address FIFO. As a specific implementation, before S520, the state of the physical address prefetch state machine is first obtained. S520 is only executed if the physical address prefetch state machine is in the initialization state. When the physical address prefetch state machine is in the initialization state, both the virtual address FIFO and the physical address FIFO are empty. This ensures the accuracy of the subsequent DMA transfer unit in processing the request corresponding to the target data packet.

[0069] The physical address prefetch state machine includes an idle state, an initialization state, and an update state. The conditions for switching from the idle state to the initialization state include detecting a valid write address channel signal, an empty virtual address FIFO, and an empty physical address FIFO. The conditions for switching from the initialization state to the update state include the DMA transfer unit receiving a write request. The conditions for switching from the update state to the idle state include both the virtual address FIFO and the physical address FIFO being empty or an anomaly occurring. When an anomaly occurs, the method further includes the step of clearing the virtual address FIFO and the physical address FIFO. The anomaly includes an instruction from upstream to terminate the transfer of the target data packet.

[0070] Compared to Embodiment 1, this embodiment has the following advantages: First, page table mapping entries covering the entire virtual address range of the target data packet to be written are pre-loaded and locked in the internal cache of the address translation unit. This reduces the latency between the DMA transfer unit sending the virtual address to the address translation unit and the address translation unit returning the physical address. Furthermore, in scenarios where the virtual address range corresponding to the target data packet is continuous, this embodiment writes the virtual starting address of each request corresponding to the target data packet into the virtual address FIFO, sequentially sends the virtual addresses in the virtual address FIFO to the address translation unit, and sequentially stores the physical addresses returned by the address translation unit into the physical address FIFO. If the DMA transfer unit… Upon receiving a request for a target data packet, the physical addresses in the physical address FIFO are sequentially used as the physical addresses corresponding to the virtual addresses in the request. This improves the efficiency of the DMA transfer unit in issuing write requests with physical addresses to the target memory. Moreover, since the DMA transfer unit has a low latency in acquiring physical addresses, the number of entries in the virtual address FIFO and physical address FIFO does not need to be large, meaning that the storage resources corresponding to the virtual address FIFO and physical address FIFO are relatively small. Even if an abnormal situation occurs, because the storage resources corresponding to the virtual address FIFO and physical address FIFO are small, the time spent consuming the address data in the virtual address FIFO and physical address FIFO is also short, improving the efficiency of abnormal handling.

[0071] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. It should also be understood that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A processing method for a DMA transport unit, characterized in that, The method includes the following steps: S100, the first data packet is sent to the candidate DMA transfer unit; the candidate DMA transfer unit is any idle DMA transfer unit; DMA is direct memory access. S200, obtain the number of in-flight requests in the first buffer during each clock cycle in the process of the candidate DMA transfer unit transferring the first data packet, and determine the ratio of the sum of the number of in-flight requests in the first buffer during each clock cycle to the number of requests for the first data packet as the average delay time in the process of the candidate DMA unit transfer; the in-flight request is a request that has been sent but has not received a response. S300, if the number of requests for the second data packet and the number of clock cycles included in the average delay time are both greater than the maximum number of uncompleted transactions in a single DMA transport unit, then proceed to S400; S400, determine the number N of DMAs to be allocated to the second data packet based on the number of requests for the second data packet, the number of clock cycles included in the average latency time, and the maximum number of uncompleted transactions in a single DMA transport unit; S500, if N≥2 and N is less than or equal to the number of idle DMA transport units, then the second data packet is split into N sub-data packets and assigned to N idle DMA transport units for transport respectively.

2. The processing method of the DMA transport unit according to claim 1, characterized in that, N = ceil(min(a / c,b / c)), where ceil is rounded up, a is the number of requests for the second data packet, b is the number of clock cycles included in the average latency, and c is the maximum number of uncompleted transactions in a single DMA transfer unit.

3. The processing method of the DMA transport unit according to claim 1, characterized in that, The S400 includes: If min(a / c,b / c)-floor(min(a / c,b / c)) is greater than the preset difference threshold, then floor(min(a / c,b / c))+1 is determined as N; otherwise, max(1,floor(min(a / c,b / c))) is determined as N; 0≤preset difference threshold<0.5, min is the minimum value, max is the maximum value, a is the number of requests for the second data packet, b is the number of clock cycles included in the average latency time, and c is the maximum number of uncompleted transactions in a single DMA transfer unit.

4. The processing method of the DMA transfer unit according to claim 1, characterized in that, S500 also includes: if N=1, then the second data packet is not split, and the second data packet is sent to any idle DMA transport unit for transport.

5. The processing method of the DMA transport unit according to claim 1, characterized in that, S500 also includes: if N is greater than the number of idle DMA transport units Q and Q≥2, then the second data packet is split into Q sub-data packets and assigned to Q idle DMA transport units for transport respectively.

6. The processing method of the DMA transfer unit according to claim 1, characterized in that, S500 further includes: if N is greater than the number of idle DMA transfer units Q and Q=1, then the second data packet is not split and the second data packet is sent to any idle DMA transfer unit for transfer.

7. The processing method of the DMA transport unit according to claim 1, characterized in that, The depth of the first buffer is greater than or equal to the maximum number of uncompleted transactions in a single DMA transfer unit.

8. The processing method of the DMA transport unit according to claim 1, characterized in that, S300 further includes: if the number of requests for the second data packet is less than or equal to the maximum number of uncompleted transactions in a single DMA transfer unit, or if the number of clock cycles included in the average delay time is less than or equal to the maximum number of uncompleted transactions in a single DMA transfer unit, then the second data packet is not split, and the second data packet is sent to any idle DMA transfer unit for transfer.

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