Method, device and chip for multi-queue descriptor equalization scheduling

Abstract

The application relates to the technical field of DMA data transmission, and discloses a multi-queue descriptor equalization scheduling method. The method comprises the following steps: obtaining a first residual moving length of a first descriptor at the head of a current queue; in the case that the first residual moving length is smaller than an initial residual equalization length, generating a first slice descriptor according to the first residual moving length, updating the initial residual equalization length to the first residual equalization length, and generating one or more second slice descriptors according to the first residual equalization length and DMA moving lengths of one or more second descriptors; transmitting the first slice descriptor and the one or more second slice descriptors to a rear-stage DMA hardware moving engine; and updating the residual moving length of the descriptor at the head of the current queue, and rotating the current queue to a next queue. The method can more evenly schedule the descriptors in different descriptor queues. The application further discloses a multi-queue descriptor equalization scheduling device and a chip.

Description

Technical Field

[0001] This application relates to the field of DMA data transfer technology, and for example to a method, apparatus and chip for balanced scheduling of descriptors between multiple queues. Background Technology

[0002] Direct Memory Access (DMA) technology enables data to be transferred directly from one memory to another with minimal or no CPU involvement, thus freeing up CPU resources and making DMA technology widely applicable.

[0003] Existing DMA technology supports multiple parallel descriptor queues. This technology has the following advantages: supporting multiple descriptor queues means that the DMA controller can handle multiple transfer tasks simultaneously or alternately (such as data transfer from different peripherals or memory regions). Each descriptor queue can correspond to an independent data channel or task (such as camera data, network packets, storage read / write, etc.), realizing parallel transfer of multiple tasks. Multiple queues allow the DMA hardware to immediately switch to another queue to continue working when one queue is idle or waiting, reducing idle waiting time and thus improving the overall data transfer efficiency of the system.

[0004] In the above implementation, in order to maximize the utilization of hardware resources, multiple descriptor queues are needed to share a single DMA hardware engine channel; the descriptor queues are scheduled by hardware, and a descriptor in one of the queues is selected for processing.

[0005] In the process of implementing the embodiments of this application, at least the following problems were found in the related technology: In the process of multiple descriptor queues sharing a single DMA hardware engine channel, descriptors in multiple descriptor queues need to be scheduled. There are various schemes for scheduling descriptors based on priority in the existing technology, but these existing technologies are all based on descriptor granularity. That is, after the data transfer of the entire length specified by the descriptor is completed, scheduling, switching, and execution of descriptor operations in other queues are performed.

[0006] When data migration lengths for descriptors in different descriptor queues cluster together, descriptor-granularity-based scheduling techniques can easily lead to unbalanced descriptor scheduling across multiple queues. For example, if multiple descriptors at the head of the first descriptor queue have migration lengths less than 2MB, while multiple descriptors at the head of the second descriptor queue have migration lengths greater than 2GB, then if scheduling is based on descriptor granularity, the DMA hardware migration engine will migrate data in a 1:1000 ratio between the two queues. Therefore, even if the migration lengths of multiple descriptors at the head of the first descriptor queue are shorter, they will still require a longer migration time. Summary of the Invention

[0007] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0008] This application provides a method, apparatus, and chip for balanced scheduling of descriptors across multiple queues, which enables relatively balanced scheduling of descriptors in different descriptor queues even when there is a clustering of long and short DMA transfer lengths of descriptors in different descriptor queues.

[0009] In some embodiments, the multi-queue descriptor balanced scheduling method includes: Obtain the first remaining transfer length of the first descriptor at the head of the current queue; the first remaining transfer length is the remaining DMA transfer length in the first descriptor. In the previous equalization process, if the first descriptor has not been sliced, the first remaining transfer length is the DMA transfer length of the first descriptor; if the first descriptor has been sliced, the first remaining transfer length is the transfer length remaining after the DMA transfer length of the first descriptor is sliced. If the first remaining transfer length is less than the initial remaining balance length, then one or more second descriptors adjacent to the first descriptor in the current queue will be processed during this balance scheduling process; wherein, the initial remaining balance length is a preset descriptor balance length determined based on the preset descriptor balance length as configuration information, and the initial remaining balance length is used to represent the total DMA transfer length to be transferred in each transfer process in each queue based on the configuration information; the sum of the DMA transfer length of one or more second descriptors and the first remaining transfer length is greater than or equal to the initial remaining balance length; A first slice descriptor is generated based on a first remaining transfer length, and a first remaining balance length is obtained by subtracting the first remaining transfer length from the initial remaining balance length, and one or more second slice descriptors are generated based on the first remaining balance length and the DMA transfer length of one or more second descriptors. The first slice descriptor and one or more second slice descriptors are transferred to the subsequent DMA hardware transfer engine, so that the subsequent DMA hardware transfer engine can transfer data according to the first slice descriptor and one or more second slice descriptors; Update the remaining transfer length of the current queue head descriptor for use in the next balanced scheduling of descriptors; balanced scheduling is the process described above, from obtaining the first remaining transfer length to transferring the first slice descriptor and one or more second slice descriptors to the subsequent DMA hardware transfer engine. Move the current queue to the next queue and process the descriptors in the next queue in the same way.

[0010] Optionally, generating a first slice descriptor based on a first remaining transfer length includes: generating a first slice descriptor using the first remaining transfer length as a new DMA transfer length.

[0011] Optionally, one or more second slice descriptors are generated based on the first remaining equalization length and the DMA move length of one or more second descriptors, including: If the DMA move length of a second descriptor is greater than the first remaining equalization length, then the first remaining equalization length is used as the new DMA move length to generate a second slice descriptor. If the DMA transfer length of the first second descriptor is less than the first remaining equalization length, then the DMA transfer length of the first second descriptor is used as the new DMA transfer length to generate the first second slice descriptor; the second remaining equalization length is obtained by subtracting the DMA transfer length of the first second descriptor from the first remaining equalization length; the second remaining equalization length is then compared with the DMA transfer length of the next second descriptor, and the second second slice descriptor is generated based on the comparison result; this process is repeated until the DMA transfer length of the second descriptor is greater than or equal to the latest remaining equalization length, and then the latest remaining equalization length is used as the new DMA transfer length to generate the last second slice descriptor.

[0012] Optionally, after obtaining the first slice descriptor, the first slice descriptor is sent to the subsequent DMA hardware transfer engine. After the subsequent DMA hardware transfer engine has completed the transfer, one or more second slice descriptors are obtained.

[0013] Optionally, rotating the current queue to the next queue includes rotating the current queue to the next queue if the DMA move length of the second descriptor is greater than or equal to the latest remaining equalization length.

[0014] Optionally, if the subsequent DMA hardware transfer engine has finished transferring the data specified by the first slice descriptor, or if the DMA transfer length of the second descriptor is less than the first remaining equalization length and the subsequent DMA hardware transfer engine has finished transferring the data specified by the second slice descriptor, the rotation starts from the queue number of the current queue minus one, and the next queue is still the current queue.

[0015] Optionally, if the DMA transfer length of the second descriptor is greater than or equal to the latest remaining equalization length, and the subsequent DMA hardware transfer engine has completed transferring the last data specified by the second slice descriptor, a round-robin operation is performed starting from the queue number of the current queue, and the first non-empty queue encountered is re-established as the current queue.

[0016] Optionally, the multi-queue descriptor balanced scheduling method further includes: if the first remaining transfer length is greater than the initial remaining balanced length, generating a first slice descriptor using the initial remaining balanced length as the new DMA transfer length; and transmitting the first slice descriptor to the subsequent DMA hardware transfer engine, so that the subsequent DMA hardware transfer engine can transfer data according to the first slice descriptor.

[0017] Optionally, when each descriptor to be processed enters the queue, an index is created for each descriptor to be processed; the DMA transfer length corresponding to the indexed descriptor is obtained, and the index and DMA transfer length corresponding to the same descriptor are stored in the remaining length management array in a one-to-one correspondence.

[0018] Optionally, obtaining the first remaining transfer length of the first descriptor at the head of the current queue includes: using the first index of the first descriptor as the address, obtaining the first remaining transfer length corresponding to the first index in the remaining length management array.

[0019] Optionally, updating the remaining transfer length of the current queue head descriptor includes: using the index of the current queue head descriptor as the address, updating the remaining transfer length corresponding to the index of the current queue head descriptor in the remaining length management array.

[0020] Optionally, if the first remaining transfer length is less than the initial remaining balance length, the first index of the first descriptor is reclaimed, and the first index and the first remaining transfer length are deleted from the remaining length management array.

[0021] Optionally, the process of generating the first slice descriptor and the second slice descriptor includes: The queue number of the original descriptor is used as the queue number of the slice descriptor; wherein, the original descriptor includes a first descriptor, or one or more second descriptors; the slice descriptor is a first slice descriptor, or one or more second slice descriptors; The first sum of the DMA move source address of the original descriptor and the DMA move length of the original descriptor is obtained. The first difference is obtained by subtracting the remaining length after the slice descriptor has been moved from the first sum. The first difference is used as the DMA move source address of the slice descriptor. Obtain the second sum of the DMA move destination address of the original descriptor and the DMA move length of the original descriptor. Subtract the remaining length after the slice has been moved from the second sum to obtain the second difference. Use the second difference as the DMA move destination address of the slice descriptor.

[0022] In some embodiments, the multi-queue descriptor balancing scheduling device includes a descriptor remaining length management module, a descriptor slice processing module, a polling and rotation control module, and a polling module; The descriptor slicing processing module obtains the first remaining transfer length of the first descriptor at the head of the current queue from the descriptor remaining length management module. The first remaining transfer length is the remaining DMA transfer length in the first descriptor. In the previous equalization process, if the first descriptor has not been sliced, the first remaining transfer length is the DMA transfer length of the first descriptor; if the first descriptor has been sliced, the first remaining transfer length is the transfer length remaining after the DMA transfer length of the first descriptor is sliced. If the first remaining transfer length is less than the initial remaining balance length, then one or more second descriptors adjacent to the first descriptor in the current queue are processed during this balance scheduling process; wherein, the initial remaining balance length is determined according to the preset descriptor balance length, which is configuration information, and the initial remaining balance length is used to represent the total DMA transfer length to be transferred in each transfer process in each queue based on the configuration information; the sum of the DMA transfer length of one or more second descriptors and the first remaining transfer length is greater than or equal to the initial remaining balance length; A first slice descriptor is generated based on a first remaining transfer length, and a first remaining balance length is obtained by subtracting the first remaining transfer length from the initial remaining balance length, and one or more second slice descriptors are generated based on the first remaining balance length and the DMA transfer length of one or more second descriptors. The first slice descriptor and one or more second slice descriptors are transferred to the subsequent DMA hardware transfer engine, so that the subsequent DMA hardware transfer engine can transfer data according to the first slice descriptor and one or more second slice descriptors; The descriptor remaining length management module updates the remaining transfer length of the current queue head descriptor for use in the next balanced scheduling of descriptors; balanced scheduling is the process described above, from obtaining the first remaining transfer length to transferring the first slice descriptor and one or more second slice descriptors to the subsequent DMA hardware transfer engine; Both the polling control module and the polling module rotate the current queue to the next queue.

[0023] Optionally, the descriptor balancing scheduling device among multiple queues further includes a descriptor enqueue control module and a descriptor queue module; When each descriptor to be processed enters the queue, the descriptor enqueue control module indexes each descriptor to be processed; obtains the DMA transfer length corresponding to the indexed descriptor; and stores the index and DMA transfer length corresponding to the same descriptor in the remaining length management array in a one-to-one correspondence. The descriptor enqueue control module assigns a queue number to each descriptor to be processed and sends the descriptor to be processed to the queue with the same queue number in the descriptor queue module; The polling module polls each queue in the descriptor queue module, designates a non-empty queue as the current queue, reads the queue number, the first index of the first descriptor at the head of the queue, and the first descriptor information, and sends the queue number, first index, and first descriptor information of the current queue to the descriptor slice processing module and the polling and round-robin control module; wherein, the first descriptor information includes the DMA transfer source address and the DMA transfer destination address of the first descriptor; The descriptor slicing processing module uses the first index of the first descriptor as the address and obtains the first remaining transfer length corresponding to the first index in the remaining length management array. The polling and round-robin control module sends the initial remaining balanced length of the current queue to the descriptor slice processing module; When the first remaining transfer length is less than the initial remaining equalization length, the descriptor slice processing module generates a first slice descriptor based on the first remaining transfer length, and sends the transfer length of the first slice descriptor to the polling and round-robin control module, and then transmits the first slice descriptor to the subsequent DMA hardware transfer engine. The polling and rotation control module obtains the first remaining balance length by subtracting the first remaining transfer length from the initial remaining balance length, and transmits the first remaining balance length to the descriptor slice processing module; The descriptor slice processing module interacts with the polling and rotation control module, and the two generate one or more second slice descriptors based on the first remaining equalization length and the DMA transfer length of one or more second descriptors; After the DMA transfer length of the second descriptor is greater than or equal to the latest remaining balanced length, and the last second slice descriptor is generated using the latest remaining balanced length as the new DMA transfer length, the descriptor slice processing module transfers the last second slice descriptor to the subsequent DMA hardware transfer engine; using the index of the current queue head descriptor as the address, the remaining transfer length corresponding to the index of the current queue head descriptor is updated in the remaining length management array in the descriptor remaining length management module; and the transfer length of the last second slice descriptor is transferred to the polling round-robin control module. The polling control module obtains a zero result by subtracting the DMA move length of the last second descriptor from the latest remaining balanced length. The zero result triggers the following operation: the queue number of the current queue is transmitted to the polling module. The polling module starts from the queue number of the current queue and takes the first non-empty queue encountered as the current queue.

[0024] In some embodiments, the multi-queue descriptor balancing scheduling chip includes a processor and a memory storing program instructions. The processor is configured to execute the multi-queue descriptor balancing scheduling method provided in the foregoing embodiments when executing the program instructions. In some embodiments, the inter-queue descriptor balancing scheduling chip includes the inter-queue descriptor balancing scheduling device provided in the foregoing embodiments.

[0025] The multi-queue descriptor balanced scheduling method, apparatus, and chip provided in this application can achieve the following technical effects: The remaining migration length is maintained and updated in real time based on the preset descriptor balance length. Specifically, when switching from other queues to the current queue, the initial remaining balance length is determined based on the preset descriptor balance length, which can reflect the degree of scheduling balance of each descriptor queue. The first remaining balance length is obtained by subtracting the first remaining migration length from the initial remaining balance length, which is the process of updating the remaining balance length.

[0026] When the first remaining transfer length is less than the initial remaining equalization length, as the remaining transfer length is updated in real time, not only is a first slice descriptor generated based on the first remaining transfer length, but also one or more second slice descriptors are generated based on the first remaining equalization length and the DMA transfer length of one or more second descriptors.

[0027] Thus, this method uses a preset descriptor balancing length as a benchmark and the initial remaining balancing length as its specific representation, updating the remaining balancing length in real time. This ensures that the entire scheduling process for the current queue descriptors is not based on descriptor granularity, but rather on the preset descriptor balancing length. When the DMA transfer length of a descriptor is less than the initial remaining balancing length, this method can process more than two descriptors in the current queue, generating slice descriptors from these descriptors and transmitting them to the subsequent DMA hardware transfer engine, allowing the engine to transfer the data specified by these descriptors.

[0028] If the relocation length of multiple descriptors at the head of the first descriptor queue is less than 2MB, while the relocation length of multiple descriptors at the head of the second descriptor queue is greater than 2GB, then if scheduling is based on descriptor granularity, the DMA hardware relocation engine can achieve a data relocation ratio of 1:1000 between the two descriptor queues.

[0029] By adopting the scheduling method based on the preset descriptor balanced length of this application, the data specified by multiple descriptors in the first descriptor queue will be moved in one scheduling cycle, which speeds up the processing speed of descriptors with smaller DMA move lengths in the descriptor queue.

[0030] In cases where the descriptor migration length distribution is uneven within a single descriptor queue, and / or uneven across multiple descriptor queues, this multi-queue descriptor balancing scheduling method can achieve balancing at the data level based on a preset descriptor balancing length. This allows descriptors with shorter migration lengths to be processed quickly. When the priorities of each descriptor are unclear, this multi-queue data-level balancing method can achieve maximal balancing at the priority level.

[0031] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0032] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrative descriptions and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are considered similar elements, and wherein: Figure 1 This is a schematic diagram of the input and output of a multi-queue descriptor balancing scheduling device provided in an embodiment of this application; Figure 2 This is a flowchart illustrating a method for balanced scheduling of descriptors across multiple queues provided in an embodiment of this application; Figure 3 This is a flowchart illustrating another method for balanced scheduling of descriptors across multiple queues provided in an embodiment of this application; Figure 4 This is a schematic diagram of a multi-queue descriptor balancing scheduling device provided in an embodiment of this application; Figure 5 This is a schematic diagram of a polling module provided in an embodiment of this application; Figure 6 This is a schematic diagram of a descriptor remaining length management module provided in an embodiment of this application; Figure 7 This is a schematic diagram of a descriptor slicing processing module provided in an embodiment of this application; Figure 8 This is a schematic diagram of a polling and rotation control module provided in an embodiment of this application. Detailed Implementation

[0033] To provide a more detailed understanding of the features and technical content of the embodiments of this application, the implementation of the embodiments of this application will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this application. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0034] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0035] Unless otherwise stated, the term "multiple" means two or more.

[0036] In this embodiment, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0037] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0038] The multi-queue descriptor balanced scheduling method provided in this application can be applied to DMA-based field programmable gate arrays (FPGAs) or chips, specifically in applications such as Remote Direct Memory Access (RDMA).

[0039] Figure 1 This is an input / output diagram of a multi-queue descriptor balanced scheduling device provided in an embodiment of this application, used to exemplarily illustrate the input and output information of the multi-queue descriptor balanced scheduling method.

[0040] Figure 1 The "preset descriptor balancing length" is the device's configuration information. In some application scenarios, the configuration information may also include device enabling. When the device is enabled, it can perform scheduling according to the multi-queue inter-descriptor balancing scheduling method provided in this application. When the device is disabled, it schedules descriptors between queues according to existing technology.

[0041] In addition, the slice descriptor is sent to the subsequent DMA hardware transfer engine, which transfers the corresponding data accordingly. When the transfer is completed, the DMA hardware transfer engine sends back a completion signal, which is the slice descriptor read enable.

[0042] The term "descriptor" in the embodiments of this application includes queue number, DMA transfer length, DMA transfer source address, and DMA transfer destination address.

[0043] In specific RDMA applications, the descriptor is the Work Queue Element (WQE), and the specific contents of the descriptor are shown in Table 1 below: Table 1 Key Information about Descriptors in RDMA Applications Figure 2 This is a flowchart illustrating a multi-queue descriptor balanced scheduling method provided in an embodiment of this application. This method can be executed by a DMA-based FPGA or chip.

[0044] Combination Figure 2 As shown, the multi-queue descriptor balanced scheduling method includes: S201. Obtain the first remaining move length of the first descriptor at the head of the current queue.

[0045] The current queue is a descriptor queue waiting to be moved.

[0046] This multi-queue descriptor load balancing scheduling method is executed cyclically. During the initial execution, the first descriptor has not been sliced, so the first remaining transfer length of the first descriptor is the DMA transfer length of the first descriptor.

[0047] The first remaining transfer length is the remaining DMA transfer length in the first descriptor. In the previous equalization process, if the first descriptor has not been sliced, the first remaining transfer length is the DMA transfer length of the first descriptor; if the first descriptor has been sliced, the first remaining transfer length is the transfer length remaining after the DMA transfer length of the first descriptor has been sliced.

[0048] If the first remaining transfer length is less than the initial remaining balance length, then one or more second descriptors adjacent to the first descriptor in the current queue will be processed during this balance scheduling process.

[0049] In the embodiments of this application, the term "DMA move length" refers to an inherent parameter of the descriptor that does not change throughout the entire balanced scheduling process.

[0050] The term "remaining move length" refers to the state parameters of the descriptor during the balanced scheduling process, which change as the scheduling process progresses.

[0051] The term "remaining balance length" refers to the parameter used to control the balance scheduling process. Its specific forms include: initial remaining balance length, first remaining balance length, second remaining balance length, ..., latest remaining balance length.

[0052] The initial remaining balance length is determined based on the preset descriptor balance length. The preset descriptor balance length is configuration information, and the initial remaining balance length represents the total DMA transfer length to be transferred in each transfer process within each queue, as determined by the configuration information. The preset descriptor balance length is a user-defined value and can be set empirically. The preset descriptor balance length can be used as the initial remaining balance length, or the sum or difference between the preset descriptor balance length and a first adjustment value can be used as the initial remaining balance length.

[0053] The sum of the DMA transfer length of one or more second descriptors and the first remaining transfer length is greater than or equal to the initial remaining equalization length, so as to facilitate the subsequent generation of one or more slice descriptors with a total DMA transfer length equal to the first remaining transfer length.

[0054] S202, generate a first slice descriptor based on the first remaining transfer length, and obtain a first remaining balance length by subtracting the first remaining transfer length from the initial remaining balance length, and generate one or more second slice descriptors based on the first remaining balance length and the DMA transfer length of one or more second descriptors.

[0055] Taking the first and second slice descriptors as examples, the slice descriptors still conform to the existing technical requirements for descriptions, namely, the slice descriptor must also include the queue number, DMA transfer length, DMA transfer source address, and DMA transfer destination address. In RDMA applications, the slice descriptor also includes the specific information shown in Table 1 above.

[0056] Those skilled in the art can, based on experience, set up specific processes for "generating a first slice descriptor based on a first remaining transfer length" and "generating one or more second slice descriptors based on a first remaining equalization length and the DMA transfer length of one or more second descriptors".

[0057] S203, Transfer the first slice descriptor and one or more second slice descriptors to the subsequent DMA hardware transfer engine.

[0058] After transferring the first slice descriptor and one or more second slice descriptors to the subsequent DMA hardware transfer engine, the subsequent DMA hardware transfer engine can transfer data based on the first slice descriptor and one or more second slice descriptors.

[0059] Those skilled in the art can, based on experience, set up the specific process for the subsequent DMA hardware transfer engine to transfer data according to descriptors (first slice descriptor, one or more second slice descriptors), which will not be elaborated here.

[0060] exist Figure 1The explanation states that after the DMA hardware transfer engine completes the transfer, it will send back a completion signal. This completion signal is the slice descriptor read enable. This structure is mainly used in schemes where the slice descriptor is retrieved again after each transfer of specified data.

[0061] Optionally, it is also possible to Figure 1 A buffer queue is set up between the output node of the slice descriptor and the subsequent DMA hardware transfer engine. In this way, without waiting for the completion signal from the subsequent DMA hardware transfer engine, the descriptors among multiple queues can be continuously and evenly scheduled according to the remaining slice descriptors in the buffer queue.

[0062] S204. Update the remaining move length of the current queue head descriptor.

[0063] If the sum of the DMA move length of one or more second descriptors and the first remaining move length equals the initial remaining equalization length, and the last second descriptor is not sliced, then the remaining move length of the current queue head descriptor is the DMA move length of that descriptor.

[0064] If the sum of the DMA transfer length of one or more second descriptors and the first remaining transfer length is greater than the initial remaining equalization length, the last second descriptor is sliced. In this case, the current queue head descriptor is the last second descriptor, and the remaining transfer length of the head descriptor is the length remaining after the DMA transfer length of the last second descriptor has been sliced. Specifically, if the sum of the DMA transfer length of one or more second descriptors and the first remaining transfer length is less than the initial remaining equalization length, this indicates that the data in the queue is about to be transferred. In this case, the first slice descriptor and one or more second descriptors are transferred to the subsequent DMA hardware transfer engine, allowing the subsequent DMA hardware transfer engine to transfer data based on the first slice descriptor and one or more second descriptors. Afterward, if no new descriptors enter the queue, the queue is not empty.

[0065] The remaining transfer length is updated in this way for use in the next leveling scheduling descriptor. Leveling scheduling is the process described above, from obtaining the first remaining transfer length to transferring the first slice descriptor and one or more second slice descriptors to the subsequent DMA hardware transfer engine.

[0066] S205. Transfer the current queue to the next queue and process the descriptors in the next queue in the same way.

[0067] That is, jump to S201, take the next queue as the current queue, take the descriptor of the head of the next queue as the first descriptor, and execute the steps from S201 to S204 in sequence.

[0068] The remaining migration length is maintained and updated in real time based on the preset descriptor balance length. Specifically, when switching from other queues to the current queue, the initial remaining balance length is determined based on the preset descriptor balance length, which can reflect the degree of scheduling balance of each descriptor queue. The first remaining balance length is obtained by subtracting the first remaining migration length from the initial remaining balance length, which is the process of updating the remaining balance length.

[0069] When the first remaining transfer length is less than the initial remaining equalization length, as the remaining transfer length is updated in real time, not only is a first slice descriptor generated based on the first remaining transfer length, but also one or more second slice descriptors are generated based on the first remaining equalization length and the DMA transfer length of one or more second descriptors.

[0070] Thus, this method uses a preset descriptor balancing length as a benchmark and the initial remaining balancing length as its specific representation, updating the remaining balancing length in real time. This ensures that the entire scheduling process for the current queue descriptors is not based on descriptor granularity, but rather on the preset descriptor balancing length. When the DMA transfer length of a descriptor is less than the initial remaining balancing length, this method can process more than two descriptors in the current queue, generating slice descriptors from these descriptors and transmitting them to the subsequent DMA hardware transfer engine, allowing the engine to transfer the data specified by these descriptors.

[0071] If the relocation length of multiple descriptors at the head of the first descriptor queue is less than 2MB, while the relocation length of multiple descriptors at the head of the second descriptor queue is greater than 2GB, then if scheduling is based on descriptor granularity, the DMA hardware relocation engine can achieve a data relocation ratio of 1:1000 between the two descriptor queues.

[0072] By adopting the scheduling method based on the preset descriptor balanced length of this application, the data specified by multiple descriptors in the first descriptor queue will be moved in one scheduling cycle, which speeds up the processing speed of descriptors with smaller DMA move lengths in the descriptor queue.

[0073] In cases where the descriptor migration length distribution is uneven within a single descriptor queue, and / or uneven across multiple descriptor queues, this multi-queue descriptor balancing scheduling method can achieve balancing at the data level based on a preset descriptor balancing length. This allows descriptors with shorter migration lengths to be processed quickly. When the priorities of each descriptor are unclear, this multi-queue data-level balancing method can achieve maximal balancing at the priority level.

[0074] For example, the moving lengths of descriptors in a descriptor queue are unevenly distributed. The data corresponding to multiple descriptors at the head of the queue has a lower priority, but the data corresponding to descriptors after these descriptors has a higher priority. Furthermore, the moving lengths of multiple descriptors at the head of the queue are all short (less than the initial remaining equilibrium length).

[0075] If scheduling is based on descriptor granularity, and only the data corresponding to one descriptor is moved at a time, multiple queue rotation cycles are required before processing descriptors with higher data priority following this descriptor queue can begin. However, if the multi-queue descriptor balanced scheduling method provided in this application is adopted, processing descriptors with higher data priority following this descriptor queue can begin after fewer queue rotation cycles.

[0076] For other descriptor queues, compared to a descriptor-based scheduling scheme, the technical solution of this application only adds one round-robin cycle to all descriptor queues. The added time is the time required to move one or more descriptors in this descriptor queue, which is the shorter move length. Compared to the case where 2G of data (2G data length is much larger than the initial remaining balanced length) is moved first, and then 2M of data (2M data length is much smaller than the initial remaining balanced length) is moved, the added time of the technical solution of this application is relatively short. The shorter time is then evenly distributed among multiple other descriptor queues, resulting in a smaller impact on the latency of each descriptor queue.

[0077] Therefore, compared with existing descriptor-based scheduling methods, the advantages of the technical solution in this application far outweigh the disadvantages. Thus, when the priorities of each descriptor are unclear, it can achieve balance at the priority level to the greatest extent.

[0078] Figure 3 This is a flowchart illustrating another method for balanced scheduling of descriptors across multiple queues provided in an embodiment of this application. Combined with... Figure 3 As shown, the multi-queue descriptor balanced scheduling method includes: S301. Obtain the first remaining move length of the first descriptor of the current queue head.

[0079] In the previous equalization process, if the first descriptor has not been sliced, the first remaining transfer length is the DMA transfer length of the first descriptor; if the first descriptor has been sliced, the first remaining transfer length is the transfer length remaining after the DMA transfer length of the first descriptor has been sliced.

[0080] S302, if the first remaining transfer length is less than the initial remaining equalization length, generate a first slice descriptor based on the first remaining transfer length, and obtain the first remaining equalization length by subtracting the first remaining transfer length from the initial remaining equalization length, and generate one or more second slice descriptors based on the first remaining equalization length and the DMA transfer length of one or more second descriptors.

[0081] That is, if the first remaining transfer length is less than the initial remaining balance length, then one or more second descriptors adjacent to the first descriptor in the current queue are processed during this balance scheduling process; wherein, the initial remaining balance length is determined according to the preset descriptor balance length; the sum of the DMA transfer length of one or more second descriptors and the first remaining transfer length is greater than or equal to the initial remaining balance length.

[0082] S303, Transfer the first slice descriptor and one or more second slice descriptors to the subsequent DMA hardware transfer engine.

[0083] After transferring the first slice descriptor and one or more second slice descriptors to the subsequent DMA hardware transfer engine, the subsequent DMA hardware transfer engine can transfer data based on the first slice descriptor and one or more second slice descriptors.

[0084] S304. If the first remaining transfer length is greater than the initial remaining equalization length, generate the first slice descriptor using the initial remaining equalization length as the new DMA transfer length.

[0085] S305, Transfer the first slice descriptor to the subsequent DMA hardware transfer engine.

[0086] This allows the subsequent DMA hardware transfer engine to transfer data based on the first slice descriptor.

[0087] S306. Update the remaining move length of the current queue head descriptor.

[0088] S307. Transfer the current queue to the next queue and process the descriptors in the next queue in the same way.

[0089] exist Figure 2 In the illustrated embodiment, by performing balanced scheduling on descriptors with shorter transfer lengths based only on a preset balanced descriptor length, the processing speed of descriptors with shorter DMA transfer lengths in the descriptor queue can be accelerated, achieving balance at the data level. Furthermore, when the priorities of each descriptor are unclear, balance is achieved to the maximum extent at the priority level.

[0090] exist Figure 3In the illustrated embodiment, descriptors with longer DMA transfer lengths in the descriptor queue are balanced based on a preset descriptor balance length. If the DMA transfer length of the head descriptor of a certain descriptor queue exceeds the initial remaining balance length, it means that transferring all the data specified by the DMA transfer length of that descriptor would take a long time. In this case, the initial remaining balance length is extracted from the DMA transfer length of the first descriptor, and the initial remaining balance length is used as the new DMA transfer length to generate the first slice descriptor. The first slice descriptor is then transmitted to the subsequent DMA hardware transfer engine, so that the subsequent DMA hardware transfer engine only transfers data according to the first slice descriptor and no longer transfers all the data specified by the first remaining transfer length. This allows for timely switching to other descriptor queues, reducing the waiting time of other descriptor queues and achieving further balancing at the data level.

[0091] When the descriptor priority is not clear, each descriptor in each descriptor queue is assigned a higher priority with equal probability. That is, the descriptor with the highest priority can be regarded as being randomly distributed at the head of multiple queues.

[0092] Therefore, the probability that a descriptor at the head of a descriptor queue has high priority is far lower than the probability that the descriptor does not have high priority.

[0093] Therefore, by slicing descriptors with longer DMA transfer lengths based on the preset descriptor equalization length, timely switching to other descriptor queues can be achieved, which is most beneficial for taking into account the possibility that the head descriptor of other descriptor queues has a higher priority.

[0094] The slice balancing scheme for descriptors with long DMA transfer lengths provided in this application embodiment can achieve maximal balancing at the priority level when the priorities of each descriptor are unclear.

[0095] In the foregoing embodiments, it has been described that those skilled in the art can set up specific processes for "generating a first slice descriptor based on a first remaining transfer length" and "generating one or more second slice descriptors based on a first remaining equalization length and the DMA transfer length of one or more second descriptors" based on experience.

[0096] The process of generating the first slice descriptor and the second slice descriptor provided in this application will be further illustrated below.

[0097] Optionally, a first slice descriptor is generated from the first remaining transfer length corresponding to the first descriptor, and one or more second slice descriptors are generated from the transfer data with a length equal to the remaining equalization length, including: The queue number of the original descriptor is used as the queue number of the slice descriptor; wherein, the original descriptor includes a first descriptor, or one or more second descriptors; the slice descriptor is a first slice descriptor, or one or more second slice descriptors; The first sum of the DMA move source address of the original descriptor and the DMA move length of the original descriptor is obtained. The first difference is obtained by subtracting the remaining length after the slice descriptor has been moved from the first sum. The first difference is used as the DMA move source address of the slice descriptor. Obtain the second sum of the DMA move destination address of the original descriptor and the DMA move length of the original descriptor. Subtract the remaining length after the slice has been moved from the second sum to obtain the second difference. Use the second difference as the DMA move destination address of the slice descriptor.

[0098] Taking the first and second slice descriptors as examples, the slice descriptor also needs to include a queue number, DMA transfer length, DMA transfer source address, and DMA transfer destination address. The above embodiments exemplify how the queue number, DMA transfer source address, and DMA transfer destination address of the slice descriptor are obtained. This ensures that each slice descriptor is an independent descriptor that can be executed, and the data specified by multiple slice descriptors corresponding to the same original descriptor is contiguous in address. Even if data specified by a longer DMA transfer length of an original descriptor is sliced ​​and transferred in stages, the transfer result of slicing and transferring data in stages is the same as that of transferring data in one go because the DMA transfer source addresses and DMA transfer destination addresses of multiple slice descriptors corresponding to the same original descriptor are contiguous.

[0099] The above embodiments exemplify how to obtain the queue number, DMA transfer source address, and DMA transfer destination address of the slice descriptor. The following will exemplify how to obtain the DMA transfer length of the slice descriptor.

[0100] In the embodiments of this application, the DMA move length of the slice descriptor is determined based on both the remaining move length and the remaining equalization length of the descriptor.

[0101] Optionally, generating a first slice descriptor based on a first remaining transfer length includes: if the first remaining transfer length is less than the initial remaining equalization length, generating a first slice descriptor using the first remaining transfer length as the new DMA transfer length.

[0102] Optionally, one or more second slice descriptors are generated based on the first remaining equalization length and the DMA move length of one or more second descriptors, including: If the DMA move length of a second descriptor is greater than the first remaining equalization length, then the first remaining equalization length is used as the new DMA move length to generate a second slice descriptor. If the DMA transfer length of the first second descriptor is less than the first remaining equalization length, then the DMA transfer length of the first second descriptor is used as the new DMA transfer length to generate the first second slice descriptor; the second remaining equalization length is obtained by subtracting the DMA transfer length of the first second descriptor from the first remaining equalization length; the second remaining equalization length is then compared with the DMA transfer length of the next second descriptor, and the second second slice descriptor is generated based on the comparison result; this process is repeated until the DMA transfer length of the second descriptor is greater than or equal to the latest remaining equalization length, and then the latest remaining equalization length is used as the new DMA transfer length to generate the last second slice descriptor.

[0103] In a scheme where a slice descriptor is reacquired after each transfer of specified data, the first slice descriptor can be sent to the subsequent DMA hardware transfer engine after the first slice descriptor is obtained. After the subsequent DMA hardware transfer engine has completed the transfer, one or more second slice descriptors can be obtained.

[0104] Similarly, each time a second slice descriptor is obtained, it is sent to the subsequent DMA transfer engine. After the subsequent DMA hardware transfer engine has completed the transfer, it is then determined whether to continue generating second slice descriptors or to rotate the current queue.

[0105] Optionally, rotating the current queue to the next queue includes rotating the current queue to the next queue if the DMA move length of the second descriptor is greater than or equal to the latest remaining equalization length.

[0106] If the DMA move length of the second descriptor is greater than or equal to the latest remaining balance length, it indicates that the current scheduling process of descriptors in the current queue based on the preset descriptor balance length has ended, and the scheduling of descriptors in the next queue can begin.

[0107] In some specific application scenarios, after the subsequent DMA hardware transfer engine has completed the transfer of the data specified by the slice descriptor, a round-robin judgment is performed on the queue. This is beneficial for the cyclic execution of the descriptor balanced scheduling method among multiple queues.

[0108] Optionally, if the subsequent DMA hardware transfer engine has finished transferring the data specified by the first slice descriptor, or if the DMA transfer length of the second descriptor is less than the first remaining equalization length and the subsequent DMA hardware transfer engine has finished transferring the data specified by the second slice descriptor, the rotation starts from the queue number of the current queue minus one, and the next queue is still the current queue.

[0109] Optionally, if the DMA transfer length of the second descriptor is greater than or equal to the latest remaining equalization length, and the subsequent DMA hardware transfer engine has completed transferring the last data specified by the second slice descriptor, a round-robin operation is performed starting from the queue number of the current queue, and the first non-empty queue encountered is re-established as the current queue.

[0110] Thus, after each subsequent DMA hardware transfer engine completes the transfer of data specified by the slice descriptor, it performs a polling and rotation judgment on the queue to achieve continuous processing of the current queue descriptors based on the preset descriptor balanced length.

[0111] Optionally, when each descriptor to be processed enters the queue, an index is created for each descriptor to be processed; the DMA transfer length corresponding to the indexed descriptor is obtained, and the index and DMA transfer length corresponding to the same descriptor are stored in the remaining length management array in a one-to-one correspondence.

[0112] The remaining length management array includes at least two values: one is the descriptor index, and the other is the remaining transfer length of the descriptor. If the descriptor has not been sliced, the remaining transfer length is the DMA transfer length of the descriptor; if the descriptor has been sliced, the remaining transfer length is the transfer length remaining after the DMA transfer length has been sliced.

[0113] Using such a remaining length management array is beneficial for accurately obtaining the first remaining transfer length when starting to schedule the first descriptor of the current queue, and for accurately updating the remaining transfer length of the head of the current queue before rotating the current queue to the next queue.

[0114] Specifically, obtaining the first remaining transfer length of the first descriptor at the head of the current queue includes: using the first index of the first descriptor as the address, obtaining the first remaining transfer length corresponding to the first index in the remaining length management array.

[0115] Update the remaining move length of the current queue head descriptor, including: using the index of the current queue head descriptor as the address, update the remaining move length corresponding to the index of the current queue head descriptor in the remaining length management array.

[0116] Additionally, if the first remaining transfer length is less than the initial remaining balanced length, the first index of the first descriptor is reclaimed, and the first index and the first remaining transfer length are deleted from the remaining length management array.

[0117] Additionally, if the remaining migration length of the second descriptor is less than the latest remaining balanced length, the index and remaining migration length of the second descriptor are reclaimed.

[0118] Figure 4 This is a schematic diagram of a multi-queue descriptor balancing scheduling device provided in an embodiment of this application.

[0119] Combination Figure 4 As shown, the descriptor balancing scheduling device between multiple queues includes a descriptor remaining length management module 41, a descriptor slice processing module 42, a polling and rotation control module 43, and a polling module 44. The descriptor slicing processing module 42 obtains the first remaining transfer length of the first descriptor at the head of the current queue from the descriptor remaining length management module 41. The first remaining transfer length is the remaining DMA transfer length in the first descriptor. In the previous equalization process, if the first descriptor has not been sliced, the first remaining transfer length is the DMA transfer length of the first descriptor; if the first descriptor has been sliced, the first remaining transfer length is the transfer length remaining after the DMA transfer length of the first descriptor is sliced. If the first remaining transfer length is less than the initial remaining balance length, then one or more second descriptors adjacent to the first descriptor in the current queue are processed during this balance scheduling process; wherein, the initial remaining balance length is determined according to the preset descriptor balance length, which is configuration information, and the initial remaining balance length is used to represent the total DMA transfer length to be transferred in each transfer process in each queue based on the configuration information; the sum of the DMA transfer length of one or more second descriptors and the first remaining transfer length is greater than or equal to the initial remaining balance length; A first slice descriptor is generated based on a first remaining transfer length, and a first remaining balance length is obtained by subtracting the first remaining transfer length from the initial remaining balance length, and one or more second slice descriptors are generated based on the first remaining balance length and the DMA transfer length of one or more second descriptors. The first slice descriptor and one or more second slice descriptors are transferred to the subsequent DMA hardware transfer engine, so that the subsequent DMA hardware transfer engine can transfer data according to the first slice descriptor and one or more second slice descriptors; The descriptor remaining length management module 41 updates the remaining transfer length of the current queue head descriptor for use in the next balanced scheduling of descriptors; balanced scheduling is the process described above from obtaining the first remaining transfer length to transferring the first slice descriptor and one or more second slice descriptors to the subsequent DMA hardware transfer engine. Both the polling control module 43 and the polling module 44 rotate the current queue to the next queue.

[0120] Optionally, the descriptor balancing scheduling device among multiple queues also includes a descriptor enqueue control module 45 and a descriptor queue module 46.

[0121] When each descriptor to be processed enters the queue, the descriptor enqueue control module 45 compiles an index for each descriptor to be processed; obtains the DMA transfer length corresponding to the indexed descriptor; and stores the index and DMA transfer length corresponding to the same descriptor in the remaining length management array in a one-to-one correspondence.

[0122] The descriptor enqueue control module 45 assigns a queue number to each descriptor to be processed and sends the descriptor to be processed to the queue with the same queue number in the descriptor queue module 46.

[0123] Specifically, when a descriptor to be processed is enqueued, the descriptor enqueue control module 45 writes the descriptor information into the corresponding QueueN according to the Queue Pair Number (QPN) shown in Table 1.

[0124] The number of queues in the descriptor queue module 46 is the same as the number of QPs, and they are sequentially numbered from 0 to N-1; where N is the number of queues.

[0125] In the specific application of RDMA, QPs are independent of each other and are usually assigned to different software. Therefore, QPs need to use the "shared" DMA hardware transfer engine in a balanced manner.

[0126] The polling module 44 polls each queue in the descriptor queue module 46, designates a non-empty queue as the current queue, reads the queue number of the current queue, the first index of the first descriptor at the head of the queue, and the first descriptor information, and sends the queue number, the first index, and the first descriptor information of the current queue to the descriptor slice processing module 42 and the polling and rotation control module 43; wherein, the first descriptor information includes the DMA transfer source address and the DMA transfer destination address of the first descriptor.

[0127] The descriptor slicing processing module 42 uses the first index of the first descriptor as the address to obtain the first remaining transfer length corresponding to the first index in the remaining length management array.

[0128] The polling and rotation control module 43 sends the initial remaining balanced length of the current queue to the descriptor slice processing module 42.

[0129] When the first remaining transfer length is less than the initial remaining equalization length, the descriptor slice processing module 42 generates a first slice descriptor based on the first remaining transfer length, and sends the transfer length of the first slice descriptor to the polling and round-robin control module 43, which then transmits the first slice descriptor to the subsequent DMA hardware transfer engine.

[0130] The polling and rotation control module 43 obtains the first remaining balance length by subtracting the first remaining transfer length from the initial remaining balance length, and transmits the first remaining balance length to the descriptor slice processing module 42.

[0131] The descriptor slice processing module 42 interacts with the polling and rotation control module 43, and the two generate one or more second slice descriptors based on the first remaining equalization length and the DMA transfer length of one or more second descriptors.

[0132] After the DMA transfer length of the second descriptor is greater than or equal to the latest remaining balanced length, and the last second slice descriptor is generated using the latest remaining balanced length as the new DMA transfer length, the descriptor slice processing module 42 transmits the last second slice descriptor to the subsequent DMA hardware transfer engine; using the index of the current queue head descriptor as the address, the remaining transfer length corresponding to the index of the current queue head descriptor is updated in the remaining length management array in the descriptor remaining length management module 41; and the transfer length of the last second slice descriptor is transmitted to the polling round-robin control module 43.

[0133] The polling control module 43 obtains a zero result by subtracting the DMA transfer length of the last second descriptor from the latest remaining balanced length. The zero result triggers the following operation: the queue number of the current queue is transmitted to the polling module 44.

[0134] The polling module 44 starts from the queue number of the current queue and takes the first non-empty queue encountered as the current queue.

[0135] The polling module 44 can use Round Robin polling, which can perform RR polling scheduling on descriptors in N queues and select the descriptor at the head of a non-empty queue for output. This level of RR polling can achieve scheduling at the granularity of raw descriptors (unsliced ​​descriptors).

[0136] Polling module 44 can be as follows Figure 5 As shown.

[0137] Among them, "RR scheduling request" is a scheduling request from N queues, which is generally derived from the non-empty indication of the queue; "RR round-robin control" of polling module 44 is the starting position of the current RR polling; "RR scheduling result" of polling module 44 is the first non-empty queue number after the queue number specified by "RR round-robin control".

[0138] For example, if the queue number indicated by "RR round-robin control" is M, then the RR polling module 44 will determine whether the corresponding "RR scheduling request" is valid in the order of M+1, M+2, ..., N-1, 0, 1, M, and output the first valid request number as the "RR scheduling result".

[0139] The polling module 44 outputs the descriptor information of the head of the corresponding queue to the descriptor slice processing module 42 and the polling round-robin control module 43 based on the queue number in the "RR scheduling result".

[0140] Optionally, if the DMA move length of the second descriptor is greater than or equal to the latest remaining equalization length, the descriptor slice processing module 42 generates a second second slice descriptor based on the latest remaining equalization length.

[0141] Optionally, the descriptor slice processing module 42 sends the first slice descriptor to the subsequent DMA hardware transfer engine. After the subsequent DMA hardware transfer engine completes the transfer, it sends back a slice descriptor read enable. After receiving the read enable, the descriptor slice processing module 42 obtains one or more second slice descriptors.

[0142] Optionally, the polling control module 43 obtains a non-zero result by subtracting the DMA transfer length of the last second descriptor from the latest remaining balanced length. The non-zero result triggers the following operation: the queue number of the current queue is decremented by one and then transmitted to the polling module 44.

[0143] The polling module 44 starts polling from the current queue number minus one. The first non-empty queue encountered is still the current queue, that is, the next queue is still the current queue.

[0144] Optionally, if the first remaining transfer length is greater than the initial remaining equalization length, the descriptor slice processing module 42 generates a first slice descriptor using the initial remaining equalization length as the new DMA transfer length; and transmits the first slice descriptor to the subsequent DMA hardware transfer engine, so that the subsequent DMA hardware transfer engine can transfer data according to the first slice descriptor.

[0145] Optionally, if the first remaining transfer length is less than the initial remaining equalization length, the descriptor slicing processing module 42 confirms that the first descriptor has been processed, transmits the first index of the first descriptor to the descriptor enqueue control module 45, and transmits the first index and the queue number of the first descriptor to the descriptor queue module 46; the descriptor enqueue control module 45 reclaims the first index; and the descriptor queue module 46 performs dequeue processing on the first descriptor.

[0146] Optionally, if the moving length of one or more second descriptors is less than the latest remaining balance length, the descriptor slicing processing module 42 confirms that one or more second descriptors have been processed, transmits the second index of one or more second descriptors to the descriptor enqueue control module 45, and transmits the queue number of one or more second descriptors to the descriptor queue module 46; the descriptor enqueue control module 45 reclaims the second index of one or more second descriptors; and the descriptor queue module 46 performs dequeue processing on one or more second descriptors.

[0147] Optionally, the polling and rotation control module 43 also updates the remaining equalization length in the following manner: After the queue number obtained by the polling module 44 changes, the remaining balanced length is re-determined according to the preset descriptor balanced length; because a change in the queue number means that the descriptor queue has been rotated.

[0148] If the queue number obtained by the polling module 44 remains unchanged, but a zero result is obtained by subtracting the DMA transfer length of the first slice descriptor from the initial remaining balanced length, or by subtracting the DMA transfer length of the last second descriptor from the latest remaining balanced length, the remaining balanced length is re-determined according to the preset descriptor balanced length. This is because a zero result indicates that the queue rotation condition has been met, but only the current queue is valid (not empty) among the N queues, so the "remaining balanced length" needs to be updated.

[0149] The queue number obtained by the polling module 44 remains unchanged, and a non-zero result is obtained by subtracting the DMA transfer length of the first slice descriptor from the initial remaining balanced length. A non-zero result is also obtained by subtracting the DMA transfer length of the second descriptor (which is not the last one) from the latest remaining balanced length. At this time, the remaining balanced length is updated, for example, from the initial balanced length to the first remaining balanced length, from the first remaining balanced length to the second remaining balanced length, and from the second remaining balanced length to the third remaining balanced length.

[0150] The following is for reference Figure 6 , Figure 7 and Figure 8 The descriptor remaining length management module 41, the descriptor slice processing module 42, and the polling and rotation control module 43 are described in detail.

[0151] The descriptor remaining length management module 41 maintains the original DMA transfer length of each queue descriptor. Its working mechanism is as follows: Figure 6 As shown, the core of the descriptor remaining length management module 41 is a DMA descriptor length array maintained based on index, namely the aforementioned remaining length management array. This array uses the descriptor index as the address and stores the DMA transfer length of the descriptor corresponding to the descriptor index. Figure 6The number of indices N and the number of queues are not directly related, but are generally greater than twice the number of queues, which facilitates the implementation of pipelined and buffered hardware processing.

[0152] During operation, the descriptor remaining length management module 41 receives the DMA transfer length and the descriptor index corresponding to each descriptor from the descriptor enqueue control module 45, and uses the descriptor index as the address to store the corresponding DMA transfer length into the corresponding array element.

[0153] The descriptor remaining length management module 41 receives the descriptor index output from the descriptor slice processing module 42, uses it to address the corresponding DMA move length, and returns it to the descriptor slice processing module 42.

[0154] After the descriptor slice processing module 42 completes the corresponding slice processing, it updates the remaining length of the descriptor (the value in the array element minus the processing length of the current slice, representing the remaining migration length of the original descriptor) to the array element addressed by the descriptor index.

[0155] The descriptor slice processing module 42 mainly generates slice descriptors based on the remaining transfer length of the current descriptor and the latest remaining balanced length of the current queue. The slice descriptor includes the following information: queue pair number QPN, slice DMA transfer length, slice DMA transfer source address, and slice DMA transfer destination address.

[0156] The descriptor slicing processing module 42 is the core module of the entire solution, combined with... Figure 7 and Figure 4 As shown, the descriptor slicing processing module 42 is the same. Figure 4 The interaction process of the relevant modules is illustrated by example.

[0157] 1) The interaction with the same polling module 44 is as follows: The polling module 44 outputs: ① the original (before slicing) descriptor information, which includes the contents shown in Table 1; ② the index corresponding to the descriptor (allocated and recycled by the descriptor enqueue control module 45); ③ the queue number corresponding to the descriptor (selected by RR polling, corresponding to the number of queueN).

[0158] 2) The interaction with the descriptor remaining length management module 41 is as follows: Based on the index corresponding to the descriptor output by the polling module 44, the DMA transfer length (i.e. the remaining transfer length) based on the descriptor index is obtained from the descriptor remaining length management module 41. After the descriptor slice is processed, based on the descriptor slice read enable, the DMA move length of the current slice descriptor is subtracted from the DMA move length based on the descriptor index, and the remaining move length is updated to the array cell addressed by the descriptor index.

[0159] 3) The interaction with the same polling and round-robin control module 43 is as follows: The polling control module 43 synchronously receives the output of the polling module 44 and outputs the remaining balanced length of the current queue to the descriptor slice processing module 42.

[0160] After the descriptor slice is processed, the DMA move length of the slice descriptor is output to the polling control module 43 according to the descriptor slice read enable.

[0161] 4) The interaction with the descriptor queue module 46 is as follows: After the descriptor slice is processed, based on the descriptor slice read enable, the DMA move length of the current slice descriptor is subtracted from the DMA move length based on the descriptor index; if the value after subtraction is 0, it means that the descriptor has been processed. Then, the queue number corresponding to the ③ descriptor is output to the descriptor queue module 46 for dequeue processing, and the descriptor will be removed from the queue.

[0162] 5) The interaction with the descriptor enqueue control module 45 is as follows: After the descriptor slice is processed, based on the descriptor slice read enable, the DMA transfer length of the current slice descriptor is subtracted from the DMA transfer length based on the descriptor index. If the value after subtraction is 0, it means that the descriptor has been processed. Then, the index corresponding to the descriptor is output to the polling and round-robin control module 43 and the descriptor enqueue control module 41 for the reclamation of the index corresponding to the descriptor. The index corresponding to the reclaimed descriptor can be allocated to the subsequently prefetched descriptor.

[0163] The following is combined Figure 4 and Figure 8 A comprehensive description of the polling and rotation control module 43 is provided.

[0164] The interaction between this module and polling module 44 is as follows: The queue number output by the polling module 44 is received, and the remaining balance length is updated under the slice descriptor read enable control.

[0165] Simultaneously, under the slice descriptor read enable control, the RR rotation control information is updated: If, after slice descriptor read is enabled, the value of the latest remaining balanced length minus the DMA move length of the current slice descriptor is 0, then the RR round-robin control information is updated to the queue number of the current queue; at this time, RR polling will start judging from the queues after the current queue, and the current queue becomes the lowest priority.

[0166] If, after slice descriptor read is enabled, the latest remaining balance length minus the DMA move length of the current slice descriptor is not zero, then the RR round-robin control information is updated to the current queue number - 1. This round-robin control allows the current queue number to be selected even when the queue corresponding to the current queue number is not empty, thus ensuring that the current queue meets the requirements of the preset descriptor balance length configuration information.

[0167] The interaction between this module and the descriptor slice processing module 42 is as follows: This module receives the same information output by the polling module 44 as the descriptor slicing processing module 42, so the latest remaining equalization length output by this module corresponds to the descriptor being processed by the descriptor slicing processing module 42.

[0168] This module receives the DMA move length of the current slice descriptor output by the descriptor slice processing module 42, and uses it to update the remaining equalization length.

[0169] In some embodiments, the multi-queue descriptor balancing scheduling chip includes a processor and a memory storing program instructions. The processor is configured to execute the multi-queue descriptor balancing scheduling method provided in the foregoing embodiments when executing the program instructions. In some embodiments, the inter-queue descriptor balancing scheduling chip includes the inter-queue descriptor balancing scheduling device provided in the foregoing embodiments.

[0170] This application provides a computer-readable storage medium storing computer-executable instructions configured to execute the multi-queue descriptor balanced scheduling method provided in the foregoing embodiments.

[0171] This application provides a computer program product, which includes a computer program stored on a computer-readable storage medium. The computer program includes program instructions, which, when executed by a computer, cause the computer to perform the multi-queue descriptor balanced scheduling method provided in the foregoing embodiments.

[0172] The aforementioned computer-readable storage medium may be a transient computer-readable storage medium or a non-transitory computer-readable storage medium.

[0173] The aforementioned storage media can be non-transitory storage media, including: USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks or optical disks, and other media that can store program code, or they can be transient storage media.

[0174] The foregoing description and accompanying drawings fully illustrate embodiments of this application to enable those skilled in the art to practice them. Other embodiments may include structural, logical, electrical, procedural, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. Moreover, the terminology used in this application is for describing embodiments only and is not intended to limit the claims. As used in the description of embodiments and claims, the singular forms “a,” “an,” and “the” are intended to equally include the plural forms unless the context clearly indicates otherwise. Additionally, when used in this application, the terms “comprise” and its variations “comprises” and / or “comprising” refer to the presence of stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Unless otherwise specified, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, or apparatus that includes that element. In this document, each embodiment may focus on describing the differences from other embodiments, and similar or identical parts between embodiments can be referred to mutually. For methods, products, etc., disclosed in the embodiments, if they correspond to the method section disclosed in the embodiments, then the relevant parts can be referred to the description of the method section.

[0175] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0176] The methods and products (including but not limited to devices and equipment) disclosed in the embodiments herein can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units may be merely a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the shown or discussed units may be through some interfaces, and the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, i.e., they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to implement this embodiment according to actual needs. Furthermore, the functional units in the embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0177] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. In some alternative implementations, the functions marked in the blocks may occur in a different order than those shown in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

Claims

1. A method for balanced scheduling of descriptors across multiple queues, characterized in that, include: Get the first remaining move length of the first descriptor at the head of the current queue; The first remaining transfer length is the remaining DMA transfer length in the first descriptor. In the previous equalization process, if the first descriptor was not sliced, the first remaining transfer length is the DMA transfer length of the first descriptor. If the first descriptor has been sliced, the first remaining transfer length is the transfer length remaining after the DMA transfer length of the first descriptor has been sliced. If the first remaining transfer length is less than the initial remaining balance length, then one or more second descriptors adjacent to the first descriptor in the current queue are processed during this balance scheduling process; wherein, the initial remaining balance length is determined according to the preset descriptor balance length, which is configuration information, and the initial remaining balance length is used to represent the total DMA transfer length to be transferred in each transfer process in each queue based on the configuration information; the sum of the DMA transfer length of one or more second descriptors and the first remaining transfer length is greater than or equal to the initial remaining balance length; A first slice descriptor is generated based on a first remaining transfer length, and a first remaining balance length is obtained by subtracting the first remaining transfer length from the initial remaining balance length, and one or more second slice descriptors are generated based on the first remaining balance length and the DMA transfer length of one or more second descriptors. The first slice descriptor and one or more second slice descriptors are transferred to the subsequent DMA hardware transfer engine, so that the subsequent DMA hardware transfer engine can transfer data according to the first slice descriptor and one or more second slice descriptors; Update the remaining transfer length of the current queue head descriptor for use in the next balanced scheduling of descriptors; balanced scheduling is the process described above, from obtaining the first remaining transfer length to transferring the first slice descriptor and one or more second slice descriptors to the subsequent DMA hardware transfer engine. Move the current queue to the next queue and process the descriptors in the next queue in the same way.

2. The multi-queue descriptor balanced scheduling method according to claim 1, characterized in that, Generating a first slice descriptor based on a first remaining transfer length includes: generating a first slice descriptor using the first remaining transfer length as a new DMA transfer length; One or more second slice descriptors are generated based on the first remaining equalization length and the DMA move length of one or more second descriptors, including: If the DMA move length of a second descriptor is greater than the first remaining equalization length, then the first remaining equalization length is used as the new DMA move length to generate a second slice descriptor. If the DMA transfer length of the first second descriptor is less than the first remaining equalization length, then the DMA transfer length of the first second descriptor is used as the new DMA transfer length to generate the first second slice descriptor; the second remaining equalization length is obtained by subtracting the DMA transfer length of the first second descriptor from the first remaining equalization length; the second remaining equalization length is then compared with the DMA transfer length of the next second descriptor, and the second second slice descriptor is generated based on the comparison result; this process is repeated until the DMA transfer length of the second descriptor is greater than or equal to the latest remaining equalization length, and then the latest remaining equalization length is used as the new DMA transfer length to generate the last second slice descriptor.

3. The multi-queue descriptor balanced scheduling method according to claim 2, characterized in that, After obtaining the first slice descriptor, the first slice descriptor is sent to the subsequent DMA hardware transfer engine. After the subsequent DMA hardware transfer engine has completed the transfer, one or more second slice descriptors are obtained. Rotating the current queue to the next queue includes: rotating the current queue to the next queue if the DMA move length of the second descriptor is greater than or equal to the latest remaining equalization length.

4. The multi-queue descriptor balanced scheduling method according to claim 3, characterized in that, If the subsequent DMA hardware transfer engine has completed transferring the data specified by the first slice descriptor, or if the DMA transfer length of the second descriptor is less than the first remaining equalization length and the subsequent DMA hardware transfer engine has completed transferring the data specified by the second slice descriptor, the rotation starts from the queue number of the current queue minus one, and the next queue is still the current queue. If the DMA move length of the second descriptor is greater than or equal to the latest remaining equalization length, and the subsequent DMA hardware move engine has moved all the data specified by the last second slice descriptor, then the current queue number is used as the starting point for round-robin operation, and the first non-empty queue encountered is used as the current queue again.

5. The multi-queue descriptor balanced scheduling method according to claim 1, characterized in that, Also includes: If the first remaining transfer length is greater than the initial remaining equalization length, the first slice descriptor is generated using the initial remaining equalization length as the new DMA transfer length. The first slice descriptor is transferred to the subsequent DMA hardware transfer engine, which then transfers data based on the first slice descriptor.

6. The multi-queue descriptor balanced scheduling method according to any one of claims 1 to 5, characterized in that, When each descriptor to be processed enters the queue, an index is created for each descriptor to be processed; the DMA transfer length corresponding to the indexed descriptor is obtained, and the index and DMA transfer length corresponding to the same descriptor are stored in the remaining length management array in a one-to-one correspondence. Obtaining the first remaining transfer length of the first descriptor at the head of the current queue includes: using the first index of the first descriptor as the address, obtaining the first remaining transfer length corresponding to the first index in the remaining length management array; Update the remaining move length of the current queue head descriptor, including: using the index of the current queue head descriptor as the address, update the remaining move length corresponding to the index of the current queue head descriptor in the remaining length management array; If the first remaining transfer length is less than the initial remaining balance length, reclaim the first index of the first descriptor and delete the first index and the first remaining transfer length from the remaining length management array.

7. The multi-queue descriptor balanced scheduling method according to any one of claims 1 to 5, characterized in that, The process of generating the first slice descriptor and the second slice descriptor includes: The queue number of the original descriptor is used as the queue number of the slice descriptor; wherein, the original descriptor includes a first descriptor, or one or more second descriptors; the slice descriptor is a first slice descriptor, or one or more second slice descriptors; The first sum of the DMA move source address of the original descriptor and the DMA move length of the original descriptor is obtained. The first difference is obtained by subtracting the remaining length after the slice descriptor has been moved from the first sum. The first difference is used as the DMA move source address of the slice descriptor. Obtain the second sum of the DMA move destination address of the original descriptor and the DMA move length of the original descriptor. Subtract the remaining length after the slice has been moved from the second sum to obtain the second difference. Use the second difference as the DMA move destination address of the slice descriptor.

8. A multi-queue descriptor balanced scheduling device, characterized in that, It includes a descriptor remaining length management module, a descriptor slice processing module, a polling and rotation control module, and a polling module; The descriptor slicing processing module obtains the first remaining transfer length of the first descriptor at the head of the current queue from the descriptor remaining length management module; the first remaining transfer length is the remaining DMA transfer length in the first descriptor. In the previous equalization process, if the first descriptor has not been sliced, the first remaining transfer length is the DMA transfer length of the first descriptor. If the first descriptor has been sliced, the first remaining transfer length is the transfer length remaining after the DMA transfer length of the first descriptor has been sliced. If the first remaining transfer length is less than the initial remaining balance length, then one or more second descriptors adjacent to the first descriptor in the current queue are processed during this balance scheduling process; wherein, the initial remaining balance length is determined according to the preset descriptor balance length, which is configuration information, and the initial remaining balance length is used to represent the total DMA transfer length to be transferred in each transfer process in each queue based on the configuration information; the sum of the DMA transfer length of one or more second descriptors and the first remaining transfer length is greater than or equal to the initial remaining balance length; A first slice descriptor is generated based on a first remaining transfer length, and a first remaining balance length is obtained by subtracting the first remaining transfer length from the initial remaining balance length, and one or more second slice descriptors are generated based on the first remaining balance length and the DMA transfer length of one or more second descriptors. The first slice descriptor and one or more second slice descriptors are transferred to the subsequent DMA hardware transfer engine, so that the subsequent DMA hardware transfer engine can transfer data according to the first slice descriptor and one or more second slice descriptors; The descriptor remaining length management module updates the remaining transfer length of the current queue head descriptor for use in the next balanced scheduling of descriptors; balanced scheduling is the process described above, from obtaining the first remaining transfer length to transferring the first slice descriptor and one or more second slice descriptors to the subsequent DMA hardware transfer engine; Both the polling control module and the polling module rotate the current queue to the next queue.

9. The multi-queue inter-descriptor balanced scheduling device according to claim 8, characterized in that, It also includes a descriptor enqueue control module and a descriptor queue module; When each descriptor to be processed enters the queue, the descriptor enqueue control module indexes each descriptor to be processed; obtains the DMA transfer length corresponding to the indexed descriptor; and stores the index and DMA transfer length corresponding to the same descriptor in the remaining length management array in a one-to-one correspondence. The descriptor enqueue control module assigns a queue number to each descriptor to be processed and sends the descriptor to be processed to the queue with the same queue number in the descriptor queue module; The polling module polls each queue in the descriptor queue module, designates a non-empty queue as the current queue, reads the queue number, the first index of the first descriptor at the head of the queue, and the first descriptor information, and sends the queue number, first index, and first descriptor information of the current queue to the descriptor slice processing module and the polling and round-robin control module; wherein, the first descriptor information includes the DMA transfer source address and the DMA transfer destination address of the first descriptor; The descriptor slicing processing module uses the first index of the first descriptor as the address and obtains the first remaining transfer length corresponding to the first index in the remaining length management array. The polling and round-robin control module sends the initial remaining balanced length of the current queue to the descriptor slice processing module; When the first remaining transfer length is less than the initial remaining equalization length, the descriptor slice processing module generates a first slice descriptor based on the first remaining transfer length, and sends the transfer length of the first slice descriptor to the polling and round-robin control module, and then transmits the first slice descriptor to the subsequent DMA hardware transfer engine. The polling and rotation control module obtains the first remaining balance length by subtracting the first remaining transfer length from the initial remaining balance length, and transmits the first remaining balance length to the descriptor slice processing module; The descriptor slice processing module interacts with the polling and rotation control module, and the two generate one or more second slice descriptors based on the first remaining equalization length and the DMA transfer length of one or more second descriptors; After the DMA transfer length of the second descriptor is greater than or equal to the latest remaining balanced length, and the last second slice descriptor is generated using the latest remaining balanced length as the new DMA transfer length, the descriptor slice processing module transfers the last second slice descriptor to the subsequent DMA hardware transfer engine; using the index of the current queue head descriptor as the address, the remaining transfer length corresponding to the index of the current queue head descriptor is updated in the remaining length management array in the descriptor remaining length management module; and the transfer length of the last second slice descriptor is transferred to the polling round-robin control module. The polling control module obtains a zero result by subtracting the DMA move length of the last second descriptor from the latest remaining balanced length. The zero result triggers the following operation: the queue number of the current queue is transmitted to the polling module. The polling module starts from the queue number of the current queue and takes the first non-empty queue encountered as the current queue.

10. A multi-queue descriptor load balancing scheduling chip, characterized in that, The system includes a processor and a memory storing program instructions, wherein the processor is configured to perform the multi-queue descriptor load balancing scheduling method as described in any one of claims 1 to 7 when executing the program instructions; Alternatively, the multi-queue descriptor balancing scheduling chip includes the multi-queue descriptor balancing scheduling device as described in claim 8 or 9.

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