A spaceborne NPU system

Abstract

The application provides a satellite-borne NPU system, which comprises a piece of space-grade high-reliability FPGA, multiple pieces of commercial high-performance NPU and peripheral supporting circuits; the FPGA is responsible for high-reliability system control, and the NPU is responsible for high-performance data processing; the FPGA provides clock, reset and other control signals for the NPU, and completes NPU firmware, operating system, driver, application software storage and loading as well as data preprocessing and service distribution; the power management function of the NPU is realized by FPGA control; meanwhile, a voltage, current and temperature multi-dimensional monitoring network is constructed with the FPGA as the core to monitor the working state of the NPU; multiple NPU adopts dynamic redundancy configuration for fault replacement and resource expansion. The advantage of the application lies in that the commercial NPU can be applied to space tasks requiring high computing power by radiation resistance reinforcement of mature commercial NPU on the ground, thereby reducing development cost and improving reliability.

Description

Technical Field

[0001] This application belongs to the field of hardened technology for spaceborne AI accelerators, specifically relating to a spaceborne NPU system. Background Technology

[0002] With the continuous development of the demand for intelligent computing in space, there is a need to operate high-performance AI processors such as NPUs in the extreme force, heat, radiation and vacuum environment of space. However, due to factors such as process and cost, there are currently few models of spaceborne NPUs available, and their computing power is generally lower than that of ground-based products.

[0003] The shortcomings of existing spaceborne NPUs are mainly reflected in the following aspects: First, there is a huge gap in computing power performance. Traditional aerospace-grade devices, in order to mitigate risks, heavily rely on mature and stable manufacturing nodes, resulting in a computing performance several orders of magnitude lower than mainstream terrestrial AI chips that follow Moore's Law. Their actual computing power lags behind terrestrial products by 3 to 4 generations, making it difficult to meet the demands of modern aerospace applications for large-scale model inference and real-time processing of massive amounts of data. Second, the development cycle and iteration speed are severely out of sync. Aerospace-grade processors must complete long-term processes such as demonstration, design, development, and on-orbit testing, often iterating every ten years, which cannot keep up with the 18-month iteration pace of terrestrial AI chips. Finally, the cost is extremely high, accompanied by significant performance loss. If all dedicated radiation-hardening methods are adopted, not only will the development cost be extremely high, but the hardening process will also introduce additional performance losses, making it difficult to simultaneously meet the dual requirements of high reliability and high computing density.

[0004] Therefore, it is of great significance to apply mature commercial high-performance NPUs to aerospace systems with high reliability after hardening. This is not only key to breaking through the bottleneck of space-based computing power, but also a core path to improving the performance ceiling and scalability of space computing platforms. Summary of the Invention

[0005] The purpose of this application is to apply commercial high-performance NPUs, after radiation hardening, to aerospace missions in order to improve the on-orbit intelligent computing power of spaceborne intelligent computing systems.

[0006] To achieve the above objectives, this application proposes a spaceborne NPU system, comprising: One aerospace-grade FPGA, multiple commercial NPUs, and peripheral circuitry; among them... The aerospace-grade FPGA is used for system management, loading and configuration management of the NPU, providing clock and control signals to the NPU, and allocating service data to the NPU; The commercial NPU is used for data processing; The peripheral supporting circuitry includes: Radiation-hardened memory, electrically connected to aerospace-grade FPGA, is used to store NPU firmware, operating system, drivers, and application software; Radiation-resistant cache, electrically connected to aerospace-grade FPGA, is used to cache business data for NPU and to cache intermediate calculation results during data preprocessing.

[0007] As an improvement to the above system, it also includes: Aerospace-grade radiation-hardened DC-DC / LDO is used to power the system; the FPGA controls the DC-DC / LDO enable pin, thereby controlling the NPU power-on; and The feedback voltage adjustment circuit is electrically connected to the FPGA and the aerospace-grade radiation-hardened DC-DC / LDO. The FPGA controls the feedback terminal voltage of the DC-DC / LDO through the feedback voltage adjustment circuit, thereby adjusting the output voltage of the DC-DC / LDO and realizing the dynamic voltage and frequency adjustment function of the NPU.

[0008] As an improvement to the above system, the FPGA has a built-in ADC function, which, together with precision resistors and thermistors, is used to monitor the voltage, current and temperature of the NPU.

[0009] As an improvement to the above system, it also includes: The intelligent fault diagnosis software module is used to determine whether the NPU is operating normally and to locate the cause of the problem after a fault occurs, based on the voltage, current, temperature and workload data of the normally operating NPU.

[0010] As an improvement to the above system, the intelligent fault diagnosis software module is implemented based on a lightweight LSTM neural network model.

[0011] As an improvement to the above system, the FPGA operates a basic state monitoring module; the basic state monitoring module includes: The data acquisition submodule is used to collect voltage, current and temperature data of the NPU and output them to the status judgment submodule; The status judgment submodule is used to determine whether the NPU is working properly based on a set threshold, or to call the intelligent fault diagnosis software module to determine the health status of the NPU. The task control submodule is used to power down a failed NPU and simultaneously activate a dynamically redundant NPU, running task software to take over the work of the failed NPU when one fails. The telemetry and remote control submodule is used to send the system's operating status information to external systems, receive remote control commands from external systems, and set the system's operating status.

[0012] As an improvement to the above system, the number of commercial NPUs is greater than the number of NPUs required for normal operation.

[0013] Compared with existing technologies, the advantages of this application are: By hardening mature commercial NPUs on the ground to withstand radiation, commercial NPUs can be applied to aerospace missions that require high computing power, reducing development costs, improving reliability, and enhancing the on-orbit intelligent computing power of spaceborne intelligent computing systems. Attached Figure Description

[0014] Figure 1 The diagram shown is a schematic diagram of the system principle of this application; Figure 2 The diagram shown is a schematic block diagram of an embodiment of this application. Detailed Implementation

[0015] The technical solution of this application will be described in detail below with reference to the accompanying drawings.

[0016] This application proposes a spaceborne NPU system. By hardening a commercial high-performance NPU against radiation to improve its reliability, the commercial high-performance NPU can be applied to aerospace missions to enhance on-orbit intelligent computing power.

[0017] like Figure 1 As shown, the spaceborne NPU system proposed in this application includes a space-grade high-reliability FPGA, multiple commercial high-performance NPUs, and their peripheral circuitry. The FPGA is responsible for high-reliability system management, while the NPUs handle high-performance data processing. The FPGA has an external radiation-hardened high-capacity memory for storing NPU firmware, operating system, drivers, and application software. The FPGA loads and configures the NPU according to the NPU loading interface protocol and timing requirements, providing clock, reset, and other control signals to the NPU. An external radiation-hardened high-speed cache is used to cache business data for the NPU and perform data preprocessing before distributing the preprocessed data to the NPU for processing. The FPGA uses devices with built-in ADCs, along with precision resistors and thermistors, to construct a low-cost, high-reliability multi-dimensional monitoring network for NPU voltage, current, and temperature, allowing the FPGA to monitor the NPU's operating status.

[0018] The NPU is powered by an aerospace-grade radiation-hardened DC-DC / LDO. The FPGA controls the enable pin of the DC-DC / LDO to control the power-on of the NPU. At the same time, the FPGA controls the feedback pin voltage of the DC-DC / LDO through a feedback voltage adjustment circuit, thereby adjusting the output voltage of the DC-DC / LDO and realizing the dynamic voltage and frequency adjustment function of the NPU.

[0019] Multiple NPUs employ a dynamic redundancy scheme, configuring more NPUs than are required for normal operation. The dynamic redundant NPUs can be used to replace faulty NPUs or expand resources. The dynamic redundant NPUs can also run intelligent fault diagnosis software after power-on loading, serving as an auxiliary to the FPGA to jointly monitor the status and diagnose faults of normally operating NPUs.

[0020] Example 1 like Figure 2 As shown, the onboard NPU system provided in this embodiment includes one aerospace-grade high-reliability FPGA (model JFM7VX690T-RT), two commercial high-performance NPUs Ascend 310 and their peripheral circuits.

[0021] The JFM7VX690T-RT is responsible for high-reliability system management, while the Ascend 310 is responsible for high-performance data processing. The JFM7VX690T-RT has an external radiation-hardened high-capacity NAND flash memory SMR29F512G08SRMP for storing the Ascend 310 firmware, operating system, drivers, and application software. The Ascend 310 firmware loading interface is the SFC interface, and the operating system loading interface is the eMMC interface. The JFM7VX690T-RT performs loading configuration management for the Ascend 310 according to the corresponding interface protocols and timing requirements, and provides clock, reset, and serial port control signals for the Ascend 310. The JFM7VX690T-RT also has an external radiation-hardened high-speed DDR3 cache SMR41J256M16MP for caching service data for the Ascend 310 and performing data preprocessing, before distributing the preprocessed service data to the Ascend 310 for processing.

[0022] The Ascend 310's high-current power supply uses an aerospace-grade radiation-hardened DC-DC converter, the RSHP4650SRH, while other power supplies use aerospace-grade radiation-hardened DC-DC converters, the RSHF4644ARH, and the LDO, the RSW1101IRH. The JFM7VX690T-RT controls the enable pins of the RSHP4650SRH / RSHF4644ARH / RSW1101IRH to power on the Ascend 310. The voltage feedback pin FB of the RSHP4650SRH is connected to the voltage output of the radiation-hardened D / A converter, the B121S101RSC. The JFM7VX690T-RT controls the output voltage of the B121S101RSC, thereby adjusting the output voltage of the RSHP4650SRH and enabling the Ascend 310's dynamic voltage and frequency regulation function.

[0023] The JFM7VX690T-RT features a built-in ADC function, which, together with precision resistors and thermistors, enables the construction of a low-cost, highly reliable multi-dimensional monitoring network for Ascend 310 voltage, current, and temperature. The JFM7VX690T-RT monitors the operating status of the Ascend 310.

[0024] One Ascend 310 chip is sufficient for normal NPU operation to meet computing power requirements. The system is configured with two Ascend 310 chips, connected to the JFM7VX690T-RT in the same manner. One chip serves as a dynamic redundancy unit, which can reduce system power consumption by not requiring power, or run an intelligent fault diagnosis software module after power-on to assist the FPGA in intelligently diagnosing faults in the normally operating Ascend 310. The intelligent fault diagnosis software module uses an existing lightweight LSTM neural network, primarily relying on data such as voltage, current, temperature, and workload of the normally operating Ascend 310 to determine whether it is operating normally and to locate the cause of faults. The JFM7VX690T-RT runs a basic status monitoring module, which includes a data acquisition submodule, a status judgment submodule, an NPU operation control submodule, and a telemetry and control submodule. The data acquisition submodule collects voltage, current, and temperature data from the Ascend 310 during normal operation and sends this data to the status judgment submodule to determine the Ascend 310's operating status. The status judgment submodule can directly determine whether the Ascend 310 is operating normally based on set thresholds, or it can call the intelligent fault diagnosis software module to determine the Ascend 310's health status. If a normally operating Ascend 310 malfunctions, the NPU operation control submodule can power down the faulty Ascend 310 and simultaneously activate the dynamically redundant Ascend 310, running the normal task software to take over the faulty 310's operation. The JFM7VX690T-RT packages its own operating status and the Ascend 310's operating status information and sends it to the upper-level main control unit via the telemetry and remote control submodule. It can also receive remote control commands from the upper-level main control unit to set its own and the Ascend 310's operating status. If the system needs resource expansion, it can also receive remote control commands from the upper-level main control unit to power on the dynamically redundant Ascend 310.

[0025] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application and are not intended to limit it. Although this application has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions to the technical solutions of this application do not depart from the spirit and scope of the technical solutions of this application, and should all be covered within the scope of the claims of this application.

Claims

1. A spaceborne NPU system, characterized in that, include: One aerospace-grade FPGA, multiple commercial NPUs, and peripheral circuitry; among them... The aerospace-grade FPGA is used for system management, loading and configuration management of the NPU, providing clock and control signals to the NPU, and allocating service data to the NPU; The commercial NPU is used for data processing; The peripheral supporting circuitry includes: Radiation-hardened memory, electrically connected to the aerospace-grade FPGA, is used to store NPU firmware, operating system, drivers, and application software; and Radiation-resistant cache, electrically connected to aerospace-grade FPGA, is used to cache business data for NPU and to cache intermediate calculation results during data preprocessing.

2. The spaceborne NPU system according to claim 1, characterized in that, Also includes: Aerospace-grade radiation-hardened DC-DC / LDO is used to power the system; the FPGA controls the enable pin of the DC-DC / LDO, thereby controlling the power-on of the NPU. and The feedback voltage adjustment circuit is electrically connected to the FPGA and the aerospace-grade radiation-hardened DC-DC / LDO. The FPGA controls the feedback terminal voltage of the DC-DC / LDO through the feedback voltage adjustment circuit, thereby adjusting the output voltage of the DC-DC / LDO and realizing the dynamic voltage and frequency adjustment function of the NPU.

3. The spaceborne NPU system according to claim 1, characterized in that, The FPGA has a built-in ADC function, which, together with precision resistors and thermistors, is used to monitor the voltage, current and temperature of the NPU.

4. The spaceborne NPU system according to claim 1, characterized in that, Also includes: The intelligent fault diagnosis software module is used to determine whether the NPU is operating normally and to locate the cause of the problem after a fault occurs, based on the voltage, current, temperature and workload data of the normally operating NPU.

5. The spaceborne NPU system according to claim 4, characterized in that, The intelligent fault diagnosis software module is implemented based on a lightweight LSTM neural network model.

6. The spaceborne NPU system according to claim 4, characterized in that, The FPGA runs a basic status monitoring software module; the basic status monitoring software module includes: The data acquisition submodule is used to collect voltage, current and temperature data of the NPU and output them to the status judgment submodule; The status judgment submodule is used to determine whether the NPU is working properly based on a set threshold, or to call the intelligent fault diagnosis software module to determine the health status of the NPU. The task control submodule is used to power down a failed NPU and simultaneously activate a dynamically redundant NPU, running task software to take over the work of the failed NPU when one fails. The telemetry and remote control submodule is used to send the system's operating status information to external systems, receive remote control commands from external systems, and set the system's operating status.

7. The spaceborne NPU system according to claim 1, characterized in that, The number of commercial NPUs is greater than the number of NPUs required for normal operation.

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