Network-on-chip interconnect system

Abstract

The present disclosure relates to a kind of network interconnection system on chip, including the multiple core clusters of M × N grid topology, core cluster includes computing core and target node;Grid topology is symmetrically divided into multiple domains;Target node in the same domain is linked by node link, computing core and target node in the same core cluster are linked by internal link, computing core in different domains only in the core cluster in symmetrical position is linked by inter-domain link;Computing core is routed to access target node in the same core cluster by internal link, computing core is routed to access target node in the same domain by node link with the target node in the same core cluster as relay, computing core is routed to access target node in the domain of relay computing core with the computing core not in the same domain as relay, through the internal link and node link of relay computing core corresponding by relay computing core, target node in the domain of relay computing core is accessed;The bandwidth of computing core on each link is determined according to the total bandwidth of the number of linked target nodes.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and more specifically, to an on-chip network interconnection system. Background Technology

[0002] As integrated circuits have entered the nanometer process, multi-core / many-core system-on-chip (SoC) architectures have become the mainstream. Traditional shared buses and crossbar interconnects face bottlenecks such as insufficient bandwidth, poor scalability, difficulty in global synchronization, and high power consumption, making it difficult to support the high concurrency, high throughput, and low latency on-chip communication requirements of dozens to hundreds of computing cores, caches, and dedicated hardware IPs. Network on Chip (NoC), drawing on the ideas of macroscopic network packet switching, constructs a distributed communication architecture using routers, links, and network interfaces, becoming a solution for on-chip communication. Among these, routing path planning is the core of NoC, directly affecting latency, throughput, power consumption, and reliability.

[0003] In existing mainstream routing schemes, the XY routing method has a single and fixed path, which easily leads to hotspot congestion on specific links, resulting in low link utilization and decreased throughput. Traditional adaptive routing methods can dynamically select routes based on local congestion status to alleviate congestion, but this is prone to deadlock, and routing decisions based on local information may not achieve overall optimization. Summary of the Invention

[0004] To overcome the problems existing in related technologies, this disclosure provides an on-chip network interconnection system.

[0005] To achieve the above objectives, this disclosure provides an on-chip network interconnection system, including a first number of core clusters, the first number of core clusters forming an M×N mesh topology, each core cluster including at least one computing core and at least one target node, the target node having a corresponding relationship with the computing core; The grid topology is symmetrically divided into multiple domains, and each domain includes a second number of core clusters, where the second number is less than the first number. The target nodes within the same domain are linked by node links; the computing cores and target nodes within the same core cluster are linked by internal links; and the computing cores within core clusters in different domains but in symmetrical positions are linked by inter-domain links. The computing core accesses the target node in the same core cluster through internal link routing. The computing core uses the target node in the same core cluster as a relay to access other target nodes in the same domain through node link routing. The computing core uses the computing core in a different domain as a relay to access the target node in the domain of the computing core that is the relay through the internal link corresponding to the computing core that is the relay and the node link in the domain where the computing core is located. The bandwidth of the computing core on each of the links is determined by dividing the total bandwidth of the computing core equally among the number of target nodes linked to it.

[0006] Optionally, each core cluster includes multiple computing cores and multiple target nodes; the multiple computing cores and multiple target nodes in the core cluster are divided into multiple isolated groups, each group includes at least one computing core and a target node corresponding to the computing core, and there is no communication link between the computing cores and target nodes in different groups in the core cluster; the multiple groups in the core cluster are all numbered according to their location, and the target nodes in the groups with the same location number in each core cluster are linked by node links.

[0007] Optionally, the mesh topology is divided into multiple core cluster partitions, each core cluster partition including multiple domains, and each domain is assigned to only one core cluster partition; wherein, core cluster partitions in symmetrical positions in the mesh topology are linked by interval links to computing cores in the same core clusters with the same position number in the same position within the two core cluster partitions; wherein, based on the interval links, the computing core uses a computing core not in the same core cluster partition as a relay, and routes access to the target node in the domain of the relay computing core through the internal links corresponding to the relay computing core and the node links within the domain.

[0008] Optionally, the grid topology is divided into two core cluster partitions with the same number of core clusters. Each core cluster partition is divided into two domains with the same number of core clusters. Each domain includes four core clusters arranged in a 2×2 layout. The computing cores in the core clusters that are only in symmetrical positions in different domains are linked by inter-domain links.

[0009] Optionally, the grid topology is divided into two core cluster partitions with the same number of core clusters, and each core cluster partition is divided into two domains with the same number of core clusters, left and right.

[0010] Optionally, the bandwidth of each node link is determined by dividing the bandwidth of the internal link between the computing core and the corresponding target node equally according to the number of target nodes in the domain to obtain the bandwidth of a single node link, and then determining it by multiplying the number of target nodes on the node link away from the computing core by the bandwidth of the single node link.

[0011] Optionally, the plurality of computing cores and the plurality of target nodes in each core cluster are divided into two mutually isolated groups, left and right.

[0012] Optionally, the number of target nodes in each core cluster is the same as the number of computing cores in that core cluster, and there is a one-to-one correspondence between the target nodes and the computing cores. Each group includes one computing core and one target node.

[0013] Optionally, the target nodes within the same domain are connected in series via node links.

[0014] Optionally, the computing core in the on-chip network interconnection system is linked to computing cores in other on-chip network interconnection systems via cross-die links; the computing core uses the computing core in a different on-chip network interconnection system as a relay, and routes access to the target node in the domain of the relay computing core through the internal link corresponding to the relay computing core and the node link in the domain.

[0015] In the above scheme, the on-chip network interconnection system constructs an M×N mesh topology for the core clusters and symmetrically divides it into multiple domains. Node links are established between target nodes within a domain, internal links within a core cluster, and inter-domain links between core clusters located symmetrically in different domains. This allows the computing cores to access target nodes within the same core cluster, other target nodes within the same domain, and target nodes in different domains through three routing modes. The bandwidth of each link is determined by the average distribution of total bandwidth among target nodes. Thus, customized routing paths can be planned for each computing core's communication with target nodes based on the chip's usage scenario, ensuring that each link's traffic is neither overloaded nor idle, achieving load balancing, avoiding congestion on hotspot paths, and improving memory access performance. Simultaneously, different virtual channels can be flexibly allocated to different routing paths, fundamentally avoiding deadlocks caused by dependency cycles. Furthermore, router nodes do not require complex address resolution, routing calculations, and multi-flow arbitration; data can be directly forwarded, reducing per-hop latency. In addition, the symmetrical routing paths have neat wiring, which is beneficial for backend implementation and timing convergence.

[0016] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings: Figure 1 This is a schematic diagram of the topology of an on-chip network interconnection system according to an exemplary embodiment.

[0018] Figure 2 This is a schematic diagram illustrating bandwidth allocation and routing path planning of an on-chip network interconnection system according to an exemplary embodiment.

[0019] Figure 3 This is a schematic diagram illustrating bandwidth allocation and routing path planning of an on-chip network interconnection system according to an exemplary embodiment.

[0020] Figure 4 This is a schematic diagram illustrating bandwidth allocation and routing path planning of an on-chip network interconnection system according to an exemplary embodiment.

[0021] Figure 5 This is a schematic diagram illustrating bandwidth allocation and routing path planning of an on-chip network interconnection system according to an exemplary embodiment. Detailed Implementation

[0022] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0023] As the number of computing cores in multi-core / many-core SoCs increases, the bandwidth and latency requirements of on-chip communication are constantly rising. Existing XY routing methods have single, fixed paths, which easily lead to hotspot congestion on specific links, resulting in low link utilization. Traditional adaptive routing methods, while capable of dynamic route selection, are prone to deadlock, and routing calculations and multi-flow arbitration increase router latency. To address these issues, embodiments of this disclosure provide an on-chip network interconnection system that achieves load balancing and avoids deadlock by symmetrically partitioning domains and customizing routing path planning.

[0024] Figure 1 This is a schematic diagram illustrating the topology of an on-chip network interconnection system according to an exemplary embodiment. (Refer to...) Figure 1 The present disclosure provides an on-chip network interconnection system, including a first number of core clusters, the first number of core clusters forming an M×N mesh topology, each core cluster including at least one computing core and at least one target node, the target node having a corresponding relationship with the computing core; The computing core can be the master device in the core cluster, which is used to initiate data access requests; the target node can be a slave device or a storage node, which is used to receive access requests from the computing core and provide data services.

[0025] In one implementation, the computing core may include computing units such as a central core cluster, a graphics core cluster, and an artificial intelligence acceleration core, for example... Figure 1 Modules directly identified by "R" in the code; target nodes can include target devices such as cache controllers, memory controllers, and direct memory access (DMA) controllers, etc. Figure 1 In this context, a "T" is used next to a module identified by "R". The correspondence between target nodes and computing cores can mean that each computing core has one or more corresponding target nodes within the same core cluster, and these target nodes can serve as the local access entry point for that computing core.

[0026] The grid topology is symmetrically divided into multiple domains, and each domain includes a second number of core clusters, where the second number is less than the first number. The target nodes within the same domain are linked by node links; the computing cores and target nodes within the same core cluster are linked by internal links; and the computing cores within core clusters in different domains but in symmetrical positions are linked by inter-domain links. Among them, see Figure 1 As shown, core cluster c10 in domain 1 and core cluster c13 in domain 2 are two core clusters in symmetrical positions in different domains, so they are linked by an inter-domain link. However, core cluster c10 in domain 1 and core cluster c12 in domain 2 are two core clusters in asymmetrical positions in different domains, so they are not linked by an inter-domain link. Similarly, whether core clusters in other positional relationships are linked by inter-domain links is determined by whether they are two core clusters in asymmetrical positions in different domains, which will not be elaborated here.

[0027] It should be noted that not all core clusters in symmetrical positions in an on-chip network interconnection system must be linked through inter-domain links. For example, core cluster c13 in domain 2 and core cluster c17 in domain 4 are two core clusters in symmetrical positions in different domains, but there is no routing requirement between core cluster c13 in domain 2 and core cluster c17 in domain 4. Therefore, core cluster c13 in domain 2 and core cluster c17 in domain 4 can be linked without inter-domain links.

[0028] The computing core accesses the target node in the same core cluster through internal link routing. The computing core uses the target node in the same core cluster as a relay to access other target nodes in the same domain through node link routing. The computing core uses the computing core in a different domain as a relay to access the target node in the domain of the computing core that is the relay through the internal link corresponding to the computing core that is the relay and the node link in the domain where the computing core is located. See Figure 1 As shown, in an on-chip network interconnect system, there are three types of communication links: The first type is node links. Target nodes within the same domain are linked via node links. Node links are used to enable data transmission between target nodes in different core clusters within the same domain, allowing computing cores to access target nodes in other core clusters within the same domain via node links, using target nodes in their own core cluster as relays.

[0029] In one implementation, target nodes within the same domain can be sequentially connected in series via communication links, forming a link path that runs through all target nodes in the domain. Data packets sent by the computing core can enter the node link from the target node of its core cluster and sequentially reach other target nodes within the same domain along the serial path.

[0030] The second type is the internal link. The computing cores and target nodes within the same core cluster are linked via internal links. These internal links are direct channels between computing cores and target nodes within the core cluster, used for computing cores to access target nodes within the same core cluster, and as relay channels for cross-domain or cross-partition routing.

[0031] In one implementation, each computing core can be connected to the target node of the corresponding group in its core cluster via an internal link, and the bandwidth of the internal link can be evenly distributed according to the total bandwidth of the computing core and the number of links connected.

[0032] The third type is inter-domain links. Computing cores in core clusters located only symmetrically in different domains are linked via inter-domain links. These links connect computing cores in symmetrically located core clusters across different domains, allowing a computing core in one domain to access target nodes within the domain of a relay computing core, using a relay computing core in another domain as a relay.

[0033] In one implementation, if the two domains are the left and right domains of the same core cluster partition, the computing core of the core cluster located at a specific position in the left domain is linked to the computing core of the same level core cluster located in a symmetrical position in the right domain through an inter-domain link.

[0034] Furthermore, based on the above three types of links, the on-chip network interconnection system supports three routing modes: The first routing mode: The computing core accesses the target node within the same core cluster via an internal link. For example, when a computing core needs to access a target node within the same core cluster, data packets can be directly transmitted from the computing core to the corresponding target node via an internal link, without needing to traverse intra-domain or inter-domain links. This is the shortest routing path with the lowest latency.

[0035] The second routing mode: The computing core uses the target node within the same core cluster as a relay to access other target nodes within the same domain via the node link. For example, when a computing core needs to access a target node in another core cluster within the same domain, the data packet first reaches the target node in its own core cluster via an internal link, then accesses the node link through that target node, and is transmitted along the node link to the target node in the target core cluster. For example, in an implementation where a domain contains four core clusters, a computing core in the first core cluster can access target nodes in the second, third, and fourth core clusters via the target node in its own core cluster. Figure 1 As shown in Domain 1, the computing core in core cluster c10 in Domain 1 can enter the node link through the target node in core cluster c10 to access the target node in core cluster c11, the target node in core cluster c14, and the target node in core cluster c15 in Domain 1, respectively.

[0036] The third routing mode: The computing core uses a computing core that is not in the same domain as it as a relay, and routes to the target node in the domain of the computing core that is the relay through the internal link corresponding to the computing core that is the relay and the node link in the domain.

[0037] In one implementation, when a computing core needs to access target nodes in different domains, the data packet is first transmitted via an inter-domain link to a computing core in a symmetrically located core cluster within the target domain. Then, it reaches the target node within that core cluster via an internal link of that relay computing core. Finally, it accesses other target nodes within the domain via node links within that domain. This routing pattern utilizes symmetrically located core clusters as relay nodes to achieve cross-domain data access.

[0038] by Figure 1As shown in Domain 1 and Domain 2, the computing core in core cluster c10 in Domain 1 can access the internal link of core cluster c13 and the corresponding node link in Domain 2 via the computing core in core cluster c13 in Domain 2, respectively accessing the target node in core cluster c12, the target node in core cluster c13, the target node in core cluster c16, and the target node in core cluster c17 in Domain 2.

[0039] The bandwidth of the computing core on each of the links is determined by dividing the total bandwidth of the computing core equally among the number of target nodes linked to it.

[0040] In this embodiment of the disclosure, load balancing can be achieved by calculating the total bandwidth of the core by evenly distributing the number of target nodes in the core link. Furthermore, the aforementioned node links, internal links, and inter-domain links can avoid hotspot path congestion and improve memory access performance.

[0041] In the above scheme, the on-chip network interconnection system constructs an M×N mesh topology for the core clusters and symmetrically divides it into multiple domains. Node links are established between target nodes within a domain, internal links within a core cluster, and inter-domain links between core clusters located symmetrically in different domains. This allows the computing cores to access target nodes within the same core cluster, other target nodes within the same domain, and target nodes in different domains through three routing modes. The bandwidth of each link is determined by the average distribution of total bandwidth among target nodes. Thus, customized routing paths can be planned for each computing core's communication with target nodes based on the chip's usage scenario, ensuring that each link's traffic is neither overloaded nor idle, achieving load balancing, avoiding congestion on hotspot paths, and improving memory access performance. Simultaneously, different virtual channels can be flexibly allocated to different routing paths, fundamentally avoiding deadlocks caused by dependency cycles. Furthermore, router nodes do not require complex address resolution, routing calculations, and multi-flow arbitration; data can be directly forwarded, reducing per-hop latency. In addition, the symmetrical routing paths have neat wiring, which is beneficial for backend implementation and timing convergence.

[0042] Optionally, each core cluster includes multiple computing cores and multiple target nodes; The plurality of computing cores and the plurality of target nodes in the core cluster are divided into a plurality of mutually isolated groups. Each group includes at least one computing core and a target node corresponding to the computing core. There is no communication link between the computing cores and the target nodes in different groups in the core cluster. In one implementation, the computing cores and target nodes within each core cluster can be divided into two isolated groups, left and right. For example, each core cluster includes two computing cores and two target nodes, vertically divided into a left group and a right group. Each group includes one computing core and one corresponding node. The computing cores in the left group can only access the target nodes in the left group, and the computing cores in the right group can only access the target nodes in the right group. There is no communication link between the left and right groups.

[0043] In this way, the group isolation mechanism makes the data traffic of different groups independent of each other, avoids cross-group traffic interference, and is conducive to achieving independent load balancing of each group.

[0044] The multiple groups in the core cluster are all numbered according to their location, and the target nodes of the groups with the same location number in the core cluster within each domain are linked by node links.

[0045] In one implementation, packets within each core cluster can be numbered according to their physical location within the core cluster; for example, the left packet is numbered group 0, and the right packet is numbered group 1. When a domain contains multiple core clusters, target nodes of packets with the same position number within each core cluster are linked via node links. For example, target nodes of the group in position 0 across the four core clusters in the domain are linked via one node link, while target nodes of the group in position 1 are linked via another node link. In this way, packets with different position numbers form their own independent node link networks, further ensuring traffic isolation between packets.

[0046] by Figure 1 Taking two groups in Domain 1 as an example, the computing cores and target nodes in core clusters c10, c11, c14, and c15 in Domain 1 are all divided into left group 0 and right group 1. Therefore, the target nodes corresponding to left group 0 in core clusters c10, c11, c14, and c15 are linked by node links, and the target nodes corresponding to left group 1 in core clusters c10, c11, c14, and c15 are linked by node links. However, there are no communication links between left group 0 and right group 1 in core clusters c10, c11, c14, and c15, thus achieving isolation between different groups.

[0047] Optionally, the mesh topology is divided into multiple core cluster partitions, each core cluster partition including multiple domains, and each domain is assigned to only one core cluster partition; for example, the upper half of the core clusters in the mesh topology constitutes the upper core cluster partition MP 0, and the lower half of the core clusters constitutes the lower core cluster partition MP 1.

[0048] In the mesh topology, the core cluster partitions located in symmetrical positions are connected by interval links to the computing cores of the groups with the same position number in the core clusters located in the same positions in the two core cluster partitions. See Figure 1 As shown, in one embodiment, the computing cores of the first group 0 of core cluster c10 in domain 1 of upper core cluster partition MP 0 are linked to the computing cores of the first group 0 of core cluster c10 in the same position in lower core cluster partition MP 1 (i.e., core cluster c10 in domain 1 of lower core cluster partition MP 1) via an interval link. The interval link is used to realize data transmission across core cluster partitions.

[0049] The computing core, based on the interval link, uses a computing core that is not in the same core cluster partition as it as a relay, and routes access to the target node in the domain of the computing core that is the relay through the internal link corresponding to the computing core that is the relay and the node link in the domain.

[0050] In one implementation, when a computing core in an upper core cluster partition needs to access a target node in a lower core cluster partition, the data packet is first transmitted via an inter-regional link to a computing core in the same core cluster in the lower core cluster partition (as a relay), then reaches the target node in that core cluster via the internal link of the relay computing core, and finally accesses other target nodes in that domain via the node link of that domain within the lower core cluster partition.

[0051] See Figure 1As shown, in the absence of cross-die routing, the mesh topology consists of MP0 in the upper half and MP1 in the lower half. Each MP contains 8 core clusters, each cluster comprising 2 compute cores and 2 target nodes. Each cluster is vertically divided into group0 and group1. The two groups, group0 and group1, within each core cluster are isolated from each other. Each compute core in group 0 can only access the target nodes of group0 within its respective cluster. Each core supports 1024 bits of bandwidth, with 512 bits of traffic within MP0. There are a total of 8 cores and 8 targets within an MP, with each core receiving 64 bits of traffic allocated to each target.

[0052] The following describes the routing path planning of the on-chip network interconnection system using specific routing examples. In one implementation, routing within a core cluster partition is used as an example. Figure 1 See Figures 2 to 5 As shown, the core cluster partition consists of 8 core clusters, divided into left and right domains. Each domain contains 4 core clusters arranged in a 2×2 layout. Each core cluster includes 2 computing cores and 2 target nodes, and is divided into 2 groups.

[0053] Taking the computing core of the first group of core cluster c10 in the left domain as an example, the total bandwidth of this computing core is 1024 bits, of which 256 bits are the traffic bandwidth within core cluster c10, 256 bits are the traffic bandwidth to another core cluster partition, 256 bits are the traffic bandwidth across the raw chip link, and 256 bits are the traffic bandwidth to core cluster c13 in the right domain. This core cluster partition contains 8 computing cores and 8 target nodes (taking the first group as an example). Each computing core is allocated 64 bits of traffic to each target node. The 512 bits of bandwidth of this computing core within the core cluster partition are carried through two routing paths, each carrying 256 bits of traffic, achieving the theoretical full bandwidth utilization of this computing core within the core cluster partition.

[0054] In one implementation, the first path can reach the target node of the first core cluster from its computing core via an internal link, and then reach the target nodes of the second, third, and fourth core clusters via node links, with each target node carrying 64 bits of traffic. For example, the 256 bits of traffic of the first routing path (which may be called the first path) are routed to the target nodes of the first group in core clusters c10, c11, c14, and c15, respectively.

[0055] The 256-bit traffic of the second routing path (which can be called the second path) is first routed to the computing core of the fifth core cluster, which is located symmetrically to the computing core in the first core cluster, and then routed to the target node of the first group in the core cluster in the domain where the fifth core cluster is located.

[0056] In one implementation, the second path originates from the computing core of the first core cluster, reaches the computing core of the fifth core cluster (as a relay) via an inter-domain link, then reaches its target node via an internal link of the fifth core cluster, and finally reaches the target nodes of the sixth, seventh, and eighth core clusters via node links, with each target node carrying 64 bits of traffic. Figure 1 In core cluster c13 of domain 2, core cluster c10 first reaches the computing core of core cluster c13 through inter-domain links (as a relay), then reaches its target node through the internal links of the computing core of core cluster c13, and finally reaches the target node of the first group in core cluster c12, core cluster c16, and core cluster c17 through node links respectively. Each target node carries 64 bits of traffic.

[0057] In the routing example above, the routing paths of the computing cores in the first and fifth core clusters are symmetrical. Combining the routing paths of the two computing cores, it can be seen that the combined bandwidth of the two routing paths reaches the full 512-bit bandwidth within the core cluster partition, achieving load-balanced traffic distribution. Similarly, other core clusters can also establish links in the same way, with the combined bandwidth of each routing path reaching 512 bits, achieving the theoretical bandwidth provided by the routing.

[0058] The aforementioned symmetrical, customized routing path planning ensures that the traffic carried on each link is neither overloaded nor idle, avoiding hotspot paths caused by traditional XY routing methods. This reduces the likelihood of local congestion globally and results in high memory access performance. Furthermore, since the routing paths are pre-planned, router nodes do not need to perform complex address resolution, route calculations, and multi-flow arbitration on data packets; data can be forwarded directly, reducing per-hop latency. In addition, different virtual channels (VCs) can be flexibly allocated to different routing paths, naturally avoiding dependency cycles on the same routing path and preventing deadlocks at the source. Symmetrical routing paths have neat routing patterns, easily meeting timing requirements and facilitating backend implementation.

[0059] Optionally, the grid topology is divided into two core cluster partitions with the same number of core clusters. Each core cluster partition is divided into two domains with the same number of core clusters. Each domain includes four core clusters arranged in a 2×2 layout. The computing cores in the core clusters that are only in symmetrical positions in different domains are linked by inter-domain links.

[0060] Optionally, the grid topology is divided into two core cluster partitions with the same number of core clusters, and each core cluster partition is divided into two domains with the same number of core clusters.

[0061] In one implementation, the mesh topology can be divided into upper and lower parts, each forming a core cluster partition. Each core cluster partition is further symmetrically divided into left and right domains. For example, the mesh topology includes 16 core clusters forming a 4×4 mesh. The upper and lower parts each contain 8 core clusters, forming two core cluster partitions. Each core cluster partition contains 8 core clusters, which are further divided into left and right domains. Each domain includes 4 core clusters arranged in a 2×2 layout. This symmetrical division ensures that core clusters exist in symmetrical positions within different domains, providing a foundation for symmetrical connections between subsequent domain links.

[0062] In this disclosure, the on-chip network interconnection system achieves full-level load balancing routing from within the core cluster to across the entire chip by symmetrically dividing domains, partitions, and cross-chip layers, and adopting a unified routing mode at each layer (i.e., accessing the target node through internal links of the relay computing core and intra-domain node links). The cumulative bandwidth of traffic carried on each link reaches the theoretical full bandwidth, without overloading or idleness, avoiding congestion on hotspot paths. Different virtual channels are flexibly allocated to different routing paths, fundamentally avoiding deadlocks caused by dependency cycles. Router nodes do not require complex address resolution, route calculation, and multi-flow arbitration; data can be forwarded directly, reducing per-hop latency. The symmetrical routing paths are well-organized, easily meeting timing requirements, and are suitable for high-performance on-chip network communication scenarios.

[0063] Optionally, the bandwidth of each node link is determined by dividing the bandwidth of the internal link between the computing core and the corresponding target node equally according to the number of target nodes in the domain to obtain the bandwidth of a single node link, and then determining it by multiplying the number of target nodes on the node link away from the computing core by the bandwidth of the single node link.

[0064] In this embodiment, the internal link bandwidth between the computing core and the corresponding target node is the total bandwidth allocated to the computing core within the domain. This internal link bandwidth is divided equally according to the number of target nodes within the domain to obtain the bandwidth of a single node link. For example, if there are 4 target nodes in a domain, and the internal link bandwidth within that domain is 256 bits, then the bandwidth of a single node link is 256 bits divided by 4, which is 64 bits. Then, the bandwidth of a certain segment on the node link is determined by multiplying the number of target nodes on the segment furthest from the computing core by the bandwidth of the single node link.

[0065] For example, combining Figure 1 See Figures 2 to 5As shown, the node links in domain 1 of core cluster partition MP 0 connect four target nodes. Starting from the target node of core cluster c10 in domain 1 of core cluster partition MP 0, the first target node needs to cover two remote target nodes (i.e., the target nodes of group 0 of core cluster c11 and group 0 of core cluster c15 in domain 1 of core cluster partition MP 0). Therefore, the bandwidth of this node link segment is 2 x 64 bits, equal to 128 bits. The second target node needs to cover one remote target node (i.e., the target node of group 0 of core cluster c14 in domain 1 of core cluster partition MP 0). Therefore, the bandwidth of this node link segment is 1 x 64 bits, equal to 64 bits. The bandwidth of the internal link from the computing core to the target node in its core cluster is 64 bits. This achieves an even distribution of bandwidth between each target node and the computing core, improving bandwidth balance and avoiding bandwidth waste.

[0066] In one implementation, the bandwidth of each node link can be allocated in decreasing order, so that the traffic carried on each link matches the number of target nodes that the link needs to serve, thus avoiding bandwidth waste.

[0067] Optionally, the plurality of computing cores and the plurality of target nodes in each core cluster are divided into two mutually isolated groups, left and right.

[0068] Optionally, the number of target nodes in each core cluster is the same as the number of computing cores in that core cluster, and there is a one-to-one correspondence between the target nodes and the computing cores. Each group includes one computing core and one target node.

[0069] Optionally, the target nodes within the same domain are connected in series via node links.

[0070] In this embodiment, the serial connection method allows data packets to originate from the target node of the core cluster where the computing core resides and sequentially reach each target node within the domain along the serial link, eliminating the need to configure a separate physical link for each source-target node pair, thus saving link resources. Simultaneously, since the bandwidth of each link segment is allocated in descending order based on the number of remote target nodes, the traffic distribution on the serial link is uniform, preventing situations where one link segment is overloaded while others are idle.

[0071] See Figure 1As shown, the target nodes can be connected sequentially via node links in various ways. For example, in domain 1, the target node of core cluster c14 can be the starting point (or ending point), connecting the target nodes of core cluster c10, c11, and c15 sequentially, with the target node of core cluster c15 as the ending point (or starting point). Alternatively, in domain 4, the target node of core cluster c12 can be the starting point (or ending point), connecting the target nodes of core cluster c13, c17, and c16 sequentially, with the target node of core cluster c16 as the ending point (or starting point), and so on. This disclosure does not impose any restrictions, and other connection methods are not enumerated.

[0072] Optionally, the computing core in the on-chip network interconnection system is linked to computing cores in other on-chip network interconnection systems via cross-die links; the computing core uses the computing core in a different on-chip network interconnection system as a relay, and routes access to the target node in the domain of the relay computing core through the internal link corresponding to the relay computing core and the node link in the domain.

[0073] In multi-die packaging scenarios, on-chip network interconnect systems can be deployed on different dies, and these systems are interconnected via cross-die links. These cross-die links connect the corresponding computing cores within the different on-chip network interconnect systems.

[0074] In this embodiment of the disclosure, based on cross-die links, the computing core uses a computing core that is not in the same on-chip network interconnection system as a relay, and routes access to the target node in the domain of the computing core that is the relay through the internal link corresponding to the computing core that is the relay and the node link in the domain.

[0075] In one implementation, the total bandwidth of the computing core is first evenly divided according to the number of cross-die links. For example, if the die containing the computing core has one link to another die, the total bandwidth of 1024 is evenly divided into 512 bits. Then, within the die containing the computing core, the bandwidth is evenly divided according to the target nodes of the links. For example, if the die containing the computing core has 16 target nodes, the 512 bits are evenly divided, resulting in 32 bits.

[0076] For example, the total bandwidth of a computing core is 1024 bits, of which 512 bits are used for cross-die routing, and the remaining 512 bits are evenly distributed among all target nodes that the computing core can link to within its own die. For instance, if the computing core can link to 16 target nodes within its own die, with 4 nodes linked within the same domain, 4 nodes linked across domains (internal link bandwidth is 128 bits), and 8 nodes linked across core cluster partitions, then the 4 nodes linked within the same domain will each receive 128 bits (internal link bandwidth is 128 bits), with each node's routing link being 32 bits. The 4 nodes linked across domains will each receive 128 bits (inter-domain link bandwidth is 128 bits), with each node's routing link being 32 bits. The 8 nodes linked across core cluster partitions will each receive 256 bits (inter-partition link bandwidth is 256 bits), with each node's routing link being 32 bits. The cumulative bandwidth carried by each routing path reaches the theoretical maximum bandwidth.

[0077] It can be explained that in cross-die link connection scenarios, the bandwidth of the computing core on each link is actually still determined by the equal distribution of the total bandwidth based on the number of target nodes connected. Because the first computing core, connected to the second computing core on the second die via a cross-die link on the first die, can connect to 16 target nodes through internal links, inter-domain links, and interval links, and the second computing core on the second die can also connect to 16 target nodes on the second die via internal links, inter-domain links, and interval links, the total bandwidth of 1024 bits is divided equally between the internal links on the second die and the links on the first die (512 bits each). Since there is only one target node on each side, the total bandwidth is first evenly distributed across the die, and then evenly distributed to each target node on the die.

[0078] In one implementation, when a computing core in the on-chip network interconnect system on the first die needs to access a target node in the on-chip network interconnect system on the second die, the data packet is first transmitted via a cross-die link to the corresponding computing core on the second die (acting as a relay), then reaches the target node in that core cluster via the internal link of the relay computing core, and finally accesses other target nodes in that domain via the node link within that domain on the second die. The cross-die link expands the applicability of the on-chip network interconnect system, enabling cross-die communication in multi-die packaging scenarios to adopt the same routing mode as the aforementioned intra-domain, cross-domain, and cross-partition communication, maintaining load balancing and avoiding deadlocks.

[0079] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0080] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0081] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. An on-chip network interconnection system, characterized in that, It includes a first number of core clusters, which constitute an M×N grid topology. Each core cluster includes at least one computing core and at least one target node, and the target node has a corresponding relationship with the computing core. The grid topology is symmetrically divided into multiple domains, and each domain includes a second number of core clusters, where the second number is less than the first number. The target nodes within the same domain are linked by node links; the computing cores and target nodes within the same core cluster are linked by internal links; and the computing cores within core clusters in different domains but in symmetrical positions are linked by inter-domain links. The computing core accesses the target node in the same core cluster through internal link routing. The computing core uses the target node in the same core cluster as a relay to access other target nodes in the same domain through node link routing. The computing core uses the computing core in a different domain as a relay to access the target node in the domain of the computing core that is the relay through the internal link corresponding to the computing core that is the relay and the node link in the domain where the computing core is located. The bandwidth of the computing core on each of the links is determined by dividing the total bandwidth of the computing core equally among the number of target nodes linked to it.

2. The on-chip network interconnection system according to claim 1, characterized in that, Each core cluster includes multiple computing cores and multiple target nodes; The plurality of computing cores and the plurality of target nodes in the core cluster are divided into a plurality of mutually isolated groups. Each group includes at least one computing core and a target node corresponding to the computing core. There is no communication link between the computing cores and the target nodes in different groups in the core cluster. The multiple groups in the core cluster are all numbered according to their location, and the target nodes of the groups with the same location number in the core cluster within each domain are linked by node links.

3. The on-chip network interconnection system according to claim 2, characterized in that, The grid topology is divided into multiple core cluster partitions, each core cluster partition includes multiple domains, and each domain is assigned to only one core cluster partition; In the mesh topology, the core cluster partitions located in symmetrical positions are connected by interval links to the computing cores of the groups with the same position number in the core clusters located in the same positions in the two core cluster partitions. The computing core, based on the interval link, uses a computing core that is not in the same core cluster partition as it as a relay, and routes access to the target node in the domain of the computing core that is the relay through the internal link corresponding to the computing core that is the relay and the node link in the domain.

4. The on-chip network interconnection system according to claim 3, characterized in that, The grid topology is divided into two core cluster partitions with the same number of core clusters. Each core cluster partition is further divided into two domains with the same number of core clusters. Each domain includes four core clusters arranged in a 2×2 layout. The computing cores in the core clusters located only in symmetrical positions in different domains are linked by inter-domain links.

5. The on-chip network interconnection system according to claim 4, characterized in that, The grid topology is divided into two core cluster partitions with the same number of core clusters, and each core cluster partition is divided into two domains with the same number of core clusters, left and right.

6. The on-chip network interconnection system according to claim 2, characterized in that, The bandwidth of each node link is determined by dividing the bandwidth of the internal link between the computing core and the corresponding target node equally according to the number of target nodes in the domain to obtain the bandwidth of a single node link, and then by multiplying the number of target nodes on the node link at the end away from the computing core by the bandwidth of the single node link.

7. The on-chip network interconnection system according to claim 2, characterized in that, The multiple computing cores and multiple target nodes in each core cluster are divided into two mutually isolated groups, left and right.

8. The on-chip network interconnection system according to claim 2, characterized in that, The number of target nodes in each core cluster is the same as the number of computing cores in that core cluster. There is a one-to-one correspondence between the target nodes and the computing cores. Each group includes one computing core and one target node.

9. The on-chip network interconnection system according to any one of claims 1-8, characterized in that, The target nodes within the same domain are connected in series via node links.

10. The on-chip network interconnection system according to any one of claims 1-8, characterized in that, The computing cores in the on-chip network interconnect system are linked to computing cores in other on-chip network interconnect systems via cross-die links; The computing core uses a computing core that is not in the same on-chip network interconnection system as a relay, and routes access to the target node in the domain of the computing core that is the relay through the internal link corresponding to the computing core that is the relay and the node link in the domain.

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