A method and apparatus for adjusting a delay B+ tree structure based on a computable storage

Abstract

The application relates to the technical field of databases, and provides a method and device for adjusting a delay B+ tree structure based on computable storage. A leaf node related to an incremental log instruction received from a host end is modified to complete a write operation of a write request of the leaf node; the incremental log instruction is generated only according to an internal node and the write request by the host end in response to the write request. The application solves the problem that, in the prior art, due to physical isolation between a host and a storage device, a performance bottleneck occurs under a write-intensive load.

Description

Technical Field

[0001] This invention relates to the field of database technology, and in particular to a method and apparatus for adjusting a computationally storable delayed B+ tree structure. Background Technology

[0002] In modern relational databases and key-value (KV) storage systems, B+ trees and their variants are the most core and widely used basic indexing data structures. By maintaining the absolute balance of the tree, B+ trees provide a stable O(log n) time complexity for data retrieval.

[0003] However, with modern non-volatile storage media achieving millions of read / write operations per second (IOPS), the architectural shortcomings of existing B+ tree technologies under write-intensive workloads have become increasingly apparent. This is particularly evident in modern non-volatile storage media such as Non-Volatile Memory Express Solid State Drives (NVMe SSDs).

[0004] Because of the physical isolation between the host and storage devices, performance bottlenecks can occur under write-intensive loads. Specifically, current technologies often employ a CPU-centric computing architecture, meaning data must be moved to the vicinity of the Central Processing Unit (CPU) before it can be processed. The CPU acts as the computing core, memory serves as a data temporary storage area, and storage devices merely act as passive data warehouses, lacking computing capabilities. In this architecture, the host refers to the server's CPU and Dynamic Random-Access Memory (DRAM), responsible for running the database process and executing all index maintenance logic of the B+ tree; the storage device refers to the NOT AND NAND flash memory in a Solid State Disk (SSD), which only provides block read / write interfaces and is unaware of the B+ tree structure. The host and storage device are two independent physical hardware units connected via the Peripheral Component Interconnect Express (PCIe) bus. They have their own independent power domains, memory spaces, and instruction sets, and there is no shared memory. The host cannot directly access the data inside the storage device; it must pass messages across the PCIe bus using appropriate protocols. This isolation means that for every modification to a B+ tree leaf node, the host must read the entire physical page (i.e., Page) across PCIe into DRAM, modify it in memory, and then write it back across PCIe. As a result, even if only a few dozen bytes are changed, the entire page still needs to be moved, leading to severe write amplification. At the same time, high-overhead, frequent Structure Modification Operations (SMOs), such as splitting or merging B+ tree nodes, are all executed synchronously by the host CPU, causing a sharp drop in throughput due to lock contention in a multi-threaded environment.

[0005] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0006] The technical problem to be solved by this invention is that the existing technology suffers from performance bottlenecks under write-intensive loads due to the physical isolation between the host and the storage device.

[0007] Firstly, a method for adjusting a delayed B+ tree structure based on computable storage is provided, including: Modify the leaf nodes involved in the incremental log instruction received from the host to complete the write operation of the write request for the leaf nodes; The incremental log instruction is generated by the host in response to the write request, based solely on the internal nodes and the write request.

[0008] Furthermore, the host maintains the routing information of the internal nodes; The method includes: Receive the write request, obtain the operation type of the write operation, and the key and value of the leaf node from the write request; Obtain the target logical block address from the routing information according to the write request; Incremental data is generated based on the operation type and the key and value of the leaf node; incremental log instructions are generated based on the incremental data and the target logical block address. The incremental log instruction is sent to the computable storage device.

[0009] Furthermore, the modification of the leaf nodes involved in the incremental log instruction received from the host to complete the write operation of the write request for the leaf nodes includes: Receive the incremental log instruction and obtain the target logical block address and the incremental data from it; The incremental data is added to the incremental log of the target logical block address in the computable storage device, and a successful response for the write operation is returned to the host within a preset delay time. Based on the status of the incremental logs accumulated in the local cache, modifications to the leaf nodes are performed asynchronously after receiving the incremental log instruction and before returning the success response.

[0010] Furthermore, the step of modifying the leaf node after receiving the incremental log instruction, and asynchronously with the return of the success response, based on the status of the incremental log accumulated in the local cache, includes: When the size of the incremental log of a leaf node reaches the split threshold, the leaf node is used as the original leaf node, and the physical page where the original leaf node is located is read. Perform structural maintenance operations on the physical page and the incremental log to obtain a new leaf node, and write the new leaf node into the non-volatile storage medium on the computeable storage device. Based on the modification from the original leaf node to the new leaf node, an asynchronous notification message is generated; the asynchronous notification message is sent to the host so that the host can update the routing information according to the asynchronous notification message.

[0011] Furthermore, the structural maintenance operation includes a splitting operation; The step of performing structural maintenance operations on the physical page and the incremental log to obtain a new leaf node, and writing the new leaf node into the non-volatile storage medium on the computeable storage device includes: The physical page and the incremental log are split to generate at least two new leaf nodes, and the at least two new leaf nodes are written into the non-volatile storage medium on the computeable storage device.

[0012] Further, after generating asynchronous notification information based on the modification from the original leaf node to the new leaf node and sending the asynchronous notification information to the host, the method further includes: A temporary mapping record is generated based on the logical block address of the original leaf node, the delimiter key on which the structure maintenance operation is based, and the logical block address generated by the structure maintenance operation. The temporary mapping record is stored in a preset mapping table within the computable storage device.

[0013] Furthermore, the method also includes: Before the host completes the update of the routing information, when the computable storage device receives a read request from the host based on the logical block address of the original leaf node sent by the internal node, the computable storage device checks the preset mapping table and determines the size relationship between the key carried by the read request and the separator key. When the key carried by the read request is greater than or equal to the delimiter key, the logical block address of the operation required by the read request is modified from the logical block address of the original leaf node to the logical block address of the new leaf node; the data required by the read request is returned according to the modified logical block address; When the host completes the update of the routing information, the computeable storage device deletes the temporary mapping record from the preset mapping table.

[0014] Furthermore, the method also includes: During the process of generating incremental log instructions, the host does not read the physical pages of leaf nodes in the computable storage device.

[0015] In a second aspect, an apparatus for adjusting a delayed B+ tree structure based on computationally readable storage is provided, the apparatus comprising: a processor and a memory for storing processor-executable instructions; The processor is configured to execute the method for adjusting the delayed B+ tree structure based on computable storage.

[0016] Thirdly, a non-volatile computer storage medium is provided, the computer storage medium storing computer-executable instructions that are executed by one or more processors to perform the method for adjusting a delayed B+ tree structure based on computable storage as described in the first aspect.

[0017] Fourthly, a computer program product containing instructions is provided that, when executed on a computer or processor, causes the computer or processor to perform the method of adjusting a delayed B+ tree structure based on computable storage as described in the first aspect.

[0018] Compared with the prior art, the beneficial effects of the present invention are as follows: This invention physically partitions the logical structure of a B+ tree. The host only maintains internal nodes for routing, while the management and structural modification operations of leaf nodes containing actual data are completely pushed down to the computeable storage device. Since host-side write operations are converted into incremental log instructions, it is no longer necessary to read the entire physical page data of a leaf node across the PCIe bus, significantly reducing the amount of data transmitted. The execution of write operations that modify leaf nodes is entirely handled by the computeable storage device, eliminating the need for complex locking mechanisms triggered by leaf node splitting or merging on the host, thus minimizing lock overhead. This reduces lock overhead on the host CPU, decreases data movement on the PCIe bus, and improves the overall write throughput of the system, solving the performance bottleneck problem in existing technologies caused by physical isolation between the host and storage devices under write-intensive loads. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating a method for adjusting a computationally storable delayed B+ tree structure according to an embodiment of the present invention. Figure 2 This is a schematic diagram illustrating a specific example of the overall framework of a method according to an embodiment of the present invention. Figure 3 This is a schematic diagram illustrating a specific example of the overall flow of a method according to an embodiment of the present invention. Figure 4 This is a schematic diagram of a host-side write request processing flow provided by an embodiment of the present invention; Figure 5This is a schematic diagram of the processing flow of incremental log instructions by a computable storage device according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the processing flow of incremental logs that have reached the split threshold in a computable storage device according to an embodiment of the present invention; Figure 7 This is a schematic diagram of a process for implementing concurrent consistency guarantee provided by an embodiment of the present invention; Figure 8 This is a flowchart illustrating a crash recovery mechanism provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of a device for adjusting a computationally storable delayed B+ tree structure according to an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0022] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0023] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, for example, the description may use the prefix "A" or "B" to describe the same type of nouns as two independent entities. In this case, the corresponding features defined with "A" and "B" are used only to distinguish between similar entities and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0024] In describing some embodiments, the terms "coupled," "coupled," and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the terms "connected" or "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other, such as "optical coupling," "wireless connection," etc. The embodiments disclosed herein are not necessarily limited to the scope of this invention.

[0025] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0026] Because of the physical isolation between the host and storage devices, existing technologies will experience performance bottlenecks under write-intensive loads, mainly in the following aspects: (1) There are serious write amplification and input / output (I / O) bottlenecks. Traditional B+ trees execute read-modify-write (RMW) logic on the host. That is, when inserting new data into a leaf node, the host must first read the 4 kilobyte (KB) or 8 KB physical page (i.e., Page) from the SSD into the host memory through the PCIe bus. After the data insertion is completed in memory, the entire dirty page is written back to the SSD.

[0027] In this situation, if a change in a physical page is only a few dozen bytes, but it requires reading and writing the entire block, the cost is extremely high. This macroscopic write amplification greatly consumes the write lifespan of the underlying NAND, namely the Program / Erase Cycles (P / E Cycles) and the PCIe bus bandwidth.

[0028] (2) There is a CPU lock contention problem caused by SMO.

[0029] To better illustrate this issue, let's first briefly explain the existing B+ tree technology: A B+ tree is a balanced multi-way tree consisting of a root node, inner nodes, and leaf nodes. The root node has no parent node, and all queries in the entire B+ tree must begin from the root node. Inner nodes have both parent nodes (where the parent node is the root node or another inner node) and child nodes (where the child nodes are other inner nodes or leaf nodes). Leaf nodes have only a parent node (where the parent node is an inner node or the root node) and no child nodes. Inner nodes and the root node store only keys and pointers to the next level node. Leaf nodes store keys and values; all actual data (values) exists only in leaf nodes. When a leaf node is full, a split operation must be triggered; when a node has too little data, a merge operation must be triggered. In multi-threaded, high-concurrency environments, B+ tree structure modification operations not only involve the current node but may also cascade upwards, leading to the splitting of inner nodes and even the root node. To ensure concurrency safety, the host CPU must employ complex locking mechanisms (e.g., latch-coupling or B-link tree mechanisms). Under extreme write-intensive loads, a significant number of CPU clock cycles are wasted on spinlock waiting and context switching, resulting in a precipitous drop in overall throughput.

[0030] (3) There is an imbalance in computing power between the host and storage devices. The existing computing architecture follows a CPU-centric paradigm, with storage devices existing only as passive block devices. With the development of Computational Storage Devices (CSDs), modern SSDs have integrated multi-core Advanced RISC Machine (ARM) processors, Field-Programmable Gate Arrays (FPGAs), or dedicated hardware acceleration engines, as well as gigabyte-level internal DRAM. The existing architecture fails to effectively utilize the abundant edge computing power on the device side, resulting in host CPU overload and storage device computing power idle.

[0031] Therefore, the applicant discovered through research that there is an urgent need for a completely new architecture that can break the physical isolation between the host and storage devices, push down the high-overhead index maintenance work, and thus completely solve the performance bottleneck under write-intensive loads.

[0032] To address the problems of existing technologies, this embodiment proposes a method for adjusting a computationally storable delayed B+ tree structure. In one embodiment, such as... Figure 1 As shown, it includes: Step 10: Modify the leaf nodes involved in the incremental log instruction received from the host to complete the write operation of the write request for the leaf nodes.

[0033] This invention relates to the fields of underlying database storage engines, data structures, and hardware acceleration technologies. The core idea is to utilize computeable storage devices (i.e., CSDs) to offload the page node maintenance operations of B+ tree indexes, thereby achieving delayed splitting and merging of B+ trees.

[0034] The specific format of the incremental log instruction and the specific implementation method for modifying leaf nodes are determined by those skilled in the art based on the specific use case. A specific example will be provided below. The specific operation type of the write operation is determined by those skilled in the art based on the specific use case. In one embodiment, it may include insertion, update, and deletion; the write request is a user request used to drive the execution of the write operation.

[0035] The architecture of this invention includes a host side and a computable storage device side. In one embodiment, such as... Figure 2As shown, the host side includes at least a database engine and host memory. The host memory manages the root node and internal nodes of the B+ tree, and the database engine executes corresponding queries and updates. The host side is located above the PCIe bus and is responsible for handling query and update requests to the B+ tree. The computable storage device side includes at least an incremental log pool and a NAND flash memory array and controller. The incremental log pool stores incremental data from received incremental log instructions, and the NAND flash memory array and controller maintain the leaf nodes of the B+ tree. The computable storage device side is located below the PCIe bus and is built on a multi-core ARM firmware layer. In one embodiment, the computable storage device side internally includes DRAM (for storing the incremental log pool and performing log appending through a transaction engine), static random access memory or block random access memory (for running the SMO engine to perform background delayed splitting and maintain a hardware routing redirection table), and a flash translation layer and a core storage management module.

[0036] In one embodiment, on the host side, the database engine maintains a truncated B+ tree (i.e., a trunked B+ tree), which serves as the routing tree. The root node and all internal nodes of this routing tree reside permanently in host memory. The structure of the internal nodes remains traditional.<Key,Pointer> The format is such that "Pointer" is no longer a pointer to a memory address, but a handle to a logical block address in a computable storage device.

[0037] Step 20: The incremental log instruction is generated by the host in response to the write request, based solely on the internal nodes and the write request.

[0038] Internal nodes refer to non-leaf nodes that lie between the root node and the leaf nodes.

[0039] In one embodiment, the method further includes: during the process of generating incremental log instructions, the host does not read the physical pages of the leaf nodes in the computable storage device.

[0040] In this embodiment of the invention, leaf nodes and corresponding physical pages are maintained on the computeable storage device side. Only the computeable storage device itself reads the physical pages from its own device.

[0041] In one embodiment, after receiving a write request for a leaf node, the host generates an incremental log instruction for the write request based solely on the internal nodes that serve as routes for that leaf node within its own internal node management system, and the write request itself. The computable storage device then modifies the leaf nodes involved in the incremental log instruction received from the host to complete the write operation corresponding to the write request. Here, the leaf node involved in the incremental log instruction refers to the leaf node corresponding to the write request.

[0042] This invention physically partitions the logical structure of a B+ tree. The host only maintains internal nodes for routing, while the management and structural modification operations of leaf nodes containing actual data are completely pushed down to the computeable storage device. Since host-side write operations are converted into incremental log instructions, it is no longer necessary to read the entire physical page data of a leaf node across the PCIe bus, significantly reducing the amount of data transmitted. The execution of write operations that modify leaf nodes is entirely handled by the computeable storage device, eliminating the need for complex locking mechanisms triggered by leaf node splitting or merging on the host, thus minimizing lock overhead. This reduces lock overhead on the host CPU, decreases data movement on the PCIe bus, and improves the overall write throughput of the system, solving the performance bottleneck problem in existing technologies caused by physical isolation between the host and storage devices under write-intensive loads.

[0043] The following is a further description of the method for adjusting the delayed B+ tree structure based on computable storage according to the present invention: like Figure 2 The diagram shown is a schematic representation of the overall framework of a method according to an embodiment of the present invention. The hardware and underlying software infrastructure of this embodiment are described below: The specific hardware environment relied upon in this embodiment includes a host equipped with a high-performance multi-core CPU and ample memory, and an NVMe compute storage device connected via a PCIe 4.0 or 5.0 interface.

[0044] The hardware features of the computable storage device in this embodiment of the invention are as follows: The firmware layer of the computable storage device provides an open interface, for example, conforming to the NVMe Computational Storage specification, or a sandbox that allows the deployment of Extended Berkeley Packet Filter (eBPF) programs. Hardware-wise, the computable storage device is equipped with a power loss protection supercapacitor (PLP), 8GB of dedicated device-side DRAM, and a multi-core ARM Cortex-R / A series embedded processor; wherein the aforementioned DRAM is used to store the Flash Translation Layer (FTL) table and the incremental log in the embodiments of the invention described below.

[0045] To solve the technical problems of the embodiments of the present invention, it is first necessary to perform topological decoupling and responsibility division. For example... Figure 3As shown, the main memory on the host side maintains a routing tree composed of internal nodes of a B+ tree; the computeable storage device manages all leaf nodes and maintains an incremental log (i.e., Delta Log) for each leaf node in the dynamic random access memory inside the computeable storage device.

[0046] In one embodiment, the host maintains routing information for the internal nodes; in another embodiment, the index lookup path formed by the internal nodes of the B+ tree maintained in the host's memory serves as routing information, which includes the following two elements: (1) Internal nodes: including the root node and all intermediate level nodes. (2) Key-value pairs: stored in each internal node.<Key,Pointer> Combination. Here, Key is the Separator Key, and Pointer is not a memory address, but a handle pointing to the logical block address (LBA) of a leaf node in a computable storage device.

[0047] Based on this, in one embodiment, the leaf nodes are managed by a computable storage device; the internal nodes are managed by the host; the host does not read data from the physical pages of the leaf nodes during the generation of the incremental log instruction; such as Figure 4 As shown, the method includes: Step 101: Receive the write request, obtain the operation type of the write operation, and the key and value of the leaf node from the write request.

[0048] The write request will carry the operation type of the write operation, as well as the key and value of the leaf node involved in the write request.

[0049] This invention provides a method for lock-free appending on the host side: when the host receives a write request corresponding to a write operation (i.e., insert, update, and delete operation), the host does not read the physical page data of the target leaf node in the computeable storage device, but instead generates an incremental log command (i.e., Delta Update Command) containing the operation type (i.e., insert, update, and delete), key, value, and target logical block address (LBA).

[0050] Step 102: Obtain the target logical block address from the routing information according to the write request.

[0051] In one embodiment, since the host maintains routing information for all internal nodes, the target logical block address of the leaf node can be obtained by querying the routing information based on the key and value of the leaf node in the write request.

[0052] Step 103: Generate incremental data based on the operation type and the key and value of the leaf node; generate incremental log instructions based on the incremental data and the target logical block address.

[0053] This invention defines a new instruction called Incremental Log Instruction (i.e., NVME_CMD_DELTA_APPEND). The payload of this Incremental Log Instruction includes: an operation type identifier (i.e., "Insert", "Update", or "Delete"), a target LBA address, a variable-length key length (i.e., Key_Len), a variable-length key (i.e., Key), a variable-length value length (i.e., Val_Len), and a variable-length value (i.e., Value). The specific implementation of the Incremental Log Instruction is determined by those skilled in the art based on the specific use case.

[0054] In one embodiment, the present invention extends the NVMe instruction set through Vendor Specific Commands (VSC).

[0055] Step 104: Send the incremental log instruction to the computable storage device.

[0056] In one embodiment, the incremental log instruction is sent to the computable storage device via the Non-Volatile Memory Express (NVMe) protocol. NVMe is a bus transport protocol specification that serves as an application layer communication protocol based on the device's logical interface, used to access non-volatile storage media via the PCIe bus or other interfaces.

[0057] In one specific instance, the host receives a write request, obtains the write operation type, and the key and value of the leaf node involved in the write request; according to the write request, it obtains the target logical block address of the leaf node from the routing information of the internal nodes maintained by the host. Incremental data is generated based on the write operation type and the key and value of the leaf node; an incremental log instruction is generated based on the incremental data and the target logical block address; and the incremental log instruction is sent to the computable storage device.

[0058] To achieve low latency and address computing power bottlenecks in this invention, in one embodiment, such as Figure 5 As shown, modifying the leaf nodes involved in the incremental log instruction received from the host to complete the write operation of the write request for the leaf nodes includes: Step 201: Receive the incremental log instruction and obtain the target logical block address and the incremental data from it.

[0059] Step 202: Add the incremental data to the incremental log of the target logical block address in the computable storage device, and return a successful response of the write operation to the host within a preset delay time.

[0060] The preset delay time is determined by those skilled in the art based on the specific use case. The preset delay time should be set as short as possible to achieve the technical effect of returning a successful response immediately.

[0061] In one embodiment, after receiving the incremental log instruction, the compute storage device appends the incremental data to the incremental log of the corresponding LBA in the internal DRAM and immediately returns a write operation success response to the host.

[0062] In one specific instance, the controller of the computable storage device allocates a dedicated log buffer pool in DRAM. This log buffer pool consists of a series of fixed-size slots. When the computable storage device receives an incremental log instruction for an operation targeting logical block address LBA_T, it uses a hash map to locate the incremental log list belonging to the target logical block address LBA_T in memory.

[0063] This invention also provides an incremental log data structure, wherein a log entry includes: (1) Opcode: occupies 1 byte; where 0x01 is Insert, 0x02 is Update, and 0x03 is Delete or Tombstone. (2) Timestamp or Log Sequence Number (LSN): occupies 8 bytes; where LSN is used for multi-version concurrency control and to resolve update conflicts with the same key. (3) Key and / or value: the actual user data.

[0064] Step 203: Based on the status of the incremental logs accumulated in the local cache, modify the leaf node after receiving the incremental log instruction and asynchronously with the return of the success response.

[0065] In one embodiment, such as Figure 6 As shown, step 203 above includes: Step 2031: When the size of the incremental log of the leaf node reaches the split threshold, the leaf node is used as the original leaf node, and the physical page where the original leaf node is located is read.

[0066] The splitting threshold is determined by those skilled in the art based on the specific use case (e.g., the environment and storage requirements of B+ tree deployment, performance requirements such as response speed), and is not limited here. In one embodiment, the splitting threshold can be 2KB.

[0067] When the host continuously writes incremental data to a certain leaf node, causing its incremental log to expand beyond the split threshold, that leaf node is referred to as the original leaf node in the background task on the computeable storage device.

[0068] like Figure 3 As shown, under continuous write load, the incremental logs of leaf nodes will continuously expand. To avoid excessive merging overhead during queries, this invention implements a threshold-based background merging and splitting engine. This engine runs on the kernel of a System on Chip (SoC) on an Advanced RISC Machine (ARM) computeable storage device as a low-priority background daemon.

[0069] In one embodiment, the daemon periodically scans the log metadata table in DRAM. If it finds that the total incremental log size of the target's LBA_A (i.e., the logical block address of the original leaf node) exceeds 2KB (assuming the Flash Page size is 4KB), then the logical block address LBA_A of the original leaf node is added to the task queue to be split and merged.

[0070] Step 2032: Perform structural maintenance operations on the physical page and the incremental log to obtain new leaf nodes, and write the new leaf nodes into the non-volatile storage medium on the computeable storage device.

[0071] In one embodiment, the structure maintenance operation includes a split operation and a merge operation. A split operation is triggered when an original leaf node is full, and a merge operation is triggered when an original leaf node has too little data.

[0072] Step 2032 includes: performing a split operation on the physical page and the incremental log to generate at least two new leaf nodes, and writing the at least two new leaf nodes into the non-volatile storage medium on the computeable storage device. Figure 2 As shown, in one embodiment, the physical page of a primary leaf node (i.e. Figure 2 The "old leaf page" in the diagram, once its size reaches the splitting threshold, can be split into two new physical pages of leaf nodes (i.e., ...). Figure 2 (The "new leaf page" in the text).

[0073] In one specific instance, when the computeable storage device detects that the incremental log size of a certain leaf node has reached a preset split threshold, the computing unit inside the computeable storage device triggers a split process in the background. The computeable storage device reads the flash page where the original leaf node was located, merges it with the incremental log, and divides it into two new leaf nodes. These new leaf nodes are then persisted to a new LBA in the NAND flash memory, thereby writing the corresponding new leaf nodes into the non-volatile storage medium of the computeable storage device.

[0074] Step 2033: Generate asynchronous notification information based on the modification from the original leaf node to the new leaf node; send the asynchronous notification information to the host so that the host can update the routing information based on the asynchronous notification information.

[0075] In one embodiment, to reclaim storage fragmentation caused by a large number of delete or update operations, a delayed merging mechanism is implemented simultaneously on the computeable storage device side. Specifically, write requests for delete operations on the host side are issued as an incremental log instruction with Opcode=0x03, and the key in the write request is marked as a tombstone in the incremental log instruction. During the garbage collection (GC) scan phase in the background of the computeable storage device, if it is found that the total amount of valid data for two consecutive logically adjacent logical block addresses is less than 4KB after merging and calculating the tombstones and expired versions of the address (i.e., both have a load rate of less than 50%), physical page merging is triggered. Within the computeable storage device, the ARM core merges the valid data of the two logical block addresses into a target logical block address (e.g., retaining the former's logical block address and discarding the latter's), and flushes the merged physical page to NAND. Subsequently, the host side is notified through a similar AEN mechanism: "The target logical block address has been merged; please delete the separator key and pointer to the logical block address in the routing tree."

[0076] A specific example of the above-mentioned data reading and merging process within the device can be as follows: The ARM core issues a read instruction to the underlying flash memory controller to read the data of the original 4KB physical page of the logical block address LBA_A of the original leaf node into the high-speed static random-access memory (SRAM) of the SoC or a pre-allocated merge buffer. Subsequently, the ARM executes a preset merge sort algorithm to physically merge the ordered old data in the SRAM with the incremental log in the DRAM according to the LSN sequence number for deduplication. The specific method of the preset merge sort algorithm and the physical merging is determined by those skilled in the art based on the specific application scenario and is not limited here. If the total amount of effective data after merging exceeds the physical limit of 4KB per page, the system will trigger page splitting logic. The ARM core finds the median key of the data distribution (e.g., the separator key) as the split point. It requests the FTL to allocate a new logical block address LBA_B (and a new physical page on NAND). Data smaller than the delimiter key is written to LBA_A' (i.e., reusing or overwriting the old logical block address), and data greater than or equal to the delimiter key is written to LBA_B. Utilizing the device's internal high-speed DMA engine, these two data sets are directly and in parallel flushed to free physical pages of the NAND flash memory.

[0077] To prevent the loss of incremental logs in DRAM due to power failure at the computeable storage device, in one embodiment, the present invention also provides a dual-insurance mechanism to achieve hardware persistence through power failure protection: During normal operation, the Flash Translation Layer (FTL) thread inside the computeable storage device controller periodically flushes the accumulated incremental logs into the reserved journal NAND zone of the NAND flash memory in an append-only manner. Once an abnormal power failure signal is detected, the computeable storage device uses the residual charge of the PLP capacitor to trigger an emergency flush, instantly dumping all dirty incremental logs and FTL mapping tables in DRAM to the NAND medium.

[0078] A specific example of the implementation details of a write operation is as follows: like Figure 3As shown, when a write request to insert value = V1 into key = K1 is received, the host searches downwards along the routing tree to determine that the target logical block address corresponding to the leaf node involved in the write request is LBA_T. Subsequently, the host converts the write request into an incremental log instruction (i.e., NVME_CMD_DELTA_APPEND), points to LBA_T, and initiates Direct Memory Access (DMA) to push it to the computeable storage device. Once a Completion Queue Entry (CQE) is received from the computeable storage device, the transaction is considered successfully persisted and a response is returned to the application layer. Throughout the entire write operation, the host CPU does not perform any data parsing, reconstruction, or space allocation on the target physical page.

[0079] The basic delayed splitting process and write optimization function provided in this embodiment of the invention are as follows: (1) The host maintains the routing information of the internal nodes; (2) After receiving the write request, the host only generates an incremental log instruction and sends it to the computable storage device; (3) The computable storage device updates the internal incremental log cache; (4) When the leaf node reaches the splitting threshold, the computable storage device completes the splitting of the leaf node in the background; (5) After completion, the host is notified to update the modified routing information.

[0080] It is worth noting that in this invention, the internal SMO of the computable storage device does not require complex locks and will not cause a precipitous drop in overall throughput. The reason why the internal SMO of the computable storage device does not require complex locks is that the structural modification occurs within the serialized control domain of the computable storage device, rather than in the multi-threaded transaction access path.

[0081] In this embodiment of the invention, the SMO inside the computable storage device is fundamentally different from the SMO in the traditional B+ tree, so there is no need to use complex latch-coupling or other locking mechanisms. The problems of the existing B+ tree are: (1) multiple CPU threads access the shared B+ tree at the same time. (2) when a thread performs node splitting, it needs to modify the current leaf node, parent node, and ancestor node; where the ancestor node refers to all upper-level intermediate nodes on the path from the root node to the current split node (excluding the current leaf node itself and its parent node), that is, the parent node's parent node and its higher-level nodes. (3) multiple transaction threads may modify related paths at the same time. In order to solve the above problems, the existing technology uses node locks, parent-child lock passing, B-link tree right-side chain, and optimistic lock verification mechanisms. However, these solutions will cause lock contention in extreme write-intensive environments, reducing system performance. For example, the modification of the existing B+ tree structure involves splitting the current node or even the root node, which requires a complex locking mechanism to ensure the accuracy of the splitting, but this will lead to lock contention in extreme write-intensive environments.

[0082] In this embodiment of the invention, firstly, the SMO is separated from the transaction path, and user write requests do not directly trigger the SMO. That is, the foreground transaction is only responsible for appending incremental logs; then the SMO is executed asynchronously by a background task. Therefore, the transaction execution path does not involve waiting for node splitting or waiting for a parent node, nor does it involve waiting for lock release during updates.

[0083] Secondly, the SMO access scope within the computeable storage device is limited. That is, what the computeable storage device maintains internally is a single leaf node, incremental logs, and local metadata. Therefore, when modifying the B+ tree, it is not necessary to directly modify the entire tree structure as in existing technologies. For example, in this embodiment of the invention, the host only maintains internal nodes as routes, while leaf node management and structural modifications are completely pushed down to the CSD for completion.

[0084] Furthermore, the computeable storage device can employ internal serialized scheduling. Specifically, since SMO is not directly triggered by user transactions but is a background maintenance task, the computeable storage device can employ: a single-queue SMO task queue, partition locks, metadata version control, and lock-free data structures.

[0085] Since the background daemon process on the computable storage device side of this embodiment scans the log metadata table and adds it to the SMO task queue for execution when the split threshold is reached, the problem of a large number of transaction threads competing for SMO locks in existing databases will not occur.

[0086] The embodiments of the present invention do not eliminate all locks, but rather move the SMO out of the high-concurrency transaction path through architectural adjustments, transforming the structural modification into a low-frequency background task within the computeable storage device, thus avoiding a precipitous drop in overall throughput.

[0087] Furthermore, relying solely on the above solutions will result in transient inconsistencies after achieving hardware-software decoupling, making it impossible to guarantee consistency during asynchronous structural adjustments.

[0088] Specifically, in existing B+ trees, node splitting and parent node updates typically occur within the same control domain, resulting in strong synchronization between structural changes and routing updates. However, this invention employs an architecture that separates the host-side routing node from the data node on the computeable storage device side. In one specific instance, this is manifested in the following: the leaf node splitting is first completed internally on the computeable storage device side, followed by asynchronous notification to the host side to update the routing information via NVMe AEN. The host-side routing information update inevitably has a time window. For example, the computeable storage device backend may have already completed the splitting of the logical block address LBA_A of the original leaf node to the logical block address LBA_A' of the new leaf node (i.e., reusing or overwriting the old logical block address) and the logical block address LBA_B of the new leaf node, but the AEN notification has not yet been processed by the host side. At this time, the host still accesses the logical block address LBA_A of the original leaf node according to the old route.

[0089] If the above scheme is combined with existing technology, the following situation may occur: the host accesses the logical block address LBA_A of the original leaf node, but the corresponding data has already been migrated to the logical block address LBA_B of the new leaf node, resulting in the inability to find the target key (i.e., Key) or returning an error result. Specifically, the state update of the routing information in the host's memory always lags behind the actual physical state changes at the underlying level of the compute storage device. This time difference may lead to serious read / write errors: when the compute storage device has completed the split from the original leaf node to at least two new leaf nodes in the background, but the AEN packet is still blocked in the NVMe completion queue and has not been processed by the host; at this time, the host receives a read request Read(Key=90). Because the routing information on the host has not been updated, the host still believes that Key=90 exists in the logical block address LBA_A of the original leaf node, and thus issues a Read(LBA_A,Key=90) command to the compute storage device. However, at this time, the compute storage device has actually moved Key=90 to the logical block address LBA_B of the new leaf node.

[0090] The aforementioned consistency issues can be resolved by those skilled in the art using existing technologies, such as: waiting for the computable storage device to complete the split before updating the data visibility state, blocking host access until routing information synchronization is complete, and then having the host maintain additional version information and retry; and adding a global consistency protocol.

[0091] However, these existing technical solutions introduce new problems: they reduce write concurrency, increase host CPU involvement, increase the number of PCIe interactions, and undermine the core idea and design goals of the "device autonomous maintenance structure" in this invention.

[0092] Based on the above-described solution, in order to achieve concurrent consistency assurance, one embodiment of the present invention, such as... Figure 7 As shown, after step 2033, the method further includes: Step 301: Generate a temporary mapping record based on the logical block address of the original leaf node, the delimiter key on which the structure maintenance operation is based, and the logical block address generated by the structure maintenance operation.

[0093] The logical block address of the original leaf node is the target logical block address of the leaf node in step 102. To distinguish it from the new leaf node after the structure maintenance operation, it is not referred to as the "target logical block address." Those skilled in the art should know that if the leaf node in step 102 and step 301 is the same leaf node, then the actual address of the "target logical block address" is equivalent to the "logical block address of the original leaf node."

[0094] Step 302: Store the temporary mapping record in a preset mapping table in the computeable storage device.

[0095] The structure maintenance operation in this embodiment of the invention is an asynchronous route update. In one embodiment, after the computeable storage device completes a background split, a route update event packet (i.e., an asynchronous notification message) is sent to the host via an asynchronous event notification mechanism (e.g., NVMe AEN or Completion Queue CQ). Upon receiving the packet, the host updates the internal nodes in memory using a lightweight lock, inserting the new separator key (i.e., Separator Key) into the routing tree. The implementation of the preset mapping table is determined by those skilled in the art based on the specific use case. In one embodiment, the preset mapping table can be an SRAM mapping table.

[0096] In one embodiment, the asynchronous update process of host routing can be as follows: After completing the aforementioned underlying physical write operation, the compute storage device constructs an asynchronous event notification (AEN packet). The content structure of this AEN packet is: [EventType: SPLIT_COMPLETE, Old_LBA: LBA_A, New_Separator_Key: Separator_Key, New_LBA: LBA_B]. The underlying NVMe driver of the host intercepts this event packet and wakes up the corresponding database maintenance thread. This thread uses a very lightweight write lock (or even a lock-free RCU mechanism) to insert the routing information [Separator_Key -> LBA_B] into the truncated B+ tree internal node in the host's memory.

[0097] In one embodiment, if the host sends a read request to the old LBA (i.e., the logical block address of the original leaf node) before the host routing update is completed, the computeable storage device can automatically intercept and redirect the request to the new LBA (i.e., the logical block address of the new leaf node) containing the target key by maintaining the right sibling pointer inside itself, without the need for host intervention, thus ensuring read-write consistency.

[0098] In one embodiment, such as Figure 8 As shown, the method further includes: Step 401: Before the host completes the update of the routing information, when the computable storage device receives a read request from the host based on the logical block address of the original leaf node sent by the internal node, the computable storage device checks the preset mapping table and determines the size relationship between the key carried by the read request and the separator key.

[0099] To achieve transparent interception and correction, this invention deploys the following mechanism within the computeable storage device, which is illustrated below with specific examples: After the computable storage device is split, in addition to sending an AEN packet to the host, the computable storage device will immediately insert a record into an SRAM mapping table: [Source_LBA: LBA_A, Range_Start:Separator_Key, Target_LBA: LBA_B]. When the computable storage device's command parsing engine receives a Read(LBA_A, Key=90) request from the host, it will first check the SRAM mapping table through a hardware comparator.

[0100] Step 402: When the key carried by the read request is greater than or equal to the delimiter key, modify the logical block address of the operation required by the read request from the logical block address of the original leaf node to the logical block address of the new leaf node; return the data required by the read request according to the modified logical block address.

[0101] The system detects that in a read request targeting the logical block address LBA_A of the original leaf node, the key Key=90 carried by the read request is greater than or equal to the value of the separator key Separator_Key, thus matching the right-hand pointer rule. The controller on the computable storage device silently changes the target address of this read request from the logical block address LBA_A of the original leaf node to the logical block address LBA_B of the new leaf node, and then retrieves the correct data from the underlying DRAM incremental log or NAND cache. The computable storage device then returns the data to the host via the PCIe bus.

[0102] Step 403: When the host completes the update of the routing information, the computeable storage device deletes the temporary mapping record in the preset mapping table.

[0103] Throughout the process, the host is completely unaware of this transparent redirection, and the application layer still perceives a strongly consistent transaction response. Once the routing information on the host is finally updated via AEN packets, the temporary sibling pointers in the SRAM table within the computed storage device will be safely cleaned up and destroyed to free up memory.

[0104] The embodiments of the present invention convert the inconsistency window during structural adjustment into a transparent redirection process within the device, so that the host does not need to be aware of the internal structural changes of the computable storage device, nor does it need to add an additional synchronization protocol, thereby enabling the system to meet consistency requirements while maintaining asynchronicity, high concurrency, and low overhead.

[0105] It is worth noting that the right-side sibling pointer in this embodiment of the invention is not a simple transplant of the Sibling Pointer in the existing B-link tree, but a device-side temporary route correction mechanism proposed for the architecture of this embodiment of the invention, which is fundamentally different from the traditional B-link tree; the two are fundamentally different in terms of application objects, life cycle and mechanism of action.

[0106] Specifically, firstly, in the existing B-link tree, the right-side sibling pointer is an extension of the B+ tree node's own data structure, and each node permanently stores the Sibling Pointer.

[0107] In this embodiment of the invention, the right-side sibling pointer belongs to the data redirection metadata used internally by the computable storage device during structural adjustments. The right-side sibling pointer in this embodiment is not a B+ tree node field, but rather an internal dynamic routing table. For example, on the computable storage device, after the leaf node splits, "[Source_LBA, Range_Start, Target_LBA]" is inserted into the SRAM mapping table for request interception and redirection.

[0108] Secondly, existing B-link trees are long-term, stored along with the nodes, and are part of the index structure. In contrast, the B-link tree in this invention is temporary, existing only within the time window when the leaf nodes have split but the routing information on the host side has not yet been updated; the B-link tree is deleted after the routing information on the host side has been updated.

[0109] If the existing B-link tree technology is directly deployed to the architecture of this embodiment of the invention, the following problems will occur: First, it cannot resolve the separation issue between the host and the computable storage device. Existing B-link trees assume that the node manager possesses the complete tree structure and that node modifications and queries occur within the same control domain. However, in the architecture of this invention, the host manages internal nodes, while the computable storage device manages leaf nodes. Therefore, existing B-link trees cannot handle the asynchronous state differences between routing information from the host and the leaf node storage on the computable storage device.

[0110] Secondly, it leads to a significant increase in equipment maintenance costs. If the existing complete B-link tree technology is used, the computational storage device needs to maintain sibling pointers, fence keys, node versions, and parent node relationships for a long time, which increases metadata space, query paths, and update complexity. However, the embodiments of this invention only need to maintain the logical block address of the original leaf node, the separator key, the logical block address of the new leaf node, and the temporary mapping.

[0111] Furthermore, host routing lag cannot be avoided. Existing B-link trees address concurrent modifications to nodes within the same tree. However, this invention addresses the asynchrony between the routing state on the host side and the physical state on the computeable storage device. The two problems stem from entirely different sources.

[0112] Therefore, the embodiments of the present invention do not simply adopt the B-link tree, but address the new problem of asynchronous separation between host routing and device data state in a computeable storage architecture by making the B-link tree a temporary, consistency guarantee mechanism through a device-side lightweight modification.

[0113] This invention also provides a crash recovery mechanism. Traditional database crash recovery is extremely time-consuming, typically involving an analysis phase, a redo phase, and an undo phase. Because this invention transfers a large amount of state to the internal computeable storage device, the crash recovery process is greatly simplified and accelerated.

[0114] Specifically, in one embodiment, the computeable storage device is also equipped with a power supply monitoring and PLP power failure protection mechanism, which can trigger an emergency write in case of abnormal power failure, to persist dirty data in DRAM to the underlying NAND flash memory media array (including B+ leaf page area and sequential log area), thereby completing all data maintenance operations in a closed loop within the computeable storage device.

[0115] When a server experiences a catastrophic power outage and restarts, upon powering up the compute storage device, the firmware on the compute storage device performs an internal consistency self-check before activating the NVMe Ready signal. The firmware scans the NAND reserved log area (i.e., the Journal Zone) and reloads the unmerged incremental logs salvaged by the PLP during the power outage into the DRAM. By reconstructing the internal metadata tables, the underlying data topology of the compute storage device instantly returns to the consistent state before the power outage.

[0116] In one embodiment, since the host's memory data (i.e., the internal routing tree) is completely lost during a power outage, the host database process no longer needs to scan terabyte-level redo logs upon startup. The host sends a dedicated scan command, NVME_CMD_GET_ROUTER_KEYS, to the compute storage device. Upon receiving the command, the compute storage device sequentially scans all leaf nodes based on its internal FTL table or the metadata records in the node header, extracting all delimiter keys and their corresponding logical block addresses, and then packages and transmits them in batches to the host. The host uses these key-value streams to rapidly reconstruct the internal node structure of the B+ tree from bottom to top in memory. Because it does not need to process massive data entities, but only constructs the index skeleton, the database routing structure, which is several gigabytes in size, can be restored within milliseconds to hundreds of milliseconds, enabling the database to quickly reach a ready state for providing services.

[0117] The host side of this invention completely eliminates the cumbersome leaf node splitting, merging, and data rearrangement operations, simplifying the read, modify, and write processes into a single incremental log delivery. This eliminates lock contention caused by SMO, allowing the host CPU to handle more concurrent transactions at full speed, resulting in extremely low host CPU overhead. It avoids repeatedly transferring unmodified page data back and forth between the host and storage devices. Splitting and merging within the computationally compliant storage device are completed using the device's high-bandwidth bus or DMA, transforming random small-block updates into large-block sequential writes to disk. This significantly reduces the write amplification factor to near the theoretical lower limit, greatly saving I / O bandwidth. Because write operations do not require waiting for physical page allocation and writing, but only need to be appended to the DRAM within the computationally compliant storage device before returning, the system's write latency reaches nanoseconds to microseconds (depending on PCIe transmission latency), increasing system throughput several times under extreme write-intensive loads. This invention also features a highly reliable crash recovery mechanism. Relying on the built-in power-loss protection capacitor and internal write-ahead log mechanism of the computeable storage device, even in the event of an extreme physical power failure, the computeable storage device can automatically recover its incremental state, achieving a millisecond-level recovery time target, which far exceeds the speed of traditional databases that rely on host replay redo logs.

[0118] The foregoing embodiments provided a method for adjusting a delayed B+ tree structure based on computationally readable storage. In this embodiment, another apparatus for adjusting a delayed B+ tree structure based on computationally readable storage will be proposed. The apparatus for adjusting a delayed B+ tree structure based on computationally readable storage includes: a processor and a memory for storing processor-executable instructions; wherein the processor is configured to execute the method for adjusting a delayed B+ tree structure based on computationally readable storage described in the foregoing embodiments.

[0119] like Figure 9 As shown, the device for adjusting a computationally storable delay B+ tree structure includes a processor 21 and a memory 22, wherein the processor 21 and the memory 22 can be connected via a bus or other means.

[0120] Processor 21 can be a CPU. Processor 21 can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above types of chips.

[0121] Memory 22, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the method for adjusting the delayed B+ tree structure based on computationally readable storage in the foregoing embodiments. The processor executes various functional applications and training processes by running the non-transitory software programs, instructions, and modules stored in the memory.

[0122] The memory 22 may include a program storage area and a training storage area. The program storage area may store the operating system and applications required for at least one function; the training storage area may store training data, etc. Furthermore, the memory may include high-speed random access memory and non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 22 may optionally include memory remotely located relative to the processor, which can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. The one or more modules stored in the memory 22, when executed by the processor 21, perform the method for adjusting a delayed B+ tree structure based on computationally readable storage as shown in the embodiments of the present invention. Specific details of the method for adjusting a delayed B+ tree structure based on computationally readable storage can be understood by referring to the corresponding descriptions and effects in the embodiments of the present invention, and will not be repeated here.

[0123] This embodiment also provides a computer storage medium storing a computer program that can be executed by a processor to perform the method for adjusting the delayed B+ tree structure based on computable storage as described in the foregoing embodiments.

[0124] The computer storage medium stores computer-executable instructions, which can execute the method for adjusting the delayed B+ tree structure based on computationally readable storage in any of the above method embodiments. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium may also include combinations of the above types of memory.

[0125] The specific steps of the method for adjusting the delayed B+ tree structure based on computable storage are described in the foregoing embodiments, and will not be repeated in this embodiment.

[0126] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for adjusting a computationally storable, delayed B+ tree structure, characterized in that, include: Modify the leaf nodes involved in the incremental log instruction received from the host to complete the write operation of the write request for the leaf nodes; The incremental log instruction is generated by the host in response to the write request, based solely on the internal nodes and the write request.

2. The method for adjusting a computationally storable delayed B+ tree structure according to claim 1, characterized in that, The host maintains the routing information of the internal nodes; The method includes: Receive the write request, obtain the operation type of the write operation, and the key and value of the leaf node from the write request; Obtain the target logical block address from the routing information according to the write request; Incremental data is generated based on the operation type and the key and value of the leaf node; incremental log instructions are generated based on the incremental data and the target logical block address. The incremental log instruction is sent to the computable storage device.

3. The method for adjusting a computationally storable delayed B+ tree structure according to claim 2, characterized in that, The method includes: Receive the incremental log instruction and obtain the target logical block address and the incremental data from it; The incremental data is added to the incremental log of the target logical block address in the computable storage device, and a successful response for the write operation is returned to the host within a preset delay time. Based on the status of the incremental logs accumulated in the local cache, modifications to the leaf nodes are performed asynchronously after receiving the incremental log instruction and before returning the success response.

4. The method for adjusting a computationally storable delayed B+ tree structure according to claim 3, characterized in that, The method includes: When the size of the incremental log of a leaf node reaches the split threshold, the leaf node is used as the original leaf node, and the physical page where the original leaf node is located is read. Perform structural maintenance operations on the physical page and the incremental log to obtain a new leaf node, and write the new leaf node into the non-volatile storage medium on the computeable storage device. Based on the modification from the original leaf node to the new leaf node, an asynchronous notification message is generated; the asynchronous notification message is sent to the host so that the host can update the routing information according to the asynchronous notification message.

5. The method for adjusting a computationally storable delayed B+ tree structure according to claim 4, characterized in that, The structural maintenance operations include splitting operations; The method includes: The physical page and the incremental log are split to generate at least two new leaf nodes, and the at least two new leaf nodes are written into the non-volatile storage medium on the computeable storage device.

6. The method for adjusting a computationally storable delayed B+ tree structure according to claim 4, characterized in that, The method further includes: A temporary mapping record is generated based on the logical block address of the original leaf node, the delimiter key on which the structure maintenance operation is based, and the logical block address generated by the structure maintenance operation. The temporary mapping record is stored in a preset mapping table within the computable storage device.

7. The method for adjusting a computationally storable delayed B+ tree structure according to claim 6, characterized in that, The method further includes: Before the host completes the update of the routing information, when the computable storage device receives a read request from the host based on the logical block address of the original leaf node sent by the internal node, the computable storage device checks the preset mapping table and determines the size relationship between the key carried by the read request and the separator key. When the key carried by the read request is greater than or equal to the delimiter key, the logical block address of the operation required by the read request is modified from the logical block address of the original leaf node to the logical block address of the new leaf node; the data required by the read request is returned according to the modified logical block address; When the host completes the update of the routing information, the computeable storage device deletes the temporary mapping record from the preset mapping table.

8. The method for adjusting a computationally storable delayed B+ tree structure according to any one of claims 1-7, characterized in that, The method further includes: During the process of generating incremental log instructions, the host does not read the physical pages of leaf nodes in the computable storage device.

9. A device for adjusting a computationally storable delayed B+ tree structure, characterized in that, The apparatus for adjusting the computationally storable delayed B+ tree structure includes: a processor and a memory for storing processor-executable instructions; The processor is configured to perform the method for adjusting a delayed B+ tree structure based on computable storage as described in any one of claims 1 to 8.

10. A non-volatile computer storage medium, characterized in that, The computer storage medium stores computer-executable instructions that are executed by one or more processors to perform the method for adjusting a delayed B+ tree structure based on computationally readable storage as described in any one of claims 1 to 8.

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