Chip verification coverage prediction and use case optimization method
Patent Information
- Application Number
- CN202611390335.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-09-09
- Publication Date
- 2026-10-09
AI Technical Summary
例如，某服务器芯片的CPU模块，从95%覆盖率提升至98%，需新增用例数量是从80%提升至95%的3倍，而验证时间占比高达总验证时间的40%，导致资源投入与效益严重失衡
[0030]1）本申请通过 LSTM加注意力机制的覆盖率预测模型，解决了传统方法需在用户例执行后才能发现覆盖率缺口，导致验证返工的问题；在执行用例前提前预测覆盖率达标情况与缺口位置，验证人员可针对性补充用例，避免执行-补漏-再执行的循环。
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Figure CN122885336A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip verification technology, and more specifically to a method for chip verification coverage prediction and use case optimization. Background Technology
[0002] In the chip verification process, "coverage compliance" is one of the core indicators for judging verification completeness, including functional coverage (covering design functionalities), code coverage (covering design code branches / statements), and assertion coverage (covering critical design assertions). However, with the exponential increase in chip design complexity (such as 7nm and below process chips, multi-core heterogeneous SoCs), the traditional post-verification model based on "executing test cases - calculating coverage - supplementing test cases" faces the following significant technical challenges in ensuring "completeness" and "no omissions":
[0003] Coverage gaps discovered after the fact lead to verification delays: In traditional processes, coverage data can only be statistically analyzed after verification test cases have been executed. If it is found that the coverage of a certain module (such as the NPU module of an AI chip or the safety island module of an automotive chip) does not reach a preset threshold (such as 98%), supplementary test cases need to be redesigned, debugged, and executed, resulting in rework of the verification process. Data from an automotive SoC chip project shows that due to coverage gaps discovered after the fact, the verification cycle was extended by an average of 15%-20%, seriously affecting the chip's time-to-market.
[0004] Test case design relies heavily on human experience, leading to risks of redundancy and omissions: The design of verification test cases is highly dependent on engineer experience. Inexperienced engineers may omit test cases for critical functionalities (such as failing to design a "DDR5 storage controller sudden transmission anomaly" test case), while experienced engineers may waste verification resources (computing power, time) due to excessive redundancy (such as repeatedly designing more than three test cases covering the same "PCIe link negotiation" function). Statistics show that in traditionally manually designed test cases, redundant test cases account for 20%-30%, while the omission rate of critical gap test cases remains at 5%-8%.
[0005] Diminishing marginal returns and resource imbalances: When coverage approaches the target threshold (e.g., from 95% to 98%), traditional methods require significant resources to design a small number of use cases, but the effect of coverage improvement is limited. For example, for a server chip's CPU module, increasing coverage from 95% to 98% requires three times the number of new use cases compared to increasing coverage from 80% to 95%, while verification time accounts for as much as 40% of the total verification time, resulting in a severe imbalance between resource investment and benefits.
[0006] Lack of cross-project knowledge reuse leads to low verification efficiency for new chips: Verification experience from different chip projects (such as mobile SoC, industrial MCU, and AI acceleration chips) is difficult to reuse: Experience in "memory module coverage optimization" in one project cannot be directly transferred to "security module verification" in another project, resulting in each new project having to design use cases and coverage improvement strategies from scratch, leading to low verification efficiency.
[0007] In existing technologies, some solutions attempt to improve design efficiency through "use case template libraries," but these still cannot solve the problems of "post-hoc patching" and "experience dependence." Although other solutions use simple statistical models (such as regression analysis) to predict coverage, their prediction accuracy is less than 70% because they do not consider the non-linear relationship between chip design parameters (such as module complexity and interface protocol type) and use case characteristics (such as use case execution duration and triggering conditions), which cannot meet actual verification needs. Therefore, there is an urgent need for a technical solution that can "predict coverage gaps in advance, intelligently optimize use cases, and reuse verification knowledge" to fundamentally solve the pain points of traditional verification. Summary of the Invention
[0008] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for chip verification coverage prediction and use case optimization.
[0009] The objective of this invention is achieved through the following technical solution:
[0010] This application discloses a chip verification coverage prediction and use case optimization method, including the following steps:
[0011] In the stage of constructing a multi-dimensional verification dataset, multi-dimensional data from the entire chip verification process are collected and preprocessed. The multi-dimensional data includes design parameter data, use case feature data, historical coverage data, and cross-project knowledge data. Then, the preprocessed multi-dimensional data is divided into training set, verification set, and test set according to the proportion.
[0012] In the training phase of the collaborative model, a collaborative model is designed, comprising a coverage prediction model and a use case optimization model. The coverage prediction model is built based on LSTM combined with an attention mechanism to predict the coverage achievement status of each module after the execution of the current use case set and the location of potential coverage gaps. The use case optimization model is built based on a random forest classifier combined with a genetic algorithm to generate supplementary use cases and select the optimal use case combination. The two models are trained and their parameters are tuned using the training and validation sets respectively to ensure that the prediction accuracy of the coverage prediction model is above a first preset threshold and the use case type prediction accuracy of the use case optimization model is above a second preset threshold. Then, the performance of the trained and tuned two models is evaluated using the test set. If the coverage prediction accuracy is above a third preset threshold and the coverage improvement after use case optimization is above a fourth preset threshold, the collaborative model meets the requirements; otherwise, tuning is performed again.
[0013] Based on the collaborative model execution verification phase, the chip design parameters and design requirement priorities are input, and an initial test case set is generated through a test case optimization model. This initial test case set is then simplified to obtain a simplified initial test case set. The features of the simplified initial test case set and the design parameters are input into a coverage prediction model, which outputs the predicted coverage and coverage gap locations for each module of the chip. If the predicted coverage reaches a fifth preset threshold, the simplified initial test case set is executed; otherwise, the coverage gap locations are extracted. The coverage gap locations and design parameters are then input into the test case optimization model to generate candidate supplementary test cases. An optimization sub-model evaluates the candidate supplementary test cases and selects the optimal combination of supplementary test cases. The simplified initial test case set and the optimal combination of supplementary test cases are executed, and actual coverage and test case execution data are collected. The actual coverage is fed back to the multi-dimensional data to update the training set, achieving iterative optimization of the collaborative model.
[0014] In the closed-loop control phase of verification completeness, the actual coverage rate is compared with the sixth preset threshold. If the functional coverage rate, code coverage rate, and assertion coverage rate of all modules meet the standards, the verification is considered complete. If there are modules that do not meet the standards, the coverage prediction and test case optimization are performed again. The coverage contribution value of each test case is calculated, redundant test cases with contribution values lower than the seventh preset threshold are removed, and the test case library is updated. The design parameters, test case features, and coverage optimization strategies are stored in the verification knowledge graph, and knowledge reuse is achieved through graph neural networks.
[0015] Furthermore, the design parameter data includes chip module type, module complexity, and design requirement priority; the module complexity includes lines of code, number of state machines, and interface protocol version; the use case feature data includes use case type, use case execution duration, use case triggering conditions, and number of functional points / code branches covered by the use case; the use case type includes functional testing, timing testing, and exception injection; the historical coverage data includes functional coverage, code coverage, assertion coverage, and corresponding coverage gap types for each stage of unit verification, integration verification, and system verification; the cross-project knowledge data includes use case design-coverage correlation data from historical chip projects and engineer verification optimization experience data.
[0016] Furthermore, the preprocessing includes cleaning and standardizing the collected multi-dimensional data, specifically including:
[0017] Remove abnormal data, including invalid coverage data caused by test case execution failures and incorrect data for entering design parameters;
[0018] The Word2Vec model is used to semantically encode unstructured data and transform it into feature vectors;
[0019] The numerical data is normalized to map the values to the [0,1] interval to adapt to the model input requirements.
[0020] Furthermore, the architecture of the coverage prediction model includes an input layer, a hidden layer, and an output layer. The input layer receives design parameter vectors, current use case feature vectors, and coverage increment data of executed use cases. The hidden layer uses an LSTM network to capture the temporal correlation between use case execution order and coverage changes, and strengthens the feature weights of key modules and high-priority design requirements through an attention mechanism. The output layer outputs the predicted coverage, coverage gap probability, and gap location for each module. The predicted coverage includes functional coverage, code coverage, and assertion coverage.
[0021] Furthermore, the architecture of the use case optimization model includes a classification sub-model and an optimization sub-model. The classification sub-model uses a random forest algorithm, taking the coverage gap type and design parameters as input, and outputs the optimal use case type and key features of the use case. The optimization sub-model uses a genetic algorithm, with the maximum coverage improvement and the shortest total execution time of the use cases as dual objective functions, to filter the candidate use cases generated by the classification sub-model and output the optimal combination of use cases.
[0022] Furthermore, the training set and validation set are used to train and fine-tune the parameters of the dual models, specifically including:
[0023] S21. Train the coverage prediction model using the training set, minimize the mean square error between the predicted coverage and the actual coverage using the Adam optimizer, and adjust the number of LSTM network layers and the weight coefficients of the attention mechanism using the validation set.
[0024] S22. Train the classification sub-model of the use case optimization model using the training set, and optimize the number of decision trees and node splitting threshold of the random forest using the grid search method.
[0025] S23. Optimize the population size, crossover probability, and mutation probability of the genetic algorithm to achieve the optimal balance between coverage improvement and verification resource consumption.
[0026] Furthermore, the simplification of the initial use case set specifically includes: removing redundant use cases that repeatedly cover the same functional point to obtain a simplified initial use case set.
[0027] Furthermore, the iterative optimization of the collaborative model specifically includes: after each preset number of verification processes, the collaborative model is retrained using the updated training set to improve its generalization ability.
[0028] Furthermore, the knowledge reuse includes: when a new chip project contains functional modules similar to those in a historical project, automatically recommending corresponding optimization use cases and coverage optimization strategies from the historical project.
[0029] The beneficial effects of this invention are:
[0030] 1) This application solves the problem that traditional methods can only find coverage gaps after user test cases are executed, leading to verification rework by using a coverage prediction model with LSTM and attention mechanism. By predicting the coverage target and gap location in advance before executing test cases, verification personnel can supplement test cases in a targeted manner, avoiding the cycle of execution-filling gaps-re-execution.
[0031] 2) This application automatically generates targeted supplementary use cases and optimal use case combinations through a use case optimization model, solving the problems of traditional use case design relying on engineer experience and being prone to omissions or redundancy; no manual intervention is required. At the same time, the use case set generated by this application has a critical gap coverage rate of 98% (compared to 88% for manual design), and the proportion of redundant use cases is reduced from 25% to below 5%, while reducing manual man-hours for use case design by 70%.
[0032] 3) This application achieves high coverage improvement with fewer additional use cases by using a genetic algorithm for bi-objective optimization (maximum coverage improvement and shortest execution time), which solves the problem of diminishing marginal benefits of resource investment when the coverage is close to the threshold in traditional methods.
[0033] 4) This application verifies that knowledge graphs and GNN models can automatically match “similar design scenarios” and reuse optimization strategies.
[0034] 5) The model in this application is trained with multi-dimensional data and can be adapted to verification scenarios of different types of chips (MCU, SoC, AI chip, automotive chip). For the functional safety requirements of automotive chips, the model can automatically strengthen the prediction weight of safety assertion coverage; for the computing power requirements of chips, the generation logic of NPU module test cases can be optimized. Attached Figure Description
[0035] Figure 1 This is a schematic diagram illustrating the steps of a chip verification coverage prediction and use case optimization method according to an embodiment of the present invention. Detailed Implementation
[0036] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0037] For example, this application discloses a chip verification coverage prediction and use case optimization method to solve the technical problems in existing chip verification technologies, such as extended verification cycles, redundant or missing use cases, and wasted resources due to the post-discovery of coverage gaps, reliance on manual experience in use case design, resource imbalance in coverage improvement, and the inability to reuse cross-project knowledge. This method proactively ensures verification completeness and eliminates omissions. The steps are illustrated in the diagram below. Figure 1 As shown, the specific steps include:
[0038] S1. In the stage of constructing a multi-dimensional verification dataset, multi-dimensional data of the entire chip verification process are collected and preprocessed. The multi-dimensional data includes design parameter data, use case feature data, coverage history data, and cross-project knowledge data. In this embodiment, the preprocessed multi-dimensional data is divided into a training set (for model training), a verification set (for model parameter tuning), and a test set (for model performance evaluation) in a ratio of 7:2:1.
[0039] S2. In the collaborative model training phase, a collaborative model is designed, comprising a coverage prediction model and a use case optimization model. The coverage prediction model is constructed based on LSTM (Long Short-Term Memory) combined with an attention mechanism, used to predict the coverage achievement status of each module after the execution of the current use case set and the location of potential coverage gaps. The use case optimization model is constructed based on a random forest classifier combined with a genetic algorithm, used to generate supplementary use cases and select the optimal use case combination. The dual models are trained and their parameters are tuned using the training set and validation set respectively, ensuring that the prediction accuracy of the coverage prediction model is above the first preset threshold (90% in this embodiment), and the use case type prediction accuracy of the use case optimization model is above the second preset threshold (85% in this embodiment). Then, the performance of the trained and tuned dual models is evaluated using the test set. If the coverage prediction accuracy is above the third preset threshold (90% in this embodiment) and the coverage improvement after use case optimization is above the fourth preset threshold (8% in this embodiment) (compared to manually designed use cases), the collaborative model meets the standard; otherwise, it is tuned again.
[0040] S3. Based on the collaborative model, the verification phase is executed. Inputting chip design parameters (e.g., a 7nm SoC chip, including CPU, NPU, PCIe 5.0, and security island modules) and design requirement priorities, the initial use case set is generated through the use case optimization model (e.g., generating 20 CPU function use cases, 15 NPU computing power use cases, and 12 PCIe use cases). The initial test case set is simplified to obtain a simplified initial test case set. The features and design parameters of the simplified initial test case set are input into the coverage prediction model, which outputs the predicted coverage and coverage gap locations of each module of the chip. If the predicted coverage reaches the fifth preset threshold (e.g., functional coverage ≥ 98%, code coverage ≥ 95%), the simplified initial test case set is executed. If it does not reach the threshold, the coverage gap locations are extracted (e.g., the low-precision computing mode switching function of the NPU module is not covered). Then, the coverage gap locations and design parameters are input into the test case optimization model to generate candidate supplementary test cases (e.g., generate 2 NPU low-precision mode switching test cases). The optimization sub-model evaluates the candidate supplementary test cases and selects the optimal supplementary test case combination (e.g., selecting 1 supplementary test case can improve the NPU functional coverage by 3% and the execution time is 0.5 hours). The simplified initial test case set and the optimal supplementary test case combination are executed, the actual coverage and test case execution data are collected, and the actual coverage is fed back to the multi-dimensional data to update the training set, thereby realizing the iterative optimization of the collaborative model.
[0041] S4. In the closed-loop control phase of verification completeness, the actual coverage rate is compared with the sixth preset threshold. If the functional coverage rate, code coverage rate, and assertion coverage rate of all modules meet the standard, the verification is deemed complete. If there are modules that do not meet the standard, the coverage prediction and test case optimization are performed again. The coverage contribution value of each test case is calculated (e.g., test case A contributes 2% coverage rate, test case B contributes 0.5%), and redundant test cases with contribution values lower than the seventh preset threshold (0.1% in this embodiment) are removed. The test case library is updated. The design parameters, test case features, and coverage optimization strategies are stored in the verification knowledge graph, and knowledge reuse for similar design scenarios is achieved through graph neural networks (GNN).
[0042] For example, the design parameter data includes chip module type (such as CPU, NPU, PCIe, security module), module complexity, and design requirement priority (high / medium / low); the module complexity includes the number of lines of code, the number of state machines, and the interface protocol version; the use case feature data includes use case type, use case execution duration, use case triggering conditions (such as initialization after reset, high load transmission), and the number of functional points / code branches covered by the use case; the use case type includes functional testing, timing testing, and exception injection; the historical coverage data includes functional coverage, code coverage, and assertion coverage at each stage of unit verification, integration verification, and system verification, as well as the corresponding coverage gap types (such as uncovered exception handling branches, untriggered security assertions); the cross-project knowledge data includes use case design-coverage correlation data for historical chip projects (same type or heterogeneous chips), and engineer verification optimization experience data (such as adding 16 burst length use cases for DDR5 modules can improve coverage by 5%).
[0043] For example, the preprocessing includes cleaning and standardizing the collected multi-dimensional data, specifically including:
[0044] Remove abnormal data, including invalid coverage data caused by test case execution failures, and incorrect data for entering design parameters;
[0045] The Word2Vec model is used to semantically encode unstructured data (such as engineers' experience texts) and transform it into feature vectors;
[0046] Normalize numerical data (such as lines of code and execution time) to map the values to the [0,1] interval to adapt to the model input requirements.
[0047] For example, the architecture of the coverage prediction model includes an input layer, a hidden layer, and an output layer. The input layer is used to receive design parameter vectors, current use case feature vectors, and coverage increment data of executed use cases. The hidden layer uses an LSTM network to capture the temporal correlation between use case execution order and coverage changes, and strengthens the feature weights of key modules (such as security modules) and high-priority design requirements through an attention mechanism. The output layer is used to output the predicted coverage, coverage gap probability (e.g., 85% probability of code coverage gap in PCIe modules), and gap location (e.g., the uncovered branch of a PCIe module due to a broken and reconnected link). The predicted coverage includes functional coverage, code coverage, and assertion coverage.
[0048] For example, the architecture of the use case optimization model includes a classification sub-model and an optimization sub-model. The classification sub-model uses a random forest algorithm, taking the coverage gap type and design parameters as input, and outputs the optimal use case type (e.g., for the gap where the abnormal branch is not covered, output an exception injection use case) and key features of the use case (e.g., triggering conditions and execution parameters). The optimization sub-model uses a genetic algorithm with the maximum coverage improvement and the shortest total use case execution time as the dual objective function (e.g., design a fitness function, fitness = 0.6 × coverage improvement + 0.4 × (1 - normalized value of total use case execution time) (the fitness function is not unique and can be adjusted by the user). It filters the candidate use cases generated by the classification sub-model and outputs the optimal use case combination (e.g., selecting 3 supplementary use cases can improve coverage by 6% and reduce the total execution time by 2 hours).
[0049] For example, the training set and validation set are used to train and fine-tune the parameters of the dual models, respectively, specifically including:
[0050] S21. Train the coverage prediction model using the training set, minimize the mean square error between the predicted coverage and the actual coverage using the Adam optimizer, and adjust the number of LSTM network layers (3-5 layers) and the weight coefficients of the attention mechanism using the validation set.
[0051] S22. Train the classification sub-model of the use case optimization model using the training set, and optimize the number of decision trees (100-200 trees) and node splitting threshold of the random forest using the grid search method.
[0052] S23. Optimize the population size, crossover probability, and mutation probability of the genetic algorithm to achieve the optimal balance between coverage improvement and verification resource consumption.
[0053] For example, the simplification of the initial use case set specifically includes: removing redundant use cases that repeatedly cover the same functional point to obtain a simplified initial use case set.
[0054] For example, the iterative optimization of the collaborative model specifically includes: after each preset number of verification processes (10 times in this embodiment), the collaborative model is retrained using the updated training set to improve its generalization ability.
[0055] For example, the knowledge reuse includes: when a new chip project contains functional modules similar to those in a historical project, automatically recommending the corresponding optimized use cases and coverage optimization strategies from the historical project (e.g., when the next project contains a PCIe 5.0 module, automatically recommending the PCIe use cases optimized in this project).
[0056] For example, taking the system-level verification of a certain AI SoC chip (including a CPU module, an NPU module, a PCIe 5.0 interface module, and a security island module) as an example:
[0057] Step 1: Constructing a multi-dimensional validation dataset
[0058] Design parameters: CPU module (500,000 lines of code, 20 state machines), NPU module (supports FP16 / FP32 precision, computing power 100TOPS), PCIe 5.0 module (supports 16 channels, speed 32GB / s), security island module (compliant with ISO26262ASIL-B standard).
[0059] Use case feature data: Collect features of 2,000 use cases from historical projects, including CPU function use cases (execution time 10 minutes, covering 5 function points) and NPU computing power use cases (execution time 30 minutes, covering 3 computing power levels);
[0060] Historical coverage data: During the unit verification phase, data such as 85% code coverage for the CPU module and 80% functional coverage for the NPU module were collected, and gap types were marked (e.g., CPU exception handling branches were not covered, NPU low-precision mode was not covered).
[0061] Cross-project knowledge data: Import use case coverage data and engineer experience from three similar AISoC projects (e.g., adding FP16 precision switching to the NPU module can improve the functional coverage by 2%).
[0062] Data preprocessing: Remove invalid coverage data (120 records) caused by test case execution timeouts; convert engineer experience text into 128-dimensional vectors using the Word2Vec model; normalize numerical data such as lines of code (500,000 lines → 0.8) and execution time (10 minutes → 0.2);
[0063] Dataset split: 1680 training data, 480 validation data, and 240 test data were obtained.
[0064] Step 2: Model Training and Optimization
[0065] Coverage prediction model training: Input layer: Design parameter vector (e.g., CPU module code lines 0.8, NPU computing power 0.9), current use case feature vector (e.g., use case type: functional test, execution time 0.2); Hidden layer: Set the LSTM network to 4 layers, and set the weight coefficient of the attention mechanism for the safety island module to 1.5 (higher than the 1.0 of other modules); Training process: Use the Adam optimizer for 100 iterations. The mean squared error of coverage prediction on the validation set decreased from 0.12 to 0.03, and the final accuracy on the test set reached 92%.
[0066] Use case optimization model training: Classification sub-model, with 150 random forest decision trees, achieved an accuracy of 87% in predicting use case types on the test set; Optimization sub-model, with a genetic algorithm population size of 50, a crossover probability of 0.8, and a mutation probability of 0.1, achieved a 12% higher coverage improvement and a 40% reduction in execution time for the optimal use case combination under the dual objective function compared to manual design.
[0067] Step 3: Verify process execution
[0068] Initial test case set generation: After inputting design parameters, the classification sub-model generates an initial test case set (25 CPU test cases, 20 NPU test cases, 15 PCIe test cases, and 10 security island test cases); the optimization sub-model removes 8 redundant test cases (such as test cases that repeatedly cover "CPU initialization") and outputs a simplified test case set (62 test cases in total).
[0069] Coverage prediction: Input concise use case set features, predict model output: CPU module code coverage 92% (meets the standard, threshold 90%), NPU module functional coverage 85% (does not meet the standard, threshold 95%), gap location: NPU's FP16 / FP32 switching function is not covered;
[0070] Supplementary test case generation: Input the gap location, the classification sub-model generates 3 NPU precision switching test cases; the optimization sub-model selects 2 optimal test cases (coverage improved by 8%, execution time 1 hour).
[0071] Use case execution and feedback: 62+2=64 use cases were executed, with actual NPU functional coverage reaching 93% (close to the threshold) and CPU code coverage reaching 93%; the actual data was fed back to the dataset, the training set was updated, and after model iteration and optimization, the prediction accuracy improved to 93% in the next iteration.
[0072] Step 4: Closed-loop management and knowledge reuse
[0073] Coverage compliance verification: The NPU functional coverage is 93%, which is less than 95%. Return to the coverage prediction in step 3 for re-prediction. The model output needs to be supplemented with one NPU low-precision calculation exception test case. After executing the supplemented test case, the NPU functional coverage reaches 96%, and the coverage of all modules meets the standard.
[0074] Use case validity assessment: Remove 2 redundant use cases with a coverage contribution of 0.05%, and update the use case library to 63.
[0075] Knowledge reuse: The NPU precision switching test case design strategy is stored in the knowledge graph. When the next AISoC project includes an NPU module, the system automatically recommends the test case, reducing the NPU test case design time for new projects from 3 days to 1 day.
[0076] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.
Claims
1. A method for predicting chip verification coverage and optimizing use cases, characterized in that, Includes the following steps: In the stage of constructing a multi-dimensional verification dataset, multi-dimensional data from the entire chip verification process are collected and preprocessed. The multi-dimensional data includes design parameter data, use case feature data, historical coverage data, and cross-project knowledge data. The preprocessed multidimensional data was then divided into training, validation, and test sets according to the proportions. In the training phase of the collaborative model, a collaborative model is designed, comprising a coverage prediction model and a use case optimization model. The coverage prediction model is built based on LSTM combined with an attention mechanism to predict the coverage achievement status of each module after the execution of the current use case set and the location of potential coverage gaps. The use case optimization model is built based on a random forest classifier combined with a genetic algorithm to generate supplementary use cases and select the optimal use case combination. The two models are trained and their parameters are tuned using the training and validation sets respectively to ensure that the prediction accuracy of the coverage prediction model is above a first preset threshold and the use case type prediction accuracy of the use case optimization model is above a second preset threshold. Then, the performance of the trained and tuned two models is evaluated using the test set. If the coverage prediction accuracy is above a third preset threshold and the coverage improvement after use case optimization is above a fourth preset threshold, the collaborative model meets the requirements; otherwise, tuning is performed again. Based on the collaborative model execution verification phase, the chip design parameters and design requirement priorities are input, and an initial use case set is generated through the use case optimization model. The initial use case set is then simplified to obtain a simplified initial use case set. The features of the simplified initial use case set and the design parameters are input into the coverage prediction model, which outputs the predicted coverage and coverage gap locations of each module of the chip. If the predicted coverage reaches the fifth preset threshold, the simplified initial use case set is executed; otherwise, the coverage gap locations are extracted. Then, the coverage gap locations and design parameters are input into the use case optimization model to generate candidate supplementary use cases. The optimization sub-model evaluates the candidate supplementary use cases and selects the optimal combination of supplementary use cases. The initial use case set and the optimal combination of supplementary use cases are then simplified. The actual coverage and use case execution data are collected, and the actual coverage is fed back to the multi-dimensional data to update the training set, thereby realizing iterative optimization of the collaborative model. In the closed-loop control phase of verification completeness, the actual coverage rate is compared with the sixth preset threshold. If the functional coverage rate, code coverage rate, and assertion coverage rate of all modules meet the standards, the verification is considered complete. If there are modules that do not meet the standards, the coverage prediction and test case optimization are performed again. The coverage contribution value of each test case is calculated, redundant test cases with contribution values lower than the seventh preset threshold are removed, and the test case library is updated. The design parameters, test case features, and coverage optimization strategies are stored in the verification knowledge graph, and knowledge reuse is achieved through graph neural networks.
2. The chip verification coverage prediction and use case optimization method according to claim 1, characterized in that: The design parameter data includes chip module type, module complexity, and design requirement priority; the module complexity includes lines of code, number of state machines, and interface protocol version; the test case feature data includes test case type, test case execution duration, test case triggering conditions, and number of functional points / code branches covered by the test case; the test case type includes functional testing, timing testing, and exception injection; the historical coverage data includes functional coverage, code coverage, assertion coverage, and corresponding coverage gap types for each stage of unit verification, integration verification, and system verification; the cross-project knowledge data includes test case design-coverage correlation data from historical chip projects and engineer verification optimization experience data.
3. The chip verification coverage prediction and use case optimization method according to claim 1, characterized in that: The preprocessing includes cleaning and standardizing the collected multi-dimensional data, specifically including: Remove abnormal data, including invalid coverage data caused by test case execution failures and incorrect data for entering design parameters; The Word2Vec model is used to semantically encode unstructured data and transform it into feature vectors; The numerical data is normalized to map the values to the [0,1] interval to adapt to the model input requirements.
4. The chip verification coverage prediction and use case optimization method according to claim 1, characterized in that: The coverage prediction model architecture includes an input layer, a hidden layer, and an output layer. The input layer receives design parameter vectors, current use case feature vectors, and coverage increment data of executed use cases. The hidden layer uses an LSTM network to capture the temporal correlation between use case execution order and coverage changes, and strengthens the feature weights of key modules and high-priority design requirements through an attention mechanism. The output layer outputs the predicted coverage, coverage gap probability, and gap location for each module. The predicted coverage includes functional coverage, code coverage, and assertion coverage.
5. The chip verification coverage prediction and use case optimization method according to claim 1, characterized in that: The architecture of the use case optimization model includes a classification sub-model and an optimization sub-model. The classification sub-model uses a random forest algorithm, takes the coverage gap type and design parameters as input, and outputs the optimal use case type and key features of the use case. The optimization sub-model uses a genetic algorithm, with the maximum coverage improvement and the shortest total execution time of the use cases as dual objective functions, to filter the candidate use cases generated by the classification sub-model and output the optimal combination of use cases.
6. The chip verification coverage prediction and use case optimization method according to claim 5, characterized in that, The training set and validation set are used to train and fine-tune the parameters of the dual models, specifically including: S21. Train the coverage prediction model using the training set, minimize the mean square error between the predicted coverage and the actual coverage using the Adam optimizer, and adjust the number of LSTM network layers and the weight coefficients of the attention mechanism using the validation set. S22. Train the classification sub-model of the use case optimization model using the training set, and optimize the number of decision trees and node splitting threshold of the random forest using the grid search method. S23. Optimize the population size, crossover probability, and mutation probability of the genetic algorithm to achieve the optimal balance between coverage improvement and verification resource consumption.
7. The chip verification coverage prediction and use case optimization method according to claim 1, characterized in that, The simplification of the initial use case set specifically includes: removing redundant use cases that repeatedly cover the same functional point to obtain a simplified initial use case set.
8. The chip verification coverage prediction and use case optimization method according to claim 1, characterized in that, The iterative optimization of the collaborative model specifically includes: after each preset number of verification processes, the collaborative model is retrained using the updated training set to improve its generalization ability.
9. The chip verification coverage prediction and use case optimization method according to claim 1, characterized in that, The knowledge reuse includes: when a new chip project contains functional modules similar to those in a historical project, automatically recommending corresponding optimized use cases and coverage optimization strategies from the historical project.