A training method and a prediction method of a pin connection prediction model, and an electronic device

Abstract

The present application relates to the technical field of industrial automation, and particularly relates to a pin connection prediction model training method, a prediction method and electronic equipment, comprising: obtaining engineering configuration candidate records to construct coarse classification clusters containing device or loop semantic boundaries; obtaining functional block diagram configuration data to extract weakly connected components; merging the coarse classification clusters and the weakly connected components across sources to form training samples that fuse engineering semantics and local topological structures; constructing a pin-level heterogeneous graph with pins as nodes and containing internal connection edges and external connection edges; performing mask training on a graph neural network model in a manner of masking external connection edges and constructing a legal candidate space based on direction and data type constraints. The present application improves the accuracy of pin-level connection prediction and engineering legality by fusing engineering semantics and graph topologies to construct training samples and constructing pin-level internal and external edge heterogeneous graphs.

Description

Technical Field

[0001] This invention relates to the field of industrial automation technology, and in particular to a training method, prediction method, and electronic device for a pin connection prediction model. Background Technology

[0002] In process industries and discrete manufacturing, programmable logic controllers (PLCs) and distributed control systems (DCS) widely adopt Function Block Diagrams (FBDs) conforming to the IEC 61131-3 standard for control logic configuration. As system scale increases, manual configuration becomes inefficient and error-prone, making intelligent assisted configuration a growing trend. Existing link prediction technologies are mainly divided into traditional heuristic methods and general graph neural network methods. Traditional heuristic methods rely solely on graph topological statistical features, lacking explicit modeling of engineering rules such as function block semantics, pin orientation, and data types, leading to recommendations that often violate process logic. While general graph neural network methods can learn node representations, they often treat function blocks as homogeneous nodes, ignoring fine-grained pin-level connections. Furthermore, existing heterogeneous graph methods typically construct training samples based only on connected component segmentation of the graph topology, failing to integrate the semantic boundaries of equipment or loops in engineering configurations, resulting in the logical knowledge of the same physical object being fragmented across multiple samples. In addition, existing technologies suffer from the limitation that model-output connection recommendations cannot directly meet the stringent legality requirements of industrial environments.

[0003] Therefore, there is an urgent need to provide a technical solution to address the above problems. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides a training method, a prediction method, and an electronic device for a pin connection prediction model.

[0005] In a first aspect, the present invention provides a training method for a pin connection prediction model, the technical solution of which is as follows:

[0006] Obtain engineering configuration candidate records, and construct a coarse classification cluster containing device or loop semantic boundaries based on the engineering configuration candidate records;

[0007] Obtain the function block diagram configuration data, and extract weakly connected components based on the connection relationships between function block instances in the function block diagram configuration data;

[0008] The coarse classification cluster and the weakly connected components are cross-source matched and merged to form training samples that integrate engineering semantics and local topological structure.

[0009] A pin-level heterogeneous graph is constructed based on the training samples, wherein the pins of the functional block instance are used as nodes of the pin-level heterogeneous graph, and internal connection edges for propagating the internal context of the instance and external connection edges for expressing the signal flow between instances are constructed. The internal connection edges and the external connection edges together constitute the edge set of the pin-level heterogeneous graph.

[0010] Based on the aforementioned pin-level heterogeneous graph, the graph neural network model is trained by masking the external connection edges, and a valid candidate space is constructed based on the pin orientation and data type constraints to obtain the trained graph neural network model.

[0011] The beneficial effects of the training method for a pin connection prediction model of the present invention are as follows:

[0012] The training method of the pin connection prediction model of the present invention improves the accuracy and engineering legitimacy of pin-level connection prediction by integrating engineering semantics and graph topology construction training samples and constructing a heterogeneous graph of pin-level inner and outer edges.

[0013] Based on the above scheme, the training method of the pin connection prediction model of the present invention can be further improved as follows.

[0014] In one alternative approach, constructing a coarse classification cluster containing device or loop semantic boundaries based on the candidate engineering configuration records includes:

[0015] The name field of the candidate engineering configuration record is separated into the tag body and pin name according to the dot number. The numeric token is extracted from the tag body to determine the main tag marker, and the main tag marker is used as the coarse classification key.

[0016] Semantic feature extraction is performed on the description text and type field of the candidate engineering configuration records to generate record-level semantic tags that include loop tags, equipment action tags, signal tags and system tags;

[0017] Based on the coarse classification key, engineering configuration candidate records with the same major tag are grouped into the same coarse classification cluster, and the record-level semantic tags within the coarse classification cluster are counted to obtain coarse classification clusters with cluster-level type tags.

[0018] Among the above-mentioned optional methods, by extracting the primary tag as a coarse classification key, it is possible to accurately group tags with different names but belonging to the same physical device or circuit. Combined with multi-dimensional semantic tag statistics, it provides accurate engineering functional boundaries for subsequent training samples, avoiding semantic drift caused by relying solely on text similarity clustering.

[0019] In one alternative approach, extracting weakly connected components based on the connection relationships between function block instances in the function block diagram configuration data includes:

[0020] Standardized connection data is generated based on the function block diagram configuration data and the function block specification library. The standardized connection data records the connection relationships between function block instances.

[0021] Using the function block instance name as the disjoint set element, traverse the source end instance and target end instance of each connection in the normalized connection data, and perform the disjoint set union without ignoring the connection direction. Function block instances with direct or indirect connections are grouped into the same weakly connected component to obtain weakly connected components that characterize the topological range of the local function block graph.

[0022] The weakly connected components are expanded into a pin-level graph structure, including:

[0023] Traverse the connections within the weakly connected components, using the combination of the source instance name and pin name as the source pin node, and the combination of the target instance name and pin name as the target pin node. Each pin node is uniquely identified by the combination of the instance name and pin name, and supplemented with functional block type, functional block type description, instance description, and pin description attributes.

[0024] The connection is retained as an external connection edge, which records the source end instance name, source end pin name, target end instance name, target end pin name, and connection line data type obtained from the function block specification library, to form a pin-level graph structure carrying engineering semantic attributes for constructing the pin-level heterogeneous graph.

[0025] In the above-mentioned optional methods, the extraction of weakly connected components by the disjoint-set data structure algorithm ensures the integrity of the local topology, and the instance-level connections are refined and expanded into pin-level graph structures with rich attributes, laying the data foundation for the subsequent construction of high-precision heterogeneous graphs, enabling the model to directly learn the engineering semantics and connection patterns at the pin level.

[0026] In one alternative approach, the step of performing cross-source matching and merging of the coarse classification cluster and the weakly connected components to form training samples that integrate engineering semantics and local topological structure includes:

[0027] Establish an association index between the coarse classification cluster and the weakly connected component based on the actual occurrence relationship of the tag number in the function block diagram configuration data;

[0028] Traverse the candidate records of engineering configurations within the coarse classification cluster, and find the weakly connected component where the candidate record of engineering configuration is located through the association index;

[0029] The candidate engineering configuration records belonging to the same coarse classification cluster are deduplicated and merged with one or more weakly connected components to form training samples with complete engineering semantic boundaries.

[0030] Among the above optional methods, the problem of the same device or loop logic being scattered in multiple locally connected components in real engineering is effectively solved by using the associated index and the set merging mechanism. This ensures the semantic completeness of the training samples and enables the model to learn scattered topological features in a unified semantic context.

[0031] In one alternative approach, the pin-level heterogeneous graph is constructed based on the training samples, wherein the pins of the function block instances are used as nodes of the pin-level heterogeneous graph, and internal connection edges for propagating the internal context of the instances and external connection edges for expressing the signal flow between instances are constructed. The internal connection edges and the external connection edges together constitute the edge set of the pin-level heterogeneous graph, including:

[0032] The pins of the function block instance are used as nodes in the pin-level heterogeneous graph, and the nodes carry the function block type, pin name, data type and direction attribute;

[0033] The connections between different pins within the same functional block instance are constructed as internal connection edges, which are used to propagate context information within the same logical unit in the graph neural network model;

[0034] The actual signal connections between pins of different functional block instances are constructed as the external connection edges, which are used to express the signal flow and data dependencies between functional block instances.

[0035] In the above-mentioned optional methods, pins are explicitly used as graph nodes instead of function blocks, and internal edges and external edges are explicitly distinguished. This enables the model to accurately capture the connection rules at the pin level. At the same time, the internal edges enable the full propagation of the internal logical context of the function blocks, which enhances the discriminative power of the node representation.

[0036] In one alternative approach, the construction rules for the outer connection edges and the inner connection edges include:

[0037] For the external connection edge, based on the connection line data type and signal flow direction, forward and reverse edges carrying data type attributes are constructed so that information can propagate along the signal flow direction and also be transmitted back in reverse to affect the upstream node representation.

[0038] For the internal connection edge, a directed full connection without self-loops is constructed between any two different pin nodes within the same functional block instance, so that any pin in the functional block instance can sense the connection status of other pins in the same instance.

[0039] Among the above optional methods, by constructing positive and negative external edges carrying data type attributes, bidirectional interaction between signal flow and information flow is realized, which improves the model's ability to understand upstream and downstream dependencies; by constructing internal fully connected edges, lossless sharing of information between pins within the functional block is ensured, which strengthens the overall semantic expression at the component level.

[0040] In an alternative approach, the training method further includes a semantic enhancement step, which comprises:

[0041] Tag-level semantic text is generated based on the function block descriptions and pin descriptions in the function block specification library, and then encoded into semantic vectors.

[0042] The semantic vectors and the structural features of the nodes are fused through a gating mechanism and used as input features of the graph neural network model to provide prior engineering knowledge support for long-tail pins and few-sample classes.

[0043] The process of masking the graph neural network model based on the pin-level heterogeneous graph by obscuring external connection edges, and constructing a valid candidate space based on pin orientation and data type constraints to obtain the trained graph neural network model includes:

[0044] Based on the pin-level heterogeneous graph, some of the external connection edges are randomly masked, and the pins at one end of the masked edge are used as query nodes, while the pin type labels at the other end are used as supervision targets.

[0045] Construct a valid candidate space based on the direction and data type of the query node;

[0046] The pin type labels outside the legal candidate space are masked, and the classification loss between the link prediction result of the query node and the supervision target is calculated only within the legal candidate space. The total loss is obtained by combining the semantic contrast loss between the structural representation and the semantic vector. The parameters of the graph neural network model are updated based on the total loss to complete the mask training.

[0047] Among the above-mentioned optional methods, semantic vectors are generated by using prior description text of functional blocks and pins, and the gating mechanism and structural features are adaptively fused to effectively alleviate the overfitting problem caused by the scarcity of long-tail pin samples in industrial scenarios. At the same time, by occluding real connection edges to simulate the scenario of engineers filling in the gaps, the training objective is kept consistent with the actual application, and hard constraints on direction and data type are embedded in the loss calculation process, forcing the model to be optimized within the legal engineering space, which fundamentally ensures the engineering usability of the prediction results.

[0048] Secondly, the present invention provides a pin connection prediction method, which is based on a graph neural network model obtained through mask training. The mask training is based on a pin-level heterogeneous graph. The pin-level heterogeneous graph uses the pins of functional block instances as nodes to construct internal connection edges for propagating the internal context of the instances and external connection edges for expressing the signal flow between instances. The mask training is performed by masking the external connection edges of the pin-level heterogeneous graph and constructing a valid candidate space based on the orientation and data type constraints of the pins. The technical solution of this method is as follows:

[0049] The pin connection prediction method includes:

[0050] In response to the received selected pin and its local context graph, the local context graph is converted into a pin-level heterogeneous graph;

[0051] The candidate connection scores of the selected pins are generated using the graph neural network model.

[0052] The valid candidate space is determined based on the direction and data type constraints of the selected pin, and invalid candidate connection scores are masked.

[0053] Output the target interface type label recommendation result for the selected pin; the target interface type label represents the functional block pin category to which the selected pin should be connected.

[0054] The beneficial effects of the pin connection prediction method of the present invention are as follows:

[0055] The pin connection prediction method of this invention ensures the engineering legitimacy of the prediction results in terms of direction and data type by reusing the pin-level heterogeneous graph construction rules and engineering constraint filtering mechanism consistent with the training phase during the inference phase. It directly provides engineers with pin connection type suggestions that comply with the IEC 61131-3 standard, reduces manual verification costs, and improves the efficiency and reliability of auxiliary configuration.

[0056] Based on the above scheme, the pin connection prediction method of the present invention can be further improved as follows.

[0057] In one alternative approach, converting the local context graph into a pin-level heterogeneous graph includes: establishing node indexes based on pin instances in the local context graph; converting external connection edges in the local context graph into forward and reverse edges carrying data type attributes; and supplementing the internal connection edges for multiple pin nodes that have already appeared within the same functional block instance to form a directed fully connected graph without self-loops.

[0058] The determination of the legal candidate space based on the direction and data type constraints of the selected pins includes: retaining only the output pin labels of the same data type for input pins, and retaining only the input pin labels of the same data type for output pins;

[0059] The step of outputting the target interface type label recommendation result for the selected pin includes: sorting the scores of the legal candidate connections and outputting the Top-K target interface type label recommendation result.

[0060] Among the above optional methods, the graph construction rules and constraint filtering logic of the training phase are strictly reused in the inference phase to ensure lossless transfer of model performance; by outputting Top-K target interface type labels instead of specific instances, the solution is given generalization ability across projects and devices.

[0061] Thirdly, the technical solution of an electronic device according to the present invention is as follows:

[0062] It includes a memory, a processor, and a program stored in the memory and running on the processor, wherein the processor executes the program to implement the steps of a training method for a pin connection prediction model as described in this invention.

[0063] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0064] The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0065] Figure 1 This is a flowchart illustrating an embodiment of a training method for a pin connection prediction model according to the present invention.

[0066] Figure 2 This is a schematic diagram of the overall architecture of the pin-connected prediction model for the offline training and online inference stages of the present invention.

[0067] Figure 3 This is a flowchart illustrating the training set construction process of the present invention.

[0068] Figure 4 This is a schematic diagram of the online inference process for pin connection prediction according to the present invention. Detailed Implementation

[0069] Exemplary embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0070] Example 1:

[0071] Figure 1 This diagram illustrates a flowchart of an embodiment of a training method for a pin connection prediction model provided by the present invention. The training method provided in this embodiment can be applied to the programming configuration software of industrial control systems and executed by a corresponding data processing module or computing device. This training method is used to construct training samples that fuse device semantics and graph topology boundaries in an industrial control function block diagram configuration scenario and train a pin-level connection prediction model, aiming to solve the semantic incompleteness problem caused by local topology fragmentation in existing technologies within industrial control configuration scenarios. Figure 1 As shown, the method mainly includes the following steps:

[0072] Step S100: Obtain engineering configuration candidate records and construct a coarse classification cluster containing device or loop semantic boundaries based on the engineering configuration candidate records.

[0073] Specifically, engineering configuration candidate records typically originate from Piping and Instrumentation Diagram (P&ID) parsing data, point table export files from DCS / PLC systems, or engineering design databases. These records contain rich business attribute information such as tag names, descriptive text, and data types. This step does not directly utilize this raw data for model training; instead, it first performs structured processing and semantic aggregation to construct coarse-grained classification clusters.

[0074] A coarse classification cluster is essentially a semantic set based on engineering business attributes. It groups candidate records belonging to the same physical equipment, the same control loop, or the same process unit together, thus establishing clear engineering semantic boundaries for subsequent data processing. For example, all tag records related to "pressure monitoring of gasifier No. 1068" will be classified into the same coarse classification cluster, regardless of their location on the drawing.

[0075] The technical purpose of this step is to extract high-level business logic units from unstructured or semi-structured engineering documents, making up for the deficiency that relying solely on graph topology cannot understand the meaning of the process.

[0076] Step S200: Obtain function block diagram configuration data, and extract weakly connected components based on the connection relationships between function block instances in the function block diagram configuration data.

[0077] Specifically, function block diagram (FBD) configuration data reflects the actual logical connections within a control system. Due to the complexity of large-scale industrial control systems, a complete control strategy is often distributed across multiple program organization units (POUs) or multiple drawings, resulting in a fragmented diagram structure.

[0078] This step uses graph theory algorithms to identify interconnected subgraph structures, or weakly connected components, within the graph, while ignoring the direction of connections. Each weakly connected component represents a topologically tightly connected local functional block network, objectively recording the actual signal transmission paths between functional block instances. Unlike the coarse classification clusters (semantic clusters) in step S100, weakly connected components are generated purely based on geometric connections and do not include business semantic judgments, but they ensure the integrity of the local topology.

[0079] Step S300: Perform cross-source matching and merging of the coarse classification cluster and the weakly connected components to form training samples that integrate engineering semantics and local topology.

[0080] Specifically, this step is the core of constructing a high-quality training set in this application. In actual engineering, the control logic of the same device or loop is often scattered across multiple disconnected local graphs. If only weakly connected components are used as training samples, the knowledge of the same device will be fragmented; conversely, if only coarse-classified clusters are used as samples, there is a lack of specific graph structure support.

[0081] This step establishes an index mapping between tag numbers and function block instances, associating and merging all weakly connected components belonging to the same coarse classification cluster. The resulting training samples encompass both the complete semantic boundaries of the device or loop and all scattered local topological fragments within that semantic unit. This fusion mechanism enables the model to learn logical connections across multiple drawings within a unified context, effectively solving the semantic fragmentation problem and providing a complete data foundation for subsequent graph learning (the process of training a graph neural network model).

[0082] Step S400: Construct a pin-level heterogeneous graph based on the training samples, wherein the pins of the functional block instances are used as nodes of the pin-level heterogeneous graph, and internal connection edges for propagating the internal context of the instances and external connection edges for expressing the signal flow between instances are constructed. The internal connection edges and the external connection edges together constitute the edge set of the pin-level heterogeneous graph.

[0083] Specifically, this application explicitly de-emphasizes the modeling granularity of the diagram down to the "pin" level, rather than the traditional "function block" level. This is because in the IEC 61131-3 standard, the actual connection occurs between pins, and the function block is merely a container for pins.

[0084] When constructing the edge set, two types of edges are explicitly distinguished: external connection edges correspond to the actual signal connections between pins of different functional block instances, carrying data type and flow information, and are used to express system-level signal flow and data dependencies; internal connection edges are constructed between different pins within the same functional block instance, and are used to propagate context information within the same logical unit in the graph neural network. For example, for a PID functional block, although there is no physical connection between its input and output pins, there is strong logical coupling. Internal connection edges allow the model to perceive this inherent logic within the component. This heterogeneous edge design enables the model to simultaneously capture microscopic component behavior patterns and macroscopic system topology, significantly improving the discriminative power of node representations.

[0085] Step S500: Based on the pin-level heterogeneous graph, the graph neural network model is trained by masking the external connection edges, and a valid candidate space is constructed based on the pin orientation and data type constraints to obtain the trained graph neural network model.

[0086] Specifically, the masking training strategy simulates the actual scenario of an engineer filling in lines during configuration by randomly removing some external connection edges from the graph. The model needs to predict the pin type that should be connected to the other end of the masked edge based on the remaining local context graph.

[0087] More importantly, this step introduces strict engineering constraints during the training phase, constructing a valid candidate space. This space only includes pin type labels that are opposite in orientation and compatible in data type, excluding all physically infeasible or standard-violation connection options. By calculating the loss within the valid candidate space, the model is forced to learn only connection patterns that conform to engineering specifications, avoiding the illusion of "topology reasonable but manufacturing illegal" that often arises in general graph neural networks, fundamentally ensuring the engineering usability of the model's output.

[0088] Through steps S100 to S500, this embodiment establishes a complete training process from engineering semantic parsing, topology fusion, heterogeneous graph representation to constraint awareness. This process not only overcomes the limitations of a single data source but also deeply embeds the hard rules of the industrial field into the training process of the artificial intelligence model, realizing the effective implementation of the technical solution in the vertical field of industrial control.

[0089] To facilitate understanding of the overall process of training in this application, which integrates engineering semantics and graph topological boundaries, constructs pin-level heterogeneous graphs, and applies engineering constraints for mask training, as follows: Figure 2 As shown, Figure 2The overall flow of the offline training and online inference phases of the training method of this application is illustrated. In the offline training phase, the process begins by acquiring candidate engineering configuration records and constructing coarse classification clusters containing device or loop semantic boundaries, while simultaneously acquiring functional block diagram configuration data to extract weakly connected components. Subsequently, the process enters a cross-source matching and merging phase, fusing the coarse classification clusters and weakly connected components to form training samples. Next, based on these training samples, a pin-level heterogeneous graph is constructed, with pins as nodes and containing internal and external connection edges. Finally, the graph neural network model is trained using masking by occluding external connection edges, and model parameters are updated within the legal candidate space constructed based on pin orientation and data type constraints. This corresponds to the overall execution order of steps S100 to S500 in the specific implementation. In the real-time inference phase, in response to the input selected pin and its local context graph, inference is performed using the trained model, and the recommended results are output after legality filtering and sorting. Figure 2 The process shown fully covers the entire implementation method of this application, from data preprocessing to model deployment.

[0090] Example 2:

[0091] In one alternative approach, constructing a coarse classification cluster containing device or loop semantic boundaries based on the candidate engineering configuration records includes:

[0092] Step S101: Separate the name field of the candidate engineering configuration record into the tag body and pin name according to the point number, extract the digital token from the tag body to determine the primary tag marker, and use the primary tag marker as the coarse classification key.

[0093] In this embodiment, the system first reads the set of candidate engineering configuration records. Each record contains at least three fields: Name, Desc, and Type. For the Name field of each record, it is parsed into two parts: the tag number body and the pin name, separated by a dot notation. This parsing method conforms to the general specification for variable naming in the IEC 61131-3 standard, which typically uses the form "tag number.pin".

[0094] Subsequently, a numeric token is extracted from the tag body to determine the primary tag identifier. Specifically, the system identifies the string of numbers following a alphanumeric segment in the tag body. Since the tag body may contain multiple numeric tokens (e.g., prefix numbers and core numbers), the system uses the string of numbers that meets preset conditions (e.g., longest length or conforming to a specific positional pattern) as the primary tag identifier. The preset extraction rule is as follows: identify the string of numbers in the tag body that meets a preset length threshold or is located after an alphanumeric segment as the primary numeric string. Typically, instrument loop numbers or equipment primary tag numbers in engineering configurations are 3 or 4 digits or longer, while the prefix plant or system number is usually 1 to 2 digits. Therefore, the system prioritizes identifying the longest numeric token in the tag body, or the longest numeric string appearing after an alphanumeric segment, as the primary tag identifier. This identifier typically corresponds to the instrument loop number, equipment primary number, or process object identifier.

[0095] For example, for a candidate engineering configuration record named "17_PI_1068.PV", the main tag number obtained after separating it by point number is "17_PI_1068", from which the extracted numeric tokens include "17" and "1068". According to the above extraction rules, the system compares the length and position characteristics of the numeric tokens. Since "1068" has more digits than "17" and "1068" immediately follows the letter fragment "PI", "1068" is determined as the main tag number marker and directly used as the coarse classification key for this record.

[0096] If a clear primary position token cannot be extracted (e.g., there is no number string in the position body that meets the number of positions condition, or multiple number strings have the same length and the primary position cannot be determined from the context), then any number token appearing in the position body can be selected as a supplementary token, or a preset placeholder token (e.g., "UNK") can be used.

[0097] The coarse classification key determined in this way can accurately associate records with different names but belonging to the same physical entity. For example, the three records "17_PI_1068.PV", "17PT_1068C.PV", and "17_PSHHHHH_1068_1.IN", despite their different full names and prefixes, can all be extracted to have the same primary identifier "1068", and therefore will be assigned the same coarse classification key. This mechanism ensures that semantic aggregation is based on definite engineering object identifiers, rather than fuzzy text similarity, thus avoiding the semantic drift problem that is prone to occur in traditional text clustering methods.

[0098] Step S102: Perform semantic feature extraction on the description text and type field of the engineering configuration candidate record to generate record-level semantic tags containing loop tags, equipment action tags, signal tags and system tags.

[0099] In this embodiment, the system performs semantic feature extraction on the descriptive text and type field of candidate engineering configuration records to generate multi-dimensional record-level semantic tags. Specifically, by cleaning and keyword matching the descriptive text, and combining it with the predefined mapping relationship of the type field, four types of semantic tags are generated: loop tags, equipment action tags, signal tags, and system tags. The predefined mapping relationship represents the correspondence between the function block type encoding in industrial control standards and the engineering semantic category it represents.

[0100] For example, when the description text contains keywords such as "pressure", "temperature", and "flow", or when the type field is "PVIEX" or "PIDEX", a loop label is generated;

[0101] When the description text contains keywords such as "valve", "motor", or "pump", or the type field is "VALVE" or "MOTOR", a device action label is generated; when the description text contains keywords such as "alarm", "interlock", "feedback", or "operation", a signal label is generated.

[0102] When the description text contains keywords such as "communication," "system," or "network," a system tag is generated. Additionally, a device token is extracted from the description text to help identify the specific device object.

[0103] Taking the aforementioned "17_PI_1068.PV" as an example, its description is "gasifier pressure (middle of 3)" and its type is "PVIEX," based on which the system generates a loop label. For "17PT_1068C.PV," its description is "gasifier pressure alarm shutdown - from SIS" and its type is "DI," and the system generates both a loop label and a signal label. This fine-grained semantic extraction ensures that each record carries rich engineering attribute information, providing a solid data foundation for subsequent cluster-level classification.

[0104] Step S103: Using the coarse classification key as the grouping basis, engineering configuration candidate records with the same major tag are grouped into the same coarse classification cluster, and the record-level semantic tags within the coarse classification cluster are counted to obtain coarse classification clusters with cluster-level type tags.

[0105] In this embodiment, the system uses the coarse classification key as the grouping basis and groups all engineering configuration candidate records with the same major tag into the same coarse classification cluster.

[0106] After grouping, statistical analysis is performed on the record-level semantic tags, type fields, and device tokens of all records within each coarse-grained cluster to determine the overall engineering attributes of the cluster, i.e., the cluster-level type tags. Specific determination rules include: counting the frequency or percentage of occurrence of system tags, loop tags, signal tags, and device action tags within the cluster.

[0107] If the proportion of system tags reaches a preset threshold, the cluster-level type tag is determined as system_like; if the proportion of loop tags reaches a preset threshold, it is determined as loop_like; if the proportion of signal tags reaches a preset threshold, it is determined as signal_like; if there is a stable and repeating major device token in the cluster and it meets specific conditions, it is determined as device_like; if none of the above conditions are met, it is marked as mixed or unknown.

[0108] For example, for a coarse cluster labeled "1068", since multiple records within it match pressure-related loop labels and the proportion of loop labels exceeds a threshold, the cluster-level type label is determined to be "loop_like". Through this bottom-up statistical aggregation, this embodiment successfully transforms discrete tag records into coarse clusters with clear engineering semantic boundaries. This not only provides accurate functional unit partitioning for the construction of subsequent training samples but also enables the model to perceive the physical entity attribution behind the data, effectively solving the semantic fragmentation problem caused by relying solely on graph topology, and significantly improving the accuracy and interpretability of link prediction in complex industrial scenarios.

[0109] Example 3:

[0110] In one alternative approach, extracting weakly connected components based on the connection relationships between function block instances in the function block diagram configuration data includes:

[0111] Step S201: Generate standardized connection data based on the function block diagram configuration data and the function block specification library. The standardized connection data records the connection relationships between function block instances.

[0112] In this embodiment, the system first reads the cleaned function block diagram configuration data and generates standardized connection data by combining it with the function block specification library. Function block diagram configuration data is typically stored in XML, JSON, or proprietary binary formats, recording the actual wiring relationships drawn in the project. However, its original format often contains a large amount of redundant information or non-standard fields and does not directly contain semantic attributes such as pin data types. Therefore, this step introduces the function block specification library as a priori knowledge source. This specification library defines the standard interface list, pin names, data types, and directions for various function blocks. By consulting the specification library, the system parses the original configuration connections into standardized triples or quadruples, explicitly recording the source instance name, source pin name, target instance name, target pin name, and connection data type.

[0113] For example, for a connection from the output pin OUT of the ADD function block instance add_1 to the input pin SP of the PID function block instance pid_1, the system not only records the connection relationship between instances, but also confirms that the data type of the connection line is REAL by querying the specification library, thereby generating normalized connection data containing complete semantic information. The technical purpose of this step is to eliminate the heterogeneity of the export formats of different configuration software and to provide an accurate data type constraint basis for subsequent graph structure construction.

[0114] Step S202: Using the function block instance name as the disjoint set element, traverse the source end instance and target end instance of each connection in the normalized connection data, and perform a disjoint set union without ignoring the connection direction. Function block instances with direct or indirect connections are grouped into the same weakly connected component to obtain a weakly connected component that represents the topological range of the local function block graph.

[0115] In this embodiment, the system extracts weakly connected components based on normalized connection data using a disjoint-set data structure (DFS) algorithm. Specifically, each functional block instance name is initialized as an independent element in the DFS. Then, all normalized connection records are traversed, and for each connection, its source and target instances are merged within the DFS.

[0116] It is important to emphasize that the merging operation here ignores the connection direction. That is, regardless of whether the signal flows from A to B or from B to A, as long as there is a physical connection between the two, they are considered to belong to the same connected set. This approach is consistent with the characteristics of industrial control logic, because in a complete control loop or device drive logic, signal flows are often bidirectionally intertwined (such as feedforward and feedback coexisting). Ignoring direction ensures that all topologically related functional blocks are completely contained within the same local area, avoiding the omission of reverse-dependent components due to unidirectional search.

[0117] After traversal and merging, each independent set in the disjoint-set data structure corresponds to a weakly connected component. This component represents a topologically tightly coupled local functional block graph region, providing a complete topological boundary for subsequent sample construction.

[0118] Step S203: Expand the weakly connected components into a pin-level graph structure.

[0119] Specifically, the system further expands the instance-level weakly connected components into a pin-level graph structure. This is a key preliminary step that distinguishes this application from traditional graph modeling methods that use functional blocks as nodes.

[0120] In this embodiment, all normalized connections within the weakly connected components are traversed. For each connection, a corresponding pin node is created using the combination of the source instance name and pin name, and the combination of the target instance name and pin name, respectively, as unique identifiers. For example, the node identifier can be represented as (inst=add_1, pin=OUT) and (inst=pid_1, pin=SP). Based on this, the system also supplements rich node attributes from the function block specification library and configuration data, including function block type, function block type description, instance description, and pin description. These attributes make each node not only a topology point but also an entity carrying complete engineering semantics. Simultaneously, the original connection relationships are preserved as external connection edges, with the edge attributes explicitly recording the source instance name, source pin name, target instance name, target pin name, and the data type of the connection line obtained from the function block specification library. For example, the linetype field of the aforementioned connection edge from add_1.OUT to pid_1.SP will be marked as REAL. At this point, the system obtains the pin-level graph structure corresponding to each weakly connected component. This structure contains a complete set of pin nodes and a set of external connection edges, providing a data foundation for the subsequent construction of a complete pin-level heterogeneous graph.

[0121] Through this unfolding mechanism, the originally coarse-grained instance-level topology is refined into a pin-level graph structure, which not only preserves the macroscopic connection relationships between components but also explicitly expresses the independent roles and attributes of different pins within a component. This data structure directly forms the input basis for subsequent construction of pin-level heterogeneous graphs, enabling the model to learn the connection rules of industrial control logic at the finest granularity, effectively solving the semantic confusion problem caused by the multi-pin characteristics of functional blocks.

[0122] It should be noted that the "weakly connected components" in this embodiment do not refer only to the instance-level connected set, but rather to the complete topology including all functional block instances, their pin nodes, and external connection edges within that set. Therefore, this step of expanding the instance-level weakly connected components into a pin-level graph structure is an integral part of the step of extracting weakly connected components. Furthermore, this step yields a pin-level graph structure containing only external connection edges; subsequent steps require the addition of internal connection edges to form a complete pin-level heterogeneous graph. This process will be described in detail in subsequent embodiment 5.

[0123] Example 4:

[0124] This embodiment details how to perform cross-source matching and merging of coarse classification clusters and weakly connected components to form training samples that integrate engineering semantics and local topology. "Cross-source" refers to cross-associating coarse classification clusters from engineering configuration candidate records (semantic source) with weakly connected components from function block diagram configuration data (topology source). "Matching" refers to establishing a mapping relationship between the two through tag numbers. "Merging" refers to deduplicating and merging multiple matched weakly connected components.

[0125] Specifically, in the actual engineering design of industrial control systems, due to reasons such as drawing pagination, modular design, or system layering, the logic belonging to the same physical device or the same control loop is often not drawn completely on the same functional block diagram, but is scattered across multiple program organization units or multiple pages of drawings. This results in the control logic of the same device being cut into multiple unconnected subgraphs when extracting weakly connected components based solely on the graph topology. If these isolated weakly connected components are directly used as training samples for the model, the model will be unable to learn the complete device behavior patterns across the drawing boundaries, causing severe semantic fragmentation. This embodiment solves this technical problem through a cross-source matching and merging mechanism, re-aggregating the discrete topological fragments under a unified engineering semantic boundary.

[0126] Figure 3 The detailed process of constructing the training set is illustrated in the illustration. Figure 3 As shown, the system first reads the engineering configuration to obtain tag records, constructs a coarse classification key for each tag record, and generates semantic labels and device tokens to form coarse classification clusters and generate cluster-level type labels. At the same time, it reads the function block graph (FBD) configuration data and extracts weakly connected components based on the connection relationships between function block (FB) instances. Then, it generates cross-source matching keys, performs matching between coarse classification clusters and weakly connected components, and forms device or loop connected component clusters after union set and closure expansion. Finally, it supplements node, edge, semantic and constraint attributes and outputs the training sample set. Figure 3The process shown corresponds to the specific implementation of coarse cluster construction, weak connected component extraction and cross-source matching and merging described in embodiments 2 to 4 of this application.

[0127] In one alternative approach, the coarse classification cluster and the weakly connected components are cross-source matched and merged to form training samples that integrate engineering semantics and local topological structure, including:

[0128] Step S301: Establish an association index between the coarse classification cluster and the weakly connected component based on the actual occurrence relationship of the tag number in the function block diagram configuration data.

[0129] In this embodiment, the first step is to establish an association index between tag numbers and weakly connected components. Since each weakly connected component already contains a specific function block instance name and its pin information when extracted in Embodiment 3, and function block instance names typically follow specific naming conventions and implicitly include tag number identifiers, or have explicit tag number binding fields in the configuration data, the system can traverse all extracted weakly connected components, parse the tag numbers corresponding to the function block instances they contain, and thus construct a reverse mapping table from "tag number" to "weakly connected component identifier (such as UUID)". This index table records which local topology each tag number actually appearing in the function block diagram configuration data belongs to. It should be understood that since a tag number may be referenced in multiple function block instances (e.g., read as an input signal by multiple logic blocks), this index relationship is essentially a one-to-many mapping.

[0130] Step S302: Traverse the candidate records of engineering configurations within the coarse classification cluster, and find the weakly connected component where the candidate record of engineering configuration is located through the association index.

[0131] In this embodiment, after the association index is constructed, the system uses the coarse classification clusters generated in Embodiment 2 as processing units to perform cross-source matching. For each coarse classification cluster, all engineering configuration candidate records contained within it are traversed, the corresponding tag number for each record is extracted, and the weak connected component where the tag number is located is found through the aforementioned association index. During this process, three situations may occur: First, all tag numbers in the cluster point to the same weak connected component, indicating that the logic of the device is topologically continuous in the current dataset; second, different tag numbers in the cluster point to multiple different weak connected components, which is the logic dispersion scenario that this application focuses on solving; third, some tag numbers do not have a corresponding connection relationship in the current functional block diagram configuration data (i.e., they do not appear in any weak connected component). These tag numbers usually only exist in the point table or P&ID and do not participate in the actual control logic configuration. They can be ignored or only used for semantic supplementation when constructing graph training samples.

[0132] Step S303: Deduplicatize and merge one or more weakly connected components associated with candidate engineering configuration records belonging to the same coarse classification cluster, so that scattered local topology fragments share the same device or loop semantics, forming training samples with complete engineering semantic boundaries.

[0133] In this embodiment, for the matched results, the system performs deduplication and set union operations. Specifically, it collects the weakly connected components associated with all engineering configuration candidate records within the same coarse classification cluster into a set, removes duplicate component identifiers, and finally forms a topology set composed of one or more weakly connected components. This set serves as the graph structure part of the training samples corresponding to the coarse classification cluster, and together with the semantic labels of the coarse classification cluster itself, constitutes a complete training sample.

[0134] By using set union, multiple local fragments that were originally isolated from each other in physical storage or graph topology are logically organized into the same sample container. In subsequent model training, although these connected components may not have direct edges between them, they share the same set of device-level or loop-level semantic context, enabling the model to learn the feature representations of these scattered fragments simultaneously in a unified semantic space.

[0135] To illustrate the above process more intuitively, a specific engineering application example is used below. Suppose that in the configuration data of an ethylene unit in a chemical plant, there exists a coarse cluster identified as "device / 1501". This cluster is aggregated based on the major tag "1501" and contains multiple engineering configuration candidate records, including "SIC_A1501A" (coal mill frequency regulation), "HIC_X1501A_A2" (hopper frequency setting), "A_1501A_SC.BKOUT" (coal mill variable frequency motor frequency regulation output), and "X_1501A_A2.BKOUT" (setting hopper frequency output). These records collectively describe the frequency control and status feedback logic of device 1501 and its related auxiliary equipment.

[0136] However, these logics are not drawn on the same diagram in the function block diagram configuration data. After processing in Example 3, the system extracted two independent weakly connected components: the first connected component (denoted as C1, corresponding to cc_000197) contains REAL and BOOL type connections between the "A_1501A_SC" instance and the "SIC_A1501A" instance, mainly expressing the frequency regulation and feedback closed loop of the coal mill body; the second connected component (denoted as C2, corresponding to cc_000211) contains the connection between the "X_1501A_A2" instance and the "HIC_X1501A_A2" instance, mainly expressing the frequency setting logic of the upstream hopper. From a pure topology perspective, there are no connections between C1 and C2, and they are two completely isolated subgraphs.

[0137] Applying the cross-source matching method of this embodiment, the system traverses the records within the "device / 1501" cluster. Through indexing, it discovers that "SIC_A1501A" and "A_1501A_SC" are located in C1, while "HIC_X1501A_A2" and "X_1501A_A2" are located in C2. Subsequently, the system performs a union of C1 and C2 to generate a new training sample. The structured representation of this sample is: {semantic boundary: device / 1501, topological set: [C1, C2], cluster-level label: loop_like}. In this way, although C1 and C2 are geometrically disconnected, they are treated as components of the same semantic whole during training. When the model performs a mask prediction task on this sample, even if only an edge in C1 is masked, the model can still perceive that the sample contains the hopper setting logic in C2 through the shared semantic embedding, thus obtaining richer contextual information than a single connected component. This approach effectively overcomes the knowledge fragmentation caused by drawing segmentation in traditional methods, and significantly improves the link prediction model's ability to understand complex industrial control logic and its generalization performance.

[0138] Example 5:

[0139] In one alternative approach, the pin-level heterogeneous graph is constructed based on the training samples, wherein the pins of the function block instances are used as nodes of the pin-level heterogeneous graph, and internal connection edges for propagating the internal context of the instances and external connection edges for expressing the signal flow between instances are constructed. The internal connection edges and the external connection edges together constitute the edge set of the pin-level heterogeneous graph, including:

[0140] Step S401: The pins of the function block instance are used as nodes of the pin-level heterogeneous graph, and the nodes carry the function block type, pin name, data type and direction attribute.

[0141] In this embodiment, the system explicitly establishes the pins of the function block instance as the unique node granularity of the pin-level heterogeneous graph, and assigns multi-dimensional engineering attributes to each node. The reason for this modeling decision is that, according to the IEC 61131-3 standard and industrial control engineering practices, the actual connection relationships in the function block diagram (FBD) occur between pins, rather than between function blocks as a whole.

[0142] A function block instance typically contains multiple input pins, output pins, and even bidirectional pins, which play distinct roles in the control logic. Using only function block instances as graph nodes would fail to distinguish the semantic differences between different interfaces within the same instance, leading to overly coarse-grained connection predictions and potential ambiguity. Therefore, this embodiment uses a combination of "instance name + pin name" as the unique key value for nodes. For example, a node can be represented as (inst=add_1, pin=OUT) or (inst=pid_1, pin=SP). In addition, each node carries four key attributes: function block type (fb_type) indicates the function block category to which the pin belongs, such as PID, ADD, MOTOR, etc.; pin name (pin_name) identifies the specific name of the interface in the function block definition; data type (data_type) records the format of the signal transmitted by the pin, such as REAL, BOOL, DINT, etc.; and direction indicates whether the pin is input, output, or bidirectional. These attributes together constitute the static feature vector of the node, enabling the graph neural network model to accurately identify the identity and functional constraints of each node in the control system, providing fine-grained discrimination criteria for subsequent link prediction.

[0143] Step S402: The connection between different pins within the same functional block instance is constructed as the internal connection edge, which is used to propagate context information within the same logical unit in the graph neural network model.

[0144] In this embodiment, the system constructs internal connection edges for different pin nodes within the same functional block instance. The core function of internal connection edges is to propagate context information within the same logical unit in the graph neural network model.

[0145] In industrial control logic, although the pins of the same functional block instance may not be physically connected, they are tightly coupled in terms of algorithmic logic. For example, for a PID control functional block, there is a defined control algorithm relationship between its process variable input pin (PV) and manipulated variable output pin (MV); for a motor drive functional block, there is a causal relationship between its start command input pin and running status feedback output pin. If the model can only observe the external connections and cannot perceive these internal relationships, it will be difficult to understand component-level behavioral patterns such as "how MV should respond when PV changes".

[0146] By constructing internal connecting edges, the system explicitly links all pin nodes within the same instance in the graph structure, forming tight subgraph clusters. This allows message passing mechanisms to flow freely within instances, enabling any pin node to aggregate state information from other pins within the same instance. For example, when a model attempts to predict the connection target of an output pin, it can "see" what signals are already connected to the instance's input pins through internal connecting edges, thus inferring the functional role that output pin should play in the current context. This design effectively compensates for the loss of internal component semantics when relying solely on external topology, significantly enhancing the richness and discriminative power of node representations.

[0147] Step S403: Construct the actual signal connections between the pins of different functional block instances as the external connection edges, which are used to express the signal flow and data dependencies between functional block instances.

[0148] In this embodiment, the system constructs external connection edges for the actual signal connections between pins of different functional block instances. These external connection edges are directly derived from the connection records extracted and normalized from the functional block diagram configuration data in Embodiment 3. Essentially, they are a digital representation of the actual signal transmission paths existing in the industrial control system. Each external connection edge precisely connects a specific output pin of a source instance to a specific input pin of a target instance and carries the data type information of the connection line. Unlike internal connection edges, external connection edges cross the boundaries of functional blocks, carrying system-level signal flow and data dependencies. They are the primary object of the link prediction task and the core carrier for model learning control strategies and process logic. For example, an external connection edge connecting the output pin of a temperature transmitter to the input pin of a PID controller not only expresses the data flow between the two devices but also implicitly implies the engineering semantics of "temperature measurement as a control loop feedback signal." By explicitly preserving these actual connections in the diagram and combining them with the aforementioned internal connection edges, the pin-level heterogeneous diagram constructed in this embodiment possesses both microscopic component cohesion and macroscopic system connectivity.

[0149] Through steps S401 to S403 described above, this embodiment establishes a dedicated graph structure construction paradigm that differs from traditional general graph models. This paradigm addresses the semantic ambiguity caused by treating functional blocks as homogeneous nodes in existing technologies by lowering the modeling granularity to the pin level and explicitly distinguishing between internal logical connections and external signal transmission edges. This refined graph structure design enables the graph neural network model not only to learn the signal flow patterns across components but also to deeply understand the internal behavioral logic of components, thus laying a solid structural foundation for high-precision, engineering-compliant link prediction.

[0150] It should be understood that although this embodiment describes a specific combination of node attributes and edge type classification, in other embodiments, depending on the specific application scenario requirements, node attributes can be extended to include more information such as pin description text and range. The edge construction rules can also be adaptively adjusted according to the definition of the function block specification library. As long as the core idea of ​​pin-level modeling and distinguishing between inner and outer edges is maintained, they should all be covered within the protection scope of this application.

[0151] Example 6:

[0152] In one alternative approach, the construction rules for the outer connection edges and the inner connection edges include:

[0153] For the external connection edge, based on the connection line data type and signal flow direction, forward and reverse edges carrying data type attributes are constructed so that information can propagate along the signal flow direction and also be transmitted back in reverse to affect the upstream node representation.

[0154] In this embodiment, when constructing external connection edges, the system explicitly constructs a pair of forward and reverse edges carrying data type attributes based on the data type and signal flow direction of the connection line. Specifically, for each original connection from the source output pin to the target input pin, if its connection line data type is a specific type (e.g., REAL, BOOL, or DINT), two directed edges are generated simultaneously in the pin-level heterogeneous graph: one is a forward edge "datatype_to" along the original signal flow direction (e.g., REAL_to), used to express the forward transmission and dependency of data from upstream to downstream; the other is a reverse edge "datatype_from" (e.g., REAL_from) opposite to the original signal flow direction, used to support the reverse backhaul of information from downstream to upstream.

[0155] The core technology behind this bidirectional edge design is to adapt to the bidirectional interaction characteristics prevalent in industrial control logic. In actual control loops, the state of downstream nodes (such as the saturation state of actuators, abnormal flags of feedback signals, etc.) often needs to be perceived by the upstream controller in order to perform anti-integral saturation processing or mode switching. If only unidirectional edges are constructed, the message passing mechanism of graph neural networks will be unable to capture this inverse dependency, resulting in the upstream node's representation learning lacking crucial downstream context. By establishing independent forward and reverse edge types for each non-unknown data type, the model can not only distinguish different signal semantics (such as distinguishing between analog control flow and digital interlocking flow), but also simultaneously complete the joint learning of forward inference and backward state perception within the same graph structure, significantly improving the model's ability to understand complex closed-loop control strategies.

[0156] For the internal connection edge, a directed full connection without self-loops is constructed between any two different pin nodes within the same functional block instance, so that any pin in the functional block instance can sense the connection status of other pins in the same instance.

[0157] In this embodiment, when constructing internal connection edges, the system executes a directed fully connected edge construction strategy without self-loops for all pin nodes within the same functional block instance. Specifically, for any functional block instance, if it contains n pin nodes (n≥2) in the current context, then directed edges with mutually dissimilar directions are constructed between each pair of these n nodes; that is, for any two different pin nodes p... i and p j , thus constructing from p i Point to p j The edge is also constructed from p j Point to p i The nodes are connected to each other, but no self-loop edges are constructed from nodes to themselves. According to the principle of permutations and combinations, n×(n-1) internal connecting edges will be generated in this instance.

[0158] To illustrate this rule more intuitively, let's take a standard adder function block (ADD) as an example. Assume this instance activates three pin nodes in the current local graph: the first input pin IN1, the second input pin IN2, and the output pin OUT. According to the rule above, the system will automatically generate six internal connection edges: IN1→IN2, IN1→OUT, IN2→IN1, IN2→OUT, OUT→IN1, and OUT→IN2. The technical significance of this fully connected mode is that it transforms the function block from a loosely set of pins into a tightly coupled semantic whole.

[0159] It's important to note that in industrial control logic, while pins within the same functional block may not be physically connected, they are strongly correlated in the algorithmic logic. For example, the value of the output pin OUT is entirely determined by IN1 and IN2, and the connection state of IN1 may implicitly predict the value of IN2 (as in differential computing scenarios). Through internal fully connected edges, graph neural networks can directly receive feature information from all other pins within the same instance when performing message aggregation. This means that when the model attempts to predict the connection target of an output pin, it can not only see the pin's own attributes but also perceive what types of signals the input pins of the functional block are connected to through internal edges, thereby inferring the current operating state of the functional block. This mechanism effectively compensates for the loss of internal component logic context when relying solely on external topology, enabling the model to more accurately understand the role of pins in component-level behavior patterns, thus improving the accuracy and robustness of link prediction.

[0160] Example 7:

[0161] In this embodiment, the semantic enhancement mechanism and the mask training process are described in detail.

[0162] The training method further includes a semantic enhancement step, which includes:

[0163] Tag-level semantic text is generated based on the function block descriptions and pin descriptions in the function block specification library, and then encoded into semantic vectors.

[0164] In this embodiment, the system generates tag-level semantic text based on the function block specification library. The function block specification library is the authoritative data source for defining standard function block interfaces in industrial control systems, containing rich natural language information such as function block descriptions (FB_desc) and pin descriptions (PIN_desc). To transform these unstructured engineering documents into a semantic representation that the model can compute, this embodiment designs a structured semantic text template. This template assembles discrete description fields into coherent natural language sentences, such as: "Function block type is {fb_type}, function block description is {FB_desc}, current pin name is {pin}, this is an {input / output pin}, data type is {datatype}. Pin function description: {PIN_desc}." Through this template-based generation method, each target interface type tag (i.e., FBType.PIN) is assigned a semantic text containing complete contextual information.

[0165] Subsequently, the system uses a pre-trained text encoder to batch encode these semantic texts, obtaining fixed-dimensional normalized semantic vectors. In practical deployments, to ensure computational efficiency and result consistency, a caching fingerprint mechanism is typically introduced, allowing the reuse of encoded vectors when the model version, template content, and text content remain unchanged. The technical purpose of this step is to explicitly transform the prior knowledge gained by human engineers reading the instruction manual into semantic embeddings in a mathematical space, laying the data foundation for subsequent feature fusion.

[0166] Furthermore, the semantic vectors and the structural features of the nodes are fused through a gating mechanism and used as input features for the graph neural network model, providing prior engineering knowledge support for long-tail pins and few-sample categories.

[0167] In this embodiment, the system adaptively fuses semantic vectors and node structural features using a gating mechanism. In the graph neural network model, the initial structural features h of the node... struct Typically, it is obtained by concatenating embedded vectors of four discrete attributes—function block type, pin name, data type, and direction—and then performing a linear transformation. This reflects the node's identity within the graph topology. The semantic vector generated in the preceding steps is then processed by a projection layer to obtain h. sem It carries the functional semantics from the engineering documents.

[0168] To enable the model to dynamically adjust its dependence on these two types of features based on the richness of the sample, this embodiment introduces a gated fusion mechanism. The specific calculation formula is as follows:

[0169] ;

[0170] ;

[0171] in, This represents a gating signal with a value range between 0 and 1, used to determine the fusion ratio of structural features and semantic features; This represents the activation function, preferably the Sigmoid function, used to map the linear output to a probability interval; This represents a learnable weight matrix used to extract gating decision criteria from the concatenated joint features; This indicates that the structural feature vector h struct With semantic feature vector h sem The concatenation operation is performed along the dimension; h represents the final hidden layer representation after fusion, which serves as the input to subsequent layers of the graph neural network. This indicates an element-wise multiplication operation.

[0172] It should be noted that the core technical advantage of this gating mechanism lies in its ability to adaptively adjust feature weights. For common pins that frequently appear in the training set, the model can learn robust structural representations from a large number of topological connections, at which point the gating signal... The tendency is to approach 1, making the final representation h primarily composed of h. struct Dominant, making full use of statistical regularities; however, for long-tail pins with scarce training samples or newly introduced functional block types, due to the lack of sufficient topological neighbor information, h struct The gating signal is often inaccurate or difficult to converge, at which point... It will automatically reduce and increase the semantic feature h. sem The weights are determined by the number of pins. This means that even if a pin has never appeared in historical configuration data, as long as its functional block description and pin description are similar to those of known pins in the semantic space, the model can obtain an effective prior representation through semantic vectors, thus possessing a certain degree of zero-shot or few-shot generalization ability. This design fundamentally solves the problem of the sharp performance decline of pure data-driven methods in industrial long-tail scenarios, seamlessly embedding expert knowledge from the engineering field into the representation learning process of deep learning models.

[0173] Following the semantic enhancement step, the specific process of the masking training step is described in detail. The step of masking the graph neural network model based on the pin-level heterogeneous graph by masking external connection edges, and constructing a valid candidate space based on pin orientation and data type constraints to obtain the trained graph neural network model, includes:

[0174] Step S501: Based on the pin-level heterogeneous diagram, randomly mask part of the external connection edge, and use the pin at one end of the masked edge as the query node and the pin type label at the other end as the supervision target.

[0175] In this embodiment, the system executes a random occlusion strategy for external connection edges based on the aforementioned constructed pin-level heterogeneous graph to simulate the wiring scenarios faced by engineers during actual configuration. Specifically, for each connected component used as a training sample, the system first collects all real external connection edges within it. During each training iteration, a ratio value r is uniformly sampled from a preset occlusion ratio range (e.g., [0.15, 0.20]), and the number of edges k to be occluded in this iteration is calculated based on the total number M of external connections in the sample. Subsequently, k external connections are randomly selected without replacement from the M external connections as the occluded edges for this iteration.

[0176] Since forward edges (datatype_to) and reverse edges (datatype_from) carrying data type attributes were constructed in Example 6, when performing the shading operation, both forward and reverse directed edges corresponding to the same physical connection must be removed from the graph structure simultaneously, while the node itself and its internal connection edges are preserved. The technical purpose of this synchronous removal mechanism is to prevent data leakage and ensure that the model cannot infer the shading forward connection through the remaining reverse edges, thereby forcing the model to truly learn the link prediction capability based on local context and node attributes, rather than the memory graph's topology.

[0177] For each occluded original connection, the system generates prediction tasks in two directions: when the source pin is the query node, the type label of the target pin serves as the supervision target; when the target pin is the query node, the type label of the source pin serves as the supervision target. This bidirectional construction method allows a single occluded sample to generate twice the number of training signals, effectively improving data utilization efficiency and enabling the model to simultaneously learn the bidirectional dependency relationship of upstream driving downstream and downstream feeding back upstream. It should be noted that the target interface type label (FBType.PIN) represents the combination of the pin's functional block category and interface name, such as "MANUAL.BKIN" or "PIDEX.MV". Furthermore, "original connection" refers to the actual physical connection without image quantization conversion, i.e., an external connection edge corresponding to the aforementioned occluded edge.

[0178] Step S502: Construct a valid candidate space based on the direction and data type of the query node.

[0179] In this embodiment, the system constructs a valid candidate space based on the direction and data type of the query pin. First, it identifies the port direction (input or output) and data type (e.g., REAL, BOOL, DINT) of the query pin as defined in the function block specification library. According to the hard constraints of industrial control logic (i.e., the basic specifications of function block diagram connections in the IEC 61131-3 standard), input pins are only allowed to connect to output pins, and output pins are only allowed to connect to input pins; furthermore, the signal data types of both connected pins must be strictly consistent. Based on these two constraints, the system dynamically filters all candidate label sets that satisfy "opposite directions and consistent data types" from the global target interface type label space, based on the direction and data type of the query pin, as the valid candidate space corresponding to that query pin.

[0180] Specifically, if the query node is an input pin, the valid candidate space only includes output pin labels with the same data type; if the query node is an output pin, the valid candidate space only includes input pin labels with the same data type. For example, when the query node is a BOOL type input pin, all output pin labels with the BOOL data type in the system (such as DI.PV, MOTOR.RUNSTA, etc.) are included in the valid candidate space, while REAL type output pin labels (such as ADD.OUT, AI.OUT) and all input pin labels are excluded. Through this dual-constraint filtering mechanism, the valid candidate space ensures that the recommended results output by the model are feasible in engineering and will not produce illegal connections at the physical level, such as "temperature signal directly connected to valve opening" or "analog signal connected to digital input".

[0181] Step S503: Apply masking to pin type labels outside the legal candidate space, calculate the classification loss between the link prediction result of the query node and the supervision target only within the legal candidate space, and obtain the total loss by combining the semantic contrast loss between the structural representation and the semantic vector. Update the parameters of the graph neural network model based on the total loss to complete the mask training.

[0182] In this embodiment, the system first masks pin type labels outside the legal candidate space. Specifically, when calculating the predicted scores (logits) output by the model, all label scores outside the legal candidate space are set to a minimum value (e.g., negative infinity), so that the probability distribution after Softmax normalization is concentrated only on legal engineering connection options. This mechanism ensures that gradient updates are driven only by prediction errors that conform to the process logic, avoiding invalid exploration of the model in the illegal solution space, and significantly improving training efficiency and model engineering usability. This is one of the key features that distinguishes this application from general graph neural network link prediction methods.

[0183] Subsequently, the system calculates the classification loss only within the valid candidate space and combines it with the semantic contrast loss to obtain the total loss, updating the model parameters based on the total loss. The total loss function is defined as:

[0184] ;

[0185] Where L represents the total loss value; L ce The classification loss is calculated as the cross-entropy loss between the predicted probability distribution of the query node and the supervised target label within the legal candidate space constructed in step S502; L ctrThis represents semantic contrast loss, used to bring the structural representation of a query node closer to its semantic vector with the correct label, while widening the distance between it and the semantic vectors of incorrect labels and hard negatives. This represents the balance coefficient, used to adjust the weight ratio of the two types of losses.

[0186] In this loss function design, the classification loss L ce This ensures the model's prediction accuracy within the legal space, while the semantic contrast loss L... ctr This further strengthens the alignment between structural features and prior semantic knowledge.

[0187] Specifically, the semantic contrastive loss introduces textual semantic vectors from the function block specification library as anchors, enabling the model to distinguish between different semantically similar but semantically different scenarios (e.g., both inputs are REAL type, but one is a temperature measurement and the other is a pressure setpoint). Furthermore, by introducing hard negative samples (i.e., labels that score highly in the legitimate candidate space but are not the correct answer), the contrastive loss effectively improves the model's ability to discriminate fine-grained engineering semantics. By minimizing this total loss L, the parameters of the graph neural network model are continuously updated and optimized, ultimately resulting in a recommendation model that possesses both high-precision link prediction capabilities and internalizes strict engineering constraints. Additionally, the structural representation of the query node is the node structure feature vector output by the graph neural network after convolutional aggregation.

[0188] It should be understood that the above-mentioned occlusion ratio range, loss weight coefficient, and temperature parameter in the contrast loss are all preferred implementation methods. In practical applications, they can be adaptively adjusted according to the specific dataset size and convergence situation. As long as the core ideas of "constraints in advance" and "structure-semantic joint optimization" are maintained, they should all be covered within the protection scope of this application.

[0189] Example 8:

[0190] In this embodiment, the specific process of online inference and result output is described in detail.

[0191] This invention provides a pin connection prediction method for recommending target connection types that meet engineering constraints for selected pins during industrial control function block diagram configuration. The prediction method is based on a graph neural network model obtained through mask training. The mask training is performed on a pin-level heterogeneous graph. The pin-level heterogeneous graph uses pins of function block instances as nodes, constructing internal connection edges for propagating the internal context of instances and external connection edges for expressing signal flow between instances. Mask training is performed by masking the external connection edges of the pin-level heterogeneous graph and constructing a valid candidate space based on pin orientation and data type constraints.

[0192] It should be noted that during the training phase (see Example 7), the system performs masked training based on a pin-level heterogeneous graph. This graph uses the pins of functional block instances as nodes, constructing internal connection edges for propagating the internal context of instances and external connection edges for expressing signal flow between instances. A valid candidate space is constructed by masking the external connection edges and based on pin orientation and data type constraints, ultimately training the graph neural network model. During the inference phase, the system directly reuses the graph neural network model parameters and the constraint logic of the valid candidate space obtained during the training phase, ensuring complete consistency between the constraint mechanisms of training and inference, forming a closed loop for ensuring engineering validity.

[0193] The pin connection prediction method includes:

[0194] Step A100: In response to the received selected pin and its local context graph, the local context graph is converted into a pin-level heterogeneous graph.

[0195] In this embodiment, the system receives the user-selected pin and its local context graph as inference input. In actual engineering configuration software interaction scenarios, when an engineer selects a pin to be connected and requests recommendations, the upstream engineering logic module automatically extracts the local topology around the pin as context. Typically, the scope of this local context graph is set to the weakly connected components of the functional block instance to which the selected pin belongs, or a subgraph extending outward from the selected pin with a preset number of hops (e.g., 3 hops), to balance computational efficiency and the integrity of context information.

[0196] The system converts the local context graph into a pin-level heterogeneous graph tensor representation that is completely consistent with the training phase. This conversion process strictly reuses the graph construction rules of the training phase: establishing node indices based on pin instances in the local context graph; converting external connection edges in the local context graph into forward and reverse edges carrying data type attributes; and supplementing the internal connection edges for multiple pin nodes that have appeared within the same functional block instance to form directed fully connected nodes without self-loops.

[0197] It is important to note that the selected pin itself must exist as a node in the input context graph, even if the pin has not yet established any external connections. It must be included in the graph structure as an isolated node or a node containing only internal edges; otherwise, the model will not be able to generate a representation vector for that node. If a function block type or pin not defined in the specification library is encountered during inference, and the unknown node is not the selected pin itself, the system can mark it as an unknown type node to participate in graph computation. However, it should be noted that the context information provided by such nodes may be limited. If the selected pin itself cannot resolve to a valid data type or direction attribute, the system will skip this recommendation and return a corresponding prompt because it cannot construct a subsequent valid candidate space, ensuring the rigor of the recommendation process.

[0198] Step A200: Generate candidate connection scores for the selected pins using the graph neural network model.

[0199] In this embodiment, the system inputs the constructed heterogeneous graph tensor into the trained graph neural network model, performs forward propagation calculations, and generates raw candidate connection scores for the selected pins corresponding to all predefined target interface type labels. These raw scores (Logits) reflect the model's initial preference for each candidate type based on the learned graph structure patterns and semantic features without any engineering constraints. However, since industrial control logic follows strict IEC 61131-3 standards and process specifications, not all statistically relevant connections are engineering-compliant. Therefore, the raw candidate connection scores cannot be directly used as a recommendation basis and must undergo constraint filtering in subsequent steps.

[0200] Step A300: Determine the valid candidate space based on the orientation and data type constraints of the selected pin, and apply a mask to invalid candidate connection scores.

[0201] In this embodiment, the system dynamically determines the legal candidate space based on the direction and data type attributes of the selected pin, and applies a mask to the candidate connection scores that are not in this space. This step is a precise reuse of the mask training constraint mechanism in Embodiment 7 during the inference stage, forming a key closed loop to ensure the engineering legality of the recommendation results.

[0202] Specifically, the system first reads the metadata of the selected pin to determine whether it is an input or output pin and obtains its data type (such as REAL, BOOL, DINT, etc.). Then, it filters the set of valid candidate tags according to preset engineering connection rules: input pins retain only output pin tags of the same data type, and output pins retain only input pin tags of the same data type. For example, when the selected pin is an output pin of data type REAL, all input pins of data type BOOL and output pins of data type REAL are considered invalid candidates; only input pin tags of data type REAL are retained in the valid candidate space.

[0203] Next, the system sets the values ​​corresponding to illegal candidate labels in the original candidate connection scores to a minimum value (such as negative infinity), so that after Softmax normalization, the probability of these illegal options approaches zero. This hard constraint masking mechanism ensures that the final output recommendation results will never contain options with incorrect direction or data type mismatch, eliminating invalid recommendations that are "topologically reasonable but technically flawed," and significantly reducing the manual verification cost for engineers.

[0204] Step A400: Output the target interface type label recommendation result for the selected pin; the target interface type label represents the functional block pin category to which the selected pin should be connected.

[0205] In this embodiment, the system sorts the scores of the legal candidate connections after constraint masking and outputs a Top-K target interface type label recommendation result. Specifically, the scores in the legal candidate space are sorted in descending order, and the top K labels are selected as the final recommendations. In a preferred embodiment of this application, the K value is set to 3 by default, that is, the three most likely connection options are shown to the user.

[0206] It is important to emphasize that the recommended objects output in this embodiment are "target interface type labels" (e.g., "MANUAL.BKIN", "PIDEX.MV", etc.), rather than specific existing functional block instances. This design reflects the essence of the link prediction task: providing type-level decision support for configuration, that is, informing the user "which pin of which type of functional block should be connected to the current pin". In practical applications, the configuration software can automatically search for matching specific instances based on the type label for the user to choose from, or prompt the user to create the corresponding type of functional block if no matching instance is found. By abstracting the recommendation granularity to type labels, this method not only avoids the recommendation failure problem caused by differences in specific instance naming, but also gives the solution a generalizable capability across projects and devices, enabling it to adapt to the auxiliary configuration needs in different engineering scenarios.

[0207] Through steps A100 to A400, this embodiment fully demonstrates how a trained model can reuse constraint mechanisms and output usable results in actual inference, achieving a closed loop from algorithm model to engineering application. This inference process not only maintains strict consistency with the training phase in terms of data structure and constraint rules, ensuring lossless transfer of model performance, but also provides users with accurate and compliant intelligent assistance through the combination of type-level recommendation and dynamic constraint filtering, effectively solving the technical pain points of complex and error-prone wiring in industrial control configuration.

[0208] Figure 4 This demonstrates an online inference process for pin connection prediction based on RGCN (Graphical Relational Network). Figure 4 As shown, the process is divided into two stages: offline training and online inference.

[0209] During the offline training phase, the system first constructs external and internal connection edges using the pins of the functional block instance as nodes, and simultaneously builds a label space and a set of legal candidates. Then, semantic vectors are generated using the functional block logic description and pin description, and RGCN forward propagation is performed on the nodes in the graph. Next, classification supervision is performed on the occluded edges, and a semantic contrastive loss is added to complete the model training, resulting in a trained RGCN model. It should be noted that in this application, the graph neural network model is preferably implemented using a relational graph convolutional network (RGCN). However, those skilled in the art should understand that in other embodiments, other heterogeneous graph neural network models such as R-GAT, HAN, and HGT can be used instead, as long as they can achieve message passing and link prediction functions on the pin-level heterogeneous graph.

[0210] During the online inference phase, after the system receives the selected pin and its local context graph, it first converts it into a pin-level heterogeneous graph and inputs it into the trained graph neural network model. The model performs forward propagation to generate candidate connection scores for the selected pin. Subsequently, a valid mask is applied according to the orientation and data type of the selected pin (i.e., "apply a valid mask according to orientation and dataset type" in the figure) to obtain the Top-K target FBType.PIN recommendation results and output them.

[0211] Example 9:

[0212] This application provides an electronic device including a processor coupled to a memory. The memory stores at least one computer program, which is loaded and executed by the processor to enable the device to implement the training method described in the foregoing embodiments.

[0213] Specifically, the processor, as the core computing unit of the device, is configured to perform a series of data processing operations, such as engineering configuration analysis, pin-level heterogeneous graph construction, graph neural network model inference, and legal candidate space filtering, as described in the aforementioned embodiments.

[0214] In practical deployments, the processor can be a central processing unit (CPU), a graphics processing unit (GPU), or a dedicated AI acceleration chip. The specific choice depends on the real-time requirements of the link prediction task and the scale of the graph model. For example, in scenarios requiring millisecond-level response to assist engineers in real-time configuration, a GPU supporting massively parallel computing can be used to accelerate the forward propagation and constraint filtering processes of the graph neural network. In offline training or batch data analysis scenarios, multi-core CPU clusters can also meet the computing power requirements. The memory is used not only to store the computer program instructions that implement the above methods but also to persistently store key information such as the parameters of the trained graph neural network model, the function block specification library, the legal candidate space mapping table, and historical engineering configuration data.

[0215] It should be understood that the specific product form of the device is not limited. It can be a workstation or personal computer used locally by engineers, a high-performance server deployed in an enterprise data center, or a virtualized computing instance providing cloud-based intelligent services. As long as it has the ability to execute the aforementioned computer programs to implement the corresponding methods, it falls within the protection scope of this application. Through this tightly coupled hardware and software architecture, this embodiment provides a reliable physical carrier for the aforementioned link prediction method, ensuring the practical feasibility and operational stability of the technical solution in industrial settings, and enabling intelligent connection recommendation services to be truly integrated into existing automated engineering design processes.

[0216] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A training method for a pin connection prediction model, characterized in that, include: Obtain engineering configuration candidate records, and construct a coarse classification cluster containing device or loop semantic boundaries based on the engineering configuration candidate records; Obtain the function block diagram configuration data, and extract weakly connected components based on the connection relationships between function block instances in the function block diagram configuration data; The coarse classification cluster and the weakly connected components are cross-source matched and merged to form training samples that integrate engineering semantics and local topological structure. A pin-level heterogeneous graph is constructed based on the training samples, wherein the pins of the functional block instance are used as nodes of the pin-level heterogeneous graph, and internal connection edges for propagating the internal context of the instance and external connection edges for expressing the signal flow between instances are constructed. The internal connection edges and the external connection edges together constitute the edge set of the pin-level heterogeneous graph. Based on the aforementioned pin-level heterogeneous graph, the graph neural network model is trained by masking the external connection edges, and a valid candidate space is constructed based on the pin orientation and data type constraints to obtain the trained graph neural network model.

2. The method according to claim 1, characterized in that, The step of constructing a coarse classification cluster containing device or loop semantic boundaries based on the candidate engineering configuration records includes: The name field of the candidate engineering configuration record is separated into the tag body and pin name according to the dot number. The numeric token is extracted from the tag body to determine the main tag marker, and the main tag marker is used as the coarse classification key. Semantic feature extraction is performed on the description text and type field of the candidate engineering configuration records to generate record-level semantic tags containing loop tags, equipment action tags, signal tags and system tags; Based on the coarse classification key, engineering configuration candidate records with the same major tag are grouped into the same coarse classification cluster, and the record-level semantic tags within the coarse classification cluster are counted to obtain coarse classification clusters with cluster-level type tags.

3. The method according to claim 1, characterized in that, The step of extracting weakly connected components based on the connection relationships between function block instances in the function block diagram configuration data includes: Standardized connection data is generated based on the function block diagram configuration data and the function block specification library. The standardized connection data records the connection relationships between function block instances. Using the function block instance name as the disjoint set element, traverse the source end instance and target end instance of each connection in the normalized connection data, and perform the disjoint set union without ignoring the connection direction. Function block instances with direct or indirect connections are grouped into the same weakly connected component to obtain weakly connected components that characterize the topological range of the local function block graph. The weakly connected components are expanded into a pin-level graph structure, including: Traverse the connections within the weakly connected components, using the combination of the source instance name and pin name as the source pin node, and the combination of the target instance name and pin name as the target pin node. Each pin node is uniquely identified by the combination of the instance name and pin name, and supplemented with functional block type, functional block type description, instance description, and pin description attributes. The connection is retained as an external connection edge, which records the source end instance name, source end pin name, target end instance name, target end pin name, and connection line data type obtained from the function block specification library, to form a pin-level graph structure carrying engineering semantic attributes for constructing the pin-level heterogeneous graph.

4. The method according to claim 1, characterized in that, The step of performing cross-source matching and merging of the coarse classification clusters and the weakly connected components to form training samples that integrate engineering semantics and local topological structure includes: Establish an association index between the coarse classification cluster and the weakly connected component based on the actual occurrence relationship of the tag number in the function block diagram configuration data; Traverse the candidate records of engineering configurations within the coarse classification cluster, and find the weakly connected component where the candidate record of engineering configuration is located through the association index; The candidate engineering configuration records belonging to the same coarse classification cluster are deduplicated and merged with one or more weakly connected components to form training samples with complete engineering semantic boundaries.

5. The method according to claim 1, characterized in that, The step of constructing a pin-level heterogeneous graph based on the training samples involves using the pins of functional block instances as nodes in the pin-level heterogeneous graph, and constructing internal connection edges for propagating the internal context of instances and external connection edges for expressing signal flow between instances. The internal connection edges and the external connection edges together constitute the edge set of the pin-level heterogeneous graph, including: The pins of the function block instance are used as nodes in the pin-level heterogeneous graph, and the nodes carry the function block type, pin name, data type and direction attribute; The connections between different pins within the same functional block instance are constructed as internal connection edges, which are used to propagate context information within the same logical unit in the graph neural network model; The actual signal connections between pins of different functional block instances are constructed as the external connection edges, which are used to express the signal flow and data dependencies between functional block instances.

6. The method according to claim 5, characterized in that, The construction rules for the external connection edges and the internal connection edges include: For the external connection edge, based on the connection line data type and signal flow direction, forward and reverse edges carrying data type attributes are constructed so that information can propagate along the signal flow direction and also be transmitted back in reverse to affect the upstream node representation. For the internal connection edge, a directed full connection without self-loops is constructed between any two different pin nodes within the same functional block instance, so that any pin in the functional block instance can sense the connection status of other pins in the same instance.

7. The method according to claim 1, characterized in that, The training method further includes a semantic enhancement step, which includes: Tag-level semantic text is generated based on the function block descriptions and pin descriptions in the function block specification library, and then encoded into semantic vectors. The semantic vectors and the structural features of the nodes are fused through a gating mechanism and used as input features of the graph neural network model to provide prior engineering knowledge support for long-tail pins and few-sample classes. The process of masking the graph neural network model based on the pin-level heterogeneous graph by obscuring external connection edges, and constructing a valid candidate space based on pin orientation and data type constraints to obtain the trained graph neural network model includes: Based on the pin-level heterogeneous graph, some of the external connection edges are randomly masked, and the pins at one end of the masked edge are used as query nodes, while the pin type labels at the other end are used as supervision targets. Construct a valid candidate space based on the direction and data type of the query node; The pin type labels outside the legal candidate space are masked, and the classification loss between the link prediction result of the query node and the supervision target is calculated only within the legal candidate space. The total loss is obtained by combining the semantic contrast loss between the structural representation and the semantic vector. The parameters of the graph neural network model are updated based on the total loss to complete the mask training.

8. A pin connection prediction method, characterized in that, The prediction method is based on a graph neural network model obtained through mask training; the mask training is based on a pin-level heterogeneous graph; the pin-level heterogeneous graph uses the pins of the functional block instance as nodes to construct internal connection edges for propagating the internal context of the instance and external connection edges for expressing the signal flow between instances, so as to mask the external connection edges of the pin-level heterogeneous graph and construct a legal candidate space based on the direction and data type constraints of the pins to perform the mask training. The pin connection prediction method includes: In response to the received selected pin and its local context graph, the local context graph is converted into a pin-level heterogeneous graph; The candidate connection scores of the selected pins are generated using the graph neural network model. The valid candidate space is determined based on the direction and data type constraints of the selected pin, and invalid candidate connection scores are masked. Output the target interface type label recommendation result for the selected pin; the target interface type label represents the functional block pin category to which the selected pin should be connected.

9. The method according to claim 8, characterized in that, The step of converting the local context graph into a pin-level heterogeneous graph includes: establishing node indexes based on pin instances in the local context graph; converting external connection edges in the local context graph into forward and reverse edges carrying data type attributes; and supplementing the internal connection edges for multiple pin nodes that have appeared in the same functional block instance to form a directed fully connected graph without self-loops. The determination of the legal candidate space based on the direction and data type constraints of the selected pins includes: retaining only the output pin labels of the same data type for input pins, and retaining only the input pin labels of the same data type for output pins; The step of outputting the target interface type label recommendation result for the selected pin includes: sorting the scores of the legal candidate connections and outputting the Top-K target interface type label recommendation result.

10. An electronic device, characterized in that, The device includes a processor coupled to a memory storing at least one computer program, which is loaded and executed by the processor to enable the device to implement the training method for the pin connection prediction model as described in any one of claims 1-7.

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