Question grading method, device, storage medium, equipment and product

Abstract

The application discloses a kind of subject's correction method, subject's correction device, computer readable storage medium, electronic equipment and computer program product, the method comprises: obtaining subject title subject, and subject title subject to be proved conclusion, answer data, reference answer, according to subject title subject, to be proved conclusion, reference answer, constructs proof obligation hypergraph, answer data and the node in proof obligation hypergraph are matched, and according to the result of matching, determine the first node and the second node in proof obligation hypergraph, according to the first node and the second node whether there is target refutation is judged, according to the judgment result of target refutation, the first node and the second node generate the correction result of answer data.Such, the present application can realize the automatic correction of mathematical proof question, and compared with traditional text similarity comparison scheme, the existence of target refutation can be judged, and the proof logic is deeply checked, so the correction accuracy is higher.

Description

Technical Field

[0001] This application relates to the field of problem correction technology, specifically to a problem correction method, a problem correction device, a computer-readable storage medium, an electronic device, and a computer program product. Background Technology

[0002] In related technologies, intelligent grading of mathematical proof questions typically involves comparing students' answer steps with the reference answer at the text or sequence level, and then determining correctness and scoring based on the similarity of the steps, thereby automating the grading of subjective proof-type questions. However, this type of grading only stops at the level of matching steps at the presentation level and cannot verify the validity of the proof obligation. For example, when students use equivalent reasoning, adjust the order of proofs, or omit common-sense premises, the system is prone to misjudging legitimate non-standard answers as incorrect, resulting in insufficient accuracy in the grading results and failing to meet grading requirements. Summary of the Invention

[0003] This application provides a method for grading questions, a device for grading questions, a computer-readable storage medium, an electronic device, and a computer program product. By constructing a proof obligation hypergraph containing proof nodes and reasoning hyperedges, and combining the answer matching results to locate suspicious nodes and constructing a proof of contradiction with true premises and false conclusions to complete logical verification, the question grading can be deepened to the logical level for verification, reducing the misjudgment rate of non-standard answers.

[0004] On the one hand, embodiments of this application provide a method for grading questions, the method comprising: Obtain the target question, as well as the conclusion to be proven, the answer data, and the reference answer for the target question; Based on the target question, the conclusion to be proved, and the reference answer, a proof obligation hypergraph is constructed, wherein the proof obligation hypergraph includes nodes and hyperedges, at least one node is connected to at least another node through a hyperedge, the node is used to indicate the proof target or proof premise corresponding to each step in the reference answer, and the hyperedge is used to indicate the mathematical theorems and / or reasoning rules satisfied among the connected nodes; The response data is matched with the nodes in the proof obligation hypergraph, and the first node and the second node in the proof obligation hypergraph are determined based on the matching result, wherein the hyperedge connected to the first node matches the response data, and the hyperedge connected to the second node does not match the response data; Based on the first node and the second node, determine whether there is a target proof by contradiction, wherein in the target proof by contradiction, the proof premise corresponding to the first node is true and the proof target corresponding to the second node is false; Based on the judgment result of the target counter-proof, the first node, and the second node, the grading result of the answer data is generated.

[0005] On the other hand, embodiments of this application provide a device for correcting questions, the device comprising: The question acquisition module is used to acquire the target question, as well as the conclusion to be proven, the answer data, and the reference answer of the target question; A hypergraph construction module is used to construct a proof obligation hypergraph based on the target question, the conclusion to be proved, and the reference answer. The proof obligation hypergraph includes nodes and hyperedges. At least one node is connected to at least another node through a hyperedge. The node is used to indicate the proof target or proof premise corresponding to each step in the reference answer. The hyperedge is used to indicate the mathematical theorems and / or reasoning rules satisfied between the connected nodes. A node determination module is used to match the response data with nodes in the proof obligation hypergraph, and determine a first node and a second node in the proof obligation hypergraph based on the matching result, wherein the hyperedge connected to the first node matches the response data, and the hyperedge connected to the second node does not match the response data; The proof-of-contrast module is used to determine whether there is a target proof-of-contrast based on the first node and the second node, wherein in the target proof-of-contrast, the premise of the proof corresponding to the first node is true and the target of the proof corresponding to the second node is false; The generation module is used to generate the grading result of the answer data based on the judgment result of the target counter-proof, the first node and the second node.

[0006] On the other hand, embodiments of this application provide a computer-readable storage medium storing a computer program adapted for loading by a processor to execute the grading method for the questions as described above.

[0007] On the other hand, embodiments of this application provide an electronic device, which includes a processor and a memory. The memory stores a computer program, and the processor executes the grading method for the questions as described above by calling the computer program stored in the memory.

[0008] On the other hand, embodiments of this application provide a computer program product, including computer instructions, which, when executed by a processor, implement the method for grading questions as described above.

[0009] The problem-grading method, problem-grading device, computer-readable storage medium, electronic device, and computer program product provided in this application can obtain a target problem, the conclusion to be proven, the answer data, and the reference answer of the target problem. Based on the target problem, the conclusion to be proven, and the reference answer, a proof obligation hypergraph is constructed. The answer data is matched with nodes in the proof obligation hypergraph, and a first node and a second node in the proof obligation hypergraph are determined based on the matching result. Based on the first node and the second node, it is determined whether a target proof of contradiction exists. Based on the determination result of the target proof of contradiction, the first node, and the second node, a grading result of the answer data is generated. This achieves automated grading of mathematical proof problems. Compared with traditional text similarity comparison schemes, it can perform in-depth verification of the proof logic through the existence judgment of the target proof of contradiction, thus achieving higher grading accuracy. Furthermore, by constructing a hypergraph of proof obligations, the proof process can be abstracted into a hyperedge network of multiple premise conjunctions, which can accommodate various legitimate answer forms such as adjusting the proof order, using equivalent reasoning, and omitting common-sense premises, thus significantly reducing the misjudgment rate. This can effectively assist teachers in their explanations and students in their self-correction. Attached Figure Description

[0010] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is one of the flowcharts illustrating the method for correcting titles provided in the embodiments of this application.

[0012] Figure 2 This is the second flowchart illustrating the method for correcting titles provided in the embodiments of this application.

[0013] Figure 3 The third flowchart illustrates the method for correcting titles provided in the embodiments of this application.

[0014] Figure 4 The fourth flowchart illustrates the method for correcting titles provided in the embodiments of this application.

[0015] Figure 5 The fifth flowchart illustrates the method for correcting titles provided in the embodiments of this application.

[0016] Figure 6 This is the sixth flowchart illustrating the method for correcting titles provided in the embodiments of this application.

[0017] Figure 7A schematic diagram of the structure of the title correction device provided in the embodiments of this application.

[0018] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] This application provides a method for grading exam questions, a device for grading exam questions, a computer-readable storage medium, an electronic device, and a computer program product. Specifically, the method for grading exam questions in this application can be executed by an electronic device, which can be a terminal or a server. The terminal can be a smartphone, tablet, laptop, smart TV, wearable smart device, smart vehicle terminal, etc. The terminal can also include a client, which can be an application client, browser client, instant messaging client, or mini-program, etc. The server can be an independent physical server, a server cluster composed of multiple physical servers, or a distributed system. It can also be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content delivery networks (CDN), and big data and artificial intelligence platforms.

[0021] For example, when the grading method for this question is run on a terminal device, the terminal device may include a display screen and a processor. The display screen is used to present a graphical user interface (GUI) and receive instructions generated by the user interacting with the GUI. The processor is used to store applications, generate the GUI, respond to instructions, and control the display of the GUI on the display screen. When the user operates the GUI through the display screen, the GUI can control the local content of the terminal device in response to the received operation instructions. The terminal device can provide the GUI to the user in various ways, such as rendering it on the terminal device's display screen or presenting the GUI through holographic projection.

[0022] For example, when the grading method for a question runs on a server, this method can be implemented and executed based on a cloud system. The cloud system includes servers and client devices. The application's runtime and the graphical user interface (GUI) presentation are separate; the storage and execution of the question grading method are completed on the server. The GUI presentation, however, is completed on the client. The client is primarily used for data reception, transmission, and GUI presentation. For example, the client can be a display device with data transmission capabilities located close to the user, such as a mobile terminal, television, computer, PDA, personal digital assistant, or head-mounted display device. However, the terminal device performing data processing is the server in the cloud.

[0023] It should be noted that, in this embodiment, the executing entity of the question grading method can be a terminal device or a server. The terminal device can be a local terminal device or a client device in the aforementioned cloud system. This embodiment does not limit the type of executing entity.

[0024] It should also be noted that the triggering operations mentioned in the subsequent detailed description of the title correction method provided in the embodiments of this application can all be regarded as triggering operations performed by the player through a finger or by controlling a medium such as a mouse, keyboard, or stylus. The specific medium used can be determined according to the type of electronic device. For example, when the electronic device is a touch screen device such as a mobile phone or tablet, the player can operate on the touch screen using any suitable object or accessory such as a finger or stylus. When the terminal device is a non-touch screen terminal device such as a desktop computer or laptop, the player can operate using an external device such as a mouse or keyboard.

[0025] It should be noted that the editing operations mentioned in the subsequent detailed description of the title editing method provided in the embodiments of this application can all be regarded as editing operations performed by the player using their fingers or controlling a medium such as a mouse, keyboard, or stylus. The specific medium used can be determined according to the type of electronic device. For example, when the electronic device is a touch screen device such as a mobile phone or tablet, the player can operate on the touch screen using any suitable object or accessory such as a finger or stylus. When the terminal device is a non-touch screen terminal device such as a desktop computer or laptop, the player can operate using an external device such as a mouse or keyboard.

[0026] The technical solution of this application will be described in detail below through specific embodiments. It should be noted that the following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0027] In related technologies, the grading of mathematical proofs, such as geometric proofs, algebraic identity proofs, and mathematical induction problems, has long relied on manual work. In the field of educational artificial intelligence (AI), most AI grading systems for subjective questions can only compare the textual similarity between students' answer steps and the reference answer. They cannot understand deep proof structures such as equivalent logic, implicit premises, and graphical auxiliary lines, which easily leads to problems such as incorrect judgments for different steps, and incorrect judgments without being able to explain the location of logical breaks, thus limiting the application of AI in strong logic problems.

[0028] For intelligent grading of subjective math questions, the technologies employed include natural language processing, optical character recognition, and large-scale modeling capabilities. Common technical approaches include converting the steps of the reference solution into a reduced representation, using a multimodal large-scale model to extract formulas and text from student answers and performing graph matching or sequence comparison with the logical relationship graph of the standard answer, and constructing a topological graph of multiple solutions for scoring when multiple solutions are identified.

[0029] However, the aforementioned technical approaches still have three shortcomings in practical applications. First, the granularity of the proof validity test is too coarse. Related schemes often equate proof questions with ordinary calculation or short-answer questions, using only the similarity between the student's steps and the standard answer steps as the evaluation criterion, ignoring whether the proof obligation is met. Coarse-grained comparison cannot handle situations where students use equivalent reasoning, skip common-sense premises, or change the order of proof—which are legitimate but non-standard—and are prone to misjudgment. Second, the causes of chain breaks are presented as black boxes and lack interpretability. When students' reasoning has problems, end-to-end large-scale grading schemes usually only provide a comprehensive score or a general logical error evaluation, failing to locate and explain the specific causes of the chain break, making the evaluation results lack educational guidance. Third, multimodal evidence is isolated and the scoring criteria are rigid. Related technologies often treat text, formulas, and graphical auxiliary lines separately, rather than anchoring them as mutually corroborating evidence to a unified proof logic node.

[0030] Based on this, please refer to Figure 1 , Figure 1 This is a flowchart illustrating a method for correcting titles provided in an embodiment of this application. It should be noted that the steps shown can be executed in a logical order different from that shown in the flowchart. The method includes: Step 110: Obtain the target question, as well as the conclusion to be proven, the answer data, and the reference answer; Step 120: Based on the target question, the conclusion to be proved, and the reference answer, construct a proof obligation hypergraph, wherein the proof obligation hypergraph includes nodes and hyperedges, at least one node is connected to at least another node through a hyperedge, the nodes are used to indicate the proof target or proof premise corresponding to each step in the reference answer, and the hyperedges are used to indicate the mathematical theorems and / or reasoning rules satisfied between the multiple connected nodes. Step 130: Match the answer data with the nodes in the proof obligation hypergraph, and determine the first node and the second node in the proof obligation hypergraph based on the matching results. The hyperedge connected to the first node matches the answer data, while the hyperedge connected to the second node does not match the answer data. Step 140: Based on the first node and the second node, determine whether there is a target proof by contradiction, where the premise of the proof corresponding to the first node is true and the target of the proof corresponding to the second node is false. Step 150: Based on the judgment result of the proof by contradiction, the first node, and the second node, generate the grading result of the answer data.

[0031] Specifically, the intelligent grading of mathematical proof questions in related technologies mostly relies on natural language processing and text similarity comparison technology. It judges the correctness of the answer solely by comparing the textual overlap between the answerer's steps and the reference answer. This has several problems, such as coarse-grained proof validity testing, easy misjudgment of legitimate answers with equivalent reasoning or order adjustment as incorrect, black-box location of logical chain breaks that cannot explain the specific cause of the error, difficulty in linking and verifying multimodal evidence, and rigid scoring standards that lack fine-grained diagnostic capabilities. As a result, it cannot support the high-precision and interpretable grading requirements of strong logic questions.

[0032] Based on this, this application provides an explicit structured data method—a hypergraph of proof obligations—that introduces between the original answer text and the final grading result. This transforms the traditional, simple grading process of directly comparing the answerer's response with the reference answer into a multi-stage process: constructing the hypergraph of proof obligations, aligning the answer evidence with the hypergraph nodes, verifying logical breaks through local rebuttal, and generating a structured grading result. Specifically, in this embodiment, the electronic device first transforms the question conditions, the conclusion to be proven, and the reasoning logic in the reference answer into an explicit hypergraph of proof obligations. Nodes carry the proof premises and conclusions, and hyperedges carry theorems and reasoning rules, defining a complete proof logic network. Then, the evidence features in the answerer's response are matched and aligned with the hypergraph nodes, distinguishing between verified nodes and questionable nodes. Subsequently, local rebuttal is constructed to verify whether there is a substantial logical break in the questionable reasoning. Finally, based on the verification result, a grading result containing step-level correctness judgments and explanations of the break is generated. Thus, this embodiment can effectively verify the proof logic through the constraints of the structured logic intermediate layer, improving judgment accuracy and result interpretability while ensuring grading efficiency.

[0033] In some embodiments, the target question can be understood as a mathematical proof question that needs to be intelligently graded, covering various question types that rely on logical deduction, such as geometric proofs, algebraic identity proofs, mathematical induction proofs, and inequality proofs.

[0034] In one example, the target problem is a geometry proof: "In △ABC, AB=AC, AD is the median of the base BC, prove that AD⊥BC."

[0035] In some embodiments, the conclusion to be proved can be understood as the mathematical proposition that the target problem requires to be finally derived and proven to be true, and is also the endpoint of the hypergraph of proof obligations.

[0036] For example, regarding the geometric proof problem mentioned above, the conclusion to be proved is "AD⊥BC".

[0037] In some embodiments, the answer data can be understood as all the answers submitted by the respondent for the target question, which may include information in multiple modalities such as textual derivations, mathematical formulas, geometric figures and auxiliary line drawings.

[0038] In one example, the response data included the respondent's written derivation process: "Because AB=AC, BD=CD, therefore △ABD≌△ACD. Therefore ∠ADB=∠ADC=90°, so AD⊥BC" and the corresponding hand-drawn diagram.

[0039] In some embodiments, the reference answer can be understood as the standard proof solution to the corresponding target question, which includes complete reasoning steps, applicable theorems, and logical derivation relationships.

[0040] For example, regarding the geometric proof problem mentioned above, the reference answer is: "Given AB=AC, BD=CD, and AD=AD, we can deduce △ABD≌△ACD based on the SSS congruence theorem. Then, since corresponding angles of congruent triangles are equal, we can obtain ∠ADB=∠ADC. Combining this with the definition of a straight angle, we can deduce that both angles are 90°, thus finally obtaining AD⊥BC."

[0041] In some embodiments, the proof obligation hypergraph can be understood as a computable graph structure formed after logically abstracting the mathematical proof process. It is composed of nodes and hyperedges and can fully present the reasoning relationships between all premises, intermediate conclusions and final conclusions in the proof process.

[0042] For example, for the geometric proof problem mentioned above, the hypergraph of proof obligation constructed for the problem includes initial condition nodes, intermediate conclusion nodes and final conclusion nodes, as well as congruence judgment hyperedges, corresponding angle derivation hyperedges and perpendicular conclusion derivation hyperedges connecting each node, covering the entire logical path from the known conditions to the conclusion to be proved.

[0043] In some embodiments, a node can be understood as a basic building block of a proof obligation hypergraph, used to indicate the proof premise or proof goal corresponding to each step in the reference answer, covering the initial conditions given in the problem, intermediate conclusions in the derivation process, and the final conclusion to be proved.

[0044] As an example, in the hypergraph of the above geometric proof problem, nodes may include multiple propositions such as "AB=AC", "BD=CD", "AD=AD", "△ABD≌△ACD", "∠ADB=∠ADC", and "AD⊥BC".

[0045] In some embodiments, a hyperedge can be understood as a reasoning association unit that connects multiple nodes in a proof obligation hypergraph, used to indicate the mathematical theorems and / or reasoning rules satisfied between the connected multiple nodes. A hyperedge can simultaneously associate multiple premise nodes with a conclusion node, indicating that when multiple premises are held together, the target conclusion can be derived through the corresponding theorems or rules.

[0046] As an example, in the hypergraph of the above geometric proof problem, the hyperedge corresponding to the SSS congruence criterion connects the three premise nodes "AB=AC", "BD=CD", and "AD=AD" with the one conclusion node "△ABD≌△ACD". This indicates that when the three premises are satisfied at the same time, the conclusion of triangle congruence can be derived by the Side-Side-Side (SSS) theorem.

[0047] In some embodiments, the first node can be understood as the node in the proof obligation hypergraph that matches the answer data, that is, the answer data contains corresponding evidence to support the proof premise or intermediate conclusion that can be confirmed, and belongs to the logical node that has been verified.

[0048] For example, in the geometric proof problem above, when the answer provided by the respondent explicitly states "AB=AC" and "BD=CD", the node corresponding to these two propositions is the first node.

[0049] In some embodiments, the second node can be understood as a node in the proof obligation hypergraph that does not match the answer data, that is, there is no corresponding evidence to support the proof target or intermediate conclusion in the answer data that cannot be directly confirmed, and it belongs to a logical node that is questionable and needs to be verified.

[0050] For example, in the geometric proof problem mentioned above, if the answer provided by the respondent does not mention the common edge "AD=AD", the node corresponding to the proposition is the second node.

[0051] In some embodiments, target proof by contradiction can be understood as a local conflict witness used to verify the validity of reasoning. Specifically, it can be understood as a logical assignment combination or counterexample that can still make the proof target corresponding to the second node false, provided that all the proof premises corresponding to the first node are true, and is used to determine whether there is a substantial logical break in the corresponding reasoning step.

[0052] For example, if a respondent mistakenly uses the Side-Side-Angle (SSA) condition to determine triangle congruence in a certain reasoning step in their response data, the objective proof by contradiction is to provide an example of a geometric figure that satisfies the condition that two sides and the angle opposite one of them are equal but the triangles are not congruent, and use this example to prove that the reasoning step is invalid.

[0053] In some embodiments, the grading result can be understood as the final processing result output after complete logical verification, used to present a complete grading diagnosis conclusion to the respondent or teacher.

[0054] To more clearly illustrate the mathematical proof problem processing method provided in the embodiments of this application, please refer to the following exemplary description: The electronic device first acquires the target question, the conclusion to be proven for the target question, the answer data submitted by the respondent, and the standard reference answer.

[0055] Then, the electronic device, based on the problem statement, the conclusion to be proven, and the reference answer, generates a hypergraph of proof obligations through logical analysis, decomposition of reasoning steps, and extraction of theorems and rules. This hypergraph uses nodes to carry all the premises and conclusions of the proof, and hyperedges to carry the mathematical theorems and reasoning rules corresponding to each reasoning step, thus transforming the linear text solution into a mesh-like logical network. Furthermore, the hypergraph of proof obligations provides a unified logical verification benchmark for subsequent grading.

[0056] Next, the electronic device performs feature extraction and content matching on the response data, compares the evidence in the response with each node in the hypergraph of the proof obligation, determines the first node that matches successfully and the second node that fails to match, completes the initial alignment of the respondent's response with the baseline logic network, and initially locates the potential logical breakpoints.

[0057] Subsequently, based on the confirmed first node and the questionable second node, the electronic device constructs logical constraints to verify whether there exists a target proof where the premise corresponding to the first node is true and the conclusion corresponding to the second node is false. If a target proof exists, it is determined that there is a substantial logical break in the corresponding reasoning step. If no target proof exists, it can be further determined whether the proof premise or proof target corresponding to the node is a default known premise. This completes the rigorous verification of the questionable reasoning, replacing the traditional similarity judgment and achieving falsifiable logical verification.

[0058] Finally, the electronic device combines the judgment results of the target proof by contradiction, the distribution of the first node and the second node, and integrates them to generate a complete correction result, including the correctness judgment of each reasoning step, the explanation of the error, the step score, and other content.

[0059] Thus, in this embodiment, the target problem, its conclusion to be proven, the answer data, and the reference answer can be obtained. Based on the target problem, the conclusion to be proven, and the reference answer, a hypergraph of proof obligation is constructed. The answer data is matched with nodes in the hypergraph of proof obligation, and the first and second nodes in the hypergraph of proof obligation are determined based on the matching results. Based on the first and second nodes, it is determined whether a target proof of contradiction exists. Based on the determination result of the target proof of contradiction, the first node, and the second node, a grading result for the answer data is generated. This achieves automated grading of mathematical proof problems. Compared to traditional text similarity comparison schemes, it can conduct in-depth verification of the proof logic through the existence judgment of the target proof of contradiction, thus achieving higher grading accuracy. Furthermore, by constructing a hypergraph of proof obligation, the proof process can be abstracted into a hyper-edge network of multiple premise conjunctions, thus accommodating various legitimate answer forms such as adjusting the proof order, using equivalent reasoning, and omitting common-sense premises, significantly reducing the misjudgment rate. This effectively assists teachers in reviewing and students in self-correction.

[0060] Please see Figure 2 In some embodiments provided in this application, step 130 above includes: Step 131: Determine the type of target proof method corresponding to the answer data; Step 132: Load the target inference rule set corresponding to the target proof method type, wherein the target inference rule set is used to determine the nodes and hyperedges in the proof obligation hypergraph that need to determine the matching relationship with the answer data; Step 133: Match the response data with the nodes in the proof obligation hypergraph according to the target reasoning rule set, and determine the first node and the second node based on the matching results.

[0061] Specifically, in the intelligent grading process of mathematical proof problems, if the proof logic paradigm of the respondent's answer is not distinguished, and the answer data is directly matched and verified against all nodes and hyperedges of the proof obligation hypergraph, then because mathematical proofs include various differentiated proof methods such as direct proof, proof by contradiction, case study, and mathematical induction, and the reasoning logic, required nodes, and legal jump rules corresponding to different proof methods differ, a single matching rule cannot adapt to the logical constraints of various proof paradigms. Ultimately, this may lead to the judgment of legal reasoning steps that conform to a specific proof paradigm as mismatched, causing the node partitioning results to be distorted, thereby increasing the grading misjudgment rate. Furthermore, indiscriminately traversing all nodes and hyperedges of the proof obligation hypergraph will introduce a large number of irrelevant nodes as interference, which not only increases unnecessary computational overhead and inefficient matching processing, but also reduces the accuracy of node matching results.

[0062] Based on this, in some embodiments provided in this application, before performing the node matching operation between the answer data and the proof obligation hypergraph, the target proof method type corresponding to the answer data is first determined, and then the target inference rule set matching the proof method type is loaded. The corresponding verification range is defined in the proof obligation hypergraph through the target inference rule set, and finally the matching verification between the answer data and the node is completed within the limited range, and the first node and the second node are obtained.

[0063] In some embodiments, the target proof method type can be understood as the category of mathematical proof logic paradigm adopted by the respondent in answering the question. It is a classification of the overall logical framework of the proof process. Different proof method types correspond to completely different reasoning structures and logical constraints.

[0064] In some examples, the types of proof methods may include common types such as direct proof, proof by contradiction, classification discussion, and mathematical induction. For example, the proof of properties in plane geometry often uses direct proof, the proof of sequence identities often uses mathematical induction, and the proof of existence and uniqueness propositions often uses proof by contradiction.

[0065] In some embodiments, the target inference rule set can be understood as a pre-configured set of verification rules that corresponds one-to-one with various proof method types. The purpose of the target inference rule set is to define the verification scope that is compatible with the current proof method in the proof obligation hypergraph, and to clearly define the nodes and hyperedges that need to be matched and verified with the answer data, while also stipulating the legal inference constraints, necessary nodes, and prohibition of jump rules under the corresponding proof paradigm.

[0066] In some examples, for the target inference rule set of mathematical induction, the basic case nodes, inductive hypothesis nodes, and recursive conclusion nodes can be designated as mandatory check nodes, and the corresponding hyperedges of recursive inference can be used as check targets to exclude irrelevant nodes related to the direct proof path.

[0067] In some examples, for the target inference rule set of proof by contradiction, the nodes of negation premises and the superedges related to contradiction derivation are locked as verification targets, thereby ensuring that the verification process conforms to the logical characteristics of the corresponding proof paradigm.

[0068] To more clearly illustrate the node matching process in the embodiments of this application, please refer to the following exemplary description: After acquiring the respondent's answer data, the electronic device first performs a proof type identification operation. By analyzing the logical expressions and structural features in the answer text, it determines the target proof type corresponding to the answer. For example, for a geometry proof problem about the properties of isosceles triangles, if the respondent's answer does not contain special logical guiding words such as "the assumption is false" or "discuss different cases," and presents an overall forward reasoning structure that gradually derives the conclusion from the known conditions, the electronic device determines that the target proof type corresponding to this answer is direct proof.

[0069] After determining the proof method type, the electronic device loads the target reasoning rule set corresponding to the direct proof type. The target reasoning rule set is used to determine the verification rules under the direct proof paradigm. For example, starting from the initial conditions of the problem, each intermediate conclusion node and the final conclusion node are verified sequentially along the hyperedge path of forward reasoning, excluding branch nodes and hyperedges corresponding to other paradigms such as proof by contradiction and case discussion. In this way, a local subgraph matching the direct proof path is selected from the complete proof obligation hypergraph, and the range of nodes and hyperedges that need to be matched and verified in the future is clarified.

[0070] Finally, based on the local subgraph range defined by the target inference rule set, the electronic device matches and verifies the respondent's answer data with each node and hyperedge within the range. Nodes that can be covered and successfully matched by the answer data are identified as first nodes, and nodes that cannot be covered and matched by the answer data are identified as second nodes, thus completing the node partitioning process.

[0071] Thus, in this embodiment, the target proof method type corresponding to the answer data can be determined, and the target inference rule set corresponding to the target proof method type can be loaded. Based on the target inference rule set, the answer data and nodes in the proof obligation hypergraph are matched, and the first and second nodes are determined based on the matching results. This allows for the adoption of appropriate matching and verification rules for different proof methods, avoiding misjudgments caused by using a single rule to evaluate different types of answers, ensuring compatibility with multiple legitimate proof paths, and improving the accuracy of node matching results. Furthermore, the verification scope can be narrowed through the target inference rule set, reducing computational redundancy and interference caused by irrelevant nodes, and improving the processing efficiency of node matching.

[0072] In some embodiments provided in this application, step 131 above includes: constructing a target identification model for identifying proof method types; extracting logical indicator words from the response data to indicate proof step transitions or branches; inputting the logical indicator words into the target identification model to obtain the target proof method type output by the target identification model.

[0073] Specifically, in the proof type identification stage of intelligent grading of mathematical proof questions, relying solely on preset fixed keyword matching or simple rule-based judgment to distinguish proof types can be problematic. Because answerers' responses are highly flexible and diverse, the same proof can correspond to multiple different expressions and sentence structures. Simple keyword comparison cannot be combined with the logical connections within the context for comprehensive judgment, easily leading to missed or incorrect judgments and failing to accurately capture the differences in the underlying logical framework of the answers. Furthermore, simple rule-based judgment cannot effectively distinguish the core structural features of different proof paradigms, easily misclassifying answers with specific introductory words but essentially other proof types.

[0074] Based on this, in some embodiments provided in this application, a target recognition model for identifying proof method types is first constructed, and then logical indicator words that can indicate the transformation or branch of proof steps are extracted from the answer data as the basis for recognition features. Finally, the extracted logical indicator words are input into the target recognition model, and the model outputs the corresponding target proof method type after completing comprehensive reasoning analysis, so as to achieve accurate and stable classification of the answer proof paradigm.

[0075] In some embodiments, the target recognition model can be understood as a recognition model specifically built for the mathematical proof paradigm classification task, which has the ability to comprehensively analyze and reason about logically guided features and output the proof method classification results.

[0076] In some examples, the target recognition model can be trained on mathematical proof answer samples labeled with different proof types. It can learn the linguistic features and logical structure features corresponding to different proof paradigms, and has the generalization ability to adapt to diverse answer expressions. It can cover the recognition needs of a variety of common proof methods such as direct proof, proof by contradiction, classification discussion, and mathematical induction.

[0077] In some embodiments, logical indicator words can be understood as distinctive words or phrases in the response text that can reflect the logical direction of the proof, mark the switching of proof steps, or open proof branches.

[0078] In some examples, different proof methods correspond to distinctive logical indicators. For instance, proof by contradiction often corresponds to indicators such as "the assumption is false," "without loss of generality," and "contradiction." Case-by-case analysis often corresponds to indicators such as "discussing different cases," "when...," and "on the other hand." Mathematical induction often corresponds to indicators such as "when n=1," "the assumption holds when n=k," and "when n=k+1." Therefore, electronic devices can use natural language processing technology to filter and extract the above-mentioned logically guiding words from the answer text, thereby obtaining one or more logical indicators.

[0079] To more clearly illustrate the process of identifying the proof method type in the embodiments of this application, please refer to the following exemplary description: First, the electronic device completes the construction of the target recognition model. By collecting mathematical proof answer samples covering multiple proof methods, each sample is labeled with the corresponding proof method type. This is used as training data to complete the model training, enabling the model to have the ability to identify proof method types based on logical features.

[0080] When a respondent answers a question about proving the identity of a sequence, an electronic device acquires the answer data and performs word segmentation and syntactic analysis on the answer text to extract logical indicator words. For example, when the respondent's answer contains phrases such as "when n=1, the equation holds," "assuming the equation holds when n=k," and "when n=k+1," the electronic device can extract logical indicator words such as "when n=1," "assuming the equation holds when n=k," and "when n=k+1," which are used to indicate the transitions in the proof stage.

[0081] Subsequently, the electronic device inputs the extracted logical indicator words into the pre-built target recognition model. The model combines lexical features with the contextual logical structure to make a comprehensive judgment, identify that the answer conforms to the paradigm features of mathematical induction, and then outputs the corresponding target proof method type as mathematical induction.

[0082] Thus, in this embodiment of the application, a target identification model for identifying proof method types can be constructed, and logical indicator words for indicating proof step transformations or branches can be extracted from the answer data. The logical indicator words are then input into the target identification model to obtain the target proof method type output by the target identification model. This allows the model to identify diverse answer expressions from respondents through its comprehensive analysis capabilities, thereby reducing the probability of missed and incorrect identification of proof methods and improving the accuracy of proof method type identification.

[0083] In some embodiments provided in this application, the target recognition model includes a finite state machine. Furthermore, the step of inputting logical indicators into the target recognition model to obtain the target proof method type output by the target recognition model includes: inputting logical indicators into the finite state machine so that the finite state machine, through the logical indicators, determines at least one of multiple proof method types as an active state, and determines the proof method type in the active state as the target proof method type.

[0084] Specifically, when identifying the type of proof method used in a respondent's answer, if a general text classification model is used as the identification carrier, it can often only output a single classification result. It is difficult to accurately capture the dynamic switching of proof paradigms during the answering process, and it cannot effectively adapt to scenarios where multiple proof methods are used in the same answer. This can easily lead to omissions or misjudgments in paradigm identification, resulting in a mismatch between the subsequently loaded inference rule set and the actual answer logic, which affects the accuracy of node matching.

[0085] Based on this, in some embodiments provided in this application, the target recognition model is configured as a structure including a finite state machine, and state nodes and state transition triggering rules corresponding to various proof method types are pre-set in the finite state machine. Then, after the extracted logical indicator words are input into the finite state machine, the finite state machine triggers the corresponding state transitions according to the logical indicator words, switching the matched proof method type to the active state, and finally determining the proof method type in the active state as the target proof method type.

[0086] In some embodiments, a finite state machine can be understood as a computational model with a finite number of discrete states that can perform directional transitions between preset states based on an input signal.

[0087] In some examples, the finite state machine can be pre-configured with state nodes corresponding to various proof methods such as direct proof, proof by contradiction, case study, and mathematical induction, and set corresponding trigger keyword rules for each node. When a matching input signal is received, the state switch can be completed.

[0088] In some embodiments, an active state can be understood as the state that is currently triggered and takes effect in a finite state machine, corresponding to the proof method type that matches the current answering logic. The proof method type in the active state will be output for use in the subsequent rule loading process. At the same time, there may be one or more active states to adapt to the answering scenario of mixed proof paradigms.

[0089] In some examples, if the respondent's answer contains both the statements "discussing different cases" and "assuming the conclusion is not true", the finite state machine can simultaneously determine both the classification discussion and proof by contradiction as active states, thus being compatible with the answer logic of the composite paradigm.

[0090] To more clearly illustrate the process of identifying the proof method type in the embodiments of this application, please refer to the following exemplary description: The electronic device pre-configures a finite state machine, setting up state nodes corresponding to four types of proof methods: direct proof, proof by contradiction, case study, and mathematical induction. The direct proof state is set as the initial default state. At the same time, corresponding transition trigger conditions are configured for each state. For example, statements such as "the assumption is not true" and "conversely" are configured as trigger conditions for the proof by contradiction state, statements such as "discussing different cases" and "discussing the following cases" are configured as trigger conditions for the case study state, and statements such as "when n=1" and "the assumption holds when n=k" are configured as trigger conditions for the mathematical induction state.

[0091] When a user answers a question about proving a sequence identity, an electronic device extracts logical indicators such as "the equation holds when n=1" and "the equation holds when n=k" from the answer data and inputs these logical indicators into a finite state machine. The finite state machine matches the input with preset transition trigger conditions, identifies the type of statement that matches the trigger condition of the mathematical induction state, and then executes a state transition, determining the proof method type corresponding to mathematical induction as the active state.

[0092] If the respondent's answer subsequently includes the statement "discussing both odd and even numbers of k," the finite state machine, after recognizing the trigger condition matching the classification discussion state, will further determine the corresponding proof method type as an active state. Ultimately, the finite state machine outputs the two active proof method types—mathematical induction and classification discussion—as the identified target proof method types, used for subsequently loading the corresponding target inference rule set.

[0093] Thus, in this embodiment, the target recognition model can be implemented using a finite state machine. Logical indicators can be input into the finite state machine, allowing it to determine at least one of multiple proof types as an active state, and identify the active proof type as the target proof type. This captures the dynamic switching of proof paradigms in the response data, making it suitable for scenarios where multiple proof types are simultaneously active, effectively adapting to mixed-paradigm response scenarios, and improving the accuracy and adaptability of proof type recognition. Furthermore, the finite state machine does not require extensive labeled sample training, has a fast response speed, and can adapt to high-concurrency intelligent grading scenarios, reducing model development and maintenance costs.

[0094] Please see Figure 3 In some embodiments provided in this application, step 130 above includes: Step 134: Perform feature extraction processing on the response data to obtain the evidence features corresponding to the response data. The evidence features include the evidence entity, the position of the evidence entity in the response data, and the confidence level. The evidence entity is the text, formula, or graphic element in the response data used to indicate the premise or intermediate conclusion of the proof. The confidence level is used to indicate the degree of credibility of the matching between the evidence entity and the node. Step 135: Construct the mapping relationship between evidence features and nodes in the hypergraph of proof obligations to obtain evidence-node mapping relationship data; Step 136: Based on the evidence-node mapping relationship data, determine the first node that matches the evidence entity and the second node that does not match the evidence entity.

[0095] Specifically, the data provided by respondents may contain multiple forms of information such as text, formulas, and graphs. These different forms of information are scattered across different areas of the response content. Therefore, without targeted feature extraction processing, it is difficult to accurately locate the effective information corresponding to the proof logic, and it is easy to miss key proof elements such as graphical auxiliary lines and implicit formula annotations, ultimately affecting the accuracy of the final result.

[0096] Based on this, in some embodiments provided in this application, the electronic device can first perform feature extraction processing on the answer data to obtain structured evidence features containing evidence entities, location information and confidence levels; then construct the mapping relationship between evidence features and hypergraph nodes of proof obligations to form standardized mapping relationship data; finally, based on the mapping relationship data, divide the first node that matches the evidence entity and the second node that does not match, so as to achieve accurate alignment of the answer content to the proof logic node.

[0097] In some embodiments, feature extraction processing can be understood as the process of identifying and extracting valid information related to the proof logic from the original response data and transforming it into computable structured data, which can transform scattered multimodal response information into a processing object in a unified format.

[0098] In some examples, feature extraction can be achieved through a large language model, which can sequentially identify the text description, the meaning of formula symbols, and auxiliary lines and markers in the figure from the respondent's answer image containing handwritten text, mathematical formulas, and geometric figures.

[0099] In some embodiments, evidence features can be understood as a structured set of representations of evidence-related information in the response, and are the output of feature extraction processing.

[0100] In some examples, a single evidence feature may contain three types of information: the content of the evidence entity, the coordinates of the corresponding answer area, and the matching confidence score. For example, a formula-type evidence feature may be recorded as: the evidence entity is AB=AC, the position coordinates are a specified pixel range, and the confidence score is 0.93.

[0101] In some embodiments, an evidence entity can be understood as the smallest unit of information in the response data that can correspond to the premise or intermediate conclusion, and its form can cover elements such as text, formulas, and graphics.

[0102] In some examples, evidentiary entities may include textual statements describing logical relationships, such as D being the midpoint of side BC, or mathematical formulas expressing quantitative or positional relationships, such as △ABD≌△ACD, or graphical elements such as auxiliary lines, perpendicular markers, and angle labels. Different forms of evidentiary entities can correspond to corresponding nodes in the hypergraph of the burden of proof.

[0103] In some embodiments, confidence level can be understood as a numerical index used to quantify the degree of credibility of the matching between the evidence entity and the node of the hypergraph of the proof obligation. It typically ranges from 0 to 1. The higher the value, the stronger the matching reliability between the evidence entity and the corresponding node. It can be used to screen effective matches and filter out identification noise.

[0104] In some examples, the matching confidence level can reach above 0.95 for clearly identified and well-written printed formula evidence; however, the matching confidence level may be as low as 0.6 for illegible handwritten text evidence. Typically, a confidence level threshold of 0.85 is set, and only evidence entities with a confidence level higher than the threshold are retained for subsequent mapping and matching.

[0105] In some embodiments, the evidence-node mapping relationship data can be understood as a structured dataset that records the corresponding associations between evidence features and nodes in the hypergraph of proof obligations. It fully preserves information such as the pairing relationship between each set of evidence and nodes, the matching confidence level, and the location of the evidence source. It serves as bridge data connecting the surface evidence of the answer with the deep proof logic.

[0106] In some examples, the evidence-node mapping data can be in the form of structured records, including fields such as evidence ID, node ID, evidence content, confidence level, and evidence location.

[0107] In some embodiments, the first node can be understood as a hypergraph node of the proof obligation that can establish a valid matching relationship with the evidence entity, and the proof premise or intermediate conclusion represented by the node has been covered in the response data; the second node can be understood as a hypergraph node of the proof obligation that cannot establish a valid matching relationship with the evidence entity, and the proof content represented by the node has not been explicitly mentioned in the response, and belongs to a potential logical break in the chain to be verified.

[0108] In some examples, if the respondent explicitly states the premises AB=AC and BD=CD in their answer, then the two premise nodes in the hypergraph of the proof obligation are the first node; if the answer does not mention the premise that AD is a common edge, then the corresponding hypergraph node is the second node.

[0109] To more clearly illustrate the matching process between the response data and the hypergraph nodes in the embodiments of this application, please refer to the following exemplary description: First, the electronic device acquires the respondent's answer data for the geometry proof question, which includes three types of content: handwritten text, mathematical formulas, and hand-drawn geometric figures.

[0110] Then, the electronic device performs feature extraction processing on the response data, identifies the response content region by region through a multimodal information processing model, extracts all information units related to the proof logic as evidence entities, records the pixel coordinate position of each evidence entity in the response image, and the confidence value of each evidence entity matching the corresponding proof content, and finally outputs a complete set of structured evidence features.

[0111] After feature extraction, the electronic device performs an evidence-node mapping construction operation. Specifically, the electronic device performs semantic and logical matching verification between each evidence entity in the evidence feature set and each node in the proof obligation hypergraph. For evidence entities with a confidence level higher than a preset threshold, a one-to-one association is established between them and the corresponding hypergraph nodes; for evidence entities with a confidence level lower than the threshold, they are filtered out as noise. After all valid associations are summarized, a complete evidence-node mapping relationship data is formed.

[0112] Finally, the electronic device classifies nodes based on the evidence-node mapping data. It traverses all nodes in the proof obligation hypergraph, marking nodes that have established a valid association with an evidence entity as first nodes, indicating that the proof content corresponding to that node has appeared in the respondent's answer; nodes that have not established an association with any evidence entity are marked as second nodes. Thus, in this embodiment, feature extraction processing can be performed on the response data to obtain the evidence features corresponding to the response data, and a mapping relationship between the evidence features and nodes in the proof obligation hypergraph can be constructed to obtain evidence-node mapping relationship data. Based on the evidence-node mapping relationship data, the first node that matches the evidence entity and the second node that does not match the evidence entity can be determined. This can transform unstructured multimodal response data into computable structured evidence, realize effective matching between response data and nodes, and cover multiple types of elements such as text, formulas, and graphics, avoiding the omission of key information. Furthermore, the confidence index can be used to filter and identify noise and quantify the reliability of matching, effectively reducing the problems of misjudgment and omission caused by surface text comparison.

[0113] In some embodiments provided in this application, the response data includes at least two of text modal information, formula modal information, and graphic modal information. Furthermore, step 134 includes: inputting the response data into a pre-trained multimodal information processing model, so that the multimodal information processing model performs feature extraction processing on each modal information in the response data to obtain evidence features.

[0114] Specifically, when dealing with response data containing multiple forms of information, if the modal-specific processing method is adopted, and text, formulas, and graphics are identified and feature extracted separately, the feature extraction processes of different modal information are independent of each other, and there is a lack of a unified semantic alignment and spatial association mechanism. This can easily lead to misalignment of evidence information from different modalities, making it impossible to accurately correspond to the same proof logic node and making it difficult to achieve cross-modal evidence mutual verification.

[0115] Based on this, in some embodiments provided in this application, the system can input response data containing at least two modalities into a pre-trained multimodal information processing model, and the model can perform targeted feature extraction processing on each modality of the response data, and finally output evidence features with a uniform format, thereby realizing the synchronous extraction, semantic alignment and structured output of multimodal information.

[0116] In some embodiments, text modal information can be understood as information content in the response data that carries the proof logic in the form of natural language text, and usually exists in the response content in the form of handwritten text, printed text, etc.

[0117] In some examples, textual modal information may include statements describing the premises of a proof, such as "D is the midpoint of the base BC", or statements deriving intermediate conclusions, such as "corresponding angles are equal from congruent triangles".

[0118] In some embodiments, formula modal information can be understood as quantitative and logical relationship information presented in the form of mathematical symbols and formula expressions in the response data, which has the characteristics of rigorous expression and high degree of symbolization.

[0119] In some examples, formula modal information may include equations such as AB=AC, geometric symbols such as △ABD≌△ACD, and may also include mathematical symbols in various forms such as theorem symbols and algebraic expressions.

[0120] In some embodiments, graphical modal information can be understood as information content in the response data presented in a visual form such as geometric figures, auxiliary lines, and markers, which can intuitively present the graphic structure, positional relationships, and auxiliary construction.

[0121] In some examples, the graphic modal information may include geometric figures such as triangles and quadrilaterals drawn by the respondent, or graphic elements such as auxiliary lines, right angle marks, short vertical line marks of equal line segments, and angle annotation symbols added by the respondent.

[0122] In some embodiments, a multimodal information processing model can be understood as an artificial intelligence model that has been pre-trained with multimodal sample data and has the ability to process multiple types of information simultaneously and extract unified features. It can integrate and understand information from different modalities and achieve cross-modal semantic association and structured feature extraction.

[0123] In some examples, the multimodal information processing model can adopt a visual-language multimodal large model architecture, which can simultaneously input complete response images containing handwritten text, mathematical formulas, and hand-drawn graphics, output structured evidence recognition results, and automatically associate information from different modalities that point to the same logic.

[0124] Thus, in this embodiment, the response data may include at least two of the following: text modality information, formula modality information, and graphic modality information. The response data can then be input into a pre-trained multimodal information processing model, which will perform feature extraction processing on each modality of the response data to obtain evidence features. This achieves unified feature extraction of multimodal response data, avoids information misalignment and missing associations caused by independent processing of different modalities, and improves the accuracy of evidence extraction.

[0125] In some embodiments provided in this application, step 135 includes: establishing a correspondence between evidence entities with a confidence level greater than a preset confidence threshold and the corresponding nodes in the proof obligation hypergraph.

[0126] Specifically, when constructing the mapping relationship between evidence features and hypergraph nodes of the proof obligation, including all evidence entities extracted from features without screening in the matching process would introduce a large amount of low-quality recognition noise. Furthermore, since the response data is mostly handwritten text, hand-drawn formulas, and graphics, problems such as character misjudgment, line misrecognition, and semantic matching deviations are inevitable during the recognition process. If these low-credibility evidence entities are included in the mapping relationship, it will cause incorrect node matching results, misjudging proof nodes not covered by the response as covered, or incorrectly anchoring irrelevant information to proof logic nodes, ultimately reducing the accuracy of the correction results.

[0127] Based on this, in some embodiments provided in this application, electronic devices can screen evidence entities by setting a pre-set confidence threshold, retain only evidence entities with a confidence level higher than the threshold, establish a pairing association with the logically corresponding nodes in the proof obligation hypergraph, and eliminate low-quality identification results with insufficient confidence, thereby ensuring the overall reliability of the mapping relationship and reducing the interference of identification noise on the subsequent approval process.

[0128] In some embodiments, the preset confidence threshold can be understood as a pre-set numerical threshold used to determine whether an evidence entity has sufficient credibility to participate in node mapping. The value of the preset confidence threshold can be flexibly adjusted according to the accuracy requirements of the correction scenario and the comprehensive information of the recognition model, and the value range of the preset confidence threshold can be from 0 to 1.

[0129] In some examples, for scenarios with high requirements for marking accuracy, such as formal exam marking and question bank quality inspection, the pre-set reliability threshold can be set to 0.85 to strictly control the quality of evidence involved in the mapping and avoid low-reliability recognition results from interfering with the matching logic.

[0130] In some examples, for scenarios with high tolerance for error, such as daily homework correction and in-class exercises, the preset reliability threshold can be appropriately lowered to 0.7 to cover more recognition results and take into account the breadth of coverage of the answer information.

[0131] In some examples, if the recognition confidence level of a printed formula is 0.94, which is higher than the preset confidence threshold of 0.85, then the evidence entity can proceed to the subsequent node mapping process. If the recognition confidence level of a illegible handwritten text is 0.62, which is lower than the preset confidence threshold of 0.85, then the evidence entity will be judged as an invalid recognition result and will not be included in the mapping construction stage.

[0132] Thus, in this embodiment of the application, evidence entities with a confidence level greater than a preset confidence threshold can be associated with corresponding nodes in the proof obligation hypergraph. This allows for the filtering of low-quality identification noise generated during feature extraction through threshold screening, preventing misidentification and fuzzy identification from interfering with the node matching process, improving the accuracy of evidence-node mapping, and reducing node classification bias caused by incorrect mapping.

[0133] In some embodiments provided in this application, step 136 includes: determining nodes with established correspondence as first nodes and nodes without established correspondence as second nodes.

[0134] Specifically, in some embodiments provided in this application, electronic devices can classify nodes of the proof obligation hypergraph by determining whether a node has established a valid correspondence with an evidence entity that meets the screening criteria, identifying nodes that have established a correspondence as first nodes and nodes that have not established a correspondence as second nodes.

[0135] In some embodiments, a node with a corresponding relationship can be understood as a hypergraph node of proof obligation that has been paired with an evidence entity that meets the confidence screening requirements in the evidence-node mapping relationship data. This means that the proof premise or intermediate conclusion corresponding to the node has been effectively identified and matched in the response data, and can then be used as a verified proof node to participate in subsequent logical deduction and verification.

[0136] In some examples, for the question "Prove that the median on the base of an isosceles triangle is perpendicular to the base", if the respondent explicitly writes the two premises "AB=AC" and "BD=CD" in their answer, and the confidence level of the corresponding evidence entity is higher than the preset threshold and has been associated with the corresponding premise node in the hypergraph, then these two premise nodes are nodes with a corresponding relationship.

[0137] In some embodiments, a node that fails to establish a corresponding relationship can be understood as a proof obligation hypergraph node in the evidence-node mapping relationship data that has not formed a pairing association with any evidence entity that meets the confidence screening requirements. This means that the proof content corresponding to the node has not been effectively identified and covered in the response data, and belongs to a potential logical missing node to be verified. It can then enter the subsequent condition check and chain break verification process.

[0138] In some examples, for the same geometric proof problem mentioned above, if the respondent does not mention the premise that "AD is a common edge, i.e., AD=AD" in their answer, and no corresponding graphical annotation evidence is effectively identified, then the node in the hypergraph of the proof obligation corresponding to the premise "AD=AD" is the node that failed to establish a corresponding relationship.

[0139] Thus, in this embodiment of the application, nodes with established relationships can be identified as first nodes, and nodes without established relationships can be identified as second nodes, thereby completing the classification of nodes in the proof obligation hypergraph, avoiding the judgment differences caused by ambiguity in classification rules, and thus ensuring the validity of the correction results.

[0140] Please see Figure 4 In some embodiments provided in this application, the method for grading questions further includes: Step 160: Obtain the target mathematical theorem and / or target inference rule indicated by the hyperedge connected to the second node; Step 170: Determine the target preconditions that the target mathematical theorem and / or target reasoning rule must satisfy; Step 180: Determine whether the evidentiary entity contains the target precondition; Step 190: If the evidence entity contains part of the conditions of the target premise, determine the correlation parameter between the first node and the missing premises of the target premise that are not contained in the evidence entity; Step 200: If the relevance parameter is higher than the preset threshold, update the second node to the first node.

[0141] Specifically, considering that respondents often omit some axiomatic premises or implicit conditions already clearly stated in the context when answering mathematical proof questions, based on common sense and problem-solving habits, strictly matching the evidence entities and hypergraph nodes of the proof obligation explicitly presented in the answer would easily lead to the judgment of such legitimate simplified expressions as node mismatch, thus misjudging them as logical breaks and deducting corresponding points. This would not only fail to reflect the respondent's level of logical mastery but also increase the overall misjudgment rate of electronic grading devices. On the other hand, if all missing premises are accepted indiscriminately, the rigor of grading would be lost, and the true omission of premises and logical jumps would be impossible to identify.

[0142] Based on this, in some embodiments provided in this application, the electronic device can, for a second node not fully covered by evidence, first locate the target mathematical theorem and reasoning rule pointed to by the hyperedge connected to the node, and then disassemble all the preconditions required for the theorem or rule to take effect, so as to verify the coverage of the preconditions by the evidence entity; if only some preconditions are missing, the correlation between the proven first node and the missing preconditions is quantitatively calculated. When the correlation is higher than a preset threshold, it is determined that the missing precondition belongs to the implicit condition reasonably omitted by the respondent, and the corresponding second node is updated to a first node with effective support.

[0143] In some embodiments, the target mathematical theorem can be understood as the specific mathematical axiom, theorem, or corollary on which the reasoning steps corresponding to the second node are based, and can be determined by the properties of the hyperedge connected to the second node.

[0144] In some examples, the target mathematical theorem may include the SSS congruence theorem for triangles, the theorem of the coincidence of the three lines of an isosceles triangle, and the parallel line property theorem in geometry, or the basic properties of equality, the recursive rules of sequences, and the additivity of inequalities in the same direction in algebra, depending on the knowledge points involved in the problem and the function of the reasoning steps.

[0145] In some embodiments, the target reasoning rule can be understood as the formal logic reasoning norm followed by the reasoning steps corresponding to the second node, which is used to constrain the derivation relationship between the premise and the conclusion and ensure the formal validity of the reasoning process.

[0146] In some examples, the target reasoning rule may include logical rules such as hypothetical reasoning, conjunction introduction, classification and merging, and equivalent substitution. For example, when a reasoning step leads to a conclusion from multiple parallel premises, the corresponding target reasoning rule is the conjunction introduction rule.

[0147] In some embodiments, the target preconditions can be understood as the set of all antecedent propositions that must be true simultaneously when the corresponding target mathematical theorem and / or target reasoning rule is legally applied.

[0148] In some examples, when the target mathematical theorem is the SSS congruence theorem for triangles, the target preconditions are the three propositions that the corresponding sides of the three sets are equal. All three conditions must be satisfied for the theorem to take effect and for the conclusion that triangles are congruent to be derived.

[0149] In some embodiments, a missing precondition can be understood as a precondition that is not covered by the evidentiary entities in the response data or is not explicitly presented in the respondent's response.

[0150] In some examples, when applying the SSS theorem to prove triangle congruence, if the respondent only explicitly states that two pairs of corresponding sides are equal without mentioning the premise of a common side, then the proposition that the common side is equal is the corresponding missing premise.

[0151] In some embodiments, the relevance parameter can be understood as a numerical indicator used to quantify the degree of correlation between the missing premise and the currently proven first node. The higher the value, the more likely the missing premise is an implicit condition that the respondent has omitted by default based on common sense, rather than a substantial logical omission.

[0152] In some embodiments, the preset degree parameter threshold can be understood as a pre-set judgment threshold, used to distinguish between recoverable reasonable implicit premises and truly omitted necessary premises.

[0153] In some examples, the preset level parameter threshold can be set to a value between 0.7 and 0.9. It can be flexibly adjusted according to the grade level, difficulty of the question, and scoring criteria. The higher the grade level and the more rigorous the question, the higher the threshold can be set.

[0154] To more clearly illustrate the process of implicit premise recovery and node state update in the embodiments of this application, please refer to the following exemplary description: After the electronic device completes feature extraction and evidence-node mapping of the response data, it identifies the node corresponding to a certain reasoning step as the second node, meaning that the node has not yet obtained complete evidence support. For the second node, the electronic device can first obtain the target mathematical theorem indicated by the hyperedge connected to the second node, such as the triangle SSS congruence theorem.

[0155] Subsequently, based on a pre-defined theorem-premise association knowledge base, the electronic device determines all the target preconditions that the SSS congruence theorem must satisfy, namely, the three preconditions that the three sets of corresponding edges are equal.

[0156] The electronic device compares the matched evidence entities with the aforementioned target preconditions one by one to determine the extent to which the evidence entities cover the preconditions. Upon verification, the respondent clearly stated two sets of conditions where corresponding edges are equal in their response, only lacking the condition that the common edge is equal. That is, the evidence entities contain part of the target preconditions.

[0157] In this scenario, the electronic device calculates the relevance parameter between the first node supported by current evidence and the missing common edge premise. For example, the electronic device uses a pre-set common sense knowledge graph to locate the node corresponding to the missing premise and the position of the proven first node in the graph, and calculates the shortest path distance between them; simultaneously, it combines the semantic relevance of the answer context to generate the final relevance parameter.

[0158] Finally, the electronic device compares the calculated relevance parameter with a preset threshold. If the parameter is higher than the preset threshold, it indicates that the equality of common edges is a common-sense implicit premise that the respondent could reasonably omit. Therefore, the electronic device updates the inference node, which was originally marked as the second node, to a first node with valid support, and determines that the preconditions for this inference step have been fully met.

[0159] Thus, in this embodiment, the target mathematical theorem and / or target inference rule indicated by the hyperedge connected to the second node can be obtained, and the target preconditions that the target mathematical theorem and / or target inference rule must satisfy can be determined. It can also be determined whether the evidence entity contains the target preconditions, and if the evidence entity contains part of the target preconditions, the correlation parameter between the first node and the missing preconditions in the target preconditions that are not contained in the evidence entity can be determined. If the correlation parameter is higher than a preset threshold, the second node is updated to the first node. This adds a fault-tolerant verification mechanism for implicit preconditions on the basis of evidence matching, thereby accommodating common common-sense skips and simplified expressions in answering questions, reducing the misjudgment rate of proof question grading, and ensuring the rigor and professionalism of the grading logic through quantitative threshold control of the recovery scale, adapting to the actual application needs of intelligent grading of mathematical proof questions.

[0160] In some embodiments provided in this application, the sub-step of determining the relevance parameter between the first node and the missing preconditions not included in the evidence entity in the target preconditions in step 190 includes: determining the shortest path distance between the node corresponding to the missing precondition and the first node through a preset knowledge graph, wherein the preset knowledge graph is used to store the association relationship between multiple preconditions; determining the semantic relevance between the missing precondition and the evidence entity corresponding to the first node; and determining the relevance parameter based on the shortest path distance and / or the semantic relevance.

[0161] Specifically, considering that in the context of answering mathematical proof questions, respondents often omit common-sense implicit premises such as common edges and basic axioms based on problem-solving conventions, if only the evidence entities that appear explicitly in the answer are rigidly matched with the nodes of the hypergraph of the proof obligation, it is easy to judge the omission of legal premises as a logical break, resulting in misjudgment in grading.

[0162] Based on this, in some embodiments provided in this application, the shortest path distance between the missing premise and the matched node can be calculated through a preset domain knowledge graph, and the semantic correlation between the two can be calculated at the same time. Based on this, the correlation parameter is quantified and used as the basis for the determination of the recovery of the implicit premise, which is compatible with the conventional problem-solving omission habit while ensuring the rigor of the correction.

[0163] In some embodiments, a pre-built knowledge graph can be understood as a pre-constructed structured knowledge network that stores various preconditions and interrelationships in the field of mathematics, and can systematically present the logical relationships between knowledge elements such as mathematical axioms, theorems, geometric properties, and operational rules.

[0164] In some examples, the pre-defined knowledge graph can contain various mathematical common sense nodes such as "triangles have equal common sides", "isosceles triangles have equal base angles", and "basic properties of equations". The nodes are connected by derivation, subordination, and equivalence relationships to form a knowledge network covering multiple branches of mathematics such as geometry and algebra.

[0165] In some embodiments, the shortest path distance can be understood as the length of the connected path between the node corresponding to the missing precondition and the first node in the topological structure of the preset knowledge graph, formed by the minimum number of associated edges. It is used to quantify the logical connection between the two nodes from the knowledge topology level. The shorter the path distance, the more direct the connection between the two in the mathematical knowledge system.

[0166] In some examples, for geometric proof scenarios, if the first node corresponds to "AD is a side of △ABC" and the missing premise corresponds to "AD=AD (common side)", the two are separated by only one related node "common side property" in the knowledge graph, and the shortest path distance is extremely small, indicating that the two are highly related.

[0167] In some embodiments, semantic relevance can be understood as the degree of similarity between the semantic expression of the missing precondition and the semantic expression of the evidence entity corresponding to the first node. This is used to measure the fit between the missing precondition and the existing response from the textual semantic dimension, and can avoid the interference of differences in expression on the correlation determination.

[0168] In some examples, if the evidence entity is stated as "AD is the common side of the triangle" and the missing premise is stated as "line segment AD is equal to itself", the two have a high degree of semantic consistency and a high degree of semantic relevance.

[0169] In some embodiments, the relevance parameter can be understood as a quantitative indicator that comprehensively reflects the degree of correlation between the first node and the missing precondition. The higher the parameter value, the easier it is for the precondition to be reasonably completed based on the existing answer information.

[0170] In some examples, the relevance parameter can be calculated separately using the normalized value of the shortest path distance and the semantic relevance value, or a comprehensive value can be obtained by weighting and fusing the two to adapt to the grading scenarios of different question types and difficulties.

[0171] To more clearly illustrate the calculation process of the relevant degree parameter in the embodiments of this application, please refer to the following exemplary description: When the electronic device recognizes that the prerequisites required for the target mathematical theorem are not fully covered by the answer evidence and that there are missing prerequisites, the electronic device retrieves a pre-constructed mathematical knowledge graph and locates the node positions corresponding to the missing prerequisites and the first node in the graph, and sets the two nodes as the starting point and ending point of the path search, respectively.

[0172] Subsequently, the graph search algorithm is used to traverse the associated edges in the knowledge graph and calculate the shortest path distance between two nodes. This is used to quantify the degree of association between the two nodes at the knowledge logic level. The shorter the path distance, the more directly the missing premise is associated with the confirmed premise knowledge, and the higher the probability that it belongs to common sense that can be omitted.

[0173] At the same time, the electronic device performs semantic encoding on the text content of the missing preconditions and the text content of the evidence entity corresponding to the first node, respectively, and maps the two into a unified semantic vector space. The semantic relevance is obtained by calculating the cosine similarity between the vectors, etc., and the semantic fit between the missing preconditions and the existing answers is verified from the text expression level to avoid the deviation of the association judgment caused by different wording.

[0174] After completing the calculation of the above two indicators, the electronic device generates the final relevance parameter according to the preset calculation rules. For example, it can choose to normalize the shortest path distance and use it directly as the relevance parameter, or use the semantic relevance directly as the relevance parameter, or configure the corresponding weight coefficients for the shortest path distance and the semantic relevance respectively, and then fuse them by weighted summation to obtain the comprehensive relevance parameter.

[0175] The calculated relevance parameters will be input into the subsequent threshold determination process. If the parameter value is higher than the preset threshold, the missing premise is determined to be a reasonably recoverable implicit premise. The corresponding second node will be updated to the first node and included in the set of established premises to support subsequent reasoning and verification.

[0176] Thus, in this embodiment, the shortest path distance between the node corresponding to the missing premise and the first node can be determined by a preset knowledge graph, the semantic relevance between the missing premise and the evidence entity corresponding to the first node can be determined, and the relevance parameter can be determined based on the shortest path distance and / or semantic relevance. This allows for the construction of a quantitative implicit premise association judgment standard from both knowledge topology and semantic expression dimensions, providing an objective and reproducible basis for implicit premise recovery. This method can accurately identify common-sense premises that can be reasonably omitted, is compatible with the common problem-solving habits of respondents, and reduces the misjudgment rate caused by rigid matching. Furthermore, it can control the completion scale through quantitative thresholds, avoiding logical loopholes introduced by unfounded premise completion, ensuring the rigor and consistency of the grading results, effectively improving the accuracy and fault tolerance of automatic grading of mathematical proof questions, and providing a reliable premise foundation for subsequent chain break location, scoring calculation, and repair suggestion generation.

[0177] Please see Figure 5 Step 140 above includes: Step 141: Determine the proof premise indicated by the first node and the proof objective indicated by the second node as logical constraint formulas; Step 142: Input the logic constraint formula into the logic solver so that the logic solver can solve for whether there exists an assignment combination that satisfies the premise of the first node being true and the objective of the second node being false. Step 143: If the logic solver returns that an assignment combination exists, then the assignment combination is determined as the target proof by contradiction.

[0178] Specifically, the automatic grading schemes for mathematical proof questions in related technologies mostly rely on text similarity comparison or semantic judgment of large models. They can only compare the similarity between the student's answer and the reference answer from a superficial level. However, this verification method is difficult to distinguish between equivalent reasoning and logical errors. It is easy to misjudge legitimate derivations that are different in expression but logically consistent as wrong, and it may also misjudge reasoning with substantial flaws as correct, resulting in a high misjudgment rate.

[0179] Based on this, in some embodiments provided in this application, the electronic device can transform the confirmed premises of proof and the proof target to be verified into a standardized logical constraint formula, input it into a logic solver to perform formal solution, and verify whether there is a case of "the premise is true but the conclusion is false" by traversing all legal assignment combinations. If it exists, the corresponding assignment combination is determined as the target proof by contradiction, thereby transforming semantic similarity judgment into reproducible formal logical verification, and realizing rigorous verification of the logical validity of the reasoning steps.

[0180] In some embodiments, logical constraint formulas can be understood as symbolic expressions that transform the premises and conclusions of mathematical propositions according to formal logic rules. They can transform the premises and conclusions to be proved described by natural language and mathematical formulas into a standardized form that can be recognized and operated by a logic solver, and can accurately reflect the logical derivation relationship between the premise set and the conclusion.

[0181] In some examples, for reasoning scenarios involving triangle congruence, the premises such as "AB=AC" and "∠B=∠C" and the conclusion "△ABD≌△ACD" can be symbolically encoded and transformed into corresponding logical constraint expressions, thus clarifying the derivation correspondence between premises and conclusions.

[0182] In some embodiments, a logic solver can be understood as a professional computing tool with the ability to solve logical constraints. It can traverse all possible combinations of variable assignments based on given logical constraints, determine the satisfiability of the constraint set, and output the corresponding solution.

[0183] In some examples, the logic solver can employ a satisfiability modular theory solver, which can support proposition verification in multiple mathematical fields such as geometry and algebra, and can accurately solve the logical validity of propositions under given premise constraints.

[0184] In some embodiments, the assignment combination can be understood as the combination result formed by assigning true or false values ​​to each propositional variable in the logical constraint formula. In the proof scenario, it corresponds to the combination of states that are true or false for each premise and conclusion proposition.

[0185] In some examples, the constraint formula for determining triangle congruence can be assigned to combinations of true and false states such as "AB=AC is true, BD=CD is false, triangle congruence is false", which can be used to characterize different propositional conditions.

[0186] In some embodiments, target proof by contradiction can be understood as a counterexample that can prove the current reasoning step is invalid, that is, an assignment combination that satisfies all proven premises as true but the conclusion to be proved as false. It can definitively determine that there is a substantial logical break in the corresponding reasoning step and is the direct objective basis for the determination of the break.

[0187] In some examples, when students use the SSA condition to determine triangle congruence, the geometric configuration that satisfies the condition that two sides and one of the angles opposite one side are equal but the triangles are not congruent is the corresponding objective proof by contradiction, which can directly prove that the reasoning step is not valid.

[0188] To more clearly illustrate the judgment process of the target counter-evidence in the embodiments of this application, please refer to the following exemplary description: Once the electronic device completes the matching of the response data with the nodes of the hypergraph of the proof obligation, and determines the matched first node and the unmatched second node, the electronic device can extract all the proof premises corresponding to the first node and the proof target to be verified corresponding to the second node. Following the normative expression rules of formal logic, it performs symbolic transformation, unifying the propositions described in natural language and mathematical formulas into logical constraint formulas recognizable by the logic solver. During the transformation process, all premise propositions corresponding to the first node are set as tautological constraints, and the conclusion propositions corresponding to the second node are treated as objects to be verified, fully preserving the logical derivation relationship between the premise set and the conclusion.

[0189] Subsequently, the electronic device inputs the constructed logical constraint formula into the logic solver. Under the fixed constraint that "all premises of the first node are true," the logic solver iterates through all legal variable assignment combinations to determine whether there exists an assignment that makes the proof target corresponding to the second node false. For example, in a scenario where a student uses the SSA condition to determine triangle congruence, the logic solver, under the premise constraint that "two sides and the angle opposite one of them are equal," iterates through all possible triangle configuration parameters to verify whether there are cases where the premise is satisfied but the triangles are not congruent.

[0190] Finally, the electronic device makes a judgment based on the return result of the logic solver. Specifically, if the logic solver returns that there is an assignment combination that satisfies the conditions, it is determined that there is a target proof by contradiction, and the assignment combination is identified as the target proof by contradiction, indicating that there is a substantial logical break in the corresponding reasoning step. If the logic solver returns that there is no assignment combination that satisfies the conditions, it is determined that there is no target proof by contradiction, and the corresponding reasoning step is logically valid.

[0191] Thus, in this embodiment of the application, the proof premise indicated by the first node and the proof target indicated by the second node can be determined as a logical constraint formula, and the logical constraint formula can be input into a logic solver so that the logic solver can solve whether there exists an assignment combination that satisfies the proof premise corresponding to the first node being true and the proof target corresponding to the second node being false. If the logic solver returns that there exists an assignment combination, the assignment combination is determined as the target proof by contradiction. This allows the validity of the reasoning steps to be determined from the logical essence, thereby accurately identifying substantive logical loopholes such as theorem misuse and insufficient premises, and can also be compatible with legal derivations that are different in expression but logically equivalent, reducing the error rate in the correction.

[0192] Furthermore, the generated target counter-proof can be directly used as an objective basis for determining chain breaks, thereby improving the rigor, interpretability, and credibility of the grading results. This provides solid logical support for subsequent error type labeling, score deduction, and repair suggestion generation, meeting the high-precision grading needs of strong logic problems such as mathematical proofs.

[0193] In some embodiments provided in this application, the method for grading questions further includes: determining the proof failure type corresponding to the answer data based on the assignment combination returned by the logic solver, wherein the proof failure type includes at least one of premise jump, theorem mismatch, and calculation error.

[0194] Specifically, in scenarios involving automated grading of mathematical proofs, relevant technologies typically only identify logical breaks in the answers and output a general logical error judgment, failing to differentiate the specific causes of these breaks. Consequently, students cannot clearly determine whether their errors stem from omitted premises, misuse of theorems, or calculation mistakes, and teachers also find it difficult to pinpoint students' knowledge weaknesses based on the grading results, thus limiting the educational guidance value of the grading results.

[0195] Based on this, in some embodiments provided in this application, the causes of chain breaks can be matched and classified based on the assignment combinations returned by the logic solver, and the proof failure types such as premise jumps, theorem mismatches, and calculation errors can be determined, thereby realizing the determination of the causes of logic chain breaks and improving the interpretability and teaching assistance value of the grading results.

[0196] In some embodiments, the proof failure type can be understood as a category label obtained by classifying the specific causes of logical breaks in students' answers. It is used to identify the reasons for reasoning failure, help users quickly understand the nature of the error, and support the generation of subsequent error diagnosis and repair suggestions.

[0197] In some embodiments, premise jump can be understood as a failure where a student misses the necessary proof premises required to derive the conclusion during the reasoning process, and directly derives the corresponding conclusion without complete preconditions, resulting in an incomplete reasoning chain.

[0198] In some examples, when students used the SSS theorem to prove triangle congruence, they did not mention the premise of a common side and directly derived congruence based on two sets of equal sides. This is a failure of the premise-skipping type, corresponding to the situation where students omitted the necessary derivation premise in their answers.

[0199] In some embodiments, theorem mismatch can be understood as a student incorrectly applying a mathematical theorem or reasoning rule that is not applicable to the current scenario, where the applicable conditions of the theorem do not match the currently proven premises, resulting in a failure type in which the derivation conclusion lacks logical validity.

[0200] In some examples, students use the SSA condition to determine whether two triangles are congruent. However, SSA is not a valid triangle congruence theorem. Even if all the premises of the statement are met, the conclusion cannot be guaranteed to be true. This is a failure of the theorem mismatch type.

[0201] In some embodiments, calculation errors can be understood as errors made by students in numerical calculations, formula transformations, symbolic operations, etc., during the reasoning process, resulting in intermediate derivation results deviating from the correct values ​​and the final conclusion being invalid.

[0202] In some examples, students fail to prove algebraic identities because of errors in the calculation of signs when combining like terms, resulting in subsequent derivations that do not match the conclusion to be proven. This is a type of failure due to calculation errors.

[0203] To more clearly illustrate the process for determining the failure type in the embodiments of this application, please refer to the following exemplary description: Once the logic solver successfully solves and returns an assignment combination that makes the proved premises true and the target conclusion false, the electronic device can parse the structural information of the assignment combination, extract the set of valid premises marked as true, the target conclusion marked as false, and the mathematical theorems and reasoning rules cited by the student in the current reasoning step.

[0204] Subsequently, the electronic device compares the set of valid premises in the assignment combination with the set of complete necessary premises required by the current reference theorem. If the set of valid premises is missing a key necessary premise, and the target conclusion can be changed from false to true after the missing premise is added in the assignment combination, then the broken chain is determined to be a premise jump type, corresponding to the student's answer that omits necessary premises and directly skips steps in the derivation.

[0205] If the comparison shows that all the premises required for the theorem cited by the student have been set to true in the assignment combination, but the logical rules of the theorem itself cannot support the derivation from premises to conclusion, that is, the theorem can still construct a counterexample that does not hold true even if all the premises are satisfied, then it is judged as a theorem mismatch type, corresponding to the student's answer that incorrectly applies the theorem.

[0206] If the premise set and the theorem reference are correct, but the numerical or expression result of the intermediate operation shown by the assignment combination deviates from the corresponding result of the correct derivation path, and this operational deviation directly leads to the final conclusion being invalid, then it is judged as a calculation error type, corresponding to the student's answer of calculation error.

[0207] After the type determination is completed, the electronic device will bind and store the corresponding proof failure type label with the broken chain location and local conflict witness information, as the basis for generating subsequent correction reports and repair suggestions.

[0208] Thus, in this embodiment of the application, the type of proof failure corresponding to the answer data can be determined based on the assignment combination returned by the logic solver. This allows the cause of the logical chain break to be determined, enabling students to clearly understand the root cause of their reasoning chain break and make targeted corrections and knowledge supplements. It also enables teachers to quickly grasp the common error types and knowledge weaknesses of students and optimize teaching content and review focus.

[0209] Furthermore, the type determination based on the logical solution results has a unified objective standard, which can ensure the consistency and accuracy of error classification among different answers, and can improve the interpretability and educational guidance value of the grading results, further expanding the teaching assistance capabilities of the automatic grading electronic device.

[0210] In some embodiments provided in this application, the method for grading questions further includes: determining whether the solution time of the logic solver for the logic constraint formula is greater than a preset timeout threshold; if the solution time is determined to be greater than the preset timeout threshold, generating a manual review request, obtaining feedback data of the manual review request, and determining whether the target counter-proof exists.

[0211] Specifically, considering the significant differences in the logical constraint complexity of various mathematical proof problems, some complex constraints involving nested branches and multi-level reasoning can cause a surge in the computational load of the logic solver, potentially leading to excessively long solution times and prolonged blocking of the grading process. Therefore, if electronic devices continuously wait for the solver's output, it will slow down the grading speed of individual problems to some extent, reducing the concurrent processing capacity of the electronic devices and the overall grading efficiency. Conversely, if a timeout is immediately followed by a default judgment that the target proof exists, it will introduce a large number of false positives, compromising the accuracy of the grading results.

[0212] Based on this, in some embodiments provided in this application, a preset timeout threshold can be set for the solution process of the logic solver to monitor the solution time in real time. When the solution time exceeds the threshold, the automatic solution is terminated and a manual review request with complete context is generated for manual review and judgment. Finally, the existence of the target counter-evidence is determined based on the manual feedback data, thereby constructing a processing mechanism with automatic solution as the main method and manual backup as the auxiliary method.

[0213] In some embodiments, the preset timeout threshold can be understood as the maximum allowed solution time of the logic solver, which is used to define the time boundary of automatic solution. The value can be flexibly configured in combination with the computing power level of electronic devices, the average complexity of the problem type and the real-time requirements of the business.

[0214] In some examples, the preset timeout threshold can be set to 3 seconds to accommodate the time required to solve most common mathematical proof problems, thus controlling the processing time of a single problem while ensuring the completion rate of the solution.

[0215] In some embodiments, the solution time can be understood as the cumulative computation and processing time of the logic solver from the time it receives the logic constraint formula to the current time. It can be obtained in real time by the timing module built into the electronic device and compared with the preset timeout threshold to determine whether the current solution task exceeds the reasonable range of automatic processing.

[0216] In some embodiments, a manual review request can be understood as instruction data generated by an electronic device after the solution timeout, which is used to trigger the manual review process. The request can carry complete contextual content such as the logical constraint formula to be judged, the corresponding question information, the student's answer data, and the matched node information. It can be pushed to the manual review pool so that the reviewers can quickly obtain complete information and make a judgment.

[0217] In some examples, manual review requests can include annotations such as the position of the current reasoning step in the proof obligation hypergraph and the set of premises that have been confirmed, to help reviewers quickly locate questionable parts and improve review efficiency.

[0218] In some embodiments, feedback data can be understood as the judgment result data issued by human reviewers for questionable reasoning steps, including whether there is target counter-evidence, description of the corresponding broken chain type, supplementary judgment basis, etc.

[0219] Thus, in this embodiment, it can be determined whether the solution time of the logic solver for the logic constraint formula exceeds a preset timeout threshold. If the solution time exceeds the preset timeout threshold, a manual review request is generated, and feedback data from the manual review request is obtained to determine whether the target counter-evidence exists. This avoids process blockage caused by complex constraints, thereby improving batch grading efficiency. Furthermore, manual review can be used to cover complex scenarios that exceed the automatic processing capacity, avoiding misjudgments caused by blind judgment and ensuring the accuracy of the grading results.

[0220] Please see Figure 6 Step 150 above includes: Step 151: Obtain multiple standard proof paths corresponding to each solution method in the reference answer in the proof obligation hypergraph, and the preset score bound to each hyperedge respectively. Each standard proof path is composed of at least some nodes and hyperedges in the proof obligation hypergraph in the order of reasoning. The preset score is determined in advance according to the scoring criteria of the target question. Step 152: Organize multiple standard proof paths into a mesh topology; Step 153: Based on the judgment result of the target proof by contradiction, the first node and the second node, determine the reasoning path corresponding to the answer data in the network topology, and the abnormal node in the reasoning path corresponding to the second node; Step 154: Determine the edge-level score weight of each hyperedge in the reasoning path based on the hyperedge in-degree and preset score of the hyperedge corresponding to the abnormal node. The hyperedge in-degree is used to indicate the number of proof premises that the mathematical theorem and reasoning rule corresponding to the hyperedge must satisfy. Step 155: Based on the edge-level score weights and the judgment results of the objective proof by contradiction, determine the score deduction for each super-edge, and generate the score details for each step in the answer data and the total score of the answer data based on the score deduction.

[0221] Specifically, in the intelligent grading schemes for mathematical proof questions proposed by related technologies, the scoring mechanism is often decoupled from the logical structure of the proof. Step-by-step scores are often treated as external supplementary text independent of the reasoning process, and scores are only awarded based on a fixed standard answer step-by-step matching. Understandably, this scoring model cannot accommodate situations where students employ multiple legitimate proof paths, such as equivalent derivation or adjustments to the order of steps, and is prone to scoring biases due to inconsistencies between the answer format and the standard answer. Furthermore, it fails to reflect the differences in logical complexity between different reasoning steps, and the score allocation is mismatched with the degree of dependency and logical depth of the steps.

[0222] Based on this, in some embodiments provided in this application, the electronic device can extract standard proof paths corresponding to multiple problem-solving methods from the constructed proof obligation hypergraph and integrate them into a mesh topology, matching the reasoning path corresponding to the student's answer and locating abnormal nodes. Subsequently, the edge-level score weight of each hyperedge is calculated by combining the in-degree of the hyperedge and the preset score, and then the score deduction is determined based on the target proof by contradiction result. Finally, a step-level scoring detail and a total score are generated, realizing fine-grained edge-level scoring compatible with multiple equivalent proof paths.

[0223] In some embodiments, a standard proof path can be understood as the logical link of each complete solution in the corresponding reference answer, which is formed by connecting some nodes and hyperedges in the hypergraph of proof obligation in the forward reasoning order, representing a logically consistent and complete reasoning process that can be proven.

[0224] In some examples, for the problem of "proving that the median on the base of an isosceles triangle is perpendicular to the base", the proof path based on SSS congruence criteria and the proof path based on SAS congruence criteria can each be regarded as an independent standard proof path.

[0225] In some embodiments, a mesh topology can be understood as a branched network structure formed by integrating multiple standard proof paths, which can accommodate all legal equivalent proof branches and thus reflect the association relationship between common nodes and alternative hyperedges of different proof paths.

[0226] In some examples, in the geometric proof problem mentioned above, the two proof paths SSS and SAS share the first and last nodes such as "AB=AC" and "AD⊥BC", and the superedges that determine equality in the middle are interchangeable. After integration, they form a mesh topology structure containing two branches.

[0227] In some embodiments, the reasoning path can be understood as the logical link corresponding to the student's actual answer. It is a combination of nodes and hyperedges matched from the mesh topology that fits the evidence of the student's answer and can reflect the student's problem-solving ideas and derivation process.

[0228] In some examples, students use the SSS approach to deduce their answers. In this case, the link obtained by the electronic device, consisting of the corresponding premise node, the equality judgment hyperedge, and the conclusion node, is the reasoning path corresponding to that answer.

[0229] In some embodiments, an abnormal node can be understood as the proof target node corresponding to the second node in the reasoning path, that is, the node where the student's answer did not complete the evidence matching and was determined to have a logical break.

[0230] In some examples, the student misuses the theorem in the congruence determination step, causing the congruence conclusion node to be invalid. In this case, the congruence conclusion node is an abnormal node in the reasoning path.

[0231] In some embodiments, the in-degree of a hyperedge can be understood as the number of proof premises that a mathematical theorem or reasoning rule corresponding to a hyperedge needs to satisfy, that is, the number of prerequisite nodes that need to be relied upon to derive the conclusion corresponding to the hyperedge, which can reflect the logical complexity of the corresponding reasoning steps.

[0232] In some examples, the SSS congruence determination of a superedge requires a prerequisite node where all three edges are equal, and the in-degree of that superedge is 3.

[0233] In some embodiments, the edge-level score weight can be understood as the weight of each hyperedge in the overall score, which is determined by combining the preset base score of the hyperedge with the logical complexity.

[0234] In some examples, congruent superedges with higher in-degree and more complex logic will have higher edge-level score weights compared to a single premise recognition step.

[0235] In some embodiments, the score deduction can be understood as the number of points that need to be deducted from the corresponding super-edge due to problems such as logical chain breakage or lack of evidence, which is directly related to the weight ratio of the super-edge and the severity of the chain breakage.

[0236] In some examples, if a superedge in the equality determination has a substantial logical break, the corresponding score deduction is determined based on the edge-level score weight of that superedge.

[0237] In some embodiments, the scoring details can be understood as a record of scores for each proof step, with the score and deduction for each reasoning hyperedge, clearly showing the scoring details for each step.

[0238] In some examples, the scoring details can sequentially display the scores and reasons for deductions for each step, such as premise identification, equality determination, and vertical conclusion.

[0239] To more clearly illustrate the edge-level scoring process in the embodiments of this application, please refer to the following exemplary description: The electronic device first extracts multiple standard proof paths corresponding to various problem-solving methods from the reference answers based on the constructed hypergraph of proof obligations. Each path is formed by connecting nodes and hyperedges within the hypergraph in a forward reasoning order. At the same time, it obtains the preset score pre-bound to each hyperedge. This preset score is converted from the step-by-step scoring standard of the question and corresponds to the basic assessment score for each reasoning step.

[0240] Subsequently, the electronic device integrates the extracted standard proof paths and organizes them into a mesh topology, so that the common nodes and replaceable hyperedges in different paths form an interconnected network, thereby carrying all legal equivalent proof branches.

[0241] After the topology structure is constructed, the electronic device combines the judgment results of the obtained target proof by contradiction and the location results of the first and second nodes to match the reasoning path corresponding to the student's answer in the mesh topology structure. At the same time, it marks all abnormal nodes in the reasoning path and clarifies the specific location and scope of impact of the logical break.

[0242] Next, the electronic device calculates the edge-level score weight of each hyperedge in the reasoning path. This is done by taking the hyperedge's in-degree and its associated preset score as input, and then performing a weighted average to obtain the corresponding edge-level score weight. A higher hyperedge in-degree indicates more preconditions and greater logical complexity for that reasoning step, resulting in a correspondingly higher score weight. This ensures that the score allocation matches the logical difficulty of the steps, avoiding the irrationality of simply assigning scores equally.

[0243] Finally, the electronic device generates the final score. Specifically, based on the judgment result of the target proof by contradiction and the distribution of abnormal nodes, the score deduction for each hyperedge is determined. For hyperedges with complete evidence and no logical breaks, the corresponding score is retained according to the weight; for hyperedges confirmed by contradiction to have logical breaks, the corresponding score is deducted according to the edge-level weight of that hyperedge.

[0244] After the electronic device summarizes the scores of all hyperedges, it generates a detailed breakdown of the scores for each proof step in the answer data, as well as the total score for the entire question, and completes the score output.

[0245] Thus, in this embodiment, multiple standard proof paths can be organized into a mesh topology. Based on the judgment result of the target proof by contradiction, the first node, and the second node, the reasoning path corresponding to the answer data in the mesh topology is determined, as well as the abnormal node corresponding to the second node in the reasoning path. Based on the in-degree of the hyperedge corresponding to the abnormal node and the preset score, the edge-level score weight of each hyperedge in the reasoning path is determined. Based on the edge-level score weight and the judgment result of the target proof by contradiction, the score deduction of each hyperedge is determined. Based on the score deduction, the scoring details of each step in the answer data and the total score of the answer data are generated. This allows the scoring mechanism to be bound to the proof logic of the question, and the complexity difference of different reasoning steps can be reflected through the edge-level weight. At the same time, the mesh topology is compatible with multiple equivalent proof paths, ultimately improving the rationality of score allocation and the accuracy of scoring, and can adapt to diverse answering ideas.

[0246] In some embodiments provided in this application, step 154 ​​above includes: weighting the in-degree of the superedge corresponding to the abnormal node and the preset score to obtain the edge-level score weight.

[0247] Specifically, in some embodiments provided in this application, when calculating the edge-level score weight of the hyperedge in the reasoning path, the electronic device can use the hyperedge in-degree of the hyperedge corresponding to the abnormal node and the bound preset score as input parameters, and integrate the logical complexity dimension and the basic assessment score dimension through weighted processing. The influence ratio of the two is adjusted by the preset weight coefficient to obtain the final edge-level score weight, thereby realizing the quantitative binding of the score weight and the logical complexity of the reasoning steps, and thus improving the rationality of score allocation and the objectivity of scoring.

[0248] In some embodiments, weighted processing can be understood as assigning corresponding weight coefficients to multiple input parameters and then merging the multiple parameters into a single output value through weighted operation. The influence of each parameter on the final result can be flexibly controlled by adjusting the weight coefficients.

[0249] In some examples, for the problem "Prove that the median on the base of an isosceles triangle is perpendicular to the base", the superedge in the SSS congruence determination has an in-degree of 3 and a preset score of 4. The electronic device can assign a weight coefficient of 0.3 to the in-degree of the superedge and a weight coefficient of 0.7 to the preset score. The edge-level score weight of the superedge is obtained by weighted summation.

[0250] In some embodiments, the weighting coefficients can be flexibly configured according to the question type and assessment focus. For example, for geometric proof questions that focus on logical deduction assessment, the weighting coefficient of the in-degree of the hyperedge can be appropriately increased, and for basic proof questions that focus on basic steps assessment, the weighting coefficient of the preset score can be appropriately increased to ensure that the scoring rules match the assessment objectives.

[0251] Thus, in this embodiment of the application, the in-degree of the hyperedge corresponding to the abnormal node and the preset score can be weighted to obtain the edge-level score weight, thereby realizing the quantification of the edge-level score weight, which can improve the reliability of the scoring results to a certain extent.

[0252] In some embodiments provided in this application, the grading results also include modification prompt information. Furthermore, the grading method for the questions further includes: determining the shortest repair path in the mesh topology from the abnormal node to the nearest valid node, wherein the valid node matches the target proof method type corresponding to the answer data; and generating modification prompt information for the answer data based on the shortest repair path.

[0253] Specifically, most intelligent grading schemes for mathematical proofs proposed in related technologies focus on score output, with error feedback generally being rather general. They either only provide vague evaluations like "logical error" or directly copy the complete standard answer path, requiring the respondent to rewrite their original answer. Understandably, this feedback method struggles to accurately guide the respondent to fill in the gaps in their reasoning chain, leaving them unclear about specific areas for correction, thus limiting the grading results' educational value.

[0254] Based on this, in some embodiments provided in this application, the electronic device can, after locating the abnormal node in the response, filter the valid nodes that match the current response proof method type within the mesh topology, calculate the shortest repair path from the abnormal node to the nearest valid node, and generate targeted modification prompts accordingly, providing the respondent with executable correction guidance that fits their proof ideas.

[0255] In some embodiments, the modification prompt information can be understood as the prompt content in the grading results used to guide the respondent to correct the logic of the answer and fill in the gaps in the reasoning. It can clearly mark the location of the error, explain the reason for the problem, and give specific directions for correction and supplementary steps to help the respondent complete the proof correction based on their original answer.

[0256] In some examples, the modified prompt message can be expressed as "SSA cannot be used for the congruence determination. It is recommended to add the condition BD=CD and use the SSS theorem to complete the congruence proof."

[0257] In some embodiments, a valid node can be understood as a proof node in a mesh topology that is logically valid, compatible with the type of target proof method used in the answer, and can serve as the endpoint for repair, representing a correct conclusion node that the respondent can reach through reasonable deduction and that conforms to the current proof paradigm.

[0258] In some examples, when the respondent uses the direct proof paradigm and a broken link occurs, the node "△ABD≌△ACD" within the same direct proof path is a valid matching node. The corresponding node under the proof by contradiction branch is not a valid node in this scenario because the proof paradigm does not match.

[0259] In some embodiments, the shortest repair path can be understood as the link that requires the fewest additional reasoning steps and has the shortest logical jump distance from the abnormal node to the nearest matching valid node, corresponding to the minimum logical cost that the respondent needs to pay to correct the current error.

[0260] In some examples, the respondent's congruence determination is broken only because the common edge premise "AD=AD" is missing. Adding this premise will restore the link to the valid node of "triangle congruence", which is the shortest repair path in this scenario, without changing the overall proof method.

[0261] To more clearly illustrate the process of generating modification prompt information in the embodiments of this application, please refer to the following exemplary description: First, the electronic device performs a graph search operation within the mesh topology based on the located abnormal nodes. During the search, a proof paradigm matching constraint is set, only nodes that match the target proof method type corresponding to the response data are considered as valid candidate nodes. This ensures that the final repair path conforms to the proof paradigm currently used by the respondent and does not lead the respondent to switch to other proof methods. This guarantees that the repair suggestion is consistent with the respondent's original thinking and avoids a break in the thought process.

[0262] Next, the electronic device uses a graph search algorithm to calculate the logical path length between each candidate valid node and the abnormal node, filters out the closest valid node, and determines the shortest repair path from the abnormal node to that valid node. This path corresponds to the fewest supplementary reasoning steps and the lowest correction cost, enabling the respondent to complete the logical chain and proof derivation with minimal adjustment cost.

[0263] Finally, the electronic device generates corresponding modification prompts based on the determined shortest repair path. These prompts clearly indicate the preconditions that need to be supplemented, the application of theorems that need to be corrected, and the intermediate reasoning steps that need to be completed. This clearly guides the respondent to complete the logical completion and error correction along their own proof logic, providing targeted, heuristic guidance.

[0264] Thus, in this embodiment, based on the abnormal node, the shortest repair path from the abnormal node to the nearest valid node in the mesh topology can be determined. Based on this shortest repair path, modification prompts for the answer data are generated. This generates correction guidance tailored to the respondent's own proof logic, avoiding the rigid feedback of directly outputting the standard answer. It allows the respondent to correct their work based on completed valid reasoning, improving the interpretability and educational value of the grading results. Simultaneously, the shortest repair path, guided by the principle of minimizing correction cost, can guide the respondent to complete the logical chain with minimal adjustment effort, helping to cultivate their logical reasoning and self-correction abilities, achieving true heuristic learning guidance.

[0265] All of the above technical solutions can be combined in any way to form optional embodiments of this application, and will not be described in detail here.

[0266] To facilitate better implementation of the title correction method in the embodiments of this application, the embodiments of this application also provide a title correction device. Please refer to... Figure 7 , Figure 7 A schematic diagram of the structure of a problem correction device provided in an embodiment of this application. The problem correction device 300 may include: The question acquisition module 310 is used to acquire the target question, as well as the conclusion to be proven, the answer data, and the reference answer of the target question; The hypergraph construction module 320 is used to construct a proof obligation hypergraph based on the target question, the conclusion to be proved, and the reference answer. The proof obligation hypergraph includes nodes and hyperedges. At least one node is connected to at least another node through a hyperedge. The node is used to indicate the proof target or proof premise corresponding to each step in the reference answer. The hyperedge is used to indicate the mathematical theorems and / or reasoning rules satisfied between the connected nodes. The node determination module 330 is used to match the answer data with the nodes in the proof obligation hypergraph, and determine the first node and the second node in the proof obligation hypergraph based on the matching result. The hyperedge connected to the first node matches the answer data, while the hyperedge connected to the second node does not match the answer data. The proof-of-contrast module 340 is used to determine whether there is a target proof-of-contrast based on the first node and the second node, wherein in the target proof-of-contrast, the premise of the proof corresponding to the first node is true and the target of the proof corresponding to the second node is false; The generation module 350 is used to generate the grading results of the answer data based on the judgment result of the target proof by contradiction, the first node, and the second node.

[0267] In some embodiments, the node determination module 330 is further configured to determine the target proof method type corresponding to the response data, load the target inference rule set corresponding to the target proof method type, and match the response data with nodes in the proof obligation hypergraph according to the target inference rule set, and determine the first node and the second node based on the matching result. The target inference rule set is used to determine the nodes and hyperedges in the proof obligation hypergraph that need to have their matching relationship with the response data determined.

[0268] In some embodiments, the node determination module 330 is further configured to construct a target identification model for identifying proof method types, extract logical indicator words from the response data to indicate proof step transitions or branches, and input the logical indicator words into the target identification model to obtain the target proof method type output by the target identification model.

[0269] In some embodiments, the target identification model includes a finite state machine. Furthermore, the node determination module 330 is also configured to input logical indicators into the finite state machine, so that the finite state machine, through the logical indicators, determines at least one of multiple proof method types as an active state, and determines the proof method type in the active state as the target proof method type.

[0270] In some embodiments, the node determination module 330 is further configured to perform feature extraction processing on the response data to obtain the evidence features corresponding to the response data, and to construct a mapping relationship between the evidence features and nodes in the proof obligation hypergraph to obtain evidence-node mapping relationship data, and to determine the first node that matches the evidence entity and the second node that does not match the evidence entity based on the evidence-node mapping relationship data. The evidence features include the evidence entity, the position of the evidence entity in the response data, and its confidence level. The evidence entity is a textual, formulaic, or graphical element in the response data used to indicate the premise of proof or intermediate conclusion, and the confidence level is used to indicate the degree of credibility of the match between the evidence entity and the node.

[0271] In some embodiments, the response data includes at least two of text modal information, formula modal information, and graphical modal information. Furthermore, the node determination module 330 is also used to input the response data into a pre-trained multimodal information processing model, so that the multimodal information processing model performs feature extraction processing on each modal information in the response data to obtain evidence features.

[0272] In some embodiments, the node determination module 330 is further configured to establish a correspondence between evidence entities with a confidence level greater than a preset confidence threshold and the corresponding nodes in the proof obligation hypergraph.

[0273] In some embodiments, the node determination module 330 is further configured to determine nodes with established correspondence as first nodes and nodes without established correspondence as second nodes.

[0274] In some embodiments, the correction device further includes a hyperedge indication information determination module, a precondition determination module, a precondition judgment module, a relevance determination module, and a node update module. The hyperedge indication information determination module is used to obtain the target mathematical theorem and / or target inference rule indicated by the hyperedge connected to the second node. The precondition determination module is used to determine the target preconditions that the target mathematical theorem and / or target inference rule must satisfy. The precondition judgment module is used to determine whether the evidence entity contains the target preconditions. The relevance determination module is used to determine the relevance parameter between the first node and the missing preconditions in the target preconditions that are not contained in the evidence entity if the evidence entity contains part of the target preconditions. The node update module is used to update the second node to the first node if the relevance parameter is higher than a preset threshold.

[0275] In some embodiments, the relevance determination module is further configured to determine the shortest path distance between the node corresponding to the missing precondition and the first node through a preset knowledge graph, and to determine the semantic relevance between the missing precondition and the evidence entity corresponding to the first node, and to determine a relevance parameter based on the shortest path distance and / or the semantic relevance. The preset knowledge graph is used to store the association relationships between multiple preconditions.

[0276] In some embodiments, the proof-of-contrast judgment module 340 is further configured to determine the proof premise indicated by the first node and the proof target indicated by the second node as a logical constraint formula, and input the logical constraint formula to the logic solver so that the logic solver can solve for whether there is an assignment combination that satisfies the proof premise corresponding to the first node being true and the proof target corresponding to the second node being false, and if the logic solver returns that there is an assignment combination, then the assignment combination is determined as the target proof-of-contrast.

[0277] In some embodiments, the grading apparatus further includes a failure type determination module. The failure type determination module is used to determine the proof failure type corresponding to the answer data based on the assignment combination returned by the logic solver, wherein the proof failure type includes at least one of premise jump, theorem mismatch, and calculation error.

[0278] In some embodiments, the correction device further includes a timeout determination module and a feedback data acquisition module. The timeout determination module is used to determine whether the solution time of the logic solver for the logic constraint formula is greater than a preset timeout threshold. The feedback data acquisition module is used to generate a manual review request if the solution time is determined to be greater than the preset timeout threshold, and to acquire the feedback data of the manual review request to determine whether the target counter-evidence exists.

[0279] In some embodiments, the generation module 350 is further configured to obtain multiple standard proof paths corresponding to each solution method in the reference answer in the proof obligation hypergraph, and preset scores bound to each hyperedge respectively; organize the multiple standard proof paths into a mesh topology; determine the reasoning path corresponding to the answer data in the mesh topology based on the judgment result of the target proof by contradiction, the first node, and the second node; determine the abnormal node corresponding to the second node in the reasoning path; determine the edge-level score weight of each hyperedge in the reasoning path based on the hyperedge in-degree of the hyperedge corresponding to the abnormal node and the preset score; determine the score deduction of each hyperedge based on the edge-level score weight and the judgment result of the target proof by contradiction; and generate the scoring details of each step in the answer data and the total score of the answer data based on the score deduction. Each standard proof path is composed of at least some nodes and hyperedges in the proof obligation hypergraph in the reasoning order. The preset score is predetermined according to the scoring criteria of the target question. The hyperedge in-degree is used to indicate the number of proof premises that the mathematical theorem and reasoning rule corresponding to the hyperedge must satisfy. In some embodiments, the generation module 350 is further used to perform weighted processing on the hyperedge in-degree and preset score of the hyperedge corresponding to the abnormal node to obtain the edge-level score weight.

[0280] In some embodiments, the grading result further includes modification prompt information. Furthermore, the grading device further includes a path determination module and a prompt determination module. The path determination module is used to determine the shortest repair path in the mesh topology from the abnormal node to the nearest valid node, wherein the valid node matches the target proof method type corresponding to the answer data. The prompt determination module is used to generate modification prompt information for the answer data based on the shortest repair path.

[0281] Each unit in the above-mentioned grading device 300 can be implemented entirely or partially through software, hardware, or a combination thereof. Each unit can be embedded in or independent of the processor in the electronic device in hardware form, or stored in the memory of the electronic device in software form, so that the processor can call and execute the operations corresponding to each unit.

[0282] The question grading device 300 can be integrated into a terminal or server that has storage and a processor and thus computing power, or the question grading device 300 can be the terminal or server.

[0283] Optionally, this application also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps in the above-described method embodiments.

[0284] Figure 8This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device may be a terminal or a server. Figure 8 As shown, the electronic device 400 includes a processor 401 with one or more processing cores, a memory 402 with one or more computer-readable storage media, and a computer program stored in the memory 402 and executable on the processor. The processor 401 and the memory 402 are electrically connected. Those skilled in the art will understand that the electronic device structure shown in the figures does not constitute a limitation on the electronic device, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0285] The processor 401 is the control center of the electronic device 400. It connects various parts of the electronic device 400 through various interfaces and lines. By running or loading software programs and / or modules stored in the memory 402, and calling data stored in the memory 402, it executes various functions of the electronic device 400 and processes data, thereby performing overall processing of the electronic device 400.

[0286] In this embodiment, the processor 401 in the electronic device 400 loads the instructions corresponding to the processes of one or more computer programs into the memory 402 according to the following steps, and the processor 401 runs the computer programs stored in the memory 402 to realize various functions: Obtain the target question, along with the conclusion to be proven, the answer data, and the reference answer; Based on the target question, the conclusion to be proved, and the reference answer, a proof obligation hypergraph is constructed. The proof obligation hypergraph includes nodes and hyperedges. At least one node is connected to at least another node through a hyperedge. The nodes are used to indicate the proof target or proof premise corresponding to each step in the reference answer. The hyperedges are used to indicate the mathematical theorems and / or reasoning rules satisfied between the multiple connected nodes. The response data is matched with the nodes in the proof obligation hypergraph, and the first and second nodes in the proof obligation hypergraph are determined based on the matching results. The hyperedges connected to the first node match the response data, while the hyperedges connected to the second node do not match the response data. Based on the first node and the second node, determine whether there is a proof by contradiction, where the premise of the proof corresponding to the first node is true and the goal of the proof corresponding to the second node is false. Based on the judgment result of the proof by contradiction, the first node, and the second node, the grading result of the answer data is generated.

[0287] For details on the implementation of each of the above operations, please refer to the previous examples, which will not be repeated here.

[0288] Optional, such as Figure 8 As shown, the electronic device 400 also includes: a display screen 403, a radio frequency circuit 404, an audio circuit 405, an input unit 406, and a power supply 407. The processor 401 is electrically connected to the display screen 403, the radio frequency circuit 404, the audio circuit 405, the input unit 406, and the power supply 407. Those skilled in the art will understand that... Figure 7 The electronic device structure shown does not constitute a limitation on the electronic device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0289] The display screen 403 can be used to display a graphical user interface (GUI) and receive operation commands generated by the user interacting with the GUI. The display screen 403 may include a display panel and a touch panel. The display panel can be used to display information input by the user or information provided to the user, as well as various graphical user interfaces of the electronic device. These graphical user interfaces can be composed of graphics, text, icons, video, and any combination thereof. The touch panel can be used to collect touch operations performed by the user on or near it (such as operations performed by the user using a finger, stylus, or any suitable object or accessory on or near the touch panel), generate corresponding operation commands, and execute the corresponding program. Optionally, the touch panel may include a touch detection device and a touch controller. The touch detection device detects the user's touch location and the signal generated by the touch operation, and transmits the signal to the touch controller. The touch controller receives touch information from the touch detection device, converts it into touch point coordinates, sends it to the processor 401, and can receive and execute commands from the processor 401. The touch panel can cover the display panel. When the touch panel detects a touch operation on or near it, it transmits the information to the processor 401 to determine the type of touch event. Subsequently, the processor 401 provides corresponding visual output on the display panel according to the type of touch event. In this embodiment, the touch panel and the display panel can be integrated into the display screen 403 to achieve input and output functions. However, in some embodiments, the touch panel and the display screen 404 can be implemented as two independent components to achieve input and output functions. That is, the display screen 404 can also be used as part of the input unit 406 to achieve input functions.

[0290] The radio frequency circuit 404 can be used to transmit and receive radio frequency signals to establish wireless communication with network devices or other electronic devices, and to transmit and receive signals with network devices or other electronic devices.

[0291] Audio circuit 405 can be used to provide an audio interface between a user and an electronic device via a speaker and a microphone. Audio circuit 405 can convert received audio data into electrical signals and transmit them to the speaker, where the speaker converts them into sound signals for output. Conversely, the microphone converts collected sound signals into electrical signals, which are then received by audio circuit 405, converted back into audio data, and then processed by processor 401 before being transmitted via radio frequency circuit 404 to, for example, another electronic device, or output to memory 402 for further processing. Audio circuit 405 may also include an earphone jack to provide communication between peripheral headphones and electronic devices.

[0292] The input unit 406 can be used to receive input numbers, characters, or object feature information (such as fingerprints, iris, facial information, etc.), and to generate keyboard, mouse, joystick, optical, or trackball signal inputs related to user settings and function control.

[0293] Power supply 407 is used to supply power to various components of electronic device 400. Optionally, power supply 407 can be logically connected to processor 401 through a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system. Power supply 407 may also include one or more DC or AC power supplies, recharging systems, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components.

[0294] although Figure 8 As not shown in the diagram, the electronic device 400 may also include a camera, sensor, wireless fidelity module, Bluetooth module, etc., which will not be described in detail here.

[0295] This application also provides a computer-readable storage medium for storing a computer program. This computer-readable storage medium can be applied to a computer device, and the computer program causes the computer device to execute the corresponding process in the question-grading method of the embodiments of this application; for brevity, further details are omitted here.

[0296] This application also provides a computer program product including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the corresponding process in the question-grading method described in the embodiments of this application. For simplicity, further details are omitted here.

[0297] This application also provides a computer program comprising computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the corresponding process in the grading method described in this application; for brevity, this will not be elaborated further.

[0298] It should be understood that the processor in this application may be an integrated circuit chip with signal processing capabilities. In implementation, the steps of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor described above can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory, and the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0299] It is understood that the memory in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM). It should be noted that the memory used in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0300] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0301] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0302] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0303] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0304] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0305] In addition, the functional units in this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0306] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer or a server) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0307] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for grading exam questions, characterized in that, The method includes: Obtain the target question, as well as the conclusion to be proven, the answer data, and the reference answer for the target question; Based on the target question, the conclusion to be proved, and the reference answer, a proof obligation hypergraph is constructed, wherein the proof obligation hypergraph includes nodes and hyperedges, at least one node is connected to at least another node through a hyperedge, the node is used to indicate the proof target or proof premise corresponding to each step in the reference answer, and the hyperedge is used to indicate the mathematical theorems and / or reasoning rules satisfied among the connected nodes; The response data is matched with the nodes in the proof obligation hypergraph, and the first node and the second node in the proof obligation hypergraph are determined based on the matching result, wherein the hyperedge connected to the first node matches the response data, and the hyperedge connected to the second node does not match the response data; Based on the first node and the second node, determine whether there is a target proof by contradiction, wherein in the target proof by contradiction, the proof premise corresponding to the first node is true and the proof target corresponding to the second node is false; Based on the judgment result of the target counter-proof, the first node, and the second node, the grading result of the answer data is generated.

2. The method for grading questions according to claim 1, characterized in that, The step of matching the response data with nodes in the proof obligation hypergraph, and determining the first and second nodes in the proof obligation hypergraph based on the matching results, includes: Determine the target proof method type corresponding to the response data; Load the target inference rule set corresponding to the target proof method type, wherein the target inference rule set is used to determine the nodes and hyperedges in the proof obligation hypergraph that need to determine the matching relationship with the answer data; According to the target reasoning rule set, the response data is matched with the nodes in the proof obligation hypergraph, and the first node and the second node are determined based on the matching result.

3. The method for grading questions according to claim 1, characterized in that, The step of matching the response data with nodes in the proof obligation hypergraph, and determining the first and second nodes in the proof obligation hypergraph based on the matching results, includes: The response data is subjected to feature extraction processing to obtain the evidence features corresponding to the response data. The evidence features include evidence entities, the position of the evidence entities in the response data, and confidence level. The evidence entities are text, formulas, or graphic elements in the response data used to indicate the premise or intermediate conclusion of the proof. The confidence level is used to indicate the degree of credibility of the matching between the evidence entity and the node. Construct a mapping relationship between the evidence features and the nodes in the hypergraph of the proof obligation to obtain evidence-node mapping relationship data; Based on the evidence-node mapping relationship data, a first node that matches the evidence entity and a second node that does not match the evidence entity are determined.

4. The method for grading questions according to claim 3, characterized in that, The method further includes: Obtain the target mathematical theorem and / or target inference rule indicated by the hyperedge connected to the second node; Determine the target preconditions that the target mathematical theorem and / or target reasoning rule must satisfy; Determine whether the evidence entity contains the target precondition; If the evidence entity contains part of the conditions of the target premise, determine the correlation parameter between the first node and the missing premise of the target premise that is not contained in the evidence entity; If the correlation parameter is higher than the preset correlation parameter threshold, the second node is updated to the first node.

5. The method for grading questions according to claim 1, characterized in that, The step of determining whether there is a target counter-evidence based on the first node and the second node includes: The proof premise indicated by the first node and the proof objective indicated by the second node are defined as logical constraint formulas; The logical constraint formula is input into the logic solver so that the logic solver can solve for whether there exists an assignment combination that satisfies the proof premise of the first node being true and the proof objective of the second node being false. If the logic solver returns that the assignment combination exists, then the assignment combination is determined as the target proof by contradiction.

6. The method for grading questions according to claim 1, characterized in that, The step of generating the grading result of the answer data based on the judgment result of the target counter-proof, the first node, and the second node includes: Obtain multiple standard proof paths corresponding to each solution method in the reference answer from the proof obligation hypergraph, and a preset score bound to each hyperedge respectively. Each standard proof path is composed of at least some of the nodes and hyperedges in the proof obligation hypergraph in the order of reasoning. The preset score is predetermined according to the scoring criteria of the target question. The multiple standard proof paths described herein are organized into a mesh topology; Based on the judgment result of the target proof by contradiction, the first node and the second node, determine the reasoning path corresponding to the answer data in the mesh topology, and the abnormal node corresponding to the second node in the reasoning path; Based on the in-degree of the hyperedge corresponding to the abnormal node and the preset score, the edge-level score weight of each hyperedge in the reasoning path is determined, wherein the in-degree of the hyperedge is used to indicate the number of proof premises that the mathematical theorem and reasoning rule corresponding to the hyperedge need to satisfy. Based on the edge-level score weights and the judgment results of the target proof by contradiction, the score deduction for each super-edge is determined, and based on the score deduction, the scoring details for each step in the answer data and the total score of the answer data are generated.

7. A device for grading questions, characterized in that, The device includes: The question acquisition module is used to acquire the target question, as well as the conclusion to be proven, the answer data, and the reference answer of the target question; A hypergraph construction module is used to construct a proof obligation hypergraph based on the target question, the conclusion to be proved, and the reference answer. The proof obligation hypergraph includes nodes and hyperedges. At least one node is connected to at least another node through a hyperedge. The node is used to indicate the proof target or proof premise corresponding to each step in the reference answer. The hyperedge is used to indicate the mathematical theorems and / or reasoning rules satisfied between the connected nodes. A node determination module is used to match the response data with nodes in the proof obligation hypergraph, and determine a first node and a second node in the proof obligation hypergraph based on the matching result, wherein the hyperedge connected to the first node matches the response data, and the hyperedge connected to the second node does not match the response data; The proof-of-contrast module is used to determine whether there is a target proof-of-contrast based on the first node and the second node, wherein in the target proof-of-contrast, the premise of the proof corresponding to the first node is true and the target of the proof corresponding to the second node is false; The generation module is used to generate the grading result of the answer data based on the judgment result of the target counter-proof, the first node and the second node.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program adapted for loading by a processor to perform the method for correcting the questions according to any one of claims 1-6.

9. An electronic device, characterized in that, The electronic device includes a processor and a memory, the memory storing a computer program, and the processor executing the method for correcting the questions according to any one of claims 1-6 by calling the computer program stored in the memory.

10. A computer program product comprising computer instructions, characterized in that, When the computer instructions are executed by the processor, they implement the method for correcting the questions as described in any one of claims 1-6.

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