Hierarchical encryption access control method and system for mobile storage device

Abstract

The application provides a hierarchical encryption access control method and system of a mobile storage device, and relates to the technical field of data storage security. The method comprises the following steps: when detecting that the mobile storage device accesses a target host, sending an authentication challenge to the target host by a security chip, wherein the authentication challenge comprises a challenge random number, a plurality of geometric elements arranged randomly, and an element selection rule; receiving a geometric response sequence returned by the target host by the security chip, wherein the geometric response sequence comprises a two-dimensional coordinate sequence and an element selection order; and connecting coordinate points in the two-dimensional coordinate sequence according to the element selection order by the security chip to generate a geometric response polyline. The application combines geometric pattern authentication with dynamic switching of partition strategies, realizes on-demand hierarchical management and control of partition access permissions under different tasks on the same mobile storage device, and takes into account operation convenience and data security.

Description

Technical Field

[0001] This invention relates to the field of data storage security technology, and in particular to a hierarchical encryption access control method and system for mobile storage devices. Background Technology

[0002] During the inspection of the settings of substation relay protection devices, maintenance personnel need to carry a dedicated mobile storage device, which is generally divided into a setting area and a firmware area: setting files can be read and written in plaintext, while firmware files must be stored in encrypted form and direct viewing is restricted.

[0003] The existing method requires the device to be inserted into the management computer before deployment, where the management software issues a "fixed value mode" or "firmware mode" command. After the built-in chip receives the command, the encryption / decryption status of each partition is fixed and remains unchanged regardless of whether a relay protection device, debugging computer, or other host is subsequently inserted. This static configuration is adequate for a single task, but if a single inspection requires both fixed value verification and firmware upgrade, it becomes difficult to accommodate the varying partition permission requirements at different stages.

[0004] For example, if the device is set to a fixed value mode before deployment, it will be unable to read the firmware file when performing a firmware upgrade, making it difficult to perform the firmware upgrade operation in the current state. If it is set to firmware mode, the firmware area will be presented in plaintext when performing a fixed value verification, which can be directly viewed or copied by maintenance personnel, posing a risk of data leakage. Summary of the Invention

[0005] This invention provides a hierarchical encrypted access control method and system for mobile storage devices. By combining geometric authentication with dynamic switching of partition policies, it enables on-demand hierarchical control of partition access permissions under different tasks on the same mobile storage device, balancing operational convenience and data security.

[0006] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows: A first aspect is a hierarchical encrypted access control method for mobile storage devices, the method comprising: When a mobile storage device is detected to be connected to the target host, the security chip sends an authentication challenge to the target host. The authentication challenge includes a challenge random number, multiple randomly arranged geometric primitives, and primitive selection rules. The security chip receives a geometric response sequence returned by the target host, the geometric response sequence including a two-dimensional coordinate sequence and a primitive selection order; The security chip connects the coordinate points in the two-dimensional coordinate sequence according to the primitive selection order to generate a geometric response polyline. Calculate the discrete Friesian distance between the geometric response polyline and the pre-stored geometric template polyline; if the discrete Friesian distance is not greater than a preset distance threshold, the target host is deemed to have passed authentication. Obtain the access identity information and current task type of the target host, and determine the target partitioning strategy based on the access identity information and the current task type; Set the visibility and encryption / decryption status of the fixed value area and the firmware area in the current session according to the target partitioning policy, and respond to the access request of the target host. The target partitioning strategy includes a first partitioning strategy and a second partitioning strategy. When the current task type is a fixed value verification task, the first partitioning strategy is adopted, which makes the fixed value area readable and writable in plaintext and the firmware area in encrypted restricted state. When the current task type is a firmware upgrade task, the second partitioning strategy is adopted, which makes the firmware area controlled to be opened to the target host in encrypted form and prohibits the firmware area from being read in plaintext.

[0007] Secondly, a hierarchical encrypted access control system for mobile storage devices includes: The access module is used to send an authentication challenge to the target host by the security chip when the mobile storage device is detected to be connected to the target host. The authentication challenge includes a challenge random number, multiple randomly arranged geometric primitives and primitive selection rules. The sorting module is used to receive a geometric response sequence returned by the target host from the security chip. The geometric response sequence includes a two-dimensional coordinate sequence and a primitive selection order. The security chip connects the coordinate points in the two-dimensional coordinate sequence according to the primitive selection order to generate a geometric response polyline. The calculation module is used to calculate the discrete Friesian distance between the geometric response polyline and the pre-stored geometric template polyline; if the discrete Friesian distance is not greater than a preset distance threshold, the target host is deemed to have passed authentication. The acquisition module is used to acquire the access identity information and current task type of the target host, and determine the target partitioning strategy based on the access identity information and the current task type; The configuration module is used to set the visibility and encryption / decryption status of the fixed value area and the firmware area in the current session according to the target partitioning policy, and to respond to the access request of the target host. The target partitioning policy includes a first partitioning policy and a second partitioning policy. When the current task type is a fixed value verification task, the first partitioning policy is adopted, which makes the fixed value area in a plaintext readable and writable state and the firmware area in an encrypted restricted state. When the current task type is a firmware upgrade task, the second partitioning policy is adopted, which makes the firmware area controlled to be opened to the target host in encrypted form and prohibits the firmware area from being read in plaintext form.

[0008] The above-described solution of the present invention has at least the following beneficial effects: By employing geometric authentication and discrete Friesian distance comparison, a challenge-response security authentication system is achieved, resisting replay and automated identification. This overcomes the problems of static passwords being easily intercepted and fixed responses being easily reverse-engineered, achieving a high-security graphical authentication effect. By parsing access identity and task type, the system dynamically switches the partitioning strategy corresponding to fixed value verification and firmware upgrade, overcoming the problem that static partition configuration cannot adapt to multi-task processes. This achieves the effect of switching partition permissions on demand without re-initialization. Under the first strategy, the fixed value area is readable and writable in plaintext while the firmware area is restricted in ciphertext. Under the second strategy, the firmware area is opened in a controlled manner while plaintext reading is prohibited. Combined with a request interception mechanism that separates plaintext and ciphertext access, the system overcomes the problems of the firmware area being accidentally exposed in plaintext and the fixed value area being misoperated. This achieves a unified approach of convenient access to fixed value data and end-to-end ciphertext isolation of firmware data. Attached Figure Description

[0009] Figure 1 This is a flowchart illustrating a hierarchical encrypted access control method for a mobile storage device provided in an embodiment of the present invention.

[0010] Figure 2 This is a schematic diagram of a hierarchical encrypted access control system for a mobile storage device provided by an embodiment of the present invention.

[0011] Figure 3 The embodiment of the present invention provides that the security chip connects the coordinate points in the two-dimensional coordinate sequence according to the primitive selection order to generate a geometric response polyline. Detailed Implementation

[0012] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0013] like Figures 1 to 3As shown, an embodiment of the present invention proposes a hierarchical encrypted access control method for mobile storage devices. The mobile storage device is deployed in a dedicated secure USB flash drive carried by maintenance personnel. The target host is the host of the relay protection device at the substation site or a debugging laptop. The internal hardware of the mobile storage device includes a security chip, a NAND Flash memory chip, and a USB Type-C interface controller. The security chip uses a dedicated secure microcontroller with Chinese national cryptographic algorithms SM2 / SM3 / SM4. Here, SM2 represents the Chinese commercial public-key cryptography algorithm standard, SM3 represents the Chinese commercial cryptographic hash algorithm standard, and SM4 represents the Chinese commercial block cipher algorithm standard. The security chip connects to the NAND Flash via an SPI bus and communicates with the target host via the USB controller. The SPI bus, or Serial Peripheral Interface Bus, is a full-duplex synchronous serial communication interface used for high-speed data transmission between chips. The NAND Flash storage space is divided into three logical partitions by the security chip during device factory initialization, specifically including a system area, a setting area, and a firmware area.

[0014] The system area stores the firmware program, authentication template data, partition policy mapping table, and encryption keys for the security chip. The setting area stores the setting files for the relay protection device, specifically including parameter configuration files for current protection, voltage protection, and time setting parameters. The firmware area stores the firmware upgrade package for the relay protection device; all firmware data is stored in encrypted form and cannot be read directly in plaintext.

[0015] The following preset parameters and data structures are pre-programmed in the internal ROM of the security chip: The normalized coordinate space is defined as a two-dimensional planar region with the origin as the reference point and the values ​​of the horizontal and vertical coordinates ranging from 0.0 to 1.0.

[0016] The preset effective time window is 60 seconds. The security chip uses the time when it sends the authentication challenge as the benchmark. If the received response timestamp falls within the range of 30 seconds before to 30 seconds after the benchmark time, taking into account the possible clock deviation between the security chip and the target host, the response is determined to be within the effective time window.

[0017] A preset distance threshold is used to determine whether the morphological difference between the geometric response polyline and the pre-stored geometric template polyline is within an acceptable range. This threshold is determined as follows: During device initialization, the security chip is used by the administrator to perform correct geometric primitive selection operations multiple times. The discrete Friesian distance between the geometric response polyline generated by each operation and the pre-stored geometric template polyline is recorded. The maximum discrete Friesian distance generated by these multiple correct operations is taken and multiplied by a preset tolerance coefficient. The resulting product is used as the preset distance threshold. The tolerance coefficient is determined based on the following criteria: When the tolerance coefficient is 1.0, the threshold equals the administrator's maximum natural deviation across all operations. In this case, any subsequent operations by the administrator that show fluctuations slightly exceeding the historical maximum deviation will be considered authentication failures, resulting in a low authentication pass rate. When the tolerance coefficient is 3.0, the threshold is three times the administrator's maximum natural deviation. In this case, randomly generated coordinate sequences by attackers have a high probability of falling within the threshold range, leading to insufficient security protection. Through multiple operation deviation statistics performed on several operators in a security chip testing environment, it was found that a tolerance coefficient between 1.3 and 1.8 strikes a balance between authentication pass rate and security protection strength. In this embodiment, the midpoint of this range, 1.5, is used as the tolerance coefficient. The preset distance threshold obtained through the above calibration process is 0.05.

[0018] A pre-stored geometric template polyline, which is a reference polyline generated and stored in the security chip by the administrator during device initialization using the following method: The administrator sequentially designates N anchor points in the normalized coordinate space, where N is a positive integer greater than or equal to 3 and not exceeding 10. For example, in this embodiment, the administrator designates 6 anchor points, with their normalized coordinates as follows: Anchor 1 (0.10, 0.20), Anchor 2 (0.35, 0.70), Anchor 3 (0.55, 0.30), Anchor 4 (0.70, 0.65), Anchor 5 (0.85, 0.40), and Anchor 6 (0.95, 0.85). The security chip connects the first and second anchor points with straight line segments according to the order in which the anchor points are designated, then connects the second and third anchor points, and so on, until the N-1th anchor point is connected to the Nth anchor point, forming a polyline composed of N-1 line segments connected end-to-end. The security chip stores the coordinates of each vertex of this polyline and the connection relationships of the line segments in its internal ROM. The security chip processes the pre-stored geometric template polylines using the same translation and scaling normalization rules as the geometric response polylines. This ensures that the pre-stored geometric template polylines also have the origin as their geometric center, and the distance between the farthest anchor point and the origin is exactly 1.0. This polyline is the pre-stored geometric template polyline and is used for morphological comparison with the subsequently generated geometric response polylines. Administrators can also pre-store multiple sets of geometric template polylines for the same device, each set corresponding to a different authentication security level. For example, a 3-anchor polyline is used for low security level, a 6-anchor polyline for medium security level, and a 10-anchor polyline for high security level.

[0019] The security chip's internal ROM also pre-stores a sine-cosine lookup table, which is a 360-row, 2-column data table. Rows 1 to 360 correspond to angles 0° and 0° respectively. 0 Up to 359 0The first column of each row stores the cosine value of the angle, and the second column stores the sine value. Both the cosine and sine values ​​are stored in 16-bit signed fixed-point number format, accurate to 4 decimal places. When the security chip needs to obtain the cosine or sine value of a certain angle, it first rounds the angle to obtain an integer angle value, and then uses this integer angle value as the row index to look up the corresponding column value in that row.

[0020] The following buffers are allocated in the internal RAM of the security chip: a challenge data buffer (1024 bytes) for temporarily storing the generated authentication challenge data; a response data buffer (2048 bytes) for temporarily storing the encrypted response data packet returned by the target host; a coordinate point sequence buffer (capable of holding 256 two-dimensional coordinate points) for storing the parsed coordinate point data; a normalization buffer (capable of holding 256 two-dimensional coordinate points) for storing the normalized coordinate points after translation and scaling; and a resampling buffer (capable of holding an equal number of sample points as the normalized coordinate points) for storing the sequence of sample points after resampling with equal arc length. All of the above preparations are completed during the device's factory shipment or administrator initialization phase.

[0021] Step 1: When a mobile storage device is detected to be connected to the target host, the security chip sends an authentication challenge to the target host. The authentication challenge includes a challenge random number, multiple randomly arranged geometric primitives, and primitive selection rules, specifically including: When maintenance personnel insert a mobile storage device into the target host via the USB Type-C interface, the VBUS pin of the USB interface controller detects a 5V supply voltage, triggering a hardware interrupt signal. The VBUS pin represents the physical pin in the USB interface used to transmit the supply voltage; the standard USB supply voltage is 5V DC. The security chip's interrupt handler recognizes this hardware interrupt, confirming the connection of an external device. The security chip then completes the USB enumeration process with the target host through the USB protocol stack, establishing a basic data communication channel. During this process, the security chip reads the target host's USB device descriptor to confirm the target host's device type identifier.

[0022] The USB enumeration process represents a series of standard communication interaction steps initiated by the USB host after a mobile storage device is connected to the USB host. These steps include device reset, device address allocation, device descriptor acquisition, configuration descriptor acquisition, and configuration settings, which are used to establish a data transmission channel between the USB device and the USB host.

[0023] The security chip uses its internal true random number generator to generate a 128-bit challenge random number. This generator utilizes the chip's internal physical noise source, specifically the clock jitter of its internal ring oscillator, as the random source. The ring oscillator is a closed oscillating circuit composed of an odd number of inverters connected end-to-end. Its oscillation frequency is subject to slight, non-deterministic fluctuations due to thermal and power supply noise in semiconductor devices, making the output phase of each sample unpredictable. The security chip performs entropy extraction on the phase values ​​from multiple consecutive samples. Entropy extraction involves extracting a bit sequence that meets cryptographic randomness requirements from the original physical noise signal. Specifically, it concatenates the least significant bit of each sampled phase into a bit sequence, performs a health check based on the SM3 algorithm, and after confirming that the statistical randomness of the sequence meets the predetermined entropy requirement, truncates the first 128 bits as the challenge random number. The generated challenge random number is temporarily stored in a challenge data buffer.

[0024] A true random number generator is a hardware module that uses inherent nondeterministic noise in physical processes as a random source to generate unpredictable bit sequences through sampling and entropy extraction algorithms. Unlike pseudo-random number generators based on deterministic mathematical algorithms, the output of a true random number generator does not depend on the initial seed value; even if the complete design parameters of the generator are known, its output sequence is computationally unpredictable.

[0025] The SM3 algorithm represents the commercial cryptographic hash algorithm standard released by the State Cryptography Administration of China. It can map input messages of arbitrary length to a fixed-length 256-bit hash value, and has irreversibility and collision resistance. In this step, it is used to perform health checks on the random number generation process.

[0026] The security chip randomly selects six geometric primitives from a pre-stored geometric primitive template library in its internal ROM. The geometric primitive template library stores 12 primitive types, each with different shape characteristics, including: circle, square, equilateral triangle, rhombus, regular pentagon, regular hexagon, pentagram, cross, arrow, sector, ring, and L-shaped polygonal line. The template data for each primitive type is stored in vector description form, containing the vertex coordinate sequence and line segment connections that constitute the primitive's outline.

[0027] Geometric primitives represent two-dimensional graphic elements with clearly defined shape boundaries and visual identifiers. In this scheme, they are used to construct the interactive interface of the graphical authentication challenge. Users complete the authentication response by selecting different geometric primitives according to rules. Each geometric primitive is defined by the following attributes: primitive type determines its appearance shape, display position determines its drawing position on the screen, size determines its display size, rotation angle determines its orientation, color determines its fill color, and primitive identifier determines its unique number in the authentication process.

[0028] For each of the six selected geometric primitives, the security chip performs the following sub-steps to generate the complete display attributes of that primitive: The security chip assigns a set of random display position coordinates to each geometric primitive within a preset display coordinate space. The preset display coordinate space is a rectangular pixel area with an horizontal coordinate range of 0 to 800 pixels and a vertical coordinate range of 0 to 600 pixels, based on a typical screen resolution of 800 by 600 pixels. The security chip generates a random horizontal coordinate value and a random vertical coordinate value for each geometric primitive. This set of coordinates determines the center point of the geometric primitive, i.e., the geometric center of the geometric primitive's bounding rectangle, and its display position on the target host screen.

[0029] The security chip performs anti-overlap checks when generating random coordinates: whenever a display position is generated for a geometric primitive, the Euclidean distance between the center point of the primitive and the center points of each primitive in the assigned position is calculated.

[0030] If the calculated Euclidean distance is less than the preset minimum spacing of 80 pixels, the currently generated random coordinates are discarded, and a new set of random coordinates is generated until the Euclidean distance between the center points of any two geometric primitives is no less than 80 pixels. This constraint ensures that the geometric primitives do not overlap on the target host screen, and the user can clearly distinguish and click on each primitive.

[0031] Display coordinate space represents the pixel coordinate area on the target host screen or interactive interface used to present geometric primitives. It is measured in pixels and is used to determine the actual display position of geometric primitives on the user interface.

[0032] Anti-overlap check refers to a verification mechanism that ensures sufficient spacing between any two graphic elements when randomly generating display positions for multiple graphic elements. It determines whether the positions need to be regenerated by calculating the spatial distance between each element and comparing it with a preset minimum spacing.

[0033] The security chip randomly assigns a boundary rectangle width to each geometric primitive. The boundary rectangle represents the smallest bounding rectangle that completely encloses the shape of the geometric primitive. The security chip randomly selects an integer value from a preset width range as the boundary rectangle width for that geometric primitive, with a minimum of 40 pixels and a maximum of 120 pixels. The height of the geometric primitive is not randomly assigned separately, but is automatically calculated according to the default aspect ratio of that primitive type. For example, the default aspect ratio of a square is 1:1, and its height equals its width; the default aspect ratio of an equilateral triangle is 1:0.866; and the default aspect ratio of a regular pentagon is 1:0.951. The height is calculated by multiplying the assigned boundary rectangle width by the default aspect ratio of the corresponding primitive type. The security chip stores both the calculated width and height values ​​together as the boundary rectangle size for that geometric primitive.

[0034] The security chip randomly assigns a rotation angle to each geometric primitive. The security chip then uses its internal random number generator to generate a value ranging from 0 to 1. 0 Up to 360 0 The random angle value. This rotation angle represents the angle by which the geometric primitive rotates clockwise around its center point, i.e., the assigned display position coordinates. The specific execution method of the rotation operation is as follows: The relative coordinates are obtained by subtracting the center point coordinates from the coordinates of each vertex constituting the geometric primitive's outline. The relative coordinates represent the vertex's position relative to the primitive's center, with the primitive's own center point as the temporary origin. Then, each relative coordinate is rotated by a specific angle. Finally, the rotated relative coordinates are added back to the center point coordinates to restore the absolute coordinates. The absolute coordinates represent the vertex's position relative to the origin of the display coordinate space, describing the vertex's actual display position on the screen. For each vertex's coordinate rotation transformation, the security chip retrieves the cosine and sine values ​​corresponding to the rotation angle from a pre-stored sine-cosine lookup table in ROM. The specific calculation steps are as follows: Step a: Look up the cosine value of the rotation angle from the sine-cosine lookup table, multiply it by the relative x-coordinate of the vertex, and obtain the first product.

[0035] Step b: Look up the sine value of the rotation angle from the sine-cosine lookup table, multiply it by the relative ordinate of the vertex, and obtain the second product.

[0036] Step c: Subtract the second product from the first product to obtain the rotated relative x-coordinate.

[0037] Step d: Look up the sine value of the rotation angle from the sine-cosine lookup table, multiply it by the relative x-coordinate of the vertex, and obtain the third product.

[0038] Step e: Look up the cosine value of the rotation angle from the sine-cosine lookup table, multiply it by the relative ordinate of the vertex, and obtain the fourth product.

[0039] Step f: Add the third product to the fourth product to obtain the rotated relative ordinate.

[0040] Step g: Add the relative x-coordinate after rotation to the absolute x-coordinate of the center point to obtain the absolute x-coordinate after rotation.

[0041] Step h: Add the absolute ordinate of the center point to the relative ordinate after rotation to obtain the absolute ordinate after rotation.

[0042] Step i: The security chip checks whether the absolute coordinates of each vertex after rotation fall within the display coordinate space, i.e., whether the x-coordinate is between 0 and 800 pixels and the y-coordinate is between 0 and 600 pixels. If the absolute coordinates of a vertex exceed the display coordinate space, the security chip truncates the vertex coordinates to the boundary of the display coordinate space along the direction from the center point of the geometric primitive to the vertex. The specific method of truncation is as follows: take the direction vector from the center point to the vertex, calculate the intersection point of this direction vector with the four boundary lines of the display coordinate space (x-coordinate=0, x-coordinate=800, y-coordinate=0, y-coordinate=600), and replace the original vertex coordinates with the coordinates of this intersection point. The truncated vertex coordinates are used for subsequent primitive rendering. The primitive coordinates calculated before truncation, i.e., the normalized coordinates of the geometric primitive's center point, are not affected by this truncation operation.

[0043] The security chip stores the rotation angle value as the rotation attribute of the geometric primitive. The coordinates of each vertex after rotation are not stored separately, because they can be recalculated at any time by the rotation angle and primitive type template.

[0044] The rotation angle represents the angle traversed by a geometric primitive when it rotates clockwise around its own center point; the value ranges from 0 to 1. 0 Up to 360 0 .

[0045] The security chip randomly selects a fill color from a predefined color set for each geometric primitive, ensuring that no two geometric primitives are assigned the same color. The predefined color set contains eight colors, each described by RGB three-channel values: red (R = 255, G = 0, B = 0), green (R = 0, G = 255, B = 0), blue (R = 0, G = 0, B = 255), yellow (R = 255, G = 255, B = 0), cyan (R = 0, G = 255, B = 255), magenta (R = 255, G = 0, B = 255), orange (R = 255, G = 165, B = 0), and purple (R = 128, G = 0, B = 128). The security chip selects colors from the color set using sampling without replacement: after selecting a color for a geometric primitive, that color is removed from the candidate color set, and subsequent geometric primitives are selected only from the remaining colors. After all 6 geometric primitives have been assigned, there are still 2 colors left unused in the color set.

[0046] RGB three-channel values ​​represent a color model that describes color using the intensity values ​​of three basic color components: red, green, and blue. Each component has a value ranging from 0 to 255, where 0 indicates that the color component emits no light at all, and 255 indicates that the color component emits light at its maximum intensity. Approximately 16.77 million colors can be represented through different combinations of these three components.

[0047] The security chip assigns a unique numerical identifier to each geometric primitive within this authentication challenge, ranging from 1 to 6. The security chip assigns these numbers sequentially according to the order in which the geometric primitives are generated: the first generated primitive is numbered 1, the second 2, and so on, up to 6 for the sixth. The security chip stores this number as the primitive identifier for that geometric primitive. This identifier is used to reference a specific primitive in the primitive selection rules and to identify the selected primitive in subsequent primitive selection sequences.

[0048] A primitive identifier is a numerical number used to uniquely identify and reference a specific geometric primitive in an authentication challenge. The same number may correspond to geometric primitives of different shapes or colors in different types of authentication challenges.

[0049] For each geometric primitive, the security chip transforms the coordinates of the primitive's center point in the display coordinate space to a normalized coordinate space, obtaining the primitive's coordinates. The specific calculation steps for the transformation are as follows: Step a: Take the x-coordinate value of the center point and divide it by the maximum x-coordinate value of 800 in the displayed coordinate space to obtain the normalized x-coordinate.

[0050] Step b: Take the ordinate value of the center point and divide it by the maximum ordinate value of 600 in the displayed coordinate space to obtain the normalized ordinate.

[0051] This set of normalized two-dimensional coordinate values ​​is the primitive coordinate of the geometric primitive. The security chip associates and stores the primitive coordinates of each of the six geometric primitives with their corresponding primitive identifiers.

[0052] Primitive coordinates represent the standardized two-dimensional coordinate values ​​of the center point of a geometric primitive in a normalized coordinate space, with both the horizontal and vertical components ranging from 0.0 to 1.0. The purpose of coordinate normalization is to eliminate the influence of differences in absolute coordinate values ​​due to varying display resolutions of the target host, ensuring that the shape comparison of geometric response polylines depends only on the relative spatial structure of the polylines rather than their absolute pixel positions.

[0053] Normalized coordinate space represents a standardized two-dimensional coordinate system where both x and y coordinates range from 0.0 to 1.0. All coordinate operations related to this space, including subsequent polyline connections, distance calculations, and shape comparisons, are performed within this space to ensure consistency in certification results across different display devices.

[0054] The security chip randomly selects a primitive selection rule type from the rule template library pre-stored in the internal ROM. The rule template library stores a total of 4 rule types, each defining a discrimination logic for sorting geometric primitives.

[0055] Rule type one is a color sorting rule. This rule requires selecting geometric primitives according to their colors in a preset color sequence. The preset color sequence is fixed as a rainbow color sequence: red, orange, yellow, green, cyan, blue, purple, and magenta. The security chip obtains the colors assigned to the six geometric primitives and arranges the geometric primitives corresponding to these colors in the rainbow color sequence. The resulting sequence of primitive identifiers is the correct selection order.

[0056] Rule type two is the size sorting rule, which requires selecting geometric primitives in descending order of their boundary rectangle area. The security chip calculates the boundary rectangle area of ​​each geometric primitive, takes the assigned boundary rectangle width, and multiplies it by the corresponding height to obtain the boundary rectangle area.

[0057] Arrange the primitive identifiers of geometric primitives in descending order of area to obtain the correct selection order.

[0058] Rule type three is the position sorting rule. This rule requires selecting geometric primitives sequentially from top to bottom and from left to right, according to the position of the center point of the geometric primitive in the display coordinate space. The security chip first arranges all primitives in ascending order of their vertical coordinates, and for primitives with the same vertical coordinate, it then arranges them in ascending order of their horizontal coordinates. The resulting sequence of primitive identifiers is the correct selection order.

[0059] Rule type four is the shape-side-count sorting rule. This rule requires selecting geometric primitives in ascending order of the number of sides they contain. A circle is considered to have 0 sides and is ranked first, an L-shaped polygon is considered to have 6 sides, and a pentagram is considered to have 10 sides. The security chip arranges the primitive identifiers of the geometric primitives in ascending order of the number of sides to obtain the correct selection order.

[0060] This embodiment assumes that the security chip randomly selects rule type one, namely the color sorting rule. The security chip generates specific rule description text based on the actual colors assigned to the six geometric primitives. For example, if the colors of the six geometric primitives are blue, yellow, red, green, magenta, and orange, then the correct selection order according to the rainbow color sequence corresponds to the primitive colors red, orange, yellow, green, blue, and magenta, respectively. The primitive selection rule description text generated by the security chip is: Please click on each geometric primitive in the rainbow color sequence: red, orange, yellow, green, blue, magenta. This description text includes the operation instructions and sorting reference, but does not directly give the primitive numbers; the operator needs to identify the color of each primitive and deduce the clicking order according to the rule.

[0061] A geometric element selection rule represents a predefined set of operational guidelines that instructs an operator to select target geometric elements from a set of displayed geometric elements in a specific order. This rule defines the criteria for element selection, such as color, size, position, or shape, and the logic for determining the selection order, such as ascending, descending, or by a fixed sequence. Only a legitimate operator who understands the rule and can correctly identify the corresponding attributes of each geometric element can generate a selection order that conforms to the rule.

[0062] The rainbow color sequence represents the sequential order of colors arranged from longest to shortest visible light wavelengths: red, orange, yellow, green, cyan, blue, violet, and magenta. The rainbow color sequence is a universally recognized and accepted color arrangement convention, and in this scheme, it is used as the default sorting reference for the selection rules of color-based primitives.

[0063] The security chip assembles the generated data into an authentication challenge data packet. The data structure of the authentication challenge data packet includes the following fields in sequence: a 2-byte protocol version number indicating the format version of the authentication challenge data packet; a 16-byte challenge random number, i.e., a generated 128-bit random number; a 1-byte number of geometric primitives, with a fixed value of 6; a variable-length list of geometric primitives, each containing a primitive type identifier, the x and y coordinates of its display position, the width of its boundary rectangle, its rotation angle, the RGB three-channel values ​​of its color, and a primitive identifier; a 1-byte primitive selection rule type, indicating which of the four rule types is being used; and a variable-length primitive selection rule description text, a rule description string encoded in UTF-8.

[0064] An authentication challenge data packet represents a binary data block formed by encapsulating the various components of the authentication challenge according to a predetermined field format. It is used for structured data transmission between the security chip and the target host. Upon receiving this data packet, the target host can parse out all authentication parameters based on the fixed field layout.

[0065] The security chip sends the assembled authentication challenge data packet to the target host via the USB data transfer channel. Simultaneously, the security chip starts its internal challenge response timer, with a timeout set to 30 seconds. If no response is received from the target host within 30 seconds, the security chip determines that the authentication challenge has timed out, terminates the authentication process, and the preset area and firmware area remain locked by default.

[0066] The challenge response timer refers to a timer module inside the security chip that counts down from the moment the authentication challenge data packet is sent, limiting the maximum waiting time for the target host to return a response. If no valid response is received after this time, the authentication challenge is automatically invalidated, thus preventing indefinite waiting due to communication interruption or no response from the target host.

[0067] Step 2: The security chip receives the geometric response sequence returned by the target host. The geometric response sequence includes a two-dimensional coordinate sequence and a primitive selection order, specifically including: After receiving the authentication challenge data packet, the target host parses out the display attribute set of 6 geometric primitives and the primitive selection rule description text. It then renders the 6 geometric primitives on its display screen according to their display position, size, rotation angle, and RGB color value. The rule description text, "Please click on each geometric primitive in the order of rainbow colors: red, orange, yellow, green, blue, magenta," along with a 30-second countdown, is displayed at the top of the screen.

[0068] The operations and maintenance personnel, i.e. the legitimate operators on the target host side, observe the six colored geometric elements on the screen (in this embodiment, they are blue, yellow, red, green, magenta, and orange respectively), and determine the clicking order according to the rainbow color sequence as red element-orange element-yellow element-green element-blue element-magenta element, and click each geometric element in sequence.

[0069] The target host records each click event: It retrieves the element identifier of the clicked geometric element and appends it to the element selection order list; it retrieves the normalized element coordinates of the clicked geometric element and appends them to the two-dimensional coordinate sequence. The two-dimensional coordinate sequence is arranged in the order of clicks, totaling 6 normalized coordinate points. The two-dimensional coordinate sequence represents an ordered set of normalized center point coordinates of each selected geometric element arranged in the element selection order, recording the specific spatial location of the operator's click. The element selection order indicates the order in which the operator selects geometric elements according to the element selection rules, recorded in an ordered list of element identifiers, used to verify whether the operator correctly executed the selection according to the rules.

[0070] The target host assembles the following four pieces of data into a plaintext geometric response sequence: a two-dimensional coordinate sequence (an array of six two-dimensional coordinate pairs), a primitive selection order (an array of six primitive identifiers), a challenge random number (128 bits transmitted as is), and a response timestamp. The response timestamp represents the local system clock value read by the target host when assembling the response data, accurate to milliseconds, and is used by the security chip to determine whether the response arrives within the valid time window to defend against replay attacks.

[0071] The target host uses the symmetric encryption key written to the sealed storage area of ​​its TPM chip via a secure channel during factory initialization to perform SM4-CBC encryption on the plaintext data of the geometric response sequence. CBC mode stands for Cipher Block Chaining, where each plaintext block is first XORed with the preceding ciphertext block before encryption. The first block is XORed with a randomly generated 128-bit initialization vector. After encryption, an SM3 hash operation is performed on the ciphertext data and the initialization vector to obtain a 256-bit message authentication code. The target host then assembles the initialization vector (16 bytes), ciphertext data (variable length), and message authentication code (32 bytes) sequentially into an encrypted response data packet and sends it to the security chip via the USB channel.

[0072] The Message Authentication Code (MAC) represents a fixed-length data block calculated using a cryptographic hash function with a shared key, allowing the receiver to simultaneously verify the integrity and authenticity of the data.

[0073] After receiving the encrypted response data packet, the security chip separates three fields: the initialization vector, the ciphertext data, and the message authentication code. An SM3 hash operation is performed on the concatenated result of the ciphertext data and the initialization vector to obtain the local message authentication code, which is then compared byte-by-byte with the received message authentication code. If all 32 bytes match, the integrity check passes; if any byte is inconsistent, the security chip discards the data packet, terminates the authentication process, and the setting area and firmware area remain in their default locked state.

[0074] After the integrity check passes, the security chip uses the shared key to perform SM4-CBC decryption on the encrypted data, obtaining the geometric response sequence plaintext data, and parsing out the challenge random number and response timestamp.

[0075] The security chip first performs a challenge random number consistency check: it reads the generated 128-bit challenge random number from the challenge data buffer and compares it bit by bit with the parsed challenge random number. If they match completely, it indicates that the response was generated specifically for this authentication challenge, eliminating the possibility of replaying historical responses. If any bit differs, the session validity check fails. Next, it performs a response timestamp timeliness check. The security chip reads the current time from its internal real-time clock and calculates the absolute time difference. Step a: Take the difference between the current time and the response timestamp to obtain the signed time difference.

[0076] Step b: If the signed time difference is negative, take the opposite of the signed time difference to obtain the absolute time difference.

[0077] Step c: If the signed time difference is not negative, the signed time difference itself is used as the absolute time difference.

[0078] If the absolute time difference does not exceed the preset valid time window length of 60 seconds, the timeliness check passes. If it exceeds 60 seconds, the session validity check fails.

[0079] If both conditions are met—that the challenge random number is consistent and the response timestamp is within the valid time window—the security chip confirms that the geometric response sequence passes the session validity check and continues execution. If either condition is not met, the response sequence is discarded and the authentication process is terminated.

[0080] The security chip parses the two-dimensional coordinate sequence and primitive selection order from the decrypted plaintext data and performs the following verifications respectively.

[0081] Coordinate point source validity verification: The security chip defines a preset tolerance error of 0.001. For each coordinate point in the two-dimensional coordinate sequence, iterate through the six recorded primitive coordinates and calculate the deviation: Step a: Take the difference between the x-coordinate of the coordinate point and the x-coordinate of the graphic element to obtain the x-coordinate deviation.

[0082] Step b: Take the absolute value of the horizontal axis deviation to obtain the absolute value of the horizontal axis deviation.

[0083] Step c: Take the difference between the ordinate of the coordinate point and the ordinate of the graphic element to obtain the ordinate deviation.

[0084] Step d: Take the absolute value of the ordinate deviation to obtain the absolute value of the ordinate deviation.

[0085] Step e: Determine whether the absolute value of the deviation of the horizontal axis does not exceed 0.001 and whether the absolute value of the deviation of the vertical axis does not exceed 0.001.

[0086] If the absolute values ​​of the deviations of both coordinate terms for a given geometric element do not exceed 0.001, then the coordinate point is determined to originate from that geometric element. If all six coordinate points find a match, the validity of the coordinate point origin passes the validation; if any coordinate point does not match, the format validation fails.

[0087] The preset tolerance indicates the maximum difference in floating-point rounding error that can be tolerated. Normalized coordinates may experience rounding errors of approximately one part per million during transmission due to floating-point precision. A tolerance of 0.001 is sufficient to cover such errors while rejecting significantly different coordinate values.

[0088] Primitive selection order rule compliance verification: The security chip constructs a mapping relationship between primitive identifiers and color RGB values ​​based on the recorded color attributes of each geometric primitive. The pre-stored rainbow color sequence is red, orange, yellow, green, cyan, blue, purple, and magenta. The security chip traverses each pair of adjacent primitive identifiers in the primitive selection order, confirming that the position index of the previous primitive color in the rainbow color sequence is less than the position index of the next primitive color. Simultaneously, it verifies that the primitive selection order contains exactly six distinct primitive identifiers, all within the range of 1 to 6, to prevent primitive identifier omissions, duplications, or exceeding the valid range.

[0089] Format verification result determination: If all 6 coordinate points in the 2D coordinate sequence match valid primitive coordinates, and the primitive selection order conforms to the primitive selection rules, the security chip confirms that the geometric response sequence passes the format verification. If either condition is not met, the authentication process terminates, and the fixed value area and firmware area remain in the default locked state.

[0090] Format validation represents a comprehensive verification of whether the structure and content of the response data meet the predetermined format requirements. It includes two dimensions: the legality of the coordinate point source (ensuring that the coordinates in the response come from a legal set of graphic elements) and the compliance of the graphic element selection order rules (ensuring that the operator has correctly performed the selection according to the rules). At the same time, it filters out false responses from malicious hosts and erroneous responses from operators.

[0091] Step 3: The security chip connects the coordinate points in the two-dimensional coordinate sequence according to the selected primitive order to generate a geometric response polyline, specifically including: The security chip extracts the two-dimensional coordinate sequence and the primitive selection order from the decrypted geometric response sequence. The six coordinate points in the two-dimensional coordinate sequence are arranged in a one-to-one correspondence with the six primitive identifiers in the primitive selection order. The first coordinate point in the two-dimensional coordinate sequence corresponds to the first clicked geometric primitive in the primitive selection order, and so on. Since the target host has already arranged the coordinate points according to the order in which the maintenance personnel clicked them when constructing the geometric response sequence, the two-dimensional coordinate sequence itself is ordered. The security chip directly uses the two-dimensional coordinate sequence as an ordered set of coordinate points.

[0092] An ordered coordinate point set represents a group of two-dimensional coordinate points arranged according to the selection order of geometric elements. The first point in the ordered coordinate point set is the normalized center coordinate of the geometric element clicked by the maintenance personnel for the first time, the second point is the normalized center coordinate of the geometric element clicked for the second time, and so on, for a total of 6 coordinate points. This ordered coordinate point set completely records the spatial trajectory in the normalized coordinate space when the maintenance personnel clicks the 6 geometric elements in sequence.

[0093] The ordered coordinate point set is translated and scaled to obtain a normalized coordinate point set. The specific operations are as follows.

[0094] Because different target hosts have different screen sizes and resolutions, the coordinate trajectories formed by operators clicking on primitives under the same authentication rules may be translated in absolute position and uniformly scaled in overall size. The security chip performs translation normalization and scaling normalization on the ordered set of coordinate points in sequence to eliminate translation and scaling differences, retaining only the geometric features of the polyline.

[0095] Translation normalization refers to moving a set of coordinate points as a whole to a temporary origin with the geometric center of that set of coordinate points as the origin, in order to eliminate the influence of absolute position offset on the geometric shape. The geometric center represents the average position of the set of points, with its x-coordinate equal to the arithmetic mean of the x-coordinates of all points and its y-coordinate equal to the arithmetic mean of the y-coordinates of all points.

[0096] Scaling normalization means scaling a set of coordinate points that have already been translated and normalized by a uniform scale, so that the distance of the point farthest from the temporary origin in the set is exactly 1.0, in order to eliminate the influence of overall scale differences on the geometric shape, while preserving the relative distance ratio between the points.

[0097] Calculate the geometric center of an ordered set of coordinate points. The specific steps for calculating the geometric center are as follows: Step a: Take the x-coordinates of the first, second, third, fourth, fifth, and sixth points in the ordered coordinate set, and sum the six x-coordinate values ​​to obtain the total x-coordinate.

[0098] Step b: Divide the sum of the x-coordinates by six to obtain the x-coordinate of the geometric center.

[0099] Step c: Take the ordinates of the first, second, third, fourth, fifth, and sixth points in the ordered coordinate set, and sum the six ordinate values ​​to obtain the total ordinate sum.

[0100] Step d: Divide the sum of the ordinates by six to obtain the ordinate of the geometric center.

[0101] Perform translation normalization. Perform the following operations on each of the six coordinate points in the ordered coordinate set: Step a: Take the x-coordinate of the current coordinate point, subtract the x-coordinate of the geometric center, and obtain the translated x-coordinate.

[0102] Step b: Take the ordinate of the current coordinate point and subtract the ordinate of the geometric center to obtain the translated ordinate.

[0103] After all six coordinate points have been translated, a normalized set of coordinate points is obtained. The coordinate points in the normalized set are distributed with the origin (0.0, 0.0) as the geometric center, meaning that the sum of the x-coordinates and y-coordinates of the six translated coordinate points is 0.0.

[0104] Calculate the distance from each point in the translated and normalized coordinate set to the origin. Perform the following calculations for each of the six translated coordinate points: Step a: Take the x-coordinate after translation, multiply it by itself, and get the x-square value.

[0105] Step b: Take the translated ordinate and multiply it by itself to get the squared ordinate.

[0106] Step c: Sum the horizontal and vertical square values ​​to obtain the sum of squares.

[0107] Step d: Take the square root of the sum of squares to obtain the distance from the coordinate point to the origin.

[0108] After calculating all six coordinate points, six distance values ​​are obtained. The maximum distance value is then identified from these six. The security chip first records the first distance value as the current maximum distance value, then sequentially reads the second through sixth distance values. Each time, the read distance value is compared with the current maximum distance value. If the read distance value is greater than the current maximum distance value, the current maximum distance value is updated to the read distance value. After all six distance values ​​have been traversed, the current maximum distance value is the final maximum distance value. Scaling normalization is then performed. The following calculations are performed on each of the six translated coordinate points: Step a: Take the translated x-coordinate and divide it by the maximum distance value to obtain the scaled and normalized x-coordinate.

[0109] Step b: Take the translated ordinate and divide it by the maximum distance value to obtain the scaled and normalized ordinate.

[0110] After scaling all six coordinate points, a normalized coordinate point set is obtained. The normalized coordinate point set represents a set of two-dimensional coordinate points processed through translation normalization and scaling normalization. This set of points has the origin as its geometric center, and the point farthest from the origin is exactly 1.0 away from it. The distances of the remaining points from the origin range from 0.0 to 1.0. Because translation normalization eliminates absolute positional offsets and scaling normalization eliminates overall scale differences, the normalized coordinate point set only retains the geometric shape information of the operator's click trajectory, the relative positional relationships between points, and the shape characteristics of the polyline formed by connecting these points.

[0111] According to the order of coordinate points in the ordered coordinate point set, the corresponding coordinate points in the normalized coordinate point set are connected by line segments to obtain the initial response polyline. The specific operation is as follows.

[0112] The security chip connects the corresponding coordinate points in the normalized coordinate set sequentially using straight line segments, following the order of the coordinate points in the ordered coordinate set. The security chip reads the first coordinate point in the normalized coordinate set and marks it as the starting point of the current line segment. It then reads the second coordinate point as the ending point and draws the first straight line segment from the starting point to the ending point. A straight line segment represents the shortest path between two coordinate points; in normalized coordinate space, this is a direct line connecting the starting and ending points. The security chip then sets the second coordinate point as the new starting point and reads the third coordinate point as the new ending point, drawing the second straight line segment from the new starting point to the new ending point. This process continues until the fifth and sixth coordinate points are connected, creating the fifth straight line segment. The five straight line segments connected end-to-end form the initial response polyline. The initial response polyline represents a continuous polyline consisting of five straight line segments formed by connecting six coordinate points in the normalized coordinate point set in the order of clicks. The shape of this polyline is determined by the spatial relationship between the six vertices and the direction of the five line segments, reflecting the geometric shape of the spatial trajectory of the maintenance personnel clicking the six geometric primitives in sequence on the interactive interface.

[0113] The initial response polyline is resampled with equal arc lengths to obtain the geometric response polyline. The specific operation is as follows.

[0114] Because different maintenance personnel have different clicking habits, the arc length distribution among the vertices on the initial response polyline may be uneven, affecting the accuracy of subsequent polyline shape comparison. The security chip performs equal arc length resampling on the initial response polyline, so that the sampling points are evenly distributed along the arc length direction on the polyline.

[0115] Equal arc length resampling involves placing new sampling points at equal arc length intervals along the actual arc length direction of the polyline. These uniformly distributed sampling points replace the original vertices, reconstructing a new polyline with the same number of points but with the sampling points evenly spaced along the arc length. Arc length represents the measured length of each segment along the actual path of the polyline, distinct from the straight-line distance between two points. The specific steps of equal arc length resampling are as follows: Calculate the total arc length of the initial response polygon. The initial response polygon consists of 5 straight line segments, and the total arc length is equal to the sum of the lengths of the 5 straight line segments. The security chip calculates the length of each straight line segment segment by segment. For the first straight line segment (connecting the first coordinate point and the second coordinate point), the following calculation is performed: Step a: Take the difference between the x-coordinate of the second coordinate point and the x-coordinate of the first coordinate point to obtain the first segment of x-coordinate difference.

[0116] Step b: Multiply the first horizontal difference value by itself to obtain the first horizontal square value.

[0117] Step c: Take the difference between the ordinate of the second coordinate point and the ordinate of the first coordinate point to obtain the first segment ordinate difference value.

[0118] Step d: Multiply the first vertical difference value by itself to obtain the first vertical square value.

[0119] Step e: Sum the horizontal square value of the first segment with the vertical square value of the first segment to obtain the sum of squares of the first segment.

[0120] Step f: Take the square root of the sum of the squares of the first segment to obtain the length of the first segment.

[0121] For the second to the fifth straight line segments, calculate the lengths of the second, third, fourth, and fifth segments sequentially using the same steps a to f as described above.

[0122] Step g: Take the lengths of the 1st segment, the 2nd segment, the 3rd segment, the 4th segment, and the 5th segment, sum the five values, and obtain the total arc length.

[0123] Calculate the equal arc length sampling interval. The security chip determines the number of sampling points after resampling, which is consistent with the original number of vertices of the initial response polygon, i.e., 6 sampling points. The sampling interval is obtained by dividing the total arc length by the number of sampling points minus 1. The sampling interval represents the arc distance between two adjacent resampling points along the arc length direction on the polygon. With 6 sampling points and 5 intervals, the sampling interval is equal to 1 / 5 of the total arc length. Sampling points are placed sequentially along the initial response polygon, starting from the starting point, according to the sampling interval. The security chip performs the following operations: Step a: Place the first resampling point at the starting point of the initial response polyline, i.e., the first coordinate point of the normalized coordinate point set. Record the current cumulative arc length as 0.0, the current line segment number as the first line segment, and the traversed arc length on the current line segment as 0.0.

[0124] Step b: Process the 2nd to 6th resampling points. For each resampling point, the target cumulative arc length is equal to the current resampling point number minus 1, multiplied by the sampling interval. For example, the target cumulative arc length of the 2nd resampling point is equal to 1 multiplied by the sampling interval, the target cumulative arc length of the 3rd resampling point is equal to 2 multiplied by the sampling interval, and so on.

[0125] The security chip starts from the current position along the broken line, adds the traversed arc length of the current line segment to the remaining length of the line segment, and determines whether the accumulated result reaches the target accumulated arc length.

[0126] If the accumulated result is less than the target accumulated arc length, the security chip updates the current accumulated arc length to the accumulated result, moves to the next line segment, increments the current line segment number by 1, sets the traversed arc length on the new line segment to 0.0, and repeats the above judgment process until the current accumulated arc length plus the remaining length of the current line segment reaches or exceeds the target accumulated arc length.

[0127] If the current cumulative arc length plus the remaining length of the current line segment reaches or exceeds the target cumulative arc length, then the required sampling point falls on the current line segment. The security chip calculates the position of the required sampling point on this line segment: Step a: Take the target cumulative arc length, subtract the current cumulative arc length, and obtain the remaining required arc length on the line segment.

[0128] Step b: Take the two endpoints of the line segment. The coordinates of the starting point of the line segment are the coordinates of the previous vertex of the line segment, and the coordinates of the ending point of the line segment are the coordinates of the next vertex of the line segment.

[0129] Step c: Take the x-coordinate of the end point of the line segment and subtract the x-coordinate of the start point of the line segment to obtain the span of the line segment.

[0130] Step d: Take the ordinate of the end point of the line segment and subtract the ordinate of the starting point of the line segment to obtain the longitudinal span of the line segment.

[0131] Step e: Take the length of the line segment, that is, the Euclidean distance between the two endpoints of the line segment.

[0132] Step f: Take the remaining required arc length and divide it by the length of the line segment to obtain the scaling factor. The scaling factor represents the relative position of the required sampling point on the line segment from the starting point along the ending point direction, and its value ranges from 0.0 to 1.0.

[0133] Step g: Take the horizontal span of the line segment, multiply it by the proportional coefficient, and obtain the horizontal offset.

[0134] Step h: Take the longitudinal span of the line segment, multiply it by the proportional coefficient, and obtain the longitudinal offset.

[0135] Step i: Take the x-coordinate of the starting point of the line segment, add the x-offset, and obtain the x-coordinate of the sampling point.

[0136] Step j: Take the ordinate of the starting point of the line segment, add the ordinate offset, and obtain the ordinate of the sampling point.

[0137] The security chip stores the calculated sampling point coordinates as the location of the resampling point, updates the current cumulative arc length to the target cumulative arc length, and updates the traversed arc length on the current line segment to the remaining required arc length.

[0138] After all six resampling points have been placed (the sixth resampling point should fall exactly at the end of the initial response polyline, i.e., the sixth coordinate point of the normalized coordinate point set), the security chip stores the six resampling points in chronological order.

[0139] The security chip connects the six resampling points sequentially with straight line segments: the first line segment is drawn from the first resampling point to the second, the second line segment from the second to the third, and so on, until the fifth line segment is drawn from the fifth to the sixth. The polygonal line formed by connecting the five line segments end to end is the geometric response polygon. This geometric response polygon has undergone three processing steps: translation normalization, scaling normalization, and equal arc length resampling, eliminating three interference factors: absolute position offset, overall scale difference, and uneven click speed.

[0140] Step 4: Calculate the discrete Friesian distance between the geometric response polyline and the pre-stored geometric template polyline; if the discrete Friesian distance is not greater than a preset distance threshold, the target host authentication is deemed successful, specifically including: The security chip performs discrete sampling on the generated geometric response polyline and the geometric template polyline pre-stored during the configuration initialization stage, respectively, in a preset normalized coordinate space. The specific operation is as follows.

[0141] Discrete sampling involves extracting a set of coordinate points along the arc length of a polygonal line at equal arc length intervals. Discrete sampling transforms a continuous polygonal line into a discrete sequence of coordinate points, allowing the comparison of the shapes of two polygonal lines to be performed at discrete points, thereby reducing computational complexity.

[0142] The security chip performs discrete sampling on the geometric response polyline. The geometric response polyline consists of 6 resampling points (i.e., 6 vertices) and 5 line segments. The security chip uses the 6 vertices of the geometric response polyline themselves as response sampling points, arranging them in order from the start to the end, resulting in a sequence of response sampling points. The first point in the response sampling point sequence is the start point of the geometric response polyline, the second point is the vertex connecting the first and second line segments, and so on, with the sixth point being the end point of the geometric response polyline. The response sampling point sequence contains a total of 6 sampling points.

[0143] The security chip performs discrete sampling on the pre-stored geometric template polyline. In this embodiment, the pre-stored geometric template polyline is generated by the administrator specifying 6 anchor points, and also consists of 6 vertices and 5 line segments. The security chip uses the 6 anchor points of the pre-stored geometric template polyline itself as template sampling points, and arranges them in order from the start point to the end point to obtain a template sampling point sequence. The template sampling point sequence contains a total of 6 sampling points.

[0144] The pre-stored geometric template polyline represents a reference polyline generated and stored in the internal ROM of the security chip by the administrator sequentially specifying multiple anchor points in the normalized coordinate space and connecting them in order during device initialization. It serves as the benchmark for authentication comparison. Both the response sampling point sequence and the template sampling point sequence have 6 sampling points, all within the normalized coordinate space.

[0145] The discrete Fréchet distance between the geometric response polyline and the pre-stored geometric template polyline is calculated as follows.

[0146] The Discrete Fréchet distance (DFR) is a distance index used to measure the similarity of two polygonal lines in terms of their spatial shape. A smaller DFR is, the more similar the two polygonal lines are in terms of their spatial shape. The specific calculation steps for the DFR are as follows: The security chip constructs all possible candidate matching paths between the response sampling point sequence (6 points in total) and the template sampling point sequence (6 points in total). A candidate matching path represents a one-to-one pairing of points in the response sampling point sequence with points in the template sampling point sequence. Each candidate matching path consists of multiple pairs of matching points arranged in ascending order of sampling number. A pair of matching points represents a pair of coordinate points consisting of a response sampling point and a template sampling point, which are assumed to correspond to each other in a polyline shape. The monotonic continuity constraint represents two constraints that the candidate matching path must satisfy: The first constraint is a monotonic constraint: the index of the matching point pair must advance in a non-decreasing direction along the candidate matching path. Specifically, if the response sampling point index in the current matching point pair is p-th and the template sampling point index is q-th, then in the next matching point pair, the response sampling point index can only be p-th (meaning it does not advance along the response polyline) or p+1 (meaning it moves forward one sampling point along the response polyline), and the template sampling point index can only be q-th (meaning it does not advance along the template polyline) or q+1 (meaning it moves forward one sampling point along the template polyline). Regression of the response sampling point index or the template sampling point index is not allowed; that is, it cannot regress from p-th to p-minus-1, nor from q-th to q-minus-1. The monotonic constraint means that the matching advancement direction along the two polylines always remains forward, without backtracking.

[0147] The second constraint is a boundary constraint: the candidate matching path must cover the complete path from the start point to the end point of both polylines. The first matching point pair of the candidate matching path must be the first response sampling point paired with the first template sampling point, and the matching must begin from the start point of each polyline. The last matching point pair of the candidate matching path must be the sixth response sampling point paired with the sixth template sampling point, and the matching must end when both polylines reach their respective ends. The boundary constraint indicates that the matching process must start from the start point of the polyline and end at the end point of the polyline, and no start or end points should be omitted.

[0148] The security chip advances in three possible ways: one step along the response polygon, one step along the template polygon, or one step along each of the two polygons. Starting from the initial matching point pair (the first response sampling point paired with the first template sampling point), it expands outward layer by layer, generating all candidate matching paths that satisfy monotonic constraints and boundary constraints. Each candidate matching path contains a set of matching point pairs arranged in ascending order of sampling number.

[0149] For each pair of matching points in each candidate matching path, the security chip calculates the spatial distance between the response sampling point and the template sampling point in the matching point pair. The spatial distance is measured using Euclidean distance in normalized coordinate space. The Euclidean distance of all matching point pairs in the candidate matching path is also calculated to obtain the spatial distance of all matching point pairs in the candidate matching path.

[0150] For each candidate matching path, the security chip finds the maximum value among the spatial distances of all matching point pairs contained in that path, and determines this maximum value as the path distance of that candidate matching path. The specific method for finding the maximum value is as follows: the security chip first records the spatial distance of the first matching point pair as the current maximum value, and then sequentially reads the spatial distances of the second, third, and so on, up to the last matching point pair in the path. Each time, the read distance value is compared with the current maximum value. If the read distance value is greater than the current maximum value, the current maximum value is updated to the read distance value. After all distances have been read, the current maximum value is the path distance. The security chip then finds the minimum value among the path distances of all candidate matching paths. The specific method for finding the minimum value is as follows: The security chip first records the path distance of the first candidate matching path as the current minimum value, and then reads the path distances of the second, third and last candidate matching paths in sequence. Each time, the read path distance is compared with the current minimum value. If the read path distance is less than the current minimum value, the current minimum value is updated to the read path distance. After all paths are read, the current minimum value is the discrete Friesian distance.

[0151] The security chip compares the calculated discrete Friesian distance with the preset distance threshold of 0.05 set during the configuration initialization phase. If the discrete Friesian distance is less than or equal to 0.05, the security chip determines that the geometric response polyline and the pre-stored geometric template polyline are sufficiently similar in spatial shape, confirming that the operator of this authentication response knows the correct primitive selection rules and can correctly execute the click operation according to the rules, and the target host authentication is successful. At this point, the security chip continues to execute subsequent steps to obtain the target host's access identity information and current task type to determine the partitioning strategy.

[0152] If the discrete Friesian distance is greater than 0.05, the security chip determines that the geometric response polyline differs too much in spatial morphology from the pre-stored geometric template polyline. In this case, the security chip determines that the target host authentication has failed, rejects the authentication request, and maintains the default locked state of the setpoint area and firmware area. The setpoint area is in a non-readable / writable state, and the firmware area is in an inaccessible state, preventing the target host from performing read / write operations on any partition of the removable storage device. The security chip records this authentication failure event in the internal audit log, including the failure timestamp, the target host's device type identifier, and the specific value of the discrete Friesian distance. Optionally, it may return an authentication failure error code to the target host.

[0153] The default locked state represents the initial security state of each partition of the mobile storage device when it fails authentication or authentication fails. That is, the fixed value area and firmware area are invisible and unreadable / unwritable to the target host, and only the security chip itself can access the system area.

[0154] Step 5: Obtain the access identity information and current task type of the target host, and determine the target partitioning strategy based on the access identity information and the current task type, specifically including: After receiving the authentication confirmation from the security chip, the target host sends a session request to the security chip. The session request represents a data packet initiated by the target host after successful authentication to request the establishment of a partition access session. It contains the target host's identity credentials and the expected operation type information for this session.

[0155] The session request data structure includes the following fields: session request protocol version number (2 bytes), access identity information (variable length), task type identifier (1 byte), session request timestamp (8 bytes), and message authentication code (32 bytes). Access identity information includes the target host's device serial number, device type code, and device authorization certificate. The task type identifier is a single-byte enumeration value: 0 indicates a value verification task, 1 indicates a firmware upgrade task, and values ​​2 to 255 are reserved for future expansion.

[0156] After receiving a session request, the security chip first performs an SM3 hash operation on the portion of the session request excluding the message authentication code to obtain a local message authentication code. This local code is then compared byte-by-byte with the message authentication code carried in the session request to verify the integrity of the session request data. If the integrity verification fails, the security chip rejects the session request, terminates the session establishment, and the setting area and firmware area remain in their default locked state. If the integrity verification passes, the security chip parses the access identity information and task type identifier from the session request.

[0157] The security chip performs device legitimacy verification on the access identity information to confirm that the target host sending the session request is an authorized and legitimate device. The specific steps of device legitimacy verification are as follows.

[0158] Device serial number verification. The security chip extracts the device serial number from the access identity information and compares it with the authorized device whitelist pre-stored in the security chip's internal ROM. The authorized device whitelist is a list of all device serial numbers authorized to access this mobile storage device, written to the security chip's ROM by the security management platform during device factory initialization or subsequent administrator configuration. The security chip reads each record in the authorized device whitelist one by one and performs a string-by-string comparison between the parsed device serial number and the whitelist record. If a matching record is found, the device serial number verification passes. If no matching record is found after traversing the entire whitelist, the device serial number verification fails, the security chip determines that the target host is an unauthorized device, terminates the session establishment, and the default locked state is maintained in the value area and firmware area.

[0159] Device authorization certificate verification. The security chip extracts the device authorization certificate from the access identity information and performs the following verification operations on the certificate: The security chip verifies the signature of the device authorization certificate. The signature of the device authorization certificate is the signature data generated by the security management platform using its private key to perform a digital signature operation on the certificate content. The security chip uses the public key of the security management platform, pre-stored in its internal ROM, to verify the signature of the device authorization certificate. Digital signature verification means performing a cryptographic verification operation on the signature data using the signer's public key to confirm that the signature was indeed generated by the security management platform holding the corresponding private key and that the certificate content has not been tampered with. If the verification fails, the device authorization certificate verification fails.

[0160] The security chip verifies the validity period of the device's authorization certificate. The security chip reads the current date from its internal real-time clock and compares it with the start and end dates of the certificate's validity period recorded in the authorization certificate. If the current date is earlier than the certificate's start date or later than its end date, the certificate has expired or is not yet valid, and the device authorization certificate verification fails.

[0161] The security chip verifies whether the device serial number in the device authorization certificate matches the parsed device serial number, in order to prevent attackers from stealing the legitimate certificates of other devices and impersonating authorized devices.

[0162] Summary of legality verification results. The security chip determines that the device legality verification is successful and the target host is an authorized legitimate device when all three of the following conditions are met simultaneously: the device serial number exists in the authorized device whitelist; the device authorization certificate signature verification is successful and the certificate is valid; and the device serial number in the device authorization certificate matches the device serial number in the session request. If any one of these conditions is not met, the device legality verification fails, the security chip terminates the session establishment, and the setting area and firmware area remain in their default locked state.

[0163] Based on the mapping relationship between the task type identifier and the local policy, the target partition policy is determined, and the specific operation is as follows.

[0164] After the device's legitimacy verification is successful, the security chip uses the parsed task type identifier to search the local policy mapping relationship pre-stored in the internal ROM to determine the target partition policy that matches the current task type. The local policy mapping relationship represents a data table stored in the security chip's ROM that establishes a one-to-one correspondence between task type identifiers and partition policies. This data table contains the following entries: Item 1: When the task type identifier is 0 (i.e., setting value verification task), the corresponding partitioning strategy is the first partitioning strategy. Setting value verification task refers to the operation process in which maintenance personnel use a mobile storage device to insert into the relay protection device or debugging computer to read the setting parameter file in the setting value area, verify whether the parameter values ​​are consistent with the standard setting value sheet, or write back the current setting value parameters of the field device to the setting value area.

[0165] Item 2: When the task type identifier is 1 (i.e., firmware upgrade task), the corresponding partitioning policy is the second partitioning policy. Firmware upgrade tasks refer to the operation process in which maintenance personnel write the new version of the firmware upgrade package in encrypted form to the firmware area of ​​the mobile storage device or read the encrypted firmware package in the firmware area to the target host and then perform firmware flashing and upgrade.

[0166] Item 3: When the task type identifier is not 0 or 1 (i.e., neither a fixed-value verification task nor a firmware upgrade task), the corresponding partitioning policy is the default locking policy. The default locking policy means that no access permissions are granted to the fixed-value area and the firmware area. The fixed-value area is in a non-readable / writable state, and the firmware area is in an inaccessible state. The target host cannot perform read or write operations on any partition of the removable storage device.

[0167] The specific search process of the security chip is as follows: The security chip reads the parsed task type identifier value and compares this value with the task type identifiers of each entry in the local policy mapping table. If a matching entry is found, the security chip determines the partition policy corresponding to that entry as the target partition policy. If no matching entry is found, i.e., the task type identifier is neither 0 nor 1, the security chip determines the default locking policy as the target partition policy.

[0168] In this embodiment, the task performed by the maintenance personnel is a fixed-value verification task, and the task type identifier in the session request sent by the target host is 0. After looking up the table, the security chip determines that the target partitioning policy is the first partitioning policy.

[0169] The security chip records the identifier of the determined target partitioning policy, the corresponding task type identifier, and the session establishment timestamp of the current session into a session state data structure in its internal RAM. This session state data structure represents a set of runtime variables maintained by the security chip during each successfully authenticated session, used to track the execution status of the partitioning policy throughout the entire lifecycle of the current session. This data structure is allocated after USB enumeration is complete and released when the session terminates (device unplugged or timeout).

[0170] Step 6: Set the visibility and encryption / decryption status of the fixed-value area and the firmware area in the current session according to the target partitioning policy, and respond to the access request from the target host; wherein, the target partitioning policy includes a first partitioning policy and a second partitioning policy; when the current task type is a fixed-value verification task, the first partitioning policy is adopted, making the fixed-value area in a plaintext readable and writable state, and the firmware area in an encrypted restricted state; when the current task type is a firmware upgrade task, the second partitioning policy is adopted, making the firmware area controlled to be opened to the target host in encrypted form, and prohibiting the firmware area from being read in plaintext, specifically including: The security chip generates a partition control table based on the determined target partitioning strategy. The partition control table is a two-dimensional control table dynamically generated by the security chip after each session is established. It is used to indicate the visibility status, read / write permissions, and encryption / decryption status of the fixed-value area and the firmware area in the current session. The rows of the partition control table correspond to the two partitions, the fixed-value area and the firmware area, and the columns correspond to the three types of control attributes: visibility status, read / write permissions, and encryption / decryption status.

[0171] When the target partitioning policy is the first partitioning policy (corresponding to fixed-value verification tasks), the contents of the partition control table are: The fixed-value area is visible, meaning the target host can enumerate and identify this partition. Read / write permissions are in plaintext, allowing the target host to read and write data in plaintext. The security chip directly transmits the data without performing encryption or decryption. In the encryption / decryption state, data is allowed in plaintext; the security chip does not encrypt or decrypt data entering or leaving the fixed-value area. The fixed-value area is in a plaintext readable / writable state.

[0172] The firmware partition is visible, meaning the target host is aware of its existence. Regarding read / write permissions, plaintext reading is prohibited, encrypted reading is allowed, and write operations are prohibited. When the target host requests firmware partition data in plaintext, the security chip refuses to return a response; when requesting in encrypted form, the security chip returns the encrypted firmware data stored in the NAND Flash in encrypted form, and the target host is prohibited from writing any data to the firmware partition. The encryption / decryption status is encrypted restricted. Encrypted restricted status means that the firmware partition only allows data to flow out in encrypted form, not in plaintext, and data inflow is prohibited. The firmware partition is in encrypted restricted status. When the target partition policy is the second partition policy (corresponding to firmware upgrade tasks), the partition control table content is: The status of the custom parameter area is set to invisible, meaning the target host cannot enumerate this partition; read and write permissions are disabled; encryption / decryption is not applicable. The custom parameter area is completely hidden in the current session to prevent accidental modification of custom parameters during firmware upgrades.

[0173] The firmware area's visibility status is set to visible; in terms of read / write permissions, plaintext read is prohibited, encrypted read is allowed, encrypted write is allowed, and plaintext write is prohibited. The target host must not read firmware area data in plaintext, but can read firmware area data in encrypted form and can write new firmware data to the firmware area in encrypted form, but must not write in plaintext; the encryption / decryption status is set to encrypted controlled open. The encrypted controlled open state indicates a secure state where the firmware area is open to the target host in encrypted form. Decryption is not performed when data is read out, and neither decryption nor encryption is performed when data is written in encrypted form. Firmware data exists in encrypted form throughout the transmission link and storage medium, and the firmware area is prohibited from being read in plaintext. When the target partition policy is the default locking policy, both the fixed-value area and the firmware area are invisible and cannot be read or written.

[0174] The security chip performs the following configuration operations based on the partition control table: The configuration interface presents a specific status. Based on the visibility status of each partition in the partition control table, the security chip configures the logical unit descriptors in the USB mass storage device protocol. If the visibility status is visible, the security chip registers the partition in the logical unit descriptor; if the visibility status is invisible, the partition is not registered. When the target host queries the logical unit list after USB enumeration, it can only see the registered partitions. The logical unit descriptor represents a data structure in the USB protocol used to describe the internal logical partition structure of the storage device.

[0175] The request interception rule table is configured, representing a set of access control rules within the security chip. Each rule consists of three parts: target partition identifier, operation type (read or write), and processing action (allow or deny). The security chip generates interception rules one by one based on the read and write permissions of each partition in the partition control table. When the target host subsequently sends an access request, the security chip first matches the partition and operation type of the access request with the rules in the interception rule table. If an allow rule is matched, substantive data read / write is performed; if a deny rule is matched, or if no allow rule is matched, the access request is denied.

[0176] Throughout the entire lifecycle of the current session, the security chip continuously listens for access requests sent by the target host. An access request represents a protocol message sent by the target host via the USB channel to perform read or write operations on a specific partition of the removable storage device. This message includes fields such as the operation type (read or write), the target partition identifier (fixed partition or firmware partition), and the operation data address and length.

[0177] Upon receiving an access request, the security chip determines whether the partition to be accessed and the operation type specified in the request conform to the partition control table. Specifically, the security chip parses the operation type and target partition identifier from the access request and uses these as a lookup key to retrieve the configured request interception rule table. If the operation type and partition corresponding to the access request are marked as allowed in the interception rule table, the security chip determines that it conforms to the partition control table and performs substantive data read / write operations according to the encryption / decryption status configuration of the partition control table. If they are marked as denied, the security chip determines that it does not conform to the partition control table, returns an access denied error code to the target host, and refuses to perform any data read / write operations.

[0178] Depending on the target partitioning strategy, the specific response behavior of the security chip to the access request is as follows: When the target partitioning policy is the first partitioning policy: For access requests to the fixed-value area, if the operation type is plaintext read or plaintext write, the security chip processes it normally as plaintext. During plaintext read, the security chip reads plaintext fixed-value data from the NAND Flash and returns it to the target host; during plaintext write, the security chip directly writes the plaintext data sent by the target host into the NAND Flash.

[0179] For access requests to the firmware area, the security chip will implement stricter controls: if the request is for plaintext read, the security chip will refuse to return any plaintext firmware data; if the request is for encrypted read, the security chip will return the firmware data of the firmware area in encrypted form, and the returned data will be completely consistent with the encrypted firmware data stored in the NAND Flash, and the security chip will not perform decryption operations; if the request is for write operations, the security chip will refuse them.

[0180] When the target partitioning policy is the second partitioning policy: the fixed value area is invisible and unreadable / unwritable in the current session, so all access requests to the fixed value area are rejected by the security chip.

[0181] For access requests to the firmware area, the security chip processes them according to the following rules: If it is a plaintext read request, the security chip refuses to return any plaintext firmware data to the target host; if it is a ciphertext read request, the security chip returns the firmware data in the firmware area in ciphertext form; if it is a ciphertext write request, the security chip receives the ciphertext data sent by the target host and directly stores it into the physical address area corresponding to the firmware area in the NAND Flash without performing decryption operations. The entire firmware upgrade package remains in ciphertext form throughout the transmission link from the target host to the NAND Flash; if it is a plaintext write request, the security chip also refuses it.

[0182] like Figure 2 As shown, embodiments of the present invention also provide a hierarchical encrypted access control system for mobile storage devices, comprising: The access module is used to send an authentication challenge to the target host by the security chip when the mobile storage device is detected to be connected to the target host. The authentication challenge includes a challenge random number, multiple randomly arranged geometric primitives and primitive selection rules. The sorting module is used to receive a geometric response sequence returned by the target host from the security chip. The geometric response sequence includes a two-dimensional coordinate sequence and a primitive selection order. The security chip connects the coordinate points in the two-dimensional coordinate sequence according to the primitive selection order to generate a geometric response polyline. The calculation module is used to calculate the discrete Friesian distance between the geometric response polyline and the pre-stored geometric template polyline; if the discrete Friesian distance is not greater than a preset distance threshold, the target host is deemed to have passed authentication. The acquisition module is used to acquire the access identity information and current task type of the target host, and determine the target partitioning strategy based on the access identity information and the current task type; The configuration module is used to set the visibility and encryption / decryption status of the fixed value area and the firmware area in the current session according to the target partitioning policy, and to respond to the access request of the target host. The target partitioning policy includes a first partitioning policy and a second partitioning policy. When the current task type is a fixed value verification task, the first partitioning policy is adopted, which makes the fixed value area in a plaintext readable and writable state and the firmware area in an encrypted restricted state. When the current task type is a firmware upgrade task, the second partitioning policy is adopted, which makes the firmware area controlled to be opened to the target host in encrypted form and prohibits the firmware area from being read in plaintext form.

[0183] It should be noted that this system is a system corresponding to the above method. All implementation methods in the above method embodiments are applicable to this embodiment and can achieve the same technical effect.

[0184] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A hierarchical encrypted access control method for a mobile storage device, the mobile storage device comprising a security chip, a setting area, and a firmware area, characterized in that, include: When a mobile storage device is detected to be connected to the target host, the security chip sends an authentication challenge to the target host. The authentication challenge includes a challenge random number, multiple randomly arranged geometric primitives, and primitive selection rules. The security chip receives a geometric response sequence returned by the target host, the geometric response sequence including a two-dimensional coordinate sequence and a primitive selection order; The security chip connects the coordinate points in the two-dimensional coordinate sequence according to the primitive selection order to generate a geometric response polyline. Calculate the discrete Fréchet distance between the geometric response polyline and the pre-stored geometric template polyline; If the discrete Fraser distance is not greater than the preset distance threshold, the target host is deemed to have passed authentication. Obtain the access identity information and current task type of the target host, and determine the target partitioning strategy based on the access identity information and the current task type; Set the visibility and encryption / decryption status of the fixed value area and the firmware area in the current session according to the target partitioning policy, and respond to the access request of the target host. The target partitioning strategy includes a first partitioning strategy and a second partitioning strategy. When the current task type is a fixed value verification task, the first partitioning strategy is adopted, which makes the fixed value area readable and writable in plaintext and the firmware area in encrypted restricted state. When the current task type is a firmware upgrade task, the second partitioning strategy is adopted, which makes the firmware area controlled to be opened to the target host in encrypted form and prohibits the firmware area from being read in plaintext.

2. The method according to claim 1, characterized in that, The security chip receives a sequence of geometric responses returned by the target host, including: The security chip instructs the target host to select the desired geometric element from multiple geometric elements according to the element selection rules; The security chip receives a geometric response sequence generated by the target host in response to the authentication challenge. The geometric response sequence includes a two-dimensional coordinate sequence of the selected geometric primitives and the primitive selection order. The security chip verifies whether each coordinate point in the two-dimensional coordinate sequence corresponds to the coordinates of geometric primitives in multiple geometric primitives, and verifies whether the primitive selection order conforms to the primitive selection rules. If each coordinate point in the two-dimensional coordinate sequence corresponds to the coordinates of a geometric primitive among multiple geometric primitives, and the primitive selection order conforms to the primitive selection rules, then the geometric response sequence is confirmed to pass the format verification.

3. The method according to claim 2, characterized in that, The security chip receives a sequence of geometric responses generated by the target host in response to the authentication challenge, including: The security chip receives an encrypted response data packet returned by the target host. The encrypted response data packet carries the geometric response sequence. The geometric response sequence includes the two-dimensional coordinate sequence and the primitive selection order. The encrypted response data packet also includes the challenge random number and the response timestamp. The security chip decrypts and verifies the integrity of the encrypted response data packet; After successful decryption, the security chip verifies whether the challenge random number in the encrypted response data packet is consistent with the challenge random number in the authentication challenge, and verifies whether the response timestamp is within a preset valid time window; If the challenge random number is consistent and the response timestamp is within the preset valid time window, the geometric response sequence is confirmed to pass the session validity check.

4. The method according to claim 3, characterized in that, The security chip connects the coordinate points in the two-dimensional coordinate sequence according to the primitive selection order to generate a geometric response polyline, including: The security chip sorts the coordinate points in the two-dimensional coordinate sequence according to the primitive selection order to obtain an ordered set of coordinate points; The security chip performs translational normalization and scaling normalization on the ordered coordinate point set to obtain a normalized coordinate point set, which falls into a preset normalized coordinate space; The security chip connects the corresponding coordinate points in the normalized coordinate point set with line segments according to the order of the coordinate points in the ordered coordinate point set to obtain the initial response polyline. The geometric response piecewise linear curve is obtained by resampling the initial response piecewise linear curve with equal arc length using a security chip.

5. The method according to claim 4, characterized in that, The discrete Fréchet distance between the geometric response polyline and the pre-stored geometric template polyline is calculated by the security chip. If the discrete Fraser distance is not greater than a preset distance threshold, then the target host is determined to be authenticated, including: The security chip performs discrete sampling on the geometric response polyline and the pre-stored geometric template polyline in a preset normalized coordinate space to obtain the response sampling point sequence and the template sampling point sequence. The pre-stored geometric template polyline is a polyline that is generated in advance according to the same type of normalization rule and resampling rule as the geometric response polyline and stored in the security chip. The security chip calculates the discrete Friesian distance between the geometric response polyline and the pre-stored geometric template polyline based on the response sampling point sequence and the template sampling point sequence. The discrete Friesian distance is used to measure the similarity in spatial morphology between the geometric response polyline and the pre-stored geometric template polyline. If the discrete Fraser distance is not greater than the preset distance threshold, the target host is deemed to have passed authentication. If the discrete Fraser distance is greater than the preset distance threshold, the target host authentication is deemed to have failed, and the security chip maintains the default locked state of the fixed value area and the firmware area.

6. The method according to claim 5, characterized in that, The security chip calculates the discrete Friesian distance between the geometric response polyline and the pre-stored geometric template polyline based on the response sampling point sequence and the template sampling point sequence, including: The security chip constructs multiple candidate matching paths that satisfy the monotonic continuity constraint between the response sampling point sequence and the template sampling point sequence. Each candidate matching path includes multiple matching point pairs arranged in ascending order of sampling number. The matching point pair consists of a response sampling point from the response sampling point sequence and a template sampling point from the template sampling point sequence. The security chip calculates the spatial distance between each pair of matching points in each candidate matching path, and determines the maximum spatial distance in each candidate matching path as the corresponding path distance. The spatial distance is the Euclidean distance in the preset normalized coordinate space. The security chip determines the path distance corresponding to the candidate matching path with the smallest path distance among the multiple candidate matching paths as the discrete Fraser distance.

7. The method according to claim 6, characterized in that, The security chip obtains the target host's access identity information and current task type, and determines the target partitioning policy based on the access identity information and current task type, including: After the target host is successfully authenticated, the security chip parses the access identity information and task type identifier from the session request sent by the target host. The task type identifier is used to indicate the current task type. The security chip verifies the device's legitimacy by checking the access identity information; After the device's legitimacy is verified, the security chip determines the target partition policy that matches the access identity information and the current task type based on the task type identifier and the mapping relationship with the local policy. If the task type identifier does not belong to the fixed value verification type or firmware upgrade type task, the security chip will determine the default locking policy as the target partition policy.

8. The method according to claim 7, characterized in that, According to the target partitioning policy, the visibility and encryption / decryption status of the fixed-value area and the firmware area in the current session are set, and the access request from the target host is responded to, including: The security chip generates a partition control table according to the target partitioning policy. The partition control table is used to indicate the visibility status, read / write permissions, and encryption / decryption status of the fixed value area and the firmware area in the current session. The security chip configures the fixed value area and firmware area according to the partition control table to present the status of the target host's interface; When an access request is received from the target host, the security chip determines whether the partition to be accessed and the operation type pointed to by the access request conform to the partition control table. If the conditions are met, the access request is responded to according to the partition control table; otherwise, the access request is rejected.

9. The method according to claim 8, characterized in that, Responding to the access request from the target host according to the target partitioning policy includes: When the target partitioning policy is the first partitioning policy, the security chip sets the fixed value area to plaintext readable and writable state and the firmware area to encrypted restricted state. In encrypted restricted state, if the access request is directed to the firmware area and the operation type is a plaintext read request, the security chip will refuse to return the plaintext data of the firmware area to the target host. In the encrypted restricted state, if the access request is directed to the firmware area and the operation type is an encrypted read request, the security chip will return the firmware data of the firmware area to the target host in encrypted form. When the target partitioning policy is the second partitioning policy, the security chip sets the firmware area to a ciphertext-controlled open state; In the encrypted controlled open state, if the access request is directed to the firmware area and the operation type is a plaintext read request, the security chip will refuse to return the plaintext data of the firmware area to the target host. In the encrypted controlled open state, if the access request is directed to the firmware area and the operation type is an encrypted read request, the security chip will return the firmware data of the firmware area to the target host in encrypted form. In the encrypted controlled open state, if the access request is directed to the firmware area and the operation type is an encrypted write request, the security chip will write firmware data to the firmware area in encrypted form.

10. A hierarchical encrypted access control system for mobile storage devices, the system implementing the method as described in any one of claims 1 to 9, characterized in that, include: The access module is used to send an authentication challenge to the target host by the security chip when the mobile storage device is detected to be connected to the target host. The authentication challenge includes a challenge random number, multiple randomly arranged geometric primitives and primitive selection rules. The sorting module is used to receive a geometric response sequence returned by the target host from the security chip. The geometric response sequence includes a two-dimensional coordinate sequence and a primitive selection order. The security chip connects the coordinate points in the two-dimensional coordinate sequence according to the primitive selection order to generate a geometric response polyline. The calculation module is used to calculate the discrete Friesian distance between the geometric response polyline and the pre-stored geometric template polyline; If the discrete Fraser distance is not greater than the preset distance threshold, the target host is deemed to have passed authentication. The acquisition module is used to acquire the access identity information and current task type of the target host, and determine the target partitioning strategy based on the access identity information and the current task type; The configuration module is used to set the visibility and encryption / decryption status of the fixed value area and the firmware area in the current session according to the target partitioning policy, and to respond to the access request of the target host. The target partitioning policy includes a first partitioning policy and a second partitioning policy. When the current task type is a fixed value verification task, the first partitioning policy is adopted, which makes the fixed value area in a plaintext readable and writable state and the firmware area in an encrypted restricted state. When the current task type is a firmware upgrade task, the second partitioning policy is adopted, which makes the firmware area controlled to be opened to the target host in encrypted form and prohibits the firmware area from being read in plaintext form.

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