A method and system for optimizing gate etch process parameters

Abstract

The application belongs to the technical field of semiconductor manufacturing, and discloses a gate etching process parameter optimization method and system, which comprises the following steps: obtaining preset characteristic data of a current batch of CMOS device preparation processes; based on the preset characteristic data, a predicted size after gate etching is obtained by combining an etching size prediction model; the etching size prediction model is a multiple linear regression model introducing the photoresist size before gate etching, the shallow trench isolation step height, the polysilicon film layer thickness and the polysilicon line width roughness; based on the predicted size after gate etching, the gate etching amount deviation is calculated; according to the gate etching amount deviation, the predetermined etching process parameters are optimized to obtain the optimization result of the predetermined gate etching process parameters; the application can effectively improve the consistency and reliability of the optimization result of the gate etching process parameters, realize high-precision control of the size after gate etching, and effectively reduce the influence of the size fluctuation after gate etching on the electrical performance and reliability of the device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, and specifically relates to a method and system for optimizing gate etching process parameters. Background Technology

[0002] CMOS (Complementary Metal-Oxide-Semiconductor) devices are electronic components based on CMOS technology, widely used in computers, communications, consumer electronics, and industrial control. In CMOS devices, the size of the gate after etching is one of the core determinants of device performance, playing a decisive role. In particular, as the process nodes of CMOS devices gradually shrink, even small fluctuations in the size of the gate after etching will significantly affect the electrical performance and reliability of the device, leading to a decrease in device yield.

[0003] Currently, to ensure the dimensional accuracy of the gate after etching, most methods rely on manual adjustment or simple feedforward adjustment strategies to optimize the gate etching process parameters. The manual adjustment strategy involves operators manually adjusting the gate etching process parameters based on their long-term accumulated production experience to control the dimensional accuracy of the gate after etching. The simple feedforward adjustment strategy involves adjusting the gate etching process parameters based on the measured dimensions after gate development or the measured dimensions of the photoresist before gate etching to achieve the goal of controlling the dimensional accuracy of the gate after etching.

[0004] However, the aforementioned optimization methods generally suffer from poor consistency and low reliability, resulting in unstable yields of CMOS devices. Specifically, manual adjustment strategies rely entirely on the experience of operators, which is not only inefficient but also leads to extremely poor consistency in gate etching process parameter adjustments due to differences in the experience and operating habits of different operators. Under the same production conditions, different gate etching dimensions may occur, making it difficult to guarantee the stability of mass production. On the other hand, simple feedforward adjustment strategies rely on a single measurement dimension for parameter adjustment. However, since the measurement dimension after gate development and the gate etching dimension do not correspond perfectly, the actual value of the gate etching dimension deviates significantly, seriously affecting the product performance of CMOS devices. Summary of the Invention

[0005] To address the technical problems existing in the prior art, this invention provides a method and system for controlling gate etching parameters of CMOS devices, in order to solve the technical problems of poor consistency and low reliability that exist in existing gate etching process parameter optimization methods.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: This invention provides a method for optimizing gate etching process parameters, including: Obtain preset feature data of the current batch of CMOS device fabrication process; wherein, the preset feature data includes photoresist size before gate etching, shallow trench isolation step height, polysilicon film thickness and polysilicon linewidth roughness; Based on preset feature data and combined with the etching size prediction model, the predicted size after gate etching is obtained; wherein, the etching size prediction model is a multiple linear regression model that incorporates the photoresist size before gate etching, the shallow trench isolation step height, the polysilicon film thickness and the polysilicon linewidth roughness. Calculate the gate etching amount deviation based on the predicted size after gate etching. Based on the deviation in gate etching amount, the predetermined etching process parameters are optimized to obtain the optimized results of the predetermined gate etching process parameters.

[0007] Furthermore, the etching size prediction model is as follows:

[0008] in, Predicted dimensions after gate etching; The photoresist size before gate etching; The height of the shallow trench isolation step; The thickness of the polycrystalline silicon film; For polysilicon linewidth roughness; , , and All are partial regression coefficients; This is a constant term.

[0009] Furthermore, the predetermined etching process parameters include the trimming time for hard mask etching.

[0010] Furthermore, the process of optimizing the predetermined etching process parameters based on the gate etching amount deviation to obtain the optimized results of the predetermined gate etching process parameters is as follows: Based on the gate etching amount deviation, and combined with the linear relationship model between the etching process parameter deviation and the gate etching amount deviation, the predetermined etching process parameter deviation is calculated. The predetermined deviation of the etching process parameters is added to the predetermined design value of the etching process parameters to obtain the optimized result of the predetermined gate etching process parameters.

[0011] Furthermore, the process of constructing the linear relationship model between the etching process parameter deviation and the gate etching amount deviation is as follows: Obtain preset historical measured data of the fabrication process of historical batches of CMOS devices; wherein, the preset historical measured data includes actual measurement data of the gate size after etching, the target size after gate etching, actual data of the predetermined etching process parameters, and the design quantity of the predetermined etching process parameters; Based on the preset historical measured data, the historical measured data of the measured deviation of gate etching amount and the predetermined deviation of etching process parameters are calculated. Based on historical measured data of the measured deviation of gate etching amount and the predetermined deviation of etching process parameters, a linear relationship model between the deviation of etching process parameters and the deviation of gate etching amount is established.

[0012] Furthermore, the measured deviation of the gate etching amount is the difference between the actual measured data of the gate size after etching and the target size after gate etching.

[0013] Furthermore, the historical measured data of the predetermined etching process parameter deviation is the difference between the actual data of the predetermined etching process parameters and the design value of the predetermined etching process parameters.

[0014] Furthermore, the gate etching deviation is the difference between the predicted size after gate etching and the target size after gate etching.

[0015] Furthermore, it also includes a feedback correction step for the etching size prediction model, as follows: Obtain the preset feature data and actual measurement data of the gate etching dimensions from the previous batch of CMOS device fabrication process; Based on the preset feature data and actual measurement data of the gate size after etching from the previous batch of CMOS device fabrication process, the model parameters of the etching size prediction model are corrected by the exponential weighted moving average algorithm to obtain the corrected etching size prediction model.

[0016] The present invention also provides a gate etching process parameter optimization system for implementing the gate etching process parameter optimization method, comprising: The data acquisition module is used to acquire preset feature data of the current batch of CMOS device fabrication process; the preset feature data includes photoresist size before gate etching, shallow trench isolation step height, polysilicon film thickness and polysilicon linewidth roughness; The post-etching size prediction module is used to obtain the predicted size of the gate after etching based on preset feature data and combined with the etching size prediction model. The etching size prediction model is a multiple linear regression model that incorporates the photoresist size before gate etching, the shallow trench isolation step height, the polysilicon film thickness, and the polysilicon linewidth roughness. The etching deviation calculation module is used to calculate the gate etching deviation based on the predicted size after gate etching. The process parameter optimization module is used to optimize the predetermined etching process parameters based on the gate etching amount deviation, and obtain the optimization result of the predetermined gate etching process parameters.

[0017] Compared with the prior art, the unexpected beneficial effects of this invention are as follows: The gate etching process parameter optimization method provided by this invention can effectively improve the consistency and reliability of the gate etching process parameter optimization results, achieve high-precision control of the gate etching dimensions, and effectively reduce the impact of gate etching dimension fluctuations on the electrical performance and reliability of the device. Specifically, by obtaining the photoresist size, shallow trench isolation step height, polysilicon film thickness, and polysilicon linewidth roughness before gate etching in the current batch of CMOS device fabrication process, and based on the etching size prediction model, the predicted gate etching dimensions are obtained, achieving accurate prediction of the gate etching dimensions. Based on the predicted gate etching dimensions, the calculated gate etching amount deviation is more consistent with reality. Based on production needs, the predetermined etching process parameters can be optimized to effectively improve the consistency and reliability of the optimization results, thereby achieving precise control of the gate etching dimension accuracy, reducing the impact of gate etching dimension fluctuations on the electrical performance and reliability of the device, and significantly improving the production yield of CMOS devices. This invention can effectively eliminate the deviation in gate etching dimension control caused by human operation differences and insufficient correlation between a single measurement index and the final state of gate etching, thereby improving the consistency control effect of gate etching dimension from the source, enabling the gate etching dimension to be more accurately controlled within the ideal range, which helps to improve the electrical performance and reliability of CMOS devices.

[0018] Furthermore, in the etching size prediction model, the photoresist size before gate etching, the shallow trench isolation step height, the polysilicon film thickness, and the polysilicon linewidth roughness are used as independent variables. The influence weight of each independent variable on the gate etching size is quantitatively characterized by partial regression coefficients, and the model bias is calibrated by constant terms, making the model prediction results more accurate and reliable. This effectively improves the prediction accuracy of the gate etching size and provides accurate data support for the optimization of subsequent etching process parameters. At the same time, the multiple linear regression model has clear physical interpretability and low computational complexity, which can effectively balance prediction accuracy and engineering practicality.

[0019] Furthermore, the trimming time of hard mask etching is determined as a predetermined etching process parameter. As a key process parameter that directly affects the size of the gate after etching, the trimming time of hard mask etching makes the optimization of the gate etching process more targeted, ensures the consistency of the optimization results of the etching process parameters, and thus guarantees the control accuracy of the size of the gate after etching.

[0020] Furthermore, by using a linear relationship model between the etching process parameter deviation and the gate etching amount deviation, and combining the gate etching amount deviation with the predetermined etching process parameter design, the optimization results of the predetermined gate etching process parameters can be calculated. This enables precise correspondence and quantitative matching between the gate etching amount deviation and the gate etching process parameter deviation, effectively eliminating adjustment deviations caused by differences in experience and operating habits of different operators, ensuring the uniformity and standardization of etching process parameter adjustments, and thus guaranteeing the uniformity of gate etching dimensions in mass production.

[0021] Furthermore, based on preset historical measured data, a linear relationship model between the etching process parameter deviation and the gate etching amount deviation is fitted. This linear relationship model fully adapts to the process correlation rules caused by equipment characteristics, material differences, and process fluctuations in the actual production process, accurately matching the variable coupling relationship in actual production. This makes the optimization of process parameters in subsequent batches more closely match the actual physical process. At the same time, it effectively overcomes the systematic deviation caused by the incomplete correspondence between a single measurement data and the gate etching size in a simple feedforward strategy, ensuring the accuracy of the linear relationship model and providing reliable support for the accurate optimization of etching process parameters.

[0022] Furthermore, the measured deviation of the gate etching amount is defined as the difference between the actual measured data of the gate size after etching and the target size after gate etching. The target size after gate etching is used as the absolute benchmark to ensure that the linear relationship model learns the real physical deviation rather than the predicted residual, thus avoiding model drift caused by the accumulation of predicted residual.

[0023] Furthermore, the historical measured data of the predetermined etching process parameter deviation is defined as the difference between the actual data of the predetermined etching process parameters and the design value of the predetermined etching process parameters. This can accurately restore the actual deviation of the etching process parameters of each historical batch, ensuring that the constructed linear relationship model can truly reflect the correspondence between the etching process parameter fluctuation and the gate etching size fluctuation, thereby effectively improving the accuracy and effectiveness of process parameter optimization.

[0024] Furthermore, defining the gate etching deviation as the difference between the predicted size and the target size after gate etching enables the control node of the gate etching size to be moved forward to before the etching operation begins. This allows the optimization of etching process parameters to be completed before the actual etching, avoiding rework or scrap losses caused by dimensional deviations after etching. This can improve production efficiency and resource utilization while ensuring the accuracy of gate etching size control.

[0025] Furthermore, an exponentially weighted moving average algorithm is introduced, and the model parameters of the etching size prediction model are optimized by using the preset feature data from the previous batch of CMOS device fabrication process and the actual measurement data of the gate etching size. This enables the adaptive evolution of the etching size prediction model, effectively suppresses the accumulation of deviations during the long-term operation of the model, and thus ensures the continuous accuracy and field availability of the model throughout its entire life cycle.

[0026] The gate etching process parameter optimization method system provided by this invention has all the advantages of the above-mentioned gate etching process parameter optimization methods. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 Flowchart of the gate etching process parameter optimization method provided in Example 1; Figure 2 The structural block diagram of the gate etching process parameter optimization system provided in Example 2. Detailed Implementation

[0029] To make the technical problems, technical solutions, and beneficial effects solved by this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0030] Before describing the specific embodiments of this application, some of the technical terms involved in the embodiments of this application are explained as follows: Gate: In CMOS devices, the gate is a conductive electrode structure formed above the semiconductor substrate and located above the channel region. It is usually adjacent to the gate dielectric layer and is used to control the carrier concentration on the surface of the semiconductor substrate by applying voltage, thereby controlling the conduction and cutoff of the conductive channel between the source and drain, and realizing the switching function of the device.

[0031] Shallow trench isolation refers to an electrically isolated region formed in a semiconductor substrate between adjacent devices.

[0032] Shallow trench isolation step: refers to the height difference structure formed between the top surface of the shallow trench isolation zone and the top surface of the active zone, which is generated by the height difference between the shallow trench filling medium and the surface of the active zone.

[0033] Polycrystalline silicon film: refers to a continuous thin film layer formed by the deposition of polycrystalline silicon.

[0034] Polysilicon linewidth roughness refers to the microscopic irregular undulations and width deviations that appear on the sidewalls along the line extension direction after polysilicon patterns are formed into line-like structures through photolithography and etching. This includes line edge roughness and linewidth fluctuations.

[0035] Gate etch dimensions: refers to the actual physical dimensions of the gate structure formed in the channel width direction after the gate material layer (such as polysilicon, metal gate) is etched and the mask is removed. It generally refers to the critical dimensions of the gate.

[0036] Photoresist size before gate etching: refers to the key linewidth size of the photoresist gate pattern formed after exposure and development in the gate patterning process, before etching the underlying gate material layer.

[0037] Hard mask etch trimming time: refers to the duration of over-etching / fine-tuning etching of the hard mask pattern in a process that uses a hard mask (such as silicon nitride or silicon oxide) as the gate etch mask.

[0038] Exponentially weighted moving average algorithm: This is a time series smoothing and forecasting method. Its core idea is to assign different weights to historical data. The closer the data is to the current time, the greater the weight, while the weight of older data decays exponentially. This makes the influence of historical data on model parameters decrease exponentially with the increase of the time interval between data points.

[0039] This invention provides a method for optimizing gate etching process parameters, comprising the following steps: Step 100: Obtain the preset feature data of the current batch of CMOS device fabrication process; wherein, the preset feature data includes the photoresist size before gate etching, the shallow trench isolation step height, the polysilicon film thickness and the polysilicon linewidth roughness.

[0040] Step 200: Based on the preset feature data and combined with the etching size prediction model, obtain the predicted size after gate etching; wherein, the etching size prediction model is a multiple linear regression model that incorporates the photoresist size before gate etching, the shallow trench isolation step height, the polysilicon film thickness, and the polysilicon linewidth roughness.

[0041] Step 300: Calculate the gate etching deviation based on the predicted size after gate etching.

[0042] Step 400: Optimize the predetermined etching process parameters based on the gate etching amount deviation to obtain the optimization results of the predetermined gate etching process parameters.

[0043] In the above embodiments, by acquiring preset characteristic data of the current batch of CMOS device fabrication process, including photoresist size before gate etching, shallow trench isolation step height, polysilicon film thickness, and polysilicon linewidth roughness, it is possible to comprehensively capture multi-dimensional process fluctuations that affect the final state of gate etching from a physical perspective, providing a comprehensive and reliable data foundation for accurately predicting the predicted size after gate etching.

[0044] Secondly, based on preset feature data, and combined with a multiple linear regression model incorporating the photoresist size before gate etching, shallow trench isolation step height, polysilicon film thickness, and polysilicon linewidth roughness, an etching size prediction model is used to predict the gate size after etching. This makes the model prediction results more accurate and reliable, thereby improving the control precision of the gate size after etching. In particular, the etching size prediction model can comprehensively capture the multidimensional process fluctuations that affect the final state of gate etching from a physical perspective. By using a multiple linear regression algorithm, discrete and complex process parameter factors are converted into quantifiable size prediction results, completely avoiding the gate size control deviation caused by human operation differences and insufficient correlation between a single measurement index and the final state of etching.

[0045] Furthermore, based on the predicted size after gate etching, the gate etching amount deviation, which characterizes the difference between the current process state and the target value, is calculated. The calculated gate etching amount deviation is closer to the actual production requirements, providing a precise quantitative basis for adjusting etching process parameters. The predetermined etching process parameters are optimized according to the gate etching amount deviation, achieving precise adjustment of the gate etching process parameters. This effectively improves the consistency and reliability of the gate etching process parameter optimization results, thereby achieving the goal of precisely controlling the dimensional accuracy after gate etching. This effectively reduces the impact of dimensional fluctuations after gate etching on the electrical performance and reliability of the device, and thus significantly improves the production yield of CMOS devices.

[0046] The following specific embodiments further explain the gate etching process parameter optimization method and system provided by the present invention: Example 1 As attached Figure 1 As shown, this embodiment 1 provides a method for optimizing gate etching process parameters, including the following steps: Step 1: Obtain the preset feature data of the current batch of CMOS device fabrication process; wherein, the preset feature data includes the photoresist size before gate etching, the shallow trench isolation step height, the polysilicon film thickness, and the polysilicon linewidth roughness.

[0047] Explanatoryly, the preset feature data obtained in step 1 serves as the input data for the etching size prediction model in subsequent step 2. The preset feature data is actually measured from the current batch of CMOS device wafers undergoing process manufacturing. The specific implementation process is as follows: After the photoresist pattern is formed, the critical linewidth dimensions of the photoresist gate pattern on the sample wafer are measured using a critical dimension scanning electron microscope to obtain the photoresist dimensions before gate etching.

[0048] After the shallow trench isolation steps are formed, the shallow trench isolation steps on the sample wafer are measured using a critical dimension scanning electron microscope to obtain the height of the shallow trench isolation steps.

[0049] After the polycrystalline silicon film is formed, the thickness of the polycrystalline silicon film on the sample wafer is measured using a spectroscopic ellipsometry or a spectroscopic reflectometer.

[0050] After polycrystalline silicon patterns are formed into linear structures through photolithography and etching, the linear structures on the sample wafer are measured using a spectroscopic ellipsometry or spectroscopic reflectometer to obtain the polycrystalline silicon linewidth roughness.

[0051] Step 2: Based on the preset feature data and combined with the etching size prediction model, obtain the predicted size after gate etching; wherein, the etching size prediction model is a multiple linear regression model that incorporates the photoresist size before gate etching, the shallow trench isolation step height, the polysilicon film thickness, and the polysilicon linewidth roughness.

[0052] Explanatoryly, step 2 is used to input the preset feature data obtained in step 1 into the etching size prediction model, thereby predicting the gate etching size that the current batch of CMOS devices may reach after completing the gate etching process; the prediction process is quantified based on the etching size prediction model to avoid the subjectivity of human experience judgment; the multiple linear regression model is a statistical modeling method used to study the linear relationship between a dependent variable and two or more independent variables.

[0053] It should be noted that the photoresist size before gate etching, as a major factor in the transfer of the front-layer pattern, can directly affect the gate size after etching; the shallow trench isolation step height, by affecting the thickness of the bottom anti-reflective coating, changes the consumption of reactive free radicals during the etching process, thus indirectly affecting the gate size after etching; the polysilicon film thickness, by adjusting the soft-landing etching time, affects the gate size after etching; and the polysilicon linewidth roughness is used to correct measurement deviations in the photoresist size before gate etching, especially as a supplementary correction for gate patterns with a gate size less than 40nm after etching.

[0054] In the etching size prediction model, the predicted size after gate etching is used as the dependent variable, and four feature data, namely the photoresist size before gate etching, the shallow trench isolation step height, the polysilicon film thickness, and the polysilicon linewidth roughness, are used as independent variables. By introducing the above four feature data as independent variables, the model can comprehensively evaluate their impact on the etching result from multiple dimensions, which has higher prediction accuracy compared with the simple feedforward strategy that only relies on a single variable.

[0055] In one possible implementation, the etching size prediction model is as follows:

[0056] in, Predicted dimensions after gate etching; The photoresist size before gate etching; The height of the shallow trench isolation step; The thickness of the polycrystalline silicon film; For polysilicon linewidth roughness; , , and All are partial regression coefficients; This is a constant term.

[0057] Interpretively, the etching size prediction model is a quaternary linear equation. By introducing the photoresist size before gate etching, the shallow trench isolation step height, the polysilicon film thickness, and the polysilicon linewidth roughness as independent variables, the model uses partial regression coefficients to quantify the influence weight of each independent variable on the gate size after etching. Combined with a constant term to calibrate the model bias, the model prediction results can be made more accurate and reliable, thereby improving the control precision of the gate size after etching and providing accurate data support for the subsequent optimization of etching process parameters.

[0058] The process of building the etching size prediction model includes: First, under stable process conditions, the photoresist size, shallow trench isolation step height, polysilicon film thickness, and polysilicon linewidth roughness before gate etching were obtained during the fabrication process of historical batches of CMOS devices. At the same time, the actual measurement data of the corresponding gate size after etching were also obtained.

[0059] Subsequently, using the photoresist size, shallow trench isolation step height, polysilicon film thickness, and polysilicon linewidth roughness before gate etching in the fabrication process of historical batches of CMOS devices as independent variables, and the actual measurement data of the corresponding gate etching dimensions as dependent variables, a multiple linear regression analysis was used to fit the data, calculate the influence of each independent variable on the dependent variable, and obtain the partial regression coefficients. Partial regression coefficient Partial regression coefficient Partial regression coefficient and constant term .

[0060] Finally, based on the partial regression coefficients Partial regression coefficient Partial regression coefficient Partial regression coefficient and constant term By constructing a multiple linear regression model, a pre-constructed etching size prediction model can be obtained.

[0061] Explanatory partial regression coefficients This represents the average change in the predicted gate size after etching caused by a one-unit change in the photoresist size before gate etching, assuming that the shallow trench isolation step height, polysilicon film thickness, and polysilicon linewidth roughness remain constant; similarly, the partial regression coefficient... Partial regression coefficient Partial regression coefficient These represent the average change in the predicted gate size after etching caused by a one-unit change in the respective independent variable, assuming other variables remain constant; constant term This represents the combined effect of other factors not included in the model on the predicted size after gate etching.

[0062] Step 3: Calculate the gate etching deviation based on the predicted size after gate etching.

[0063] Explanatoryly, step 3 is used to quantify the gap between the predicted size after gate etching and the process design target, in order to measure whether the current process state deviates from the expected target, and to provide accurate numerical basis for subsequent process parameter optimization; the sign and magnitude of the gate etching deviation can directly reflect the amount of etching that needs to be compensated.

[0064] Specifically, when the gate etching deviation is positive, it indicates that the predicted gate size after etching is greater than the process design target, meaning that the etching amount is insufficient under the current process conditions, and the etching amount needs to be increased by adjusting the process parameters; when the gate etching deviation is negative, it indicates that the predicted gate size after etching is less than the process design target, meaning that the etching amount is excessive under the current process conditions, and the etching amount needs to be reduced by adjusting the process parameters; when the gate etching deviation is zero, it indicates that the predicted gate size after etching is equal to the process design target, meaning that the etching amount has reached the ideal state under the current process conditions, and no adjustment of the process parameters is required.

[0065] In this embodiment 1, the gate etching amount deviation is the difference between the predicted size after gate etching and the target size after gate etching; the calculation process of the gate etching amount deviation is as follows:

[0066] in, This refers to the deviation in gate etching amount; The target size after gate etching is the critical gate size that is expected to be achieved after the etching process in CMOS device design, and it is set according to the electrical performance requirements of CMOS devices.

[0067] Step 4: Optimize the predetermined etching process parameters based on the gate etching amount deviation to obtain the optimization results of the predetermined gate etching process parameters.

[0068] Explanatoryly, step 4 is used to reverse calculate the specific values ​​of the predetermined etching process parameters based on the gate etching amount deviation value calculated in step 3, thereby realizing automatic optimization of process parameters to compensate for the deviation of the current process parameters, so that the final gate etching size approaches the target value; after obtaining the optimization results of the predetermined gate etching process parameters, they are applied to the gate etching process of the current matching CMOS device to obtain a gate structure with higher dimensional accuracy.

[0069] In one possible implementation, the predetermined etching process parameters include the trimming time for hard mask etching.

[0070] Explained, the trimming time of hard mask etching is a key process parameter that has a direct and significant impact on the post-etched gate size. Optimizing the hard mask etching trimming time makes the gate etching process optimization more targeted, ensuring the consistency of the optimization results and thus guaranteeing the accuracy of the post-etched gate size. Specifically, by adjusting the hard mask etching trimming time, the linewidth of the hard mask pattern can be precisely controlled, thereby affecting the mask size during subsequent gate material layer etching and ultimately determining the post-etched gate size. For example, in a certain CMOS manufacturing process, for every 1 second increase in the hard mask etching trimming time, the post-etched gate size will decrease by 0.8 nm.

[0071] The specific implementation process is as follows: Step 41: Based on the gate etching amount deviation, and combined with the linear relationship model between the etching process parameter deviation and the gate etching amount deviation, calculate the predetermined etching process parameter deviation.

[0072] Explained, in step 41, the gate etching amount deviation calculated in step 3 is used as input to the linear relationship model between the etching process parameter deviation and the gate etching amount deviation, thus calculating the predetermined etching process parameter deviation. For example, taking the trimming time of hard mask etching as an example, the linear relationship model between the etching process parameter deviation and the gate etching amount deviation is expressed as follows:

[0073] in, The slope of the linear relationship between the gate etching deviation and the trimming time of the hard mask etching. This represents the trimming time deviation during hard mask etching.

[0074] In one possible implementation, the process of constructing a linear relationship model between the etching process parameter deviation and the gate etching amount deviation is as follows: Step 411: Obtain the preset historical measured data of the fabrication process of historical batches of CMOS devices; wherein, the preset historical measured data includes the actual measurement data of the gate size after etching, the target size after gate etching, the actual data of the predetermined etching process parameters, and the design quantity of the predetermined etching process parameters.

[0075] Step 412: Based on the preset historical measured data, calculate the historical measured data of the gate etching amount deviation and the predetermined etching process parameter deviation; wherein, the gate etching amount deviation is the difference between the actual measured data of the gate size after etching and the target size after gate etching; the historical measured data of the predetermined etching process parameter deviation is the difference between the actual data of the predetermined etching process parameters and the design amount of the predetermined etching process parameters.

[0076] Step 413: Based on the historical measured data of the measured deviation of the gate etching amount and the predetermined deviation of the etching process parameters, establish a linear relationship model between the deviation of the etching process parameters and the deviation of the gate etching amount; wherein, with the predetermined deviation of the etching process parameters as the independent variable and the deviation of the gate etching amount as the dependent variable, perform linear regression fitting on the historical measured data of the measured deviation of the gate etching amount and the predetermined deviation of the etching process parameters to obtain the linear relationship model between the deviation of the etching process parameters and the deviation of the gate etching amount.

[0077] It should be noted that the linear relationship model between the etching process parameter deviation and the gate etching amount deviation is established using a large amount of preset historical measured data through mathematical statistical methods to reflect the real process response relationship between the process parameter adjustment and the etching amount change. In particular, by introducing preset historical measured data of the historical batch CMOS device fabrication process, the parameters of the linear relationship model are made timely and accurate, thereby improving the accuracy of the linear relationship model and providing reliable support for the precise optimization of etching process parameters.

[0078] Step 42: Add the predetermined etching process parameter deviation to the predetermined etching process parameter design value to obtain the predetermined gate etching process parameter optimization result. This allows for the accurate calculation of the predetermined etching process parameter optimization result based on the specific value of the etching amount deviation, ensuring the accuracy and consistency of the etching process parameter optimization, and thus achieving precise control of the gate size after etching.

[0079] Optionally, this embodiment 1 also includes a feedback correction step for the etching size prediction model, as follows: Acquire the preset feature data and actual measurement data of the gate etching size during the fabrication process of the previous batch of CMOS devices; based on the preset feature data and actual measurement data of the gate etching size during the fabrication process of the previous batch of CMOS devices, use the exponential weighted moving average algorithm to correct the model parameters of the etching size prediction model, and obtain the corrected etching size prediction model, which is used to predict the gate etching size during the fabrication process of the next batch of CMOS devices.

[0080] The explanatory feedback correction step of the etching size prediction model serves as an online adaptive correction mechanism for the etching size prediction model, enabling the model to track the slow drift of the process over time and maintain its prediction accuracy. Optionally, the model parameters of the etching size prediction model include all partial regression coefficients and constant terms in the etching size prediction model.

[0081] Specifically, the model parameters of the etching size prediction model are corrected by using an exponentially weighted moving average algorithm, so that the model parameters can be dynamically adjusted according to the latest process performance, quickly respond to process changes, and avoid drastic fluctuations in parameters due to single measurement anomalies. This ensures the accuracy of the predicted gate etching size and effectively improves the reliability of the gate etching process parameter optimization results.

[0082] The specific implementation process is as follows: First, acquire the preset feature data, predetermined etching process parameter deviations, and actual measurement data of the gate etching size from the previous batch of CMOS device fabrication process. The preset feature data from the previous batch of CMOS device fabrication process is of the same data type as the preset feature data from the current batch of CMOS device fabrication process acquired in step 1, and will not be elaborated further here. Next, calculate the equivalent predicted value of the gate etching size based on the predetermined etching process parameter deviations and the actual measurement data of the gate etching size from the previous batch of CMOS device fabrication process. Then, establish new training sample points based on the preset feature data from the previous batch of CMOS device fabrication process and the equivalent predicted value of the gate etching size. Finally, using the new training sample points, correct all partial regression coefficients and constant terms in the etching size prediction model using an exponentially moving weighted average algorithm to obtain the corrected etching size prediction model.

[0083] For example, in a certain CMOS manufacturing process, the trimming time of hard mask etching is used as a predetermined etching process parameter, and the partial regression coefficients in the etching size prediction model are analyzed using an exponentially moving weighted average algorithm. Taking the correction process as an example, the following example illustrates the process: Based on the actual measurement data of the gate etching dimensions of the previous batch of CMOS devices and the predetermined etching process parameter deviations, the equivalent predicted value of the gate etching dimensions is calculated. It is assumed that during the fabrication of the previous batch of CMOS devices, the predicted gate etching dimension was 50nm, the target gate etching dimension was 45nm, and that for every 1s increase in the hard mask etching trimming time, the gate etching dimension would decrease by 0.8nm. In this case, the hard mask etching trimming time deviation is... .

[0084] Subsequently, after completing the gate etching operation of the previous batch of CMOS devices, the actual measured size of the gate after etching was obtained as 46nm; at this time, the equivalent predicted size of the gate after etching during the fabrication process of the previous batch of CMOS devices was... Based on the equivalent predicted value and corresponding predicted size of the gate after etching during the fabrication of the previous batch of CMOS devices, the prediction error of the gate after etching size is calculated; therefore, the prediction error of the gate after etching size is... .

[0085] Next, based on the preset learning rate and the prediction error of the gate etching size, the partial regression coefficient is calculated. The temporary update value; where the partial regression coefficients are... The calculation process for the temporary update value is as follows:

[0086] in, The partial regression coefficients in the current feedback correction rounds are used to adjust the values. Temporary update value; Partial regression coefficients The initial value; Set the learning rate; This represents the prediction error of the gate size after etching.

[0087] Assuming a preset learning rate Take 0.01, partial regression coefficient The initial value is 2, and the photoresist size before gate etching in the previous batch of CMOS device fabrication was 58nm; at this time, the partial regression coefficient... The temporary update values ​​are as follows: .

[0088] Then, based on the preset smoothing factor, the partial regression coefficients were... Temporary update values ​​and partial regression coefficients The partial regression coefficient is calculated by performing an exponentially weighted moving average on the current value. The correction value; where the partial regression coefficient The calculation process for the correction value is as follows:

[0089] After recursion, we get:

[0090] in, Partial regression coefficients In the The correction value after the feedback correction; For the feedback correction rounds of the etching size prediction model, , The maximum value of the feedback correction round; Set as the preset smoothing factor; For the first The partial regression coefficient corresponding to the next feedback correction round The temporary update value; when the feedback correction round is greater than or equal to 50. Take the partial regression coefficients corresponding to the most recent 50 feedback correction rounds. The temporary update value.

[0091] Assuming a preset smoothing factor A value of 0.9 indicates that the old data accounts for 90% and the latest data accounts for 10% during the correction process, to avoid drastic fluctuations in parameters; therefore, when the feedback correction round is 1, the partial regression coefficient... The correction value is calculated as follows: .

[0092] in, Partial regression coefficients The correction value after the first feedback correction.

[0093] It should be noted that the correction process for other partial regression coefficients and constant terms in the etching size prediction model is the same as that for the partial regression coefficients mentioned above. The correction process is based on the same principle, and will not be elaborated here.

[0094] The gate etching process parameter optimization method described in Embodiment 1 acquires preset feature data of the current batch of CMOS device fabrication process, including the photoresist size before gate etching, shallow trench isolation step height, polysilicon film thickness, and polysilicon linewidth roughness. This allows for a comprehensive physical capture of multidimensional process fluctuations affecting the final state of gate etching, providing a comprehensive and reliable data foundation for subsequent accurate prediction. Furthermore, it incorporates a multiple linear regression model that includes the photoresist size before gate etching, shallow trench isolation step height, polysilicon film thickness, and polysilicon linewidth roughness as an etching size prediction model to obtain the predicted size after gate etching. This method transforms the discrete and complex effects of process parameters into quantifiable size prediction results, making the model prediction results more accurate and reliable, thereby improving the control precision of the size after gate etching.

[0095] In this embodiment, the gate etching deviation, which characterizes the difference between the current process state and the target value, is calculated based on the predicted size after gate etching. The calculated gate etching deviation closely matches actual production requirements, providing a precise quantitative basis for process parameter adjustment. By optimizing the predetermined etching process parameters according to the gate etching deviation, the gate etching process parameters can be precisely adjusted, effectively improving the consistency and reliability of the gate etching process parameter optimization results. This achieves the goal of precisely controlling the dimensional accuracy after gate etching, effectively reducing the impact of dimensional fluctuations after gate etching on the electrical performance and reliability of the device, thereby significantly improving the production yield of CMOS devices.

[0096] Example 2 As attached Figure 2 As shown, this embodiment 2 provides a gate etching process parameter optimization system, including a data acquisition module, a post-etching size prediction module, an etching amount change calculation module, and a process parameter optimization module.

[0097] The data acquisition module is used to acquire preset feature data of the current batch of CMOS device fabrication process; the preset feature data includes photoresist size before gate etching, shallow trench isolation step height, polysilicon film thickness, and polysilicon linewidth roughness.

[0098] The post-etching size prediction module is used to obtain the predicted size of the gate after etching based on preset feature data and combined with the etching size prediction model. The etching size prediction model is a multiple linear regression model that incorporates the photoresist size before gate etching, the shallow trench isolation step height, the polysilicon film thickness, and the polysilicon linewidth roughness.

[0099] The etching amount deviation calculation module is used to calculate the gate etching amount deviation based on the predicted size after gate etching. Optionally, the gate etching amount deviation is the difference between the predicted size after gate etching and the target size after gate etching.

[0100] The process parameter optimization module is used to optimize predetermined etching process parameters based on the gate etching amount deviation, thereby obtaining the optimized results of the predetermined gate etching process parameters. Optionally, the predetermined etching process parameters include the trimming time for hard mask etching.

[0101] In one possible implementation, the etching size prediction model is as follows:

[0102] in, Predicted dimensions after gate etching; The photoresist size before gate etching; The height of the shallow trench isolation step; The thickness of the polycrystalline silicon film; For polysilicon linewidth roughness; , , and All are partial regression coefficients; This is a constant term.

[0103] In one possible implementation, the process of optimizing predetermined etching process parameters based on the gate etching amount deviation to obtain the optimized result of the predetermined gate etching process parameters is as follows: Based on the gate etching amount deviation, and combined with the linear relationship model between the etching process parameter deviation and the gate etching amount deviation, the predetermined etching process parameter deviation is calculated. The predetermined etching process parameter deviation is added to the predetermined etching process parameter design amount to obtain the optimized result of the predetermined gate etching process parameters.

[0104] In one possible implementation, the process of constructing a linear relationship model between the etching process parameter deviation and the gate etching amount deviation is as follows: Acquire preset historical measured data of the fabrication process of historical batches of CMOS devices. This preset historical measured data includes actual measurement data of the gate etching dimension after etching, the target gate etching dimension after etching, actual data of predetermined etching process parameters, and the design quantities of predetermined etching process parameters. Based on this preset historical measured data, calculate the historical measured data of the gate etching amount deviation and the predetermined etching process parameter deviation. The gate etching amount deviation is the difference between the actual measurement data of the gate etching dimension after etching and the target gate etching dimension. The predetermined etching process parameter deviation is the difference between the actual data of the predetermined etching process parameters and the design quantities of the predetermined etching process parameters. Based on these historical measured data, establish a linear relationship model between the etching process parameter deviation and the gate etching amount deviation.

[0105] In one possible implementation, a feedback correction step for the etch size prediction model is also included, as follows: Obtain the preset feature data and actual measurement data of the gate etching size during the fabrication process of the previous batch of CMOS devices; based on the preset feature data and actual measurement data of the gate etching size during the fabrication process of the previous batch of CMOS devices, the model parameters of the etching size prediction model are corrected by the exponential weighted moving average algorithm to obtain the corrected etching size prediction model.

[0106] It should be noted that all relevant content of each step involved in the gate etching process parameter optimization method described in the aforementioned embodiment 1 can be referenced to the functional description of the corresponding functional module of the gate etching process parameter optimization system in this embodiment 2, and will not be repeated here.

[0107] The module division in this embodiment 2 is illustrative and only represents one logical functional division. In actual implementation, there may be other division methods. In addition, each functional module in this embodiment 2 can be integrated into a processor, exist as a separate physical entity, or have two or more modules integrated into one module. The integrated module can be implemented in hardware or as a software functional module.

[0108] The gate etching process parameter optimization method and system described in this invention uses preset feature data from the current batch of CMOS device fabrication process and an etching size prediction model to predict the gate etching size. This allows for a more accurate and comprehensive consideration of factors affecting the gate etching size, resulting in a more precise predicted gate etching size. Based on the predicted gate etching size, a reasonable gate etching amount deviation is calculated, and the predetermined etching process parameters are optimized accordingly. This enables the gate etching size to be more precisely controlled within the ideal range, which helps improve the electrical performance and reliability of CMOS devices, reduces the generation of defective products due to deviations in the gate etching size, thereby stabilizing product yield and avoiding production losses caused by unstable yield.

[0109] The above embodiments are merely one of the implementation methods for achieving the technical solution of the present invention. The scope of protection claimed by the present invention is not limited to this embodiment, but also includes any variations, substitutions and other implementation methods that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention.

Claims

1. A method for optimizing gate etching process parameters, characterized in that, include: Obtain preset feature data of the current batch of CMOS device fabrication process; wherein, the preset feature data includes photoresist size before gate etching, shallow trench isolation step height, polysilicon film thickness and polysilicon linewidth roughness; Based on preset feature data and combined with the etching size prediction model, the predicted size after gate etching is obtained; wherein, the etching size prediction model is a multiple linear regression model that incorporates the photoresist size before gate etching, the shallow trench isolation step height, the polysilicon film thickness and the polysilicon linewidth roughness. Calculate the gate etching amount deviation based on the predicted size after gate etching. Based on the deviation in gate etching amount, the predetermined etching process parameters are optimized to obtain the optimized results of the predetermined gate etching process parameters.

2. The method for optimizing gate etching process parameters according to claim 1, characterized in that, The etching size prediction model is as follows: in, Predicted dimensions after gate etching; The photoresist size before gate etching; The height of the shallow trench isolation step; The thickness of the polycrystalline silicon film; For polysilicon linewidth roughness; , , and All are partial regression coefficients; This is a constant term.

3. The method for optimizing gate etching process parameters according to claim 1, characterized in that, The predetermined etching process parameters include the trimming time for hard mask etching.

4. The method for optimizing gate etching process parameters according to claim 1, characterized in that, The process of optimizing predetermined etching process parameters based on the gate etching amount deviation to obtain the optimized results of predetermined gate etching process parameters is as follows: Based on the gate etching amount deviation, and combined with the linear relationship model between the etching process parameter deviation and the gate etching amount deviation, the predetermined etching process parameter deviation is calculated. The predetermined deviation of the etching process parameters is added to the predetermined design value of the etching process parameters to obtain the optimized result of the predetermined gate etching process parameters.

5. The method for optimizing gate etching process parameters according to claim 4, characterized in that, The process of constructing the linear relationship model between etching process parameter deviation and gate etching amount deviation is as follows: Obtain preset historical measured data of the fabrication process of historical batches of CMOS devices; wherein, the preset historical measured data includes actual measurement data of the gate size after etching, the target size after gate etching, actual data of the predetermined etching process parameters, and the design quantity of the predetermined etching process parameters; Based on the preset historical measured data, the historical measured data of the measured deviation of gate etching amount and the predetermined deviation of etching process parameters are calculated. Based on historical measured data of the measured deviation of gate etching amount and the predetermined deviation of etching process parameters, a linear relationship model between the deviation of etching process parameters and the deviation of gate etching amount is established.

6. The method for optimizing gate etching process parameters according to claim 5, characterized in that, The measured deviation of the gate etching amount is the difference between the actual measured data of the gate size after etching and the target size after gate etching.

7. The method for optimizing gate etching process parameters according to claim 5, characterized in that, The historical measured data of the deviation of the predetermined etching process parameters are the difference between the actual data of the predetermined etching process parameters and the design value of the predetermined etching process parameters.

8. The method for optimizing gate etching process parameters according to claim 1, characterized in that, The gate etching deviation is the difference between the predicted size after gate etching and the target size after gate etching.

9. The method for optimizing gate etching process parameters according to claim 4, characterized in that, It also includes a feedback correction step for the etching size prediction model, as follows: Obtain the preset feature data and actual measurement data of the gate etching dimensions from the previous batch of CMOS device fabrication process; Based on the preset feature data and actual measurement data of the gate size after etching from the previous batch of CMOS device fabrication process, the model parameters of the etching size prediction model are corrected by the exponential weighted moving average algorithm to obtain the corrected etching size prediction model.

10. A gate etching process parameter optimization system, characterized in that, A method for optimizing gate etching process parameters as described in any one of claims 1-9, comprising: The data acquisition module is used to acquire preset feature data of the current batch of CMOS device fabrication process; the preset feature data includes photoresist size before gate etching, shallow trench isolation step height, polysilicon film thickness and polysilicon linewidth roughness; The post-etching size prediction module is used to obtain the predicted size of the gate after etching based on preset feature data and combined with the etching size prediction model. The etching size prediction model is a multiple linear regression model that incorporates the photoresist size before gate etching, the shallow trench isolation step height, the polysilicon film thickness, and the polysilicon linewidth roughness. The etching deviation calculation module is used to calculate the gate etching deviation based on the predicted size after gate etching. The process parameter optimization module is used to optimize the predetermined etching process parameters based on the gate etching amount deviation, and obtain the optimization result of the predetermined gate etching process parameters.

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