A tb-rm dual-logic collaborative optimization method for larger scale circuits

Abstract

The application belongs to the field of electronic design automation, and provides a TB-RM dual-logic collaborative optimization method for large-scale circuits, which comprises the following steps: reading and analyzing a Boolean logic circuit, constructing a corresponding NAND graph, and initializing key optimization parameters; taking the NAND graph and global statistical features as optimization state information, and establishing an optimization operation set; selecting a structure-level optimization operation in the optimization operation set to perform TB structure arrangement on the NAND graph, and obtaining a circuit after redundancy elimination; detecting local substructures satisfying a predefined XOR logic pattern in the circuit after redundancy elimination, and constructing a candidate set; adopting a two-stage decision mechanism to perform RM logic re-expression on the local substructures; evaluating the TB structure arrangement operation and the RM logic re-expression operation respectively until a preset termination condition is met, and outputting an optimal TB-RM dual-logic optimized circuit. The scheme improves the overall optimization effect of large-scale combinational logic circuits under the premise of ensuring logic equivalence.

Description

Technical Field

[0001] This invention relates to the field of Electronic Design Automation (EDA) technology, and in particular to a TB (Traditional Boolean)–RM (Reed–Muller) dual logic co-optimization method for large-scale combinational logic circuits. Background Technology

[0002] As integrated circuit process nodes continue to evolve and design scales continue to increase, logic synthesis and optimization play an increasingly important role in the digital circuit design process. The logic synthesis stage not only needs to ensure the correctness of circuit function, but also needs to balance indicators such as area and delay to meet the performance and cost requirements of engineering applications.

[0003] Existing logic synthesis optimization methods are typically based on traditional logic representations such as And-Inverter Graphs (AIGs), optimizing circuit structures through pre-defined graph transformation operations (such as rewriting and balancing). These methods offer advantages such as high engineering maturity and strong stability, but the optimization process often relies on fixed rules or static scripts, making it difficult to adaptively select optimization operations for different circuit structures. This results in untapped optimization potential in some circuits.

[0004] On the other hand, Reed-Muller (RM) logic can achieve a more compact implementation in circuit structures containing XOR / XNOR features, with the potential to reduce logic size and improve implementation quality. However, when RM logic-related optimization methods are directly applied in large-scale circuits, they are prone to problems such as increased candidate space, difficulty in re-expression decision-making, and impact on circuit structure sharing, which leads to unstable optimization results and makes it difficult to meet engineering usability requirements.

[0005] Therefore, there is an urgent need for a logic circuit synthesis optimization method that can leverage the advantages of TB logic and RM logic while maintaining engineering availability, and achieve stable optimization for large-scale circuits. Summary of the Invention

[0006] To address the problems of fixed optimization strategies, insufficient cross-logic representation coordination, and instability of XOR structure re-expression in large-scale circuits in existing technologies, this invention provides a TB-RM dual-logic collaborative optimization method for larger-scale circuits, thereby expanding the optimization space and improving the optimization effect in the logic synthesis stage.

[0007] To achieve the above objectives, this invention provides a TB-RM dual logic co-optimization method for large-scale circuits, comprising the following steps: Read and parse the input Boolean logic circuit, construct the NAND graph corresponding to the Boolean logic circuit, and initialize the key optimization parameters; The NAND graph and the pre-obtained global statistical features are used as optimization state information, and a set of optimization operations is established. Select a structure-level optimization operation from the set of optimization operations to perform TB structure rectification on the NAND graph to obtain a circuit with redundancy elimination; In the circuit after redundancy elimination, detect local substructures that satisfy a predefined XOR logic pattern and construct a candidate set; A two-stage decision-making mechanism is used to re-represent the local substructures in the candidate set using RM logic, resulting in an optimized circuit with the re-represented structure. The TB structure reorganization operation and the RM logic re-expression operation are evaluated separately until the evaluation results are combined to determine that the preset termination condition is met, and then the optimal TB-RM dual logic optimization circuit is output.

[0008] Furthermore, the TB structural reorganization operation is evaluated, including: local structural improvement evaluation, baseline deviation constraint evaluation, and final evaluation; The local structure improvement evaluation is used to reflect the changes in the number of AND gate nodes and the number of logic layers before and after the TB structure reorganization operation. The formula is as follows:

[0009]

[0010] In the formula, This represents the change in the number of gate nodes before and after the TB structure reorganization operation. This indicates the change in the number of logical layers before and after the TB structure reorganization operation. This represents the number of nodes at step t. This represents the logical layer number at step t. This indicates a reward for improving local structural features. and These are the node reward weight and the level reward weight, respectively.

[0011] Furthermore, the baseline deviation constraint evaluation is used to assess the degradation behavior of the constraint optimization process when the structural quality is significantly worse than the preset baseline, as shown in the following formula:

[0012] In the formula, Indicates baseline deviation penalty, and These represent the penalty coefficients for deviations from the relative baseline node and the penalty coefficients for deviations from the baseline level, respectively. and This serves as the baseline for the number of nodes and levels.

[0013] Furthermore, the final evaluation is used to evaluate the optimal circuit result obtained at the end of a single optimization round, as shown in the following formula:

[0014] In the formula, This represents the final reward, and provides an additional reward if the best result is not worse than the baseline, otherwise... This represents the multiplier factor for the final reward. and These represent the optimal number of nodes and the optimal number of levels in the optimized circuit, respectively.

[0015] Furthermore, the TB structure reorganization operation and the RM logic re-expression operation adopt a shared structure representation space with the unified encoding of non-graph nodes; The shared structure representation space is a node representation space obtained by uniformly encoding the nodes in the AND and NOT graphs. The TB structure arrangement operation and the RM logic re-expression operation share the node representation space to realize the encoding and comparison of local substructures.

[0016] Furthermore, the two-stage decision-making mechanism includes: Candidate selection phase: Select the target substructure from the unselected local substructures in the candidate set; Rewrite determination phase: The selected target substructure is rewritten. If it is determined that rewriting is to be performed, the target substructure is logically re-expressed. Otherwise, the target substructure is skipped.

[0017] Furthermore, the evaluation criteria for evaluating the RM logic re-expression operation include: A pre-defined negative evaluation is assigned to the skipping behavior. ; A penalty is imposed on failures in logical equivalence verification. ; A positive evaluation is assigned to the successful logical re-expression based on the change in the number of XOR logic units and the joint situation with the change in the number of logic units. .

[0018] Furthermore, the failure of the logical equivalence verification is defined as follows: when performing equivalence verification on the re-expressed optimized circuit, it is determined that the re-expressed optimized circuit and the original circuit do not satisfy logical equivalence.

[0019] Furthermore, the set of optimization operations includes: non-graph transformation operations related to TB structure rearrangement operations and XOR candidate selective rewriting operations related to RM structure re-expression operations.

[0020] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention combines the non-graph-level structure organization and the selective re-expression of the XOR logic substructure through the TB–RM phased collaborative optimization method, which expands the logic synthesis optimization space while maintaining engineering usability.

[0021] (2) The present invention enables the optimization process to adaptively adjust the optimization operation for different circuit structures through the evaluation index-driven optimization strategy iteration update mechanism, thereby improving the stability of the optimization process and suppressing the abnormal degradation of intermediate states.

[0022] (3) In the structural arrangement stage, the present invention organizes the redundant structure of the circuit and selectively rewrites the XOR logic feature substructure in the logic re-expression stage, thereby improving the overall optimization effect of large-scale combinational logic circuits while ensuring logical equivalence. Attached Figure Description

[0023] Figure 1 The flowchart illustrates a TB–RM dual logic co-optimization method for large-scale circuits provided by this invention. Detailed Implementation

[0024] The technical solution of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0025] like Figure 1 As shown, the TB-RM dual logic collaborative optimization method for large-scale circuits provided in this embodiment of the invention specifically includes the following steps: Step 110: Read and parse the input Boolean logic circuit, construct the corresponding NAND graph of the Boolean logic circuit, and initialize the key optimization parameters.

[0026] In practical applications, the input Boolean logic circuit file can be read and parsed to extract the circuit logic function and topology, and construct the NAND graph structure corresponding to the Boolean logic circuit. At the same time, the key optimization parameters are initialized, including the upper limit of the number of iterations, the upper limit of the number of interactions, the termination threshold, the baseline parameters, the weight coefficients, and the penalty coefficients.

[0027] Step 120: Use the NAND graph and the pre-obtained global statistical features as optimization state information, and establish a set of optimization operations.

[0028] In this embodiment, the current NAND graph structure and global statistical features, including the number of circuit nodes, the number of logic layers, and the fan-in and fan-out distribution, can be used together as optimization state information; an optimization operation set including TB structure reorganization and RM logic re-expression can be established to provide an operational basis for subsequent optimization decisions.

[0029] Step 130: Select the structure-level optimization operation from the set of optimization operations to perform TB structure rectification on the AND-NOT graph to obtain the circuit after redundancy elimination.

[0030] In practical applications, based on the optimization state information, appropriate structure-level optimization operations can be selected from the set of optimization operations to perform TB structure reorganization on the NAND graph, eliminate redundant nodes, merge duplicate logic, simplify the circuit topology, and obtain the circuit after redundancy elimination.

[0031] Step 140: In the circuit after redundancy elimination, detect local substructures that satisfy the predefined XOR logic pattern and construct a candidate set.

[0032] In the circuit after redundancy elimination, all local substructures can be traversed to detect local substructures that satisfy the predefined XOR logic pattern, and the local substructures that meet the conditions can be collected to construct a candidate set of XOR local substructures.

[0033] Step 150: Use a two-stage decision-making mechanism to perform RM logic re-expression on the local substructures in the candidate set to obtain the optimized circuit of the re-expression.

[0034] Specifically, this embodiment adopts a two-stage decision-making mechanism of candidate selection and rewriting determination. The local substructures in the candidate set are re-expressed using RM logic, and the XOR logic rewriting is completed under the premise of ensuring logical equivalence, resulting in the optimized circuit after re-expression.

[0035] Step 160: Evaluate the TB structure reorganization operation and the RM logic re-expression operation respectively until the evaluation results determine that the preset termination condition is met, and then output the optimal TB-RM dual logic optimization circuit.

[0036] This embodiment performs phase evaluations on the TB structure reorganization operation and the RM logic re-expression operation, and updates the optimization strategy based on the evaluation results. The above optimization steps are executed cyclically. When the number of iterations reaches the upper limit, the circuit quality is not significantly improved, or other preset termination conditions are met, the current optimal TB-RM dual logic optimization circuit is output.

[0037] In one embodiment, when evaluating the TB structure improvement operation, a three-order evaluation system is specifically adopted, including: local structure improvement evaluation, baseline deviation constraint evaluation, and final evaluation.

[0038] The local structure improvement evaluation reflects the changes in the number of gate nodes and the number of logic layers before and after the TB structure reorganization operation. The calculation process requires first calculating the changes in the number of nodes and the number of logic layers, and then calculating the local structure improvement reward. The specific formula is as follows:

[0039]

[0040] In the formula, This represents the change in the number of gate nodes before and after the TB structure reorganization operation. This indicates the change in the number of logical layers before and after the TB structure reorganization operation. This represents the number of nodes at step t. This represents the logical layer number at step t. This indicates a reward for improving local structural features. and These are the node reward weight and the level reward weight, respectively.

[0041] Furthermore, baseline deviation constraint evaluation is used to constrain the degradation behavior of the optimization process when the structural quality is significantly worse than the preset baseline, thereby avoiding degradation due to the circuit structure being significantly worse than the preset baseline. The specific formula is as follows:

[0042] In the formula, Indicates baseline deviation penalty, and These represent the penalty coefficients for deviations from the relative baseline node and the penalty coefficients for deviations from the baseline level, respectively. and This serves as the baseline for the number of nodes and levels. When the current number of circuit nodes or levels exceeds the baseline, a penalty term is applied to suppress degradation operations.

[0043] Furthermore, the final evaluation is used to evaluate the optimal circuit result obtained at the end of a single optimization round. Specifically, it can be used to comprehensively score the optimal circuit result at the end of a single optimization round, as shown in the following formula:

[0044] In the formula, This represents the final reward, and provides an additional reward if the best result is not worse than the baseline, otherwise... This represents the multiplier factor for the final reward. and These represent the optimal number of nodes and the optimal number of levels in the optimized circuit, respectively.

[0045] If the optimal circuit result is not worse than the baseline, an additional reward is given; if it is worse than the baseline, the reward is reduced or a penalty is imposed to guide the optimization towards a better direction.

[0046] In one embodiment, the TB structure reorganization operation and the RM logic re-expression operation adopt a shared structure representation space with the non-graph node uniform encoding.

[0047] The shared structure representation space is: the node representation space obtained by uniformly encoding the nodes in the AND and NOT graphs. The TB structure arrangement operation and the RM logical re-expression operation share the node representation space to realize the encoding and comparison of local substructures.

[0048] In this embodiment, all nodes in the AND-NOT graph are uniformly numbered, feature extracted, and vectorized to form a unified node encoding space. The TB structure arrangement stage and the RM logic re-expression stage share this representation space to achieve a unified description of the circuit structure, fast encoding of local substructures, feature extraction, and similarity comparison, ensuring that the dual logic optimization works collaboratively on the same structure.

[0049] In one embodiment, the two-stage decision-making mechanism specifically includes: Candidate selection phase: Select the target substructure from the unselected local substructures in the candidate set.

[0050] Rewrite determination phase: This phase can determine the rewrite benefit of the target substructure. Specifically, it determines whether to rewrite the selected target substructure. If it is determined that rewriting is to be performed, the target substructure is logically re-expressed. Otherwise, the target substructure is skipped.

[0051] Understandably, if it is determined that rewriting can reduce nodes, lower the number of layers, or improve circuit regularity, then the logic re-expression operation is performed; if it is determined that rewriting has no benefit or may damage the circuit structure, then the target substructure is skipped and no rewriting is performed.

[0052] This two-stage decision-making mechanism, through a step-by-step approach of first screening target substructures and then judging the benefits of rewriting, can accurately locate XOR logic substructures with optimization value, avoid invalid rewriting and resource waste, and improve the rewriting success rate while ensuring logical equivalence. At the same time, it can flexibly control the rewriting scope and optimization intensity, making RM logic re-expression more stable and efficient, forming a good synergy with TB structure consolidation, and significantly improving the overall optimization effect of large-scale circuits.

[0053] In one embodiment, the evaluation criteria for evaluating the RM logic re-expression operation include: A pre-defined negative evaluation is assigned to the skipping behavior. .

[0054] A penalty is imposed on failures in logical equivalence verification. .

[0055] A positive evaluation is assigned to the successful logical re-expression based on the change in the number of XOR logic units and the joint situation with the change in the number of logic units. .

[0056] Understandably, adopting a differentiated evaluation mechanism for RM logic re-expression operations—by assigning negative evaluations to skipping candidate substructures, penalizing rewriting behaviors that fail to verify logical equivalence, and assigning positive evaluations to successful re-expression behaviors that maintain logical equivalence and achieve circuit structure optimization—can effectively guide the optimization process to prioritize the rewriting of valuable XOR substructures, suppress meaningless skipping operations and invalid rewriting, and ensure that RM logic re-expression improves circuit optimization within a stable and controllable range.

[0057] Specifically, a logical equivalence verification failure occurs when the optimized circuit of the re-expressed circuit is tested for equivalence and it is determined that the optimized circuit of the re-expressed circuit is not logically equivalent to the original circuit.

[0058] In this embodiment, the optimized circuit after the RM logic re-expression is compared with the original circuit using formal verification or simulation verification methods. If there is at least one set of input combinations that makes the outputs of the two inconsistent, it is determined that the re-expressed circuit does not satisfy the logical equivalence of the original circuit, the rewrite is invalid and a penalty is imposed.

[0059] In one embodiment, the set of optimization operations includes: NAND-non-graph transformation operations related to TB structure rearrangement operations and XOR candidate selective rewrite operations related to RM structure re-expression operations.

[0060] In this embodiment, the optimization operation set includes two types of core operations, as follows: TB structure management related operations: refers to non-graph level graph transformation operations, including node rewriting, redundancy elimination, structure balancing, subgraph merging, fan-in and fan-out optimization, and other AIG standard optimization operations; RM logic re-expression related operations: refers to the selective rewriting operation of XOR candidate substructures, including XOR pattern matching, substructure extraction, RM logic replacement, equivalence checking and other re-expression operations oriented towards Reed-Muller logic.

[0061] In practical applications, the two types of operations mentioned above are uniformly incorporated into the optimization decision space, thereby enabling TB–RM dual-logic collaborative optimization.

[0062] In summary, this invention, through phased collaborative optimization of TB-RM and a unified graph structure representation mechanism, can expand the logic optimization space while maintaining engineering usability. Furthermore, through iterative updates of adaptive optimization strategies, it achieves automatic adjustment of the logic optimization decision-making process, thereby improving the overall optimization effect of large-scale combinational logic circuits.

[0063] The above description is merely a preferred embodiment of the present invention and does not constitute any limitation on the technical scope of the present invention. Therefore, any minor modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention shall still fall within the scope of the technical solution of the present invention.

Claims

1. A TB–RM dual-logic collaborative optimization method for large-scale circuits, characterized in that, Includes the following steps: Read and parse the input Boolean logic circuit, construct the NAND graph corresponding to the Boolean logic circuit, and initialize the key optimization parameters; The NAND graph and the pre-obtained global statistical features are used as optimization state information, and a set of optimization operations is established. Select a structure-level optimization operation from the set of optimization operations to perform TB structure rectification on the NAND graph to obtain a circuit with redundancy elimination; In the circuit after redundancy elimination, detect local substructures that satisfy a predefined XOR logic pattern and construct a candidate set; A two-stage decision-making mechanism is used to re-represent the local substructures in the candidate set using RM logic, resulting in an optimized circuit with the re-represented structure. The TB structure reorganization operation and the RM logic re-expression operation are evaluated separately until the evaluation results are combined to determine that the preset termination condition is met, and then the optimal TB-RM dual logic optimization circuit is output.

2. The method according to claim 1, characterized in that, The evaluation of TB structural improvement operations includes: evaluation of local structural improvement, evaluation of baseline deviation constraints, and final evaluation. The local structure improvement evaluation is used to reflect the changes in the number of AND gate nodes and the number of logic layers before and after the TB structure reorganization operation. The formula is as follows: ， ， In the formula, This represents the change in the number of gate nodes before and after the TB structure reorganization operation. This indicates the change in the number of logical layers before and after the TB structure reorganization operation. This represents the number of nodes at step t. This represents the logical layer number at step t. This indicates a reward for improving local structural features. and These are the node reward weight and the level reward weight, respectively.

3. The method according to claim 2, characterized in that, The baseline deviation constraint evaluation is used to assess the degenerate behavior of the constraint optimization process when the structural quality is significantly worse than the preset baseline. The formula is as follows: ， In the formula, Indicates baseline deviation penalty, and These represent the penalty coefficients for deviations from the relative baseline node and the penalty coefficients for deviations from the baseline level, respectively. and This serves as the baseline for the number of nodes and levels.

4. The method according to claim 2, characterized in that, The final evaluation is used to evaluate the optimal circuit result at the end of a single optimization round, and the formula is as follows: ， In the formula, This represents the final reward, and provides an additional reward if the best result is not worse than the baseline, otherwise it is not. This represents the multiplier factor for the final reward. and These represent the optimal number of nodes and the optimal number of levels in the optimized circuit, respectively.

5. The method according to claim 1, characterized in that, The TB structure reorganization operation and the RM logic re-expression operation adopt a shared structure representation space with the unified encoding of non-graph nodes; The shared structure representation space is a node representation space obtained by uniformly encoding the nodes in the AND and NOT graphs. The TB structure arrangement operation and the RM logic re-expression operation share the node representation space to realize the encoding and comparison of local substructures.

6. The method according to claim 1, characterized in that, The two-stage decision-making mechanism includes: Candidate selection phase: Select the target substructure from the unselected local substructures in the candidate set; Rewrite determination phase: The selected target substructure is rewritten. If it is determined that rewriting is to be performed, the target substructure is logically re-expressed. Otherwise, the target substructure is skipped.

7. The method according to claim 1, characterized in that, The evaluation criteria for assessing the RM logic re-expression operation include: A pre-defined negative evaluation is assigned to the skipping behavior. ; A penalty is imposed on failures in logical equivalence verification. ; A positive evaluation is assigned to the successful logical re-expression based on the change in the number of XOR logic units and the joint situation with the change in the number of logic units. .

8. The method according to claim 7, characterized in that, The failure of the logical equivalence verification is as follows: when performing equivalence verification on the re-expressed optimized circuit, it is determined that the re-expressed optimized circuit and the original circuit do not satisfy logical equivalence.

9. The method according to claim 1, characterized in that, The set of optimization operations includes: non-graph transformation operations related to TB structure rearrangement operations and XOR candidate selective rewriting operations related to RM structure re-expression operations.

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