Clock frequency detection circuit and memory

Abstract

The application discloses a clock frequency detection circuit and a memory. The detection circuit comprises a first processing module, a charge pump and a second processing module. The first processing module is used for receiving a reference clock signal and a clock signal to be tested, and outputs a first clock signal based on the reference clock signal and a second clock signal based on the clock signal to be tested. The charge pump receives the first clock signal and outputs a first voltage signal within a first time length of the first clock signal, and receives the second clock signal and outputs a second voltage signal within a second time length of the second clock signal. The second processing module receives the first voltage signal and the second voltage signal, and outputs a first count value and a second count value based on the corresponding voltage signal count. The first count value is related to the reference frequency of the reference clock signal. The control module receives the first count value and the second count value, and calculates the frequency of the clock signal to be tested based on the first count value and the second count value. In this way, the frequency of the clock signal to be tested can be calculated.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to clock frequency detection circuits and memories. Background Technology

[0002] With the development of electronic technology, clocks are crucial for high-speed electronic devices, ensuring the synchronization of various modules and coordinating their actions. The clock frequency directly determines the operating speed of each module. Therefore, the clock signal frequency can be monitored, allowing for timely adjustments if the frequency is too high or too low, thus preventing any impact on the system operation of the electronic device.

[0003] However, clock frequency detection circuits in related technologies typically use different devices to control and detect the high and low levels of the clock separately, which is extremely easy to affect the accuracy of the clock frequency detection results due to device parameter drift or mismatch. Summary of the Invention

[0004] This application provides a clock frequency detection circuit and memory. Based on a reference clock signal and a clock signal to be tested, a first clock signal and a second clock signal are obtained respectively. Then, the same charge pump, second processing module and control module are used to detect the first clock signal and the second clock signal to detect the frequency of the clock signal to be tested. This can avoid the phenomenon that the detection results are affected by device drift or mismatch when using different charge pumps, second processing modules and / or control modules, thereby improving the detection accuracy.

[0005] To address the aforementioned technical problems, this application provides a clock frequency detection circuit, comprising a first processing module, a charge pump, a second processing module, and a control module. The first processing module is configured to receive a reference clock signal and a clock signal to be tested, and output a first clock signal based on the reference clock signal and a second clock signal based on the clock signal to be tested. The charge pump is configured to receive the first clock signal and output a first voltage signal within a first time length of the first clock signal, and to receive the second clock signal and output a second voltage signal within a second time length of the second clock signal. The second processing module is configured to receive the first voltage signal, count based on the first voltage signal, and output a first count value, and to receive the second voltage signal, count based on the second voltage signal, and output a second count value. The first count value is related to a reference frequency of the reference clock signal. The control module receives the first count value and the second count value, and calculates the frequency of the clock signal to be tested based on the first count value and the second count value.

[0006] In some embodiments, the second processing module includes a comparator, an AND gate, and a counter. The inverting input of the comparator is coupled to the output of a charge pump and receives a first voltage signal and a second voltage signal, respectively. The non-inverting input of the comparator is coupled to a reference voltage terminal. The comparator outputs a third voltage signal based on the first voltage signal and a fourth voltage signal based on the second voltage signal. The first input of the AND gate is coupled to the output of the comparator, and the second input of the AND gate receives an enable signal. The AND gate outputs a fifth voltage signal during the high levels of the third voltage signal and the enable signal, and outputs a sixth voltage signal during the high levels of the fourth voltage signal and the enable signal. The enable terminal of the counter is coupled to the output of the AND gate, receives the fifth voltage signal, counts based on the fifth voltage signal, and outputs a first count value; and receives the sixth voltage signal, counts based on the sixth voltage signal, and outputs a second count value.

[0007] In some embodiments, after receiving the first count value, the control module sends a reset signal to the counter and the charge pump; the counter and the charge pump perform a reset operation based on the reset signal.

[0008] In some embodiments, the charge pump includes a first switching circuit and a charging / discharging circuit. The control terminal of the first switching circuit is coupled to the output terminal of the first processing module; the first terminal of the charging / discharging circuit is coupled to the first switching circuit, the second terminal of the charging / discharging circuit is grounded, and the control terminal of the charging / discharging circuit receives a reset signal; the coupling point between the charging / discharging circuit and the first switching circuit serves as the output terminal of the charge pump; the first switching circuit charges the charging / discharging circuit during a low level of a first clock signal and outputs a first voltage signal during the charging cycle; the first switching circuit charges the charging / discharging circuit during a low level of a second clock signal and outputs a second voltage signal during the charging cycle; and the charging / discharging circuit has completed a discharging operation according to the reset signal before the first switching circuit receives the second clock signal.

[0009] In some embodiments, the first switching circuit includes a current source and a first switching device. A first terminal of the first switching device is coupled to the output terminal of the current source, a second terminal of the first switching device is coupled to a charging / discharging circuit, and a control terminal of the first switching device is coupled to the output terminal of a first processing module. The first switching device is turned on during a low level of a first clock signal, charging the charging / discharging circuit through the current source and outputting a first voltage signal during the charging cycle. The first switching device is turned on during a low level of a second clock signal, charging the charging / discharging circuit through the current source and outputting a second voltage signal during the charging cycle. Before the first switching device receives the second clock signal, the charging / discharging circuit has completed a discharge operation according to a reset signal.

[0010] In some embodiments, the charging and discharging circuit includes a capacitor and a second switching device. The first plate of the capacitor is coupled to a first switching circuit, and the second plate of the capacitor is grounded. The first terminal of the second switching device is coupled to the first plate of the capacitor, and the second terminal of the second switching device is grounded. The control terminal of the second switching device is used to receive a reset signal. The first switching circuit charges the capacitor during a low level of a first clock signal and outputs a first voltage signal during the charging cycle, while the second switching device is in a cutoff state. The first switching circuit also charges the capacitor during a low level of a second clock signal and outputs a second voltage signal during the charging cycle, while the second switching device is in a cutoff state. Before the first switching circuit receives the second clock signal, the second switching device is turned on according to the reset signal to complete the discharging operation of the capacitor.

[0011] In some embodiments, the first processing module includes a second switching circuit, which is used to receive a reference clock signal and a clock signal to be tested, and to output the reference clock signal and the clock signal to be tested; a rising edge detection circuit, which is coupled to the output terminal of the second switching circuit, receives the reference clock signal, and outputs a first clock signal related to the rising edge of the reference clock signal; and the rising edge detection circuit receives the clock signal to be tested and outputs a second clock signal related to the rising edge of the clock signal to be tested.

[0012] In some embodiments, the rising edge detection circuit includes: an inverter, the input of which is coupled to the output of a second switching circuit, receiving a reference clock signal and a clock signal to be tested, respectively; the inverter inverts the reference clock signal to output a seventh voltage signal, and inverts the clock signal to be tested to output an eighth voltage signal; a delay unit, the input of which is coupled to the output of the inverter, delaying the seventh voltage signal to output a ninth voltage signal, and delaying the eighth voltage signal to output a tenth voltage signal; and a NAND gate, the first input of which is coupled to the output of the delay unit. The second input terminal of the NAND gate is coupled to the output terminal of the second switching circuit; wherein, the NAND gate outputs a first voltage signal based on the reference clock signal and the ninth voltage signal during the first time length, and outputs a second voltage signal based on the test clock signal and the tenth voltage signal during the second time length; wherein, when the NAND gate is simultaneously at a high level of the reference clock signal and at a high level of the ninth voltage signal, it outputs a first voltage signal with a low level, and when the NAND gate is simultaneously at a high level of the test clock signal and at a high level of the tenth voltage signal, it outputs a second voltage signal with a low level.

[0013] In some embodiments, the second switching circuit includes a third switching device and a fourth switching device; when the third switching device is turned on and the fourth switching device is turned off, a reference clock signal is provided to the rising edge detection circuit; when the fourth switching device is turned on and the third switching device is turned off, a clock signal to be tested is provided to the rising edge detection circuit.

[0014] In some embodiments, the control module obtains the frequency of the clock signal to be tested by dividing the product of a first count value and the frequency of the reference clock signal by a second count value; wherein the first count value is inversely proportional to the reference frequency of the reference clock signal, and the second count value is inversely proportional to the frequency of the clock signal to be tested.

[0015] In order to solve the above-mentioned technical problems, this application provides another aspect of a memory, which includes the detection circuit described above.

[0016] The clock frequency detection circuit provided in some embodiments of this application includes a first processing module, a charge pump, a second processing module, and a control module. The first processing module is configured to receive a reference clock signal and a clock signal to be tested, and output a first clock signal based on the reference clock signal and a second clock signal based on the clock signal to be tested. The charge pump is configured to receive the first clock signal and output a first voltage signal within a first time length of the first clock signal, and to receive the second clock signal and output a second voltage signal within a second time length of the second clock signal. The second processing module is configured to receive the first voltage signal, count based on the first voltage signal, and output a first count value, and to receive the second voltage signal, count based on the second voltage signal, and output a second count value, wherein the first count value is related to a reference frequency of the reference clock signal. The control module receives the first count value and the second count value, and calculates the frequency of the clock signal to be tested based on the first count value and the second count value. In the process of detecting the frequency of the clock signal under test, using the same devices (i.e., charge pump, second processing module and control module) to detect the first clock signal and the second clock signal corresponding to the clock signal under test and the reference clock signal can avoid device drift or mismatch that occurs when using different charge pumps, second processing modules and / or control modules for detection, thus avoiding affecting the detection results and improving the detection accuracy. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0018] Figure 1This is a schematic diagram of the clock frequency detection circuit provided in some embodiments of this application;

[0019] Figure 2 This is a schematic diagram of the structure of the second processing module provided in some embodiments of this application;

[0020] Figure 3 This is a schematic diagram of the charge pump provided in some embodiments of this application;

[0021] Figure 4 This is a schematic diagram of the structure of the first switching circuit provided in some embodiments of this application;

[0022] Figure 5 This is a schematic diagram of the charging and discharging circuit provided in some embodiments of this application;

[0023] Figure 6 This is a schematic diagram of the structure of the first processing module provided in some embodiments of this application;

[0024] Figure 7 This is a schematic diagram of the structure of the second switching circuit provided in some embodiments of this application;

[0025] Figure 8 This is a schematic diagram of the rising edge detection circuit provided in some embodiments of this application;

[0026] Figure 9 This is a schematic diagram of the clock frequency detection circuit provided in some embodiments of this application;

[0027] Figure 10 yes Figure 9 The timing diagram of the clock frequency detection circuit shown is shown.

[0028] Figure 11 This is a schematic diagram of the memory structure provided in some embodiments of this application. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0030] See Figure 1 , Figure 1 This is a schematic diagram of the clock frequency detection circuit provided in some embodiments of this application. The clock frequency detection circuit 10 includes a first processing module 101, a charge pump 102, a second processing module 103, and a control module 104.

[0031] The first processing module 101 is configured to receive a reference clock signal and a clock signal to be tested, and output a first clock signal based on the reference clock signal and a second clock signal based on the clock signal to be tested. That is, the first processing module 101 can output the first clock signal and the second clock signal respectively as needed.

[0032] The charge pump 102 receives a first clock signal and outputs a first voltage signal within a first time length of the first clock signal.

[0033] The charge pump 102 receives a second clock signal and outputs a second voltage signal within a second time length of the second clock signal.

[0034] The second processing module 103 receives a first voltage signal, counts based on the first voltage signal, and outputs a first count value; and receives a second voltage signal, counts based on the second voltage signal, and outputs a second count value. The first count value is related to the reference frequency of the reference clock signal, and the second count value is related to the frequency of the clock signal to be tested.

[0035] For example, the first count value is positively correlated with the reference frequency of the reference clock signal, and the second count value is positively correlated with the frequency of the clock signal under test.

[0036] For example, the first count value is negatively correlated with the reference frequency of the reference clock signal, and the second count value is negatively correlated with the frequency of the clock signal under test.

[0037] In some embodiments, the ratio between the first time length and the second time length can be determined according to the actual situation.

[0038] In some embodiments, the first time length and the second time length can be determined based on the corresponding reference voltage value in the second processing module 103. The first time length ends when the first voltage signal is greater than the reference voltage value. The second time length ends when the second voltage signal is greater than the reference voltage value.

[0039] In some embodiments, the first time length is related to the reference frequency of the reference clock signal, and the second time length is related to the frequency of the clock signal to be tested.

[0040] For example, the first time length is positively correlated with the reference frequency of the reference clock signal, and the second time length is positively correlated with the frequency of the clock signal to be tested.

[0041] For example, the first time length is negatively correlated with the reference frequency of the reference clock signal, and the second time length is negatively correlated with the frequency of the clock signal under test.

[0042] In some embodiments, a first time length is related to a low level of a first clock signal, and a second time length is related to a low level of a second clock signal. Based on this, a first count value is related to a low level of the first clock signal and also to the frequency of a reference clock signal; a second count value is related to a low level of the second clock signal and also to the frequency of the clock signal under test.

[0043] In other embodiments, the first time length is related to the high level of the first clock signal, and the second time length is related to the high level of the second clock signal. Based on this, the first count value is related to the high level of the first clock signal and the frequency of the reference clock signal; the second count value is related to the high level of the second clock signal and the frequency of the clock signal under test.

[0044] The control module 104 receives the first count value and the second count value, and calculates the frequency of the clock signal to be tested based on the first count value and the second count value.

[0045] In some embodiments of this application, the clock frequency detection circuit 10 uses the same devices (i.e., charge pump 102, second processing module 103, and control module 104) to detect the first clock signal and the second clock signal corresponding to the reference clock signal and the clock signal to be tested. This can avoid device drift or mismatch that occurs when different charge pumps 102, second processing module 103, and / or control module 104 are used for detection, thus avoiding affecting the detection results and improving the detection accuracy.

[0046] In some embodiments, such as Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of the second processing module provided in some embodiments of this application. The second processing module 103 includes a comparator 1031, an AND gate 1032 and a counter 1033.

[0047] In this configuration, the inverting input of comparator 1031 is coupled to the output of charge pump 102, and receives a first voltage signal and a second voltage signal respectively. The non-inverting input of comparator 1031 is coupled to a reference voltage terminal. Comparator 1031 outputs a third voltage signal based on the first voltage signal and a fourth voltage signal based on the second voltage signal. In some embodiments, the second voltage signal is generated after the first voltage signal has finished.

[0048] The first input terminal of AND gate 1032 is coupled to the output terminal of comparator 1031, and the second input terminal of AND gate 1032 receives an enable signal; wherein, AND gate 1032 outputs a fifth voltage signal during the high level of the third voltage signal and the enable signal, and AND gate 1032 outputs a sixth voltage signal during the high level of the fourth voltage signal and the enable signal.

[0049] The enable terminal of counter 1033 is coupled to the output terminal of AND gate 1032. Counter 1033 receives a fifth voltage signal and counts based on the fifth voltage signal to output a first count value; and counter 1033 receives a sixth voltage signal and counts based on the sixth voltage signal to output a second count value.

[0050] For example, the inverting input of comparator 1031 ( Figure 2 (Used as a "-") for receiving the first voltage signal or the second voltage signal. Figure 2 In this text, "VC1" represents the first voltage signal and the second voltage signal, and the non-inverting input of comparator 1031 ( Figure 2 (Used as a "+") for receiving reference voltage signals. Figure 2 (represented by "VREF" in Chinese). Based on this, the two input terminals of comparator 1031 are used to receive a first voltage signal and a reference voltage signal, and compare the first voltage signal and the reference voltage signal to output a third voltage signal. Figure 2 In this context, "CNT_GT" represents the third voltage signal.

[0051] The two input terminals of comparator 1031 are used to receive a second voltage signal and a reference voltage signal, and compare the second voltage signal and the reference voltage signal to output a fourth voltage signal. Figure 2 In this context, "CNT_GT" represents the fourth voltage signal.

[0052] The first input of AND gate 1032 is used to receive a third voltage signal or a fourth voltage signal, and the second input of AND gate 1032 is used to receive an enable signal. Figure 2 (represented as "CNT_EN" in Chinese). Based on this, the two inputs of AND gate 1032 are used to receive the third voltage signal and the enable signal, and output the fifth voltage signal during the high level of the third voltage signal and the enable signal.

[0053] The two inputs of AND gate 1032 are used to receive a fourth voltage signal and an enable signal, and output a sixth voltage signal during the high level of the fourth voltage signal and the enable signal.

[0054] The enable terminal of counter 1033 (denoted as "EN" in the figure) is used to receive the fifth or sixth voltage signal. The pulse input terminal of counter 1033 ( Figure 2 (In Chinese, "CLK" is used to indicate the clock signal of the counter.) Figure 2 (represented by "CLK_CNT" in Chinese), the reset pin of counter 1033 is used to receive the reset signal. Figure 2 (RST is used as a symbol in the diagram). Based on this, the counter 1033 receives the fifth voltage signal and the enable signal, and when the enable signal is valid, it counts the fifth voltage signal and outputs the first count value to the control module 104.

[0055] Counter 1033 receives the sixth voltage signal and the enable signal, and counts the sixth voltage signal when the enable signal is valid, and outputs the second count value to the control module 104.

[0056] In some embodiments, when the first clock signal is detected, the enable signal received by AND gate 1032 is valid (i.e., high level), the first voltage signal is less than the reference voltage signal, the third voltage signal output by the output terminal of comparator 1031 is high level, after the third voltage signal and the enable signal are input to AND gate 1032, AND gate 1032 outputs high level, and the counter 1033 is started. The counter 1033 starts counting, and the count value increases continuously under the drive of the counter clock signal.

[0057] As the first voltage signal increases, when the first voltage signal exceeds the reference voltage signal, the third voltage signal output from the comparator 1031 becomes low. The third voltage signal and the enable signal are input to the AND gate 1032, which then outputs a low level, shutting down the counter 1033. The counter 1033 then outputs its first count value to the control module 104 for storage.

[0058] In some embodiments, when detecting the second clock signal, the enable signal received by AND gate 1032 is valid (i.e., high level), the second voltage signal is less than the reference voltage signal, the fourth voltage signal output by the output terminal of comparator 1031 is high level, after the fourth voltage signal and the enable signal are input to AND gate 1032, AND gate 1032 outputs high level, starting counter 1033, counter 1033 starts counting, and the count value continuously increases under the drive of the counter clock signal.

[0059] As the second voltage signal increases, when the second voltage signal is greater than the reference voltage signal, the fourth voltage signal output by the comparator 1031 becomes low. After the fourth voltage signal and the enable signal are input to the AND gate 1032, the AND gate 1032 outputs a low level, shutting down the counter 1033. The counter 1033 then outputs the second count value at this time to the control module 104 for storage.

[0060] It is understandable that the count value in counter 1033 needs to be cleared before detecting the first clock signal or the second clock signal.

[0061] It is worth noting that since the inverting input of comparator 1031 is used to receive the first voltage signal, the first count value is proportional to the time it takes for the first voltage signal to rise from 0 to the reference voltage signal. Because the change in the first voltage signal under each pulse of the first clock signal is fixed, based on the inverse relationship between time and frequency, it can be determined that the time for the first voltage signal to rise from 0 to the reference voltage signal is inversely proportional to the reference frequency of the reference clock signal.

[0062] If the increase in the first voltage signal is determined by the high level of the first clock signal, since the change in the first voltage signal under each pulse of the first clock signal is fixed, the higher the frequency of the high level of the first clock signal, the greater the rise in the first voltage signal and the faster the rise speed, meaning the shorter the time it takes for the first voltage signal to rise from 0 to the reference voltage signal. Therefore, the first count value is inversely proportional to the frequency of the high level of the first clock signal.

[0063] If the increase in the first voltage signal is determined by the low level of the first clock signal, since the change in the first voltage signal under each pulse of the first clock signal is fixed, the higher the frequency of the low level of the first clock signal, the greater the rise in the first voltage signal and the faster the rise speed, meaning the shorter the time it takes for the first voltage signal to rise from 0 to the reference voltage signal. Based on this, the first count value is inversely proportional to the frequency of the low level of the first clock signal.

[0064] Furthermore, since the inverting input of comparator 1031 is used to receive the second voltage signal, the second count value is proportional to the time it takes for the second voltage signal to rise from 0 to the reference voltage signal. Because the change in the second voltage signal under each pulse of the second clock signal is fixed, based on the inverse relationship between time and frequency, it can be determined that the time for the second voltage signal to rise from 0 to the reference voltage signal is inversely proportional to the frequency of the clock signal under test.

[0065] If the increase in the second voltage signal is determined by the high level of the second clock signal, since the change in the second voltage signal under each pulse of the second clock signal is fixed, the higher the frequency of the high level of the second clock signal, the greater the rise in the second voltage signal and the faster the rise speed, meaning the shorter the time it takes for the second voltage signal to rise from 0 to the reference voltage signal. Therefore, the second count value is inversely proportional to the frequency of the high level of the second clock signal.

[0066] If the increase in the second voltage signal is determined by the low level of the second clock signal, since the change in the second voltage signal under each pulse of the second clock signal is fixed, the higher the frequency of the low level of the second clock signal, the greater the rise in the second voltage signal and the faster the rise speed. In other words, the time it takes for the first voltage signal to rise from 0 to the reference voltage signal is shorter. Therefore, the second count value is inversely proportional to the frequency of the low level of the second clock signal.

[0067] In some embodiments, after receiving the first count value, the control module 104 sends a reset signal to the counter 1033 and the charge pump 102; the counter 1033 and the charge pump 102 perform a reset operation based on the reset signal. The counter 1033 clears the count value based on the reset signal. The charge pump 102 performs a discharge operation based on the reset signal.

[0068] In some embodiments, after receiving the second count value, the control module 104 sends a reset signal to the counter 1033 and the charge pump 102; the counter 1033 and the charge pump 102 perform a reset operation based on the reset signal. The counter 1033 clears its count value based on the reset signal. The charge pump 102 performs a discharge operation based on the reset signal.

[0069] In some embodiments, the control module 104 sends a reset signal to both the counter 1033 and the charge pump 102 simultaneously, or the control module 104 sends a reset signal to the counter 1033, and the counter 1033 sends a reset signal to the charge pump 102 through the reset terminal.

[0070] It is understandable that after the counter 1033 finishes counting, if it wants to count other signals, it needs to use a reset signal to clear the count value to zero in order to avoid abnormal phenomena such as inaccurate counting or counting interruption.

[0071] In some embodiments, such as Figure 3 As shown, Figure 3 This is a schematic diagram of the structure of a charge pump provided in some embodiments of this application. The charge pump 102 includes a first switching circuit 1021 and a charging / discharging circuit 1022. The control terminal of the first switching circuit 1021 is coupled to the output terminal of the first processing module 101.

[0072] The first terminal of the charging and discharging circuit 1022 is coupled to the first switching circuit 1021, the second terminal of the charging and discharging circuit 1022 is grounded, and the control terminal of the charging and discharging circuit 1022 receives a reset signal; wherein, the coupling point between the charging and discharging circuit 1022 and the first switching circuit 1021 serves as the output terminal of the charge pump 102.

[0073] The first switching circuit 1021 charges the charging and discharging circuit 1022 during the low level of the first clock signal and outputs the first voltage signal during the charging cycle; before the first switching circuit 1021 receives the first clock signal, the charging and discharging circuit 1022 has completed the discharging operation according to the reset signal.

[0074] The first clock signal actually alternates between high and low levels. During the low level period of the first clock signal, the first switching circuit 1021 charges the charging and discharging circuit 1022, meaning it can output a gradually increasing first voltage signal during the low level period. During the high level period, since the charging and discharging circuit 1022 has already been charged during the low level period, it can maintain the output of the first voltage signal during the high level period. The voltage value of the first voltage signal will not increase during the high level period.

[0075] The first switching circuit 1021 charges the charging and discharging circuit 1022 during the low level of the second clock signal and outputs the second voltage signal during the charging cycle; the charging and discharging circuit 1022 has completed the discharging operation according to the reset signal before the first switching circuit 1021 receives the second clock signal.

[0076] The second clock signal actually alternates between high and low levels. During the low level period of the second clock signal, the first switching circuit 1021 charges the charging and discharging circuit 1022, meaning it can output a gradually increasing second voltage signal during the low level period. During the high level period, since the charging and discharging circuit 1022 has already been charged during the low level period, it can maintain the output of the second voltage signal during the high level period. The voltage value of the second voltage signal will not increase during the high level period.

[0077] It is understood that before the control terminal of the first switching circuit 1021 receives the first clock signal or the second clock signal output by the first processing module 101, the charging and discharging circuit 1022 receives the reset signal sent by the control module 104 or the counter 1033, and performs a reset operation based on the reset signal when the reset signal is valid, so as to set the initial state of the charging and discharging circuit 1022.

[0078] It is worth noting that before counting different signals, a discharge operation needs to be performed on the charging and discharging circuit 1022 to bring it to its initial state. This avoids the first switching circuit 1021 and the charging and discharging circuit 1022 affecting the magnitude of the output first voltage signal or second voltage signal, which in turn affects subsequent counting operations.

[0079] In some embodiments, such as Figure 4 As shown, Figure 4This is a schematic diagram of the structure of a first switching circuit provided in some embodiments of this application. The first switching circuit 1021 includes a current source 201 and a first switching device 202. The first terminal of the first switching device 202 is coupled to the output terminal of the current source 201, the second terminal of the first switching device 202 is coupled to the charging and discharging circuit 1022, and the control terminal of the first switching device 202 is coupled to the output terminal of the first processing module 101.

[0080] The first switching device 202 is turned on during the low level of the first clock signal, and charges the charging and discharging circuit 1022 through the current source 201, and outputs the first voltage signal during the charging cycle; the charging and discharging circuit 1022 has completed the discharging operation according to the reset signal before the first switching device 202 receives the first clock signal.

[0081] The first clock signal actually alternates between high and low levels. During the low level period of the first clock signal, the first switching device 202 charges the charging and discharging circuit 1022 through the current source 201. That is, the first switching circuit 1021 can output a gradually increasing first voltage signal to the second processing module 103 during the low level period. During the high level period, the first switching device 202 is turned off. Since the charging and discharging circuit 1022 has already been charged during the low level period, the output of the first voltage signal can be maintained by the charging and discharging circuit 1022 during the high level period. The voltage value of the first voltage signal will not increase during the high level period.

[0082] The first switching device 202 is turned on during the low level of the second clock signal, charging the charging and discharging circuit 1022 through the current source 201, and outputting the second voltage signal during the charging cycle; wherein, before the first switching device 202 receives the second clock signal, the charging and discharging circuit 1022 has completed the discharging operation according to the reset signal.

[0083] The second clock signal actually alternates between high and low levels. During the low level period of the second clock signal, the first switching device 202 charges the charging and discharging circuit 1022 through the current source 201. That is, the first switching circuit 1021 can output a gradually increasing second voltage signal to the second processing module 103 during the low level period. During the high level period, the first switching device 202 is turned off. Since the charging and discharging circuit 1022 has already been charged during the low level period, the output of the second voltage signal can be maintained by the charging and discharging circuit 1022 during the high level period. The voltage value of the second voltage signal will not increase during the high level period.

[0084] In some embodiments, the first switching device 202 is a field-effect transistor. Specifically, the first switching device 202 is a PMOS (Positive channel Metal Oxide Semiconductor) transistor, the source of the PMOS transistor is coupled to the current source 201, the gate of the PMOS transistor is coupled to the output terminal of the first processing module 101, and the drain of the PMOS transistor is coupled to the charging and discharging circuit 1022.

[0085] In some embodiments, such as Figure 5 As shown, Figure 5 This is a schematic diagram of the structure of a charging and discharging circuit provided in some embodiments of this application. The charging and discharging circuit 1022 includes a capacitor 203 and a second switching device 204.

[0086] In this circuit, the first plate of capacitor 203 is coupled to the first switching circuit 1021, and the second plate of capacitor 203 is grounded. Capacitor 203 can be an electrolytic capacitor, a polarized capacitor, a non-polarized capacitor, or other types; no restrictions are imposed here.

[0087] The first terminal of the second switching device 204 is coupled to the first plate of the capacitor 203, the second terminal of the second switching device 204 is grounded, and the control terminal of the second switching device 204 is used to receive a reset signal. Figure 5 (Used as "RST" in Chinese).

[0088] In this circuit, the first switching circuit 1021 charges the capacitor 203 during the low level of the first clock signal and outputs a first voltage signal during the charging cycle, while the second switching device 204 is in the off state. Before the first switching circuit 1021 receives the first clock signal, the second switching device 204 is turned on according to a reset signal to complete the discharge operation of the capacitor 203.

[0089] The first clock signal actually alternates between high and low levels. During the low level period of the first clock signal, the first switching circuit 1021 charges the capacitor 203, allowing it to output a gradually increasing first voltage signal during the low level period. During the high level period, the first switching device 202 is turned off. Since the capacitor 203 has already been charged during the low level period, it can maintain the output of the first voltage signal during the high level period. The voltage value of the first voltage signal does not increase during the high level period.

[0090] The first switching circuit 1021 charges the capacitor 203 during the low level of the second clock signal and outputs a first voltage signal during the charging cycle, while the second switching device 204 is in the off state. Specifically, before the first switching circuit 1021 receives the second clock signal, the second switching device 204 is turned on according to a reset signal to complete the discharge operation of the capacitor 203.

[0091] The second clock signal actually alternates between high and low levels. During the low level period of the second clock signal, the first switching circuit 1021 charges the capacitor 203, allowing it to output a gradually increasing second voltage signal during the low level period. During the high level period, the first switching device 202 is turned off. Since the capacitor 203 has already been charged during the low level period of the second clock signal, it can maintain the output of the second voltage signal during the high level period. The voltage value of the second voltage signal does not increase during the high level period.

[0092] In some embodiments, the control terminal of the second switching device 204 serves as a reset signal input terminal for receiving a reset signal.

[0093] In some embodiments, the second switching device 204 is a field-effect transistor. Specifically, the second switching device 204 is an NMOS (N-Metal-Oxide-Semiconductor) transistor. The gate of the NMOS transistor is coupled to the reset terminal of the counter 1033, the source of the NMOS transistor is coupled to the lower plate of the capacitor 203, the drain of the NMOS transistor is coupled to the upper plate of the capacitor 203, the upper plate of the capacitor 203 is coupled to the drain of the NMOS transistor, and the lower plate of the capacitor 203 is grounded.

[0094] It is understandable that the second switching device 204, acting as a bleeder, can control the charging and discharging process of the capacitor 203.

[0095] It is understood that the first processing module 101 is used to receive the reference clock signal and the clock signal to be tested, and output the first clock signal to the charge pump 102 based on the reference clock signal and the second clock signal to the charge pump 102 based on the clock signal to be tested, so as to control the operation of the charge pump 102 based on the first clock signal and the second clock signal respectively.

[0096] In some embodiments, such as Figure 6 As shown, Figure 6 This is a schematic diagram of the structure of the first processing module provided in some embodiments of this application. The first processing module 101 includes a second switching circuit 1011 and a rising edge detection circuit 1012.

[0097] The second switching circuit 1011 is used to receive the reference clock signal and the clock signal to be tested, and to output the reference clock signal and the clock signal to be tested.

[0098] The input terminal of the rising edge detection circuit 1012 is coupled to the output terminal of the second switching circuit 1011. The rising edge detection circuit 1012 is used to receive the reference clock signal and output a first clock signal related to the rising edge of the reference clock signal. Figure 6 (represented by "CLKR_PUL" in Chinese).

[0099] The rising edge detection circuit 1012 receives the clock signal to be tested and outputs a second clock signal related to the rising edge of the clock signal to be tested. Figure 6 (represented by "CLKR_PUL" in Chinese).

[0100] In some embodiments, such as Figure 7 As shown, the second switching circuit 1011 includes a third switching device 301 and a fourth switching device 302. When the third switching device 301 is turned on and the fourth switching device 302 is turned off, a reference clock signal is provided to the rising edge detection circuit 1012. Figure 7 The clock signal to be tested is provided to the rising edge detection circuit 1012 when the fourth switching device 302 is turned on and the third switching device 301 is turned off (using "CLK_REF"). Figure 7 (In Chinese, it is represented by "CLK_IN").

[0101] For example, the input terminal of the third switching device 301 is used to receive a reference clock signal, the output terminal of the third switching device 301 is coupled to the input terminal of the rising edge detection circuit 1012, and the output terminal of the rising edge detection circuit 1012 is coupled to the control terminal of the first switching device 202 in the charge pump 102.

[0102] For example, the input terminal of the fourth switching device 302 is used to receive the clock signal to be tested, the output terminal of the fourth switching device 302 is coupled to the input terminal of the rising edge detection circuit 1012, and the output terminal of the rising edge detection circuit 1012 is coupled to the control terminal of the first switching device 202 in the charge pump 102.

[0103] When the third switching device 301 is turned on, the reference clock signal flows through the third switching device 301 and outputs the reference clock signal to the rising edge detection circuit 1012.

[0104] When the fourth switching device 302 is turned on, the clock signal to be tested flows through the fourth switching device 302 and outputs the clock signal to be tested to the rising edge detection circuit 1012.

[0105] It is understood that the third switch device 301 and the fourth switch device 302 are not turned on at the same time. That is, when acquiring the clock signal to be tested, the fourth switch device 302 is turned on and the third switch device 301 is turned off. When acquiring the reference clock signal, the third switch device 301 is turned on and the fourth switch device 302 is turned off, so as to control the charge pump 102 to work using different signals.

[0106] In some embodiments, such as Figure 8 As shown, the rising edge detection circuit 1012 includes an inverter 303, a delay unit 304, and a NAND gate 305.

[0107] The input terminal of inverter 303 is coupled to the output terminal of the second switching circuit 1011, and receives the reference clock signal and the clock signal to be tested respectively. Inverter 303 inverts the reference clock signal and outputs the seventh voltage signal. Inverter 303 inverts the clock signal to be tested and outputs the eighth voltage signal.

[0108] The input terminal of the delay unit 304 is coupled to the output terminal of the inverter 303. The delay unit 304 delays the seventh voltage signal and outputs the ninth voltage signal. The delay unit 304 delays the eighth voltage signal and outputs the tenth voltage signal.

[0109] The first input terminal of the NAND gate 305 is coupled to the output terminal of the delay unit 304, and the second input terminal of the NAND gate 305 is coupled to the output terminal of the second switching circuit 1011.

[0110] Specifically, NAND gate 305 outputs a first voltage signal based on the reference clock signal and the ninth voltage signal within a first time period, and NAND gate 305 outputs a second voltage signal based on the clock signal to be tested and the tenth voltage signal within a second time period.

[0111] Specifically, when NAND gate 305 is simultaneously at a high level of the reference clock signal and at a high level of the ninth voltage signal, it outputs a first voltage signal with a low level. When NAND gate 305 is simultaneously at a high level of the clock signal to be tested and at a high level of the tenth voltage signal, it outputs a second voltage signal with a low level.

[0112] In some embodiments, after receiving the rising edge of both the reference clock signal and the ninth voltage signal simultaneously, and when both the reference clock signal and the ninth voltage signal are at a high level, the NAND gate 305 begins to output a first voltage signal with a low level. After receiving the rising edge of both the test clock signal and the tenth voltage signal simultaneously, and when both the test clock signal and the tenth voltage signal are at a high level, the NAND gate 305 begins to output a second voltage signal with a low level. The duration of the low level of the first voltage signal is equal to the delay duration of the seventh voltage signal by the delay unit 304; the duration of the low level of the second voltage signal is equal to the delay duration of the eighth voltage signal by the delay unit 304.

[0113] In some embodiments, when detecting the reference clock signal, the reference clock signal actually alternates between high and low levels. The operating logic of the NAND gate 305 is as follows: input 0, 0, output 1; input 0, 1, output 1; input 1, 0, output 1; input 1, 1, output 0.

[0114] When the reference clock signal received by NAND gate 305 is high, if the ninth voltage signal is low, NAND gate 305 will output a high-level first voltage signal.

[0115] When the reference clock signal received by NAND gate 305 is high, if the ninth voltage signal is high, NAND gate 305 will output a low-level first voltage signal.

[0116] When the reference clock signal received by NAND gate 305 is low, if the ninth voltage signal is low, NAND gate 305 will output a high-level first voltage signal.

[0117] When the reference clock signal received by NAND gate 305 is low, if the ninth voltage signal is high, NAND gate 305 will output a high-level first voltage signal.

[0118] Therefore, after the first voltage signal is input to the charge pump 102, the control terminal of the first switching device 202 in the charge pump 102 is turned on when the first voltage signal is low, and controls the first switching circuit 1021 in the charge pump 102 to charge the capacitor 203.

[0119] The control terminal of the first switching device 202 in the charge pump 102 is cut off when the first voltage signal is high level, and the capacitor 203 is used to maintain the output of the first voltage signal.

[0120] In some embodiments, when detecting the clock signal under test, the clock signal under test actually alternates between high and low levels. The working logic of the NAND gate 305 is as follows: input 0, 0, output 1; input 0, 1, output 1; input 1, 0, output 1; input 1, 1, output 0.

[0121] When the clock signal to be tested received by NAND gate 305 is high, if the tenth voltage signal is low, NAND gate 305 will output a high-level second voltage signal.

[0122] When the clock signal to be tested received by NAND gate 305 is high, if the tenth voltage signal is high, NAND gate 305 will output a low-level second voltage signal.

[0123] When the clock signal to be tested received by NAND gate 305 is low, if the tenth voltage signal is low, NAND gate 305 will output a high-level second voltage signal.

[0124] When the clock signal to be tested received by NAND gate 305 is low, if the tenth voltage signal is high, NAND gate 305 will output a high-level second voltage signal.

[0125] Therefore, after the second voltage signal is input to the charge pump 102, the control terminal of the first switching device 202 in the charge pump 102 is turned on when the second voltage signal is low, and controls the first switching circuit 1021 in the charge pump 102 to charge the capacitor 203.

[0126] The control terminal of the first switching device 202 in the charge pump 102 is cut off when the second voltage signal is high, and the capacitor 203 is used to maintain the output of the first voltage signal.

[0127] In other embodiments, the rising edge detection circuit 1012 includes an inverter 303, a delay unit 304, and a NAND gate 305.

[0128] The input terminal of the delay unit 304 is coupled to the output terminal of the second switching circuit 1011, and receives the reference clock signal and the clock signal to be tested respectively. The delay unit 304 delays the reference clock signal and outputs the seventh voltage signal, and the delay unit 304 delays the clock signal to be tested and outputs the eighth voltage signal.

[0129] The input terminal of inverter 303 is coupled to the output terminal of delay unit 304. Inverter 303 inverts the seventh voltage signal and outputs the ninth voltage signal. Inverter 303 inverts the eighth voltage signal and outputs the tenth voltage signal.

[0130] The first input terminal of the NAND gate 305 is coupled to the output terminal of the inverter 303, and the second input terminal of the NAND gate 305 is coupled to the output terminal of the second switching circuit 1011.

[0131] In some embodiments, the first count value is inversely proportional to the reference frequency of the reference clock signal, and the second count value is inversely proportional to the frequency of the clock signal under test. Therefore, the control module 104 obtains the frequency of the clock signal under test by dividing the product of the first count value and the reference frequency of the reference clock signal by the second count value.

[0132] For example, the formula relating the first count value to the reference frequency of the reference clock signal is as follows:

[0133]

[0134] Where i represents the first count value; k is a constant determined by the current value provided by the current source 201, the capacitance value of the capacitor 203, and the pulse width of the first clock signal; f CLK_REF This indicates the reference frequency of the reference clock signal.

[0135] For example, the formula relating the second count value to the frequency of the clock signal under test is as follows:

[0136]

[0137] Where j represents the second count value; k is a constant determined by the current value provided by current source 201, the capacitance value of capacitor 203, and the pulse width of the second clock signal; f CLK_IN This indicates the frequency of the clock signal to be tested.

[0138] For example, in the first count value is The second count value is Under the premise that the frequency of the clock signal to be tested can be determined as:

[0139]

[0140] In some embodiments, the first count value is proportional to the frequency of the reference clock signal, and the second count value is proportional to the frequency of the clock signal under test. Therefore, the control module 104 obtains the frequency of the clock signal under test by dividing the product of the second count value and the reference frequency of the reference clock signal by the first count value.

[0141] For example, the formula relating the first count value to the reference frequency of the reference clock signal is as follows:

[0142] i = k × f CLK_REF

[0143] Where i represents the first count value; k is a constant determined by the current value provided by the current source 201, the capacitance value of the capacitor 203, and the pulse width of the first clock signal; f CLK_REF This indicates the frequency of the reference clock signal.

[0144] For example, the formula relating the second count value to the frequency of the clock signal under test is as follows:

[0145] j = k × f CLK_IN

[0146] Where j represents the second count value; k is a constant determined by the current value provided by current source 201, the capacitance value of capacitor 203, and the pulse width of the second clock signal; f CLK_IN This indicates the frequency of the clock signal to be tested.

[0147] For example, when the first count value is i = k × f CLK_REF The second count value is j = k × f CLK_IN Under the premise that the frequency of the clock signal to be tested can be determined as:

[0148]

[0149] In some embodiments, the control module 104 includes a processor. The processor involved in this application may be referred to as a CPU (Central Processing Unit), which may be an integrated circuit chip, or a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0150] In some embodiments, the control module 104 may also include a controller or other components, which are not limited herein.

[0151] In summary, in an application scenario, such as Figure 9 As shown, Figure 9 This is a schematic diagram of the clock frequency detection circuit provided in some embodiments of this application. The clock frequency detection circuit 10 includes a comparator 1031, an AND gate 1032, a counter 1033, a current source 201, a first switching device 202, a capacitor 203, a second switching device 204, a third switching device 301, a fourth switching device 302, an inverter 303, a delay unit 304, a NAND gate 305, and a processor 1041.

[0152] The input terminal of the third switching device 301 is used to receive a reference clock signal. Figure 9 (represented by "CLK_REF" in Chinese), the output of the third switching device 301 is coupled to the input of the inverter 303 and the second input of the NAND gate 305. The output of the inverter 303 is coupled to the input of the delay unit 304. The output of the delay unit 304 is coupled to the first input of the NAND gate 305. The output of the NAND gate 305 is coupled to the control terminal of the first switching device 202. The NAND gate 305 outputs the first clock signal ( Figure 9 (represented by "CLKR_PUL") to the control terminal of the first switching device 202.

[0153] The input terminal of the fourth switching device 302 is used to receive the clock signal to be tested. Figure 9 (represented by "CLK_IN"), the output of the fourth switching device 302 is coupled to the input of the inverter 303 and the second input of the NAND gate 305. The output of the inverter 303 is coupled to the input of the delay unit 304. The output of the delay unit 304 is coupled to the first input of the NAND gate 305. The output of the NAND gate 305 is coupled to the control terminal of the first switching device 202. The NAND gate 305 outputs the second clock signal ( Figure 9 (represented by "CLKR_PUL") to the control terminal of the first switching device 202.

[0154] The control terminal of the first switching device 202 is used to receive a first clock signal or a second clock signal. Figure 9 In this code, “CLKR_PUL” represents the signal input to the control terminal of the first switching device 202 (i.e., the first clock signal and the second clock signal). The first terminal of the first switching device 202 is coupled to the output terminal of the current source 201, and the second terminal of the first switching device 202 is coupled to the first plate of the capacitor 203. The second plate of the capacitor 203 is grounded.

[0155] The first terminal of the second switching device 204 is coupled to the first plate of the capacitor 203, the second terminal of the second switching device 204 is grounded, and the control terminal of the second switching device 204 is used to receive a reset signal. Figure 9 (Used as "RST" in Chinese).

[0156] The inverting input of comparator 1031 ( Figure 9 (Used as a "-") The coupling point between the first switching device 202 and the capacitor 203 is connected. The inverting input of the comparator 1031 receives the first voltage signal and the second voltage signal respectively. Figure 9 (represented by "VC1" in Chinese), the non-inverting input of comparator 1031 ( Figure 9 (Indicated by "+") is coupled to the reference voltage terminal and used to receive the reference voltage signal. Figure 9 (referred to as "VREF" in Chinese).

[0157] The first input terminal of AND gate 1032 is coupled to the output terminal of comparator 1031, and the output terminal of comparator 1031 outputs a third voltage signal and a fourth voltage signal. Figure 9 (Indicated by "CNT_GT"), the second input of AND gate 1032 receives the enable signal ( Figure 9 (This is indicated by "CNT_EN" in Chinese).

[0158] The enable pin of counter 1033 ( Figure 9 The output of AND gate 1032 (indicated by "EN") is used to receive the fifth and sixth voltage signals, and the pulse input of counter 1033 is used to receive the pulse signals. Figure 9 (In Chinese, "CLK" is used to indicate the clock signal of the counter.) Figure 9 (represented by "CLK_CNT" in Chinese), the reset pin of counter 1033 is used to receive the reset signal. Figure 9 (Used as "RST" in the diagram), the output of counter 1033 is coupled to processor 1041, and the output of counter 1033 outputs the first count value and the second count value. Figure 9CNT is used in Chinese.<n:0> (Illustration) and stored in processor 1041.

[0159] based on Figure 9 The clock frequency detection circuit 10 shown is... Figure 9 The timing diagram of the clock frequency detection circuit 10 shown can be found in [reference needed]. Figure 10 .

[0160] exist Figure 10 In this context, RST represents the reset signal; CLK_REF represents the reference clock signal; CLK_IN represents the clock signal to be tested; S1 represents the status signal of the third switching device 301; S2 represents the status signal of the fourth switching device 302; CLKR_PUL represents the signal input to the control terminal of the first switching device 202. Specifically, CLKR_PUL during the time period T1 to T2 is the first clock signal output within the first time length mentioned above, and CLKR_PUL during the time period T3 to T4 is the second clock signal output within the second time length mentioned above; VC1 represents the first voltage signal. The first voltage signal is VC1 during the T1-T2 time period, and the second voltage signal is VC1 during the T3-T4 time period. CNT_GT represents the third or fourth voltage signal; specifically, CNT_GT during the T1-T2 time period is the third voltage signal output within the first time period, and the fourth voltage signal during the T2-T3 time period. CNT_EN represents the enable signal; CLK_CNT represents the counter clock signal; CNT_EN represents the enable signal; CLK_CNT represents the counter clock signal. <n:0>This represents the first or second count value, specifically, the CNT within the time period T1 to T2. <n:0>The first count value within the first time period, CNT within the time interval T3 to T4. <n:0>This is the second count value within the second time period.

[0161] Right now, Figure 10 The corresponding clock frequency detection process is as follows (not shown in the figure):

[0162] Step S1: Set the initial state, make the RST signal valid, discharge the upper plate of capacitor 203, and at the same time clear the count value in counter 1033.

[0163] Step S2: The third switching device 301 is closed, and the reference clock signal CLK_REF is input to the rising edge detection circuit 1012. The rising edge detection circuit 1012 outputs a low pulse CLKR_PUL related to the rising edge of CLK_REF. The first switching device 202 of the charge pump 102 is a PMOS transistor. Therefore, during the low level of CLKR_PUL, the current source 201 in the charge pump 102 is controlled to charge the capacitor 203, and the voltage VC1 begins to rise.

[0164] Step S3: The CNT_EN signal goes high. At the same time, since the VC1 voltage is lower than the reference voltage VREF in the initial stage, the CNT_GT output by comparator 1031 is high. After ANDing with CNT_EN, it outputs a high level, enabling counter 1033. The count value increases continuously under the drive of the counter clock signal CLK_CNT.

[0165] Step S4: VC1 rises under the drive of CLKR_PUL. When the voltage exceeds the reference voltage VREF, the comparator 1031 output goes low, turning off the counter 1033 and storing the current first count value i into the processor 1041. The first count value i is proportional to the time it takes for VC1 to rise from 0 to VREF. Since the change in VC1 under each CLKR_PUL pulse is fixed, the first count value i is proportional to the reference frequency f of the reference clock signal. CLK_REF It is inversely proportional, that is, i = k * (1 / f) CLK_REF ), where k is a constant (determined by the IREF current value, C1 capacitance value, and CLKR_PUL pulse width).

[0166] Step S5: The RST signal becomes valid again, discharging the upper plate of capacitor 203 and simultaneously resetting the count value in counter 1033 to zero.

[0167] Step S6: The fourth switch 302 closes, transmitting the clock signal CLK_IN to be tested to the rising edge detection circuit 1012. Steps S2 to S4 are repeated to obtain the frequency f of the clock signal under test. CLK_IN The second count value j is inversely proportional, i.e., j = k * (1 / f) CLK_IN k is a constant (determined by the IREF current value, C1 capacitance value, and CLKR_PUL pulse width), and the second count value j is stored in processor 1041.

[0168] Step S7: Based on the results of steps S4 and S6, we can obtain i / j = f CLK_IN / f CLK_REF That is, f CLK_IN =i / j*f CLK_REF The processor 1041 can calculate the frequency of the clock signal CLK_IN to be tested based on this relationship.

[0169] See Figure 11 , Figure 11 This is a schematic diagram of the structure of a memory provided in some embodiments of this application. The memory 100 includes the clock frequency detection circuit 10 described in any of the above embodiments, which will not be repeated here.

[0170] In some embodiments, the memory 100 may be any medium capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), or an optical disc.

[0171] In one application scenario, memory 100 is a double data rate static random-access memory (DDR SRAM).

[0172] In some embodiments of this application, a clock frequency detection circuit 10 is provided in the memory 100. The clock frequency detection circuit 10 can be used to detect the clock frequency when the memory 100 is working, and a detection result with high accuracy can be obtained.

[0173] In summary, the clock frequency detection circuit 10 provided in some embodiments of this application can use the same device to detect the first clock signal and the second clock signal corresponding to the reference clock signal and the clock signal to be tested during the clock high level and low level. By using the same device for time-division detection, the first count value and the second count value can be affected in the same way when device drift or mismatch occurs. That is, the first count value and the second count value increase or decrease proportionally, but the ratio of the first count value and the second count value remains unchanged. This can avoid the influence of device drift or mismatch on the detection results, thereby improving the detection accuracy.

[0174] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A clock frequency detection circuit, characterized in that, The detection circuit includes: The first processing module is configured to receive a reference clock signal and a clock signal to be tested, and to output a first clock signal based on the reference clock signal and a second clock signal based on the clock signal to be tested. A charge pump receives a first clock signal and outputs a first voltage signal within a first time length of the first clock signal; and receives a second clock signal and outputs a second voltage signal within a second time length of the second clock signal. The second processing module receives the first voltage signal, counts based on the first voltage signal, and outputs a first count value; it also receives the second voltage signal, counts based on the second voltage signal, and outputs a second count value; wherein the first count value is related to the reference frequency of the reference clock signal. The control module receives the first count value and the second count value, and calculates the frequency of the clock signal under test based on the first count value and the second count value.

2. The detection circuit according to claim 1, characterized in that, The second processing module includes: A comparator, wherein the inverting input of the comparator is coupled to the output of the charge pump, and receives the first voltage signal and the second voltage signal respectively, and the non-inverting input of the comparator is coupled to a reference voltage; wherein the comparator outputs a third voltage signal based on the first voltage signal, and the comparator outputs a fourth voltage signal based on the second voltage signal; An AND gate, wherein the first input of the AND gate is coupled to the output of the comparator, and the second input of the AND gate receives an enable signal; wherein the AND gate outputs a fifth voltage signal during the high level of the third voltage signal and the enable signal, and outputs a sixth voltage signal during the high level of the fourth voltage signal and the enable signal; The counter, whose enable terminal is coupled to the output terminal of the AND gate, receives the fifth voltage signal and counts based on the fifth voltage signal to output the first count value; and receives the sixth voltage signal and counts based on the sixth voltage signal to output the second count value.

3. The detection circuit according to claim 2, characterized in that, After receiving the first count value, the control module sends a reset signal to the counter and the charge pump; the counter and the charge pump perform a reset operation based on the reset signal.

4. The detection circuit according to claim 2, characterized in that, The charge pump includes: A first switching circuit, wherein the control terminal of the first switching circuit is coupled to the output terminal of the first processing module; A charging and discharging circuit, wherein a first terminal of the charging and discharging circuit is coupled to the first switching circuit, a second terminal of the charging and discharging circuit is grounded, and a control terminal of the charging and discharging circuit receives a reset signal; wherein the coupling point between the charging and discharging circuit and the first switching circuit serves as the output terminal of the charge pump. The first switching circuit charges the charging and discharging circuit during the low level of the first clock signal and outputs the first voltage signal during the charging cycle. The first switching circuit charges the charging and discharging circuit during the low level of the second clock signal and outputs the second voltage signal during the charging cycle; wherein, before the first switching circuit receives the second clock signal, the charging and discharging circuit has completed the discharging operation according to the reset signal.

5. The detection circuit according to claim 4, characterized in that, The first switching circuit includes: Current source; A first switching device, wherein a first terminal of the first switching device is coupled to the output terminal of the current source, a second terminal of the first switching device is coupled to the charging and discharging circuit, and a control terminal of the first switching device is coupled to the output terminal of the first processing module. The first switching device is turned on during the low level of the first clock signal, charges the charging and discharging circuit through the current source, and outputs the first voltage signal during the charging cycle. The first switching device is turned on during the low level of the second clock signal, charging the charging and discharging circuit through the current source, and outputting the second voltage signal during the charging cycle; wherein, before the first switching device receives the second clock signal, the charging and discharging circuit has completed the discharging operation according to the reset signal.

6. The detection circuit according to claim 4, characterized in that, The charging and discharging circuit includes: A capacitor, wherein the first plate of the capacitor is coupled to the first switching circuit, and the second plate of the capacitor is grounded; The second switching device has a first terminal coupled to the first plate of the capacitor, a second terminal grounded, and a control terminal for receiving the reset signal. The first switching circuit charges the capacitor during the low level of the first clock signal and outputs the first voltage signal during the charging cycle, while the second switching device is in the off state. The first switching circuit charges the capacitor during the low level of the second clock signal and outputs the second voltage signal during the charging cycle, while the second switching device is in the off state; wherein, before the first switching circuit receives the second clock signal, the second switching device is turned on according to the reset signal to complete the discharge operation of the capacitor.

7. The detection circuit according to claim 1, characterized in that, The first processing module includes: The second switching circuit is used to receive the reference clock signal and the clock signal to be tested, and to output the reference clock signal and the clock signal to be tested. A rising edge detection circuit is coupled to the output of the second switching circuit, receives the reference clock signal, and outputs a first clock signal related to the rising edge of the reference clock signal. The rising edge detection circuit receives the clock signal to be tested and outputs a second clock signal related to the rising edge of the clock signal to be tested.

8. The detection circuit according to claim 7, characterized in that, The rising edge detection circuit includes: An inverter, the input of which is coupled to the output of the second switching circuit, receives the reference clock signal and the clock signal to be tested, respectively; the inverter inverts the reference clock signal and outputs a seventh voltage signal, and the inverter inverts the clock signal to be tested and outputs an eighth voltage signal; The delay unit has its input terminal coupled to the output terminal of the inverter. The delay unit delays the seventh voltage signal and outputs the ninth voltage signal. The delay unit delays the eighth voltage signal and outputs the tenth voltage signal. A NAND gate, wherein the first input terminal of the NAND gate is coupled to the output terminal of the delay unit, and the second input terminal of the NAND gate is coupled to the output terminal of the second switching circuit; Specifically, the NAND gate outputs the first voltage signal based on the reference clock signal and the ninth voltage signal within the first time length, and outputs the second voltage signal based on the clock signal to be tested and the tenth voltage signal within the second time length; wherein, when the NAND gate is simultaneously at a high level of the reference clock signal and at a high level of the ninth voltage signal, it outputs the first voltage signal with a low level, and when the NAND gate is simultaneously at a high level of the clock signal to be tested and at a high level of the tenth voltage signal, it outputs the second voltage signal with a low level.

9. The detection circuit according to claim 7, characterized in that, The second switching circuit includes a third switching device and a fourth switching device; When the third switching device is turned on and the fourth switching device is turned off, the reference clock signal is provided to the rising edge detection circuit; when the fourth switching device is turned on and the third switching device is turned off, the clock signal to be tested is provided to the rising edge detection circuit.

10. The detection circuit according to any one of claims 1-9, characterized in that, The control module obtains the frequency of the clock signal under test by dividing the product of the first count value and the reference frequency of the reference clock signal by the second count value; wherein, the first count value is inversely proportional to the reference frequency of the reference clock signal, and the second count value is inversely proportional to the frequency of the clock signal under test.

11. A memory, characterized in that, The memory includes the detection circuit according to any one of claims 1-10.

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