Chip package signal integrity simulation analysis method and system

Abstract

The application discloses a chip packaging signal integrity simulation analysis method and system, which is suitable for analyzing interconnection characteristics of various chip packages such as Internet of Things chips, radio frequency chips and processors, and belongs to the technical field of electromagnetic simulation of high-speed interconnection of chip packaging. The application obtains chip packaging structure parameters, constructs a partitioned three-dimensional electromagnetic simulation model, forms regional parasitic parameters and regional port responses, calculates interface continuity residuals by using geometric calibration port impedance and a common frequency grid, jointly updates frequency interpolation weights and the number of wire bonding space segments, constructs a wideband equivalent circuit model after satisfying a closed-loop termination condition, and outputs signal integrity evaluation results, so that the wideband cascade response deviation is reduced.

Description

Technical Field

[0001] This invention belongs to the field of electromagnetic simulation technology for high-speed interconnects in chip packaging, specifically relating to a method and system for simulation and analysis of signal integrity in chip packaging. Background Technology

[0002] Input and output signals from high-speed serial communication chips, RF chips, and high-speed switching chips must sequentially pass through chip pads, bonding wires, package substrate traces, bottom package pads, and external circuit board interfaces. As the rise time of high-speed signals shortens and the effective frequency range expands, the influence of bonding wire arc geometry, electromagnetic coupling between adjacent bonding wires, package substrate dielectric loss, reference plane openings, and pad transition structures on signal propagation increases. Chip package signal integrity simulation requires electromagnetic modeling of the internal structure of the chip package, extracting parasitic inductance, parasitic capacitance, distributed transmission line parameters, and port responses, and converting the regional models corresponding to different structures into broadband equivalent circuit models capable of full-link analysis.

[0003] Different structures within a chip package possess varying geometric dimensions and electromagnetic properties. Bonding wires exhibit elongated, curved structures and high-frequency coupling between adjacent bonding wires; package substrate traces have multi-layered planar structures and are affected by dielectric losses and reference plane openings; pad interfaces exhibit current diffusion, local impedance abrupt changes, and open boundaries. Using the same electromagnetic field solution method to process the complete chip package model results in a high degree of model freedom but also significant computational resource consumption. When employing a partitioned solution method, different solution regions typically have different spatial grids, frequency sampling points, port reference impedances, port reference directions, and solution accuracies.

[0004] After electromagnetic field solutions are obtained from different solution regions, a full-link model is formed by interpolating scattering parameters or cascading equivalent circuits. When frequency sampling points are inconsistent, interpolation calculations may alter amplitude and phase relationships; insufficient spatial segmentation may prevent adequate characterization of high-frequency current distributions at bond line apex, pad neck, and strongly coupled locations. Directly cascading different solution regions to form regional port responses may result in discontinuous port voltages and non-conserved port currents at the boundaries of adjacent solution regions. Local errors can also accumulate in multi-level networks, affecting insertion loss, return loss, crosstalk, and eye diagram parameters.

[0005] Existing frequency response alignment methods typically perform interpolation based solely on adjacent frequency sampling points, while spatial discretization methods usually predetermine the number of segments based on the target frequency, signal wavelength, or empirical grid size. Regional port response interpolation and spatial discretization adjustment are independent of each other and cannot be coordinated based on the same physical interface errors. Simply increasing the number of frequency sampling points cannot eliminate spatial discretization errors, nor can simply increasing the number of bond line spatial segments eliminate regional port response errors caused by frequency sampling point misalignment.

[0006] Therefore, it is necessary to address the issues of port voltage discontinuity, port current non-conservation, and broadband cascade response deviation caused by inconsistencies in frequency sampling, port reference impedance, port reference direction, and spatial discretization scale in different solution regions, and to ensure that the interpolation of regional port responses and the number of bond line spatial segments are updated in a closed loop based on the same interface continuity residual. Summary of the Invention

[0007] This invention solves the technical problems of port voltage discontinuity, port current non-conservation, and wideband cascade response deviation caused by inconsistencies in frequency sampling, port reference impedance, port reference direction, and spatial discretization scale in different solution regions.

[0008] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0009] Provides methods for simulation and analysis of signal integrity in chip packages, including:

[0010] Obtain chip packaging structure parameters, construct a partitioned three-dimensional electromagnetic simulation model including bonding line solution area, packaging substrate solution area and pad interface solution area based on the chip packaging structure parameters, and establish interface port mapping relationship between adjacent solution areas;

[0011] Electromagnetic field solutions are performed on the bonding wire solution region, the packaging substrate solution region, and the pad interface solution region respectively to obtain the region parasitic parameters and region port responses;

[0012] Based on the bonding arc height, bonding wire length, bonding wire diameter, and relative permittivity of the packaging substrate, a geometrically calibrated port impedance is formed, and the port response of the region is converted to a unified reference impedance and mapped to a common frequency grid.

[0013] Based on the interface port mapping relationship and the regional port response, the port voltage and port current of adjacent solution regions are recovered to form the interface continuity residual characterizing voltage continuity and current conservation.

[0014] When the closed-loop termination condition is not met, the frequency interpolation weight and the number of bond line spatial segments are jointly updated using the interface continuity residual. The new frequency point is determined based on the updated frequency interpolation weight, and the electromagnetic field solution of the corresponding solution region is re-executed. The electromagnetic field solution of the bond line solution region is re-executed based on the updated number of bond line spatial segments. The change in the full-link response is calculated based on the newly formed regional port response.

[0015] When the interface continuity residual and the change in the full-link response simultaneously satisfy the closed-loop termination condition, a broadband equivalent circuit model is constructed based on the regional parasitic parameters and regional port responses after the closed-loop termination. A high-speed signal excitation is injected into the broadband equivalent circuit model to obtain the signal integrity evaluation results of the high-speed interconnect of the chip package.

[0016] Furthermore, the chip packaging structure parameters include the coordinates of the starting point of the bonding wire, the coordinates of the ending point of the bonding wire, the coordinates of the arc apex of the bonding wire, the length of the bonding wire, the diameter of the bonding wire, the arc height of the bonding wire, the conductivity of the bonding wire material, the thickness of the dielectric layer of the packaging substrate, the relative permittivity of the packaging substrate, the dielectric loss tangent of the packaging substrate, the pad size, the pad spacing, the internal trace width, the internal trace spacing, and the position of the internal trace layer.

[0017] The partitioned three-dimensional electromagnetic simulation model is divided into solution regions according to structural scale, material boundaries, and port connection relationships;

[0018] The interface port mapping relationship includes the port number of adjacent solution regions, the port voltage reference polarity, the port current reference direction, the port reference impedance, the port connection coordinates, and the port cross-section normal vector.

[0019] Furthermore, the geometric calibration port impedance is formed based on the ratio of the bonding arc height to the bonding wire length, the bonding wire diameter, and the relative permittivity of the packaging substrate. The arc-shaped geometric calibration coefficient corresponding to the geometric calibration port impedance is selected from a preset set of candidate coefficients, and the selection result is the candidate coefficient that minimizes the interface continuity residual of the current iteration.

[0020] The common frequency grid is formed based on the intersection of the effective frequency ranges of each solution region and the effective spectrum of the high-speed signal excitation, and encrypted frequency points are set in the Nyquist frequency neighborhood, the encapsulated resonant frequency neighborhood, and the higher harmonic frequency neighborhood.

[0021] Furthermore, the interface continuity residual is calculated according to the following formula:

[0022] ;

[0023] in: For the first Interface continuity residuals in round iterations For iteration rounds, This refers to the port number of the interface. This represents the total number of interface port pairs between adjacent solution regions. The frequency point number in the common frequency grid. The total number of frequency points in the common frequency grid. For the first In the first iteration Frequency interpolation weights at each frequency point For the first For the first side port of the adjacent solution region in the interface port, at the... Port voltage at each frequency point For the first For the second side port of the adjacent solution region in the interface port, at the... Port voltage at each frequency point For the first In the first iteration For the interface port at the first Geometric calibration port impedance at each frequency point For the first For the first side port of the adjacent solution region in the interface port, at the... Port current at each frequency point For the first For the second side port of the adjacent solution region in the interface port, at the... Port current at each frequency point It is a squared canonical quantity of voltage.

[0024] Furthermore, the voltage continuity error and current conservation error corresponding to each frequency point in the common frequency grid are calculated respectively, and the normalized sum of the voltage continuity error and the current conservation error is used as the residual contribution of the corresponding frequency point.

[0025] The frequency interpolation weights of the corresponding frequency points are updated based on the residual contribution. New frequency points are determined based on the updated frequency interpolation weights. The new frequency points are written into the region solution task of the corresponding solution region and electromagnetic field solution is performed. Before the electromagnetic field solution of the new frequency points is completed, complex linear interpolation is performed on the complex form of the region port response.

[0026] The regional port response obtained by solving the electromagnetic field at the newly added frequency point is used to update the common frequency grid and form the full-link scattering parameter matrix for the current iteration.

[0027] Furthermore, when the closed-loop termination condition is not met, the number of bond line spatial segments is updated according to the following formula:

[0028] ;

[0029] The closed-loop termination condition is:

[0030] ;

[0031] in: For the first The number of bond line space segments in each iteration. For the first The number of bond line space segments in each iteration. For floor operations, This is the dimensionless piecewise adjustment coefficient corresponding to the interface continuity residual. This refers to the dimensionless piecewise adjustment coefficient corresponding to the change in the overall response. For the first Interface continuity residuals in round iterations For the first Round iteration and the first The change in end-to-end response between iterations. The threshold for interface continuity residuals. The threshold for end-to-end response change. For logical AND operation.

[0032] Furthermore, the bonding wire solution region is used to form a high-frequency parasitic inductance matrix, a high-frequency parasitic capacitance matrix, and a bonding wire region port response using a full-wave electromagnetic field solution algorithm;

[0033] The solution region of the packaging substrate is formed by using the quasi-static finite element method to generate distributed transmission line parameters and port responses of the packaging substrate region.

[0034] The solution region for the pad interface is formed using the boundary element method to generate the port impedance matrix and the port response of the pad interface region.

[0035] Furthermore, mutual inductance matrix sparsification and main diagonal row sum compensation are performed on the high-frequency parasitic inductance matrix, and the mutual inductance retention threshold satisfies:

[0036] ;

[0037] The sparsification of the mutual inductance matrix is ​​performed according to the following formula:

[0038] ;

[0039] The main diagonal row and compensation are performed according to the following formula:

[0040] ;

[0041] in: For the sparsified first root bond line and the first Mutual inductance between root bond lines For sparsification, the first root bond line and the first Mutual inductance between root bond lines For the first root bond line and the first Mutual inductance retention threshold between root bond lines This is the first bond line number. This is the second bonding line number. For the compensated first Root bond line self-inductance, For the first time before compensation Root bond line self-inductance.

[0042] Furthermore, the broadband equivalent circuit model includes a bonding wire segmented equivalent circuit, a package substrate distributed transmission line circuit, and a pad interface lumped parameter circuit.

[0043] The regional port response after closed-loop termination is converted into scattering parameters under a unified reference impedance and then network cascaded. Passivity checks, causality checks, and port reference consistency checks are performed on the network cascaded results. The network cascaded results that pass the checks are used for crosstalk, insertion loss, return loss, and eye diagram calculations.

[0044] Furthermore, the high-speed signal excitation is a pseudo-random binary sequence or a four-level pulse amplitude modulation sequence;

[0045] The signal integrity assessment results include differential insertion loss, differential return loss, differential-to-common-mode conversion, near-end crosstalk, far-end crosstalk, eye height, eye width, and total jitter.

[0046] Furthermore, the chip is packaged as a high-speed serial transceiver chip package with a data transmission rate of 112Gbps, and the high-speed signal excitation is a four-level pulse amplitude modulation sequence.

[0047] The common frequency grid covers the effective spectrum of the four-level pulse amplitude modulation sequence, and sets frequency interpolation weights higher than the low-frequency range in the Nyquist frequency neighborhood and the package resonant frequency neighborhood.

[0048] Furthermore, the partitioned three-dimensional electromagnetic simulation model runs on a computing node with a multi-core processor;

[0049] The domain solution task is written into the domain solution task queue according to the domain identifier and iteration round. The interface continuity residual, frequency interpolation weight and bond line spatial segment number formed in the previous iteration round are written into the domain solution task corresponding to the next iteration round.

[0050] The chip package signal integrity simulation and analysis system includes a processor, memory, data bus, region solution task queue, structural parameter acquisition module, partition model establishment module, region electromagnetic solution module, interface continuity correction module, closed-loop control module, broadband equivalent circuit construction module, and signal integrity analysis module.

[0051] The structural parameter acquisition module receives chip packaging layout data and packaging process parameters through the data bus, and outputs the chip packaging structural parameters to the partition model establishment module.

[0052] The partition model building module constructs a partition three-dimensional electromagnetic simulation model based on the chip packaging structure parameters, forming a solution region identifier, interface port mapping relationship and region solution task, and writes the region solution task into the region solution task queue;

[0053] The region electromagnetic solution module is executed by the processor using electromagnetic solution instructions stored in the memory, reads region solution tasks from the region solution task queue, forms region parasitic parameters and region port responses, writes the region parasitic parameters and the region port responses into the memory according to the solution region identifier and iteration round, and outputs the region port responses to the interface continuity correction module.

[0054] The interface continuity correction module forms a geometrically calibrated port impedance based on the bonding arc height, bonding wire length, bonding wire diameter, and relative permittivity of the packaging substrate. It converts the port response of the region to a unified reference impedance and maps it to a common frequency grid. Based on the interface port mapping relationship, it recovers the port voltage and port current of adjacent solution regions and forms the interface continuity residual.

[0055] The closed-loop control module receives the interface continuity residual, forms the full-link response change based on the full-link response of the current iteration round and the previous iteration round, and updates the frequency interpolation weight and the number of bond line spatial segments when the closed-loop termination condition is not met, forming a new region solving task and writing it into the region solving task queue. When the closed-loop termination condition is met, a closed-loop termination identifier is formed.

[0056] After receiving the closed-loop termination flag, the broadband equivalent circuit construction module reads the regional parasitic parameters and regional port responses after the closed-loop termination from the memory, forms a broadband equivalent circuit model, and outputs the broadband equivalent circuit model to the signal integrity analysis module through the data bus.

[0057] The signal integrity analysis module injects high-speed signal excitation into the broadband equivalent circuit model to form insertion loss, return loss, crosstalk, and eye diagram parameters.

[0058] Compared with the prior art, the present invention has the following beneficial effects:

[0059] This invention employs a chip package signal integrity simulation analysis method and system. It establishes solution regions for bonding wires, the package substrate, and the pad interface based on the geometric dimensions, material boundaries, and conductor connections of the chip package's internal structure. By unifying the port voltage reference polarity, port current reference direction, and port reference impedance through interface port mapping, it connects the regional port responses generated by different electromagnetic field solution methods under unified conditions. Geometric calibration of port impedance, combined with bonding arc height, bonding wire length, bonding wire diameter, and the relative permittivity of the package substrate, reduces the impact of differences in arc geometry on port reference conditions. The interface continuity residual simultaneously characterizes port voltage continuity and port current conservation, and jointly drives the update of frequency interpolation weights and the number of bonding wire spatial segments. This creates a closed loop between frequency sampling adjustment and spatial discretization adjustment around the same electromagnetic physical error, reducing error transfer caused by individually adjusting frequency sampling or increasing the number of bonding wire spatial segments. For newly added frequency points, the electromagnetic field solution is re-executed. After updating the number of bonding wire spatial segments, a new discrete model of the bonding wire solution region is established, improving the consistency between the regional port response and the full-link scattering parameter matrix. The closed-loop termination condition simultaneously constrains both the interface continuity residual and the change in the full-link response, preventing the interface continuity residual from meeting the requirements while the full-link response remains unstable. Sparsification of the mutual inductance matrix, along with main diagonal row compensation, reduces weak mutual inductance elements in the high-frequency parasitic inductance matrix while preserving the influence of these elements on local self-inductance. Based on the regional parasitic parameters and regional port responses after closed-loop termination, a broadband equivalent circuit model is constructed, providing a unified model foundation for the analysis of insertion loss, return loss, near-end crosstalk, far-end crosstalk, differential-to-common-mode conversion, eye height, eye width, and total jitter, and improving the stability and repeatability of signal integrity assessment for high-speed interconnects in chip packages. Attached Figure Description

[0060] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained from these drawings without creative effort.

[0061] Figure 1 This is a flowchart of the chip packaging signal integrity simulation analysis method of the present invention.

[0062] Figure 2 This is a flowchart illustrating the construction of a partitioned three-dimensional electromagnetic simulation model according to the present invention.

[0063] Figure 3 This is a flowchart for solving the regional electromagnetic field of this invention.

[0064] Figure 4This is a flowchart illustrating the formation of the interface continuity residual in this invention.

[0065] Figure 5 This is a flowchart of the frequency interpolation weight update of the present invention.

[0066] Figure 6 This is a flowchart illustrating the update of the number of bond line spatial segments in this invention.

[0067] Figure 7 This is a flowchart illustrating the situation where the closed-loop termination condition of this invention is not met.

[0068] Figure 8 This is a flowchart of the mutual inductance matrix sparsification process of the present invention.

[0069] Figure 9 This is a flowchart of the closed-loop termination and signal integrity assessment of the present invention. Detailed Implementation

[0070] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of the embodiments of the invention. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0071] The following is in conjunction with the appendix Figures 1-9 The embodiments of the present invention will be described in detail below.

[0072] Example 1: This example discloses a method and system for simulating and analyzing signal integrity in chip packaging.

[0073] The chip package signal integrity simulation analysis method acquires chip package layout data, bonding process parameter tables, package substrate stack-up tables, material property tables, and simulation task configurations, and extracts chip package structural parameters from the aforementioned inputs. These chip package structural parameters include bonding wire geometry parameters, package substrate stack-up parameters, pad layout parameters, internal trace topology parameters, material electromagnetic parameters, and simulation task parameters. The structural parameter acquisition module standardizes the length unit to [missing information]. Unify the frequency unit to The unit of conductivity will be standardized to Unify the impedance unit to The chip packaging structure parameters, after unit unification, coordinate unification, and material property checks, are output to the partition model creation module.

[0074] The partitioned model building module divides the partitioned 3D electromagnetic simulation model into three regions based on structural scale, material boundaries, and conductor connection relationships: the bond wire solution region, the package substrate solution region, and the pad interface solution region. The bond wire solution region includes the chip pads, the bond wire body, and the package substrate side bond pads; the package substrate solution region includes the package substrate dielectric layer, internal traces, reference plane, vias, and reference plane openings; the pad interface solution region includes the bottom pads of the package, solder balls or pins, and the external interface reference plane.

[0075] Interface ports are set at the connection sections of adjacent solution regions. Each interface port has a unique port number, port voltage reference polarity, port current reference direction, port reference impedance, port connection coordinates, and port section normal vector. Corresponding interface ports in adjacent solution regions form an interface port mapping relationship.

[0076] The region parasitic parameters and region port responses generated by the region electromagnetic solution module are not directly cascaded into networks. The interface continuity correction module transforms the region port responses to geometrically calibrated port impedances and maps the region port responses, after completing the unified reference impedance transformation, to a common frequency grid. Based on the interface port mapping relationship, the interface continuity correction module recovers the port voltages and port currents on both sides of adjacent solution regions, forming the interface continuity residual through the port voltage difference and port current sum.

[0077] The closed-loop control module increases the frequency interpolation weights corresponding to high residual frequency points based on the interface continuity residual, and updates the number of bond line spatial segments according to the interface continuity residual and the change in the overall response. The updated number of bond line spatial segments is used to regenerate the discrete model of the bond line solution region. After the region electromagnetic solution module re-executes the electromagnetic field solution for the corresponding region and regenerates the region port response, the interface continuity correction module recalculates the interface continuity residual, and the closed-loop control module recalculates the change in the overall response.

[0078] Step S1: Obtain chip package structure parameters;

[0079] The inputs to step S1 include the chip packaging layout file, bonding process parameter table, packaging substrate stack-up table, material property table, and simulation task configuration. The output of step S1 is the chip packaging structure parameters.

[0080] The geometric parameters of the bonding wire include the coordinates of the bonding wire start point, the coordinates of the bonding wire end point, the coordinates of the bonding wire apex, the bonding wire length, the bonding wire diameter, the bonding arc height, and the bonding wire material. The electrical conductivity of the bonding wire material is a material electromagnetic parameter and is obtained from the material property table. The bonding wire length is calculated based on the arc length of the three-dimensional center trajectory of the bonding wire. The bonding arc height is the vertical distance between the highest point of the bonding wire trajectory and the reference plane of the chip pad.

[0081] The stack-up parameters of the packaging substrate include the number of dielectric layers, dielectric layer thickness, relative permittivity of the packaging substrate, dielectric loss tangent of the packaging substrate, conductor layer thickness, conductor conductivity, and reference plane opening position. Pad layout parameters include chip pad size, side bonding pad size of the packaging substrate, bottom pad size of the package, pad spacing, and pad connection relationships.

[0082] Internal routing topology parameters include routing start coordinates, routing end coordinates, routing width, routing thickness, routing spacing, routing layer position, and differential pair relationship. Simulation task parameters include target frequency lower limit, target frequency upper limit, initial frequency sampling points, port reference impedance, port excitation parameters, initial frequency interpolation weight, candidate coefficient lower limit, dimensionless interval between adjacent candidate coefficients, maximum candidate coefficient index, dimensionless frequency interpolation weight update coefficient, fundamental frequency subdivision number, dimensionless frequency subdivision adjustment coefficient, dimensionless regularization coefficient, dimensionless scattering parameter regularization coefficient, maximum arc length ratio, curvature discrete threshold, dimensionless piecewise adjustment coefficient corresponding to interface continuity residual, dimensionless piecewise adjustment coefficient corresponding to end-link response change, parallelism judgment angle threshold, spacing fluctuation threshold, mutual inductance retention threshold table, mutual inductance retention threshold reduction ratio, local mesh refinement ratio reduction magnitude, interface continuity residual threshold, end-link response change threshold, passivity tolerance, and causality tolerance.

[0083] The structural parameter acquisition module converts the length parameter into a uniform value. Convert the frequency parameters to a uniform format. Convert the conductivity to a uniform value. Convert impedance to uniform form When the coordinates of the apex of the bonding line are missing, the structural parameter acquisition module reconstructs the three-dimensional center trajectory of the bonding line based on the bonding arc height, the coordinates of the starting point of the bonding line, and the coordinates of the ending point of the bonding line.

[0084] Step S2: Construct a partitioned three-dimensional electromagnetic simulation model;

[0085] Step S2 receives chip packaging structure parameters and forms a partitioned three-dimensional electromagnetic simulation model, solution area identifiers, and interface port mapping relationships.

[0086] The partition model building module divides the bonding wires and corresponding bonding pads into the bonding wire solution area, the package substrate dielectric layer, internal traces, transition holes and reference planes into the package substrate solution area, and the package bottom pads, solder balls or pins and external interface reference planes into the pad interface solution area.

[0087] When the first and second side ports on the connecting cross section of adjacent solution regions have different cross-sectional shapes, the partition model building module projects the field distributions of the first and second side ports onto the common port basis functions, respectively. The common port basis functions of the differential signal ports include differential modes and common modes. The modal amplitudes of the common port basis functions are written into the region port response.

[0088] The initial number of spatial segments for the bonding wire is determined based on the bonding wire length, the upper limit of the target frequency, the effective wavelength of the dielectric, and the curvature of the bonding wire trajectory. During this determination, the maximum arc length of a single spatial segment is limited by the effective wavelength of the dielectric corresponding to the highest effective frequency, and the curvature discretization accuracy is limited by the tangential variation between adjacent positions on the bonding wire trajectory. The smallest positive integer that simultaneously satisfies both the maximum arc length constraint and the curvature discretization constraint is taken as the initial number of spatial segments for the bonding wire. The maximum arc length ratio and the curvature discretization threshold are provided by the simulation task configuration. Forced segmentation nodes are set at the bonding wire arc apex, pad neck, and locations of abrupt changes in material properties. The initial number of spatial segments for the bonding wire is only used as the initial input for closed-loop calculations.

[0089] Step S3: Perform the regional electromagnetic field solution;

[0090] The regional electromagnetic solution module receives the partitioned three-dimensional electromagnetic simulation model and the regional solution task, and generates regional parasitic parameters and regional port responses.

[0091] The bonding wire solution region employs a full-wave electromagnetic field solution algorithm. This algorithm discretizes the bonding wire conductor surface and the pad surface, calculates the surface current density and charge distribution at the target frequency, and uses this information to generate a high-frequency parasitic inductance matrix, a high-frequency parasitic capacitance matrix, and the port response of the bonding wire region.

[0092] The quasi-static finite element method is used to solve for the electrostatic and magnetic fields in the internal trace cross-section or local three-dimensional region, forming unit-length resistance, inductance, conductance, and capacitance matrices, as well as the port responses of the package substrate region. The dimensions of the unit-length resistance matrix are... The dimensions of the inductance matrix per unit length are The dimensions of the conductivity matrix per unit length are The dimensions of a unit-length capacitance matrix are .

[0093] The solution region for the pad interface is determined using either the boundary element method or the full-wave finite element method, forming the port impedance matrix and the port response of the pad interface region. When the solution region for the pad interface has open boundaries, absorbing or radiating boundaries are set at the outer boundary of the model.

[0094] Different solution regions can use different frequency sampling points. For the bond wire solution region, denser frequency sampling points are set in the neighborhood of the bond wire resonant frequency; for the package substrate solution region, denser frequency sampling points are set in the dielectric loss variation range; and for the pad interface solution region, denser frequency sampling points are set in the port impedance abrupt change range. The region electromagnetic solution module writes the region parasitic parameters and region port responses into memory according to the solution region identifier and iteration cycle.

[0095] Step S4: Form the geometrically calibrated port impedance and common frequency grid;

[0096] The geometric calibration port impedance is formed by the base port impedance and the arc geometric calibration amount. The base port impedance is obtained by performing a quasi-static field solution on the port cross-section formed by the bond wire and the reference conductor, based on the bond wire diameter, the distance to the reference conductor, and the relative permittivity of the package substrate. The arc geometric calibration amount is formed based on the ratio of the bond arc height to the bond wire length.

[0097] For the l-th interface port, in a preferred embodiment, the geometrically calibrated port impedance is calculated according to the following formula:

[0098] ;

[0099] in: For the first In the first iteration For the interface port at the first Geometric calibration port impedance at each frequency point For the first In the first iteration For the interface port at the first The basic port impedance at each frequency point For the first The arc-shaped geometric calibration coefficients of the round iteration, For the first The bonding arc height of the bonding line corresponding to the interface port. For the first The bond wire length corresponding to the bond wire of the interface port. This refers to the port number of the interface. This refers to the frequency point number within the common frequency grid. The dimensions of both the geometric calibration port impedance and the fundamental port impedance are [dimensions missing]. The arc geometry calibration coefficient and the ratio of the bonding arc height to the bonding line length are both dimensionless quantities.

[0100] The arc geometry calibration coefficients are selected from the candidate coefficient set, and the candidate coefficient set and the arc geometry calibration coefficients are determined according to the following formula:

[0101] ;

[0102] in: For the candidate coefficient set, This is the lower limit of the candidate coefficients. The candidate coefficient index is... The dimensionless interval between adjacent candidate coefficients. For a set of integers, The largest index of the candidate coefficients, For the first The arc-shaped geometric calibration coefficients of the round iteration, Candidate coefficients are used for the k-th iteration. Interface continuity residuals formed over time The independent variable selection operation aims to minimize the interface continuity residual. After the number of bond line spatial segments changes, the candidate coefficient selection is re-executed using the updated region port response.

[0103] The lower frequency limit of the common frequency grid is no lower than the common lower limit of the effective frequency range of different solution regions, and the upper frequency limit of the common frequency grid is no higher than the common upper limit of the effective frequency range of different solution regions, and it covers the effective spectrum of high-speed signal excitation. The common frequency grid sets encrypted frequency points in the Nyquist frequency neighborhood, the encapsulated resonant frequency neighborhood, and the higher harmonic frequency neighborhood.

[0104] The regional port response is mapped to a common frequency grid using a complex linear interpolation method. During complex linear interpolation, the real and imaginary parts of each element of the regional port response matrix are linearly interpolated separately, and the complex form of the regional port response is reconstructed based on the interpolated real and imaginary parts.

[0105] Step S5: Restore port voltage and port current and calculate interface continuity residual;

[0106] The port excitation is provided by the simulation task configuration. The incident voltage wave frequency, amplitude, phase, and port mode of the externally excited port remain consistent between adjacent solution regions. Unexcited ports are terminated with the corresponding geometrically calibrated port impedance. When the region port response is a scattering parameter, the interface continuity correction module generates incident and reflected voltage waves for each pair of interface ports in adjacent solution regions based on the port excitation and scattering parameters. Then, it recovers the port voltage and port current of the first-side port in the adjacent solution region of the l-th pair of interface ports according to the following formula:

[0107] ;

[0108] The port voltage and port current of the second side port of the adjacent solution region in the l-th pair of interface ports are recovered according to the following formula:

[0109] ;

[0110] in: For the first side port of the adjacent solution region in the l-th pair of interface ports, in the l-th pair of interface ports, Port voltage at each frequency point For the first side port of the adjacent solution region in the l-th pair of interface ports, in the l-th pair of interface ports, Incident voltage wave at a frequency point For the first side port of the adjacent solution region in the l-th pair of interface ports, in the l-th pair of interface ports, Reflected voltage wave at a frequency point For the first side port of the adjacent solution region in the l-th pair of interface ports, in the l-th pair of interface ports, Port current at each frequency point For the first In the l-th round of iteration, the l-th pair of interface ports is in the th round. Geometric calibration port impedance at each frequency point For the second side port of the adjacent solution region in the l-th pair of interface ports, in the l-th pair of interface ports, Port voltage at each frequency point For the second side port of the adjacent solution region in the l-th pair of interface ports, in the l-th pair of interface ports, Incident voltage wave at a frequency point For the second side port of the adjacent solution region in the l-th pair of interface ports, in the l-th pair of interface ports, Reflected voltage wave at a frequency point For the second side port of the adjacent solution region in the l-th pair of interface ports, in the l-th pair of interface ports, Port current at each frequency point The current direction transformation coefficient is determined based on the interface port mapping relationship corresponding to the l-th pair of interface ports, and The interface port mapping relationship sets the current reference direction of the first port of each pair of interface ports to the direction of flow into the connection interface, and the original current reference direction of the second port is consistent with the direction of flow into the connection interface. When the original current reference direction at the second-side port is opposite to the direction flowing into the connection interface, The dimensions of the incident voltage wave, reflected voltage wave, and port voltage are all [missing information]. The dimensions of the port current are .

[0111] When the port reference impedances of adjacent solution regions are inconsistent, the interface continuity correction module first converts the port responses of both regions to the same geometrically calibrated port impedance. The interface port mapping relationship unifies the current reference direction of both ports to the direction flowing into the connection interface. After the reference direction is unified, the port voltages on both sides of the ideal connection interface are equal, and the sum of the currents flowing into the connection interface on both sides is 0.

[0112] Interface continuity residuals are calculated using the following formula:

[0113] ;

[0114] in: For the first Interface continuity residuals in round iterations For iteration rounds, This refers to the port number of the interface. This represents the total number of interface port pairs between adjacent solution regions. The frequency point number in the common frequency grid. The total number of frequency points in the common frequency grid. For the first In the first iteration Frequency interpolation weights at each frequency point For the first side port of the adjacent solution region in the l-th pair of interface ports, in the l-th... Port voltage at each frequency point For the second side port of the adjacent solution region in the l-th pair of interface ports, in the l-th pair of interface ports, Port voltage at each frequency point For the first In the l-th round of iteration, the l-th pair of interface ports is in the th round. Geometric calibration port impedance at each frequency point For the first side port of the adjacent solution region in the l-th pair of interface ports, in the l-th... Port current at each frequency point For the second side port of the adjacent solution region in the l-th pair of interface ports, in the l-th pair of interface ports, Port current at each frequency point It is a squared canonical quantity of voltage.

[0115] The voltage square canonical is set according to the following formula:

[0116] ;

[0117] in: It is a squared canonical quantity of voltage. These are dimensionless canonical coefficients. This is the reference voltage amplitude for high-speed signal excitation. The dimensions of the voltage square canonical quantity are... .

[0118] The numerator of the formula for calculating interface continuity residuals includes the square of the port voltage difference between each interface port pair and the square of the product of the geometrically calibrated port impedance and the port current. All calculated terms are dimensionless. The denominator of the formula for calculating the interface continuity residual includes the square of the port voltage for each interface port pair, the square of the product of the geometrically calibrated port impedance and the port current, and the voltage square canonical quantity. The dimensions of the denominator are... The interface continuity residual is a dimensionless quantity.

[0119] Step S6: Jointly update the frequency interpolation weights and the number of bond line spatial segments;

[0120] The residual contribution of the p-th frequency point in the common frequency grid is calculated according to the following formula:

[0121] ;

[0122] in: For the first In the first iteration The residual contribution at each frequency point For iteration rounds, This refers to the port number of the interface. This represents the total number of interface port pairs between adjacent solution regions. The frequency point number in the common frequency grid. The total number of frequency points in the common frequency grid. For the first side port of the adjacent solution region in the l-th pair of interface ports, in the l-th... Port voltage at each frequency point For the second side port of the adjacent solution region in the l-th pair of interface ports, in the l-th pair of interface ports, Port voltage at each frequency point For the first In the l-th round of iteration, the l-th pair of interface ports is in the th round. Geometric calibration port impedance at each frequency point For the first side port of the adjacent solution region in the l-th pair of interface ports, in the l-th... Port current at each frequency point For the second side port of the adjacent solution region in the l-th pair of interface ports, in the l-th pair of interface ports, Port current at each frequency point This is a voltage squared regularity. The residual contribution is dimensionless.

[0123] The frequency interpolation weights are updated according to the following formula:

[0124] ;

[0125] in: For the first In the first iteration Frequency interpolation weights at each frequency point For the first In the first iteration Frequency interpolation weights at each frequency point The coefficients are updated using dimensionless frequency interpolation weights. For the first In the first iteration The residual contribution at each frequency point The index of the normalized summation for the frequency interpolation weights. This represents the total number of frequency points in the common frequency grid.

[0126] The updated frequency interpolation weights sum to 1. The th in the common frequency grid The number of local frequency subdivisions corresponding to each frequency point is determined by the following formula:

[0127] ;

[0128] in: For the first In the first iteration The number of local frequency subdivisions corresponding to each frequency point in the interval. The number of subdivisions of the base frequency, This is a dimensionless frequency subdivision adjustment coefficient. The total number of frequency points in the common frequency grid. For the first In the first iteration Frequency interpolation weights at each frequency point For maximum value calculation, This is for rounding up.

[0129] The interface continuity correction module writes the new frequency points into the region solution task of the corresponding solution domain. The region electromagnetic solution module performs electromagnetic field solving at the new frequency points and updates the common frequency grid using the region port response formed by the new frequency points. Before the electromagnetic field solving of the new frequency points in the corresponding solution domain is completed, when the target frequency... Located at adjacent original frequency sampling points and In between, the area port response is subjected to complex linear interpolation according to the following formula:

[0130] ;

[0131] ;

[0132] in: For the first The dimensionless interpolation ratio corresponding to each target frequency point For the target frequency, Sampling points of adjacent original frequencies that are no higher than the target frequency. Sampling points at adjacent original frequencies that are not lower than the target frequency. For the first Target frequency in round iteration The corresponding regional port response matrix, For the first Frequency in round iteration The corresponding regional port response matrix, For the first Frequency in round iteration The corresponding regional port response matrix. The dimension of frequency is... The region port response matrices before and after interpolation have the same dimensions.

[0133] When the closed-loop termination condition is not met, the number of bond line space segments is updated according to the following formula:

[0134] ;

[0135] The closed-loop termination condition is:

[0136] ;

[0137] in: For the first The number of bond line space segments in each iteration. For the first The number of bond line space segments in each iteration. For floor operations, This is the dimensionless piecewise adjustment coefficient corresponding to the interface continuity residual. This refers to the dimensionless piecewise adjustment coefficient corresponding to the change in the overall response. For the first Interface continuity residuals in round iterations For the first Round iteration and the first The change in end-to-end response between iterations. The threshold for interface continuity residuals. The threshold for end-to-end response change. For logical AND operation.

[0138] The interface continuity residual and the change in the full-link response are both dimensionless, as are the piecewise adjustment coefficients and the spatial piecewise update factor. The number of bond line spatial segments is a positive integer. The initial frequency interpolation weights are provided and normalized by the simulation task configuration, ensuring that the sum of all initial frequency interpolation weights is 1. The lower limit of candidate coefficients, the dimensionless interval between adjacent candidate coefficients, the maximum index of candidate coefficients, the dimensionless frequency interpolation weight update coefficient, the number of basic frequency subdivisions, the dimensionless frequency subdivision adjustment coefficient, the dimensionless regularization coefficient, the dimensionless scattering parameter regularization coefficient, the maximum arc length ratio, the curvature discretization threshold, the reduction ratio of the mutual inductance retention threshold, and the reduction magnitude of the local mesh refinement ratio are all provided by the simulation task configuration. The dimensionless interval between adjacent candidate coefficients is greater than 0, the maximum index of the candidate coefficient is a positive integer, and each candidate coefficient in the candidate coefficient set ensures that the geometric calibration port impedance remains positive. The dimensionless frequency interpolation weight update coefficient is greater than 0, the number of fundamental frequency subdivisions is a positive integer, the dimensionless frequency subdivision adjustment coefficient is not less than 0, the dimensionless regularization coefficient and the dimensionless scattering parameter regularization coefficient are both greater than 0, the maximum arc length ratio and the curvature discrete threshold are both greater than 0, and the reduction ratio of mutual inductance retention threshold and the reduction ratio of local mesh refinement are both greater than 0 and less than 1. The interface continuity residual threshold is set based on the allowable normalized port voltage continuity error and the normalized port current conservation error; the full-link response change threshold is set based on the allowable relative change of the scattering parameter matrix in adjacent iterations; the segment adjustment coefficient is set based on the maximum allowable spatial segment growth ratio in a single round, the interface continuity residual threshold and the full-link response change threshold are both greater than 0, and the segment adjustment coefficient is not less than 0. When the closed-loop termination condition has been met, the bond line spatial segment number update is no longer performed.

[0139] New spatial segmentation nodes are allocated based on the curvature of the bond wire trajectory, the surface current density gradient, and the coupling strength of adjacent bond wires. The closed-loop control module generates candidate segmentation positions on the bond wire trajectory, calculates the absolute value of the bond wire trajectory curvature, the magnitude of the surface current density gradient, and the coupling strength of adjacent bond wires for each candidate segmentation position, normalizes these three indicators, sums them to form a segmentation priority, and inserts new spatial segmentation nodes in descending order of priority until the number of bond wire spatial segments reaches the updated number of bond wire spatial segments. More new spatial segmentation nodes are obtained at bond wire apex, pad neck, and positions with small distances to adjacent bond wires.

[0140] Step S7: Perform sparsification of the mutual inductance matrix and compensation of the main diagonal rows;

[0141] The high-frequency parasitic inductance matrix contains self-inductance and mutual inductance elements. The number of off-diagonal mutual inductance elements increases with the number of bond lines. The parallel coupling length is determined as follows: A nearest-point correspondence is established based on the three-dimensional center trajectories of the two bond lines. The tangential angle and center distance at corresponding positions are calculated sequentially along the three-dimensional center trajectories. A continuous arc segment is defined as the parallel coupling arc segment where the tangential angle is not greater than the parallelism judgment angle threshold, and the difference between the maximum and minimum center distances at consecutive corresponding positions is divided by the average center distance, which is not greater than the spacing fluctuation threshold. The smaller of the arc lengths of the parallel coupling arc segments corresponding to the two bond lines is taken, and the arc lengths of all parallel coupling arc segments are summed to obtain the parallel coupling length. The parallelism judgment angle threshold and spacing fluctuation threshold are provided by the simulation task configuration. The simulation task configuration includes a mutual inductance retention threshold table, indexed by the bond line spacing interval, the parallel coupling length interval, and the upper limit interval of the common frequency grid. For each bonded wire pair, the closed-loop control module determines the intervals containing the bond wire spacing, parallel coupling length, and upper limit of the common frequency grid. It then reads the corresponding mutual inductance retention threshold from the mutual inductance retention threshold table and ensures that bonded wire pairs with interchanged bond wire numbers read the same mutual inductance retention threshold. The mutual inductance retention threshold satisfies the following conditions:

[0142] ;

[0143] in: For the first root bond line and the first Mutual inductance retention threshold between root bond lines For the first root bond line and the first Mutual inductance retention threshold between root bond lines This is the first bond line number. This is the index of the second bonding line. The aforementioned symmetry ensures that the mutual inductance matrix remains symmetric after sparsification.

[0144] Sparsification of the mutual inductance matrix is ​​performed according to the following formula:

[0145] ;

[0146] in: For the sparsified first root bond line and the first Mutual inductance between root bond lines For sparsification before the first root bond line and the first Mutual inductance between root bond lines For the first root bond line and the first Mutual inductance retention threshold between root bond lines This is the first bond line number. This is the second bonding line number.

[0147] The main diagonal row and compensation are performed according to the following formula:

[0148] ;

[0149] in: For the compensated first Root bond line self-inductance, For the first time before compensation Root bond line self-inductance, For sparsification, the first root bond line and the first Mutual inductance between root bond lines For the sparsified first root bond line and the first Mutual inductance between root bond lines This is the first bond line number. This is the second bond line number. The dimensions of mutual inductance, mutual inductance retention threshold, self-inductance, main diagonal line, and compensation are all [missing information]. .

[0150] The sparsified high-frequency parasitic inductance matrix undergoes symmetry and positive definiteness checks. The symmetry check compares corresponding off-diagonal elements to see if they satisfy... Completed; the positive definiteness check is performed by calculating the minimum eigenvalue of the high-frequency parasitic inductance matrix. If the minimum eigenvalue is greater than 0, the high-frequency parasitic inductance matrix is ​​considered to have passed the positive definiteness check. If the high-frequency parasitic inductance matrix fails the positive definiteness check, the closed-loop control module reduces the mutual inductance retention threshold according to the ratio given by the simulation task configuration, recovers some mutual inductance elements, and then re-executes the main diagonal row and compensation until the high-frequency parasitic inductance matrix passes the symmetry check and the positive definiteness check.

[0151] Step S8: Calculate the end-to-end response change and construct a broadband equivalent circuit model;

[0152] After updating the frequency interpolation weights and the number of bond line spatial segments, the regional electromagnetic solution module re-executes the electromagnetic field solution for the corresponding solution region and constructs the full-link scattering parameter matrix for the current iteration based on the newly formed regional port response.

[0153] The full-link scattering parameter matrix generated in the first iteration serves as the baseline response, and the loop closure termination condition is not determined in the first iteration. From the second iteration onwards, the change in the full-link response is calculated using the following formula:

[0154] ;

[0155] in: For the first Round iteration and the first The change in end-to-end response between iterations. For the first In the first iteration The full-link scattering parameter matrix at each frequency point For the first In the first iteration The full-link scattering parameter matrix at each frequency point Let Frobenius norm be the matrix. It is a dimensionless scattering parameter canonical quantity. The frequency point number in the common frequency grid. This represents the total number of frequency points in the common frequency grid.

[0156] The scattering parameter canonical value is set according to the following formula:

[0157] ;

[0158] in: It is a dimensionless scattering parameter canonical quantity. These are the dimensionless scattering parameter canonical coefficients. The total number of frequency points in the common frequency grid. The scattering parameter matrix, matrix Frobenius norm, scattering parameter canonicality, and end-link response variation are all dimensionless quantities.

[0159] When the interface continuity residual is not greater than the interface continuity residual threshold and the total link response change is not greater than the total link response change threshold, the closed-loop control module generates a closed-loop termination flag and fixes the frequency interpolation weight, the number of bond line spatial segments, the geometric calibration port impedance, the regional parasitic parameters, and the regional port response.

[0160] The broadband equivalent circuit model includes a bond wire segmented equivalent circuit, a package substrate distributed transmission line circuit, and a pad interface lumped parameter circuit. The bond wire segmented equivalent circuit is formed based on the compensated self-inductance, retained mutual inductance, and high-frequency parasitic capacitance matrix. The package substrate distributed transmission line circuit is formed based on the unit-length resistance matrix, unit-length inductance matrix, unit-length conductance matrix, and unit-length capacitance matrix. The pad interface lumped parameter circuit is formed based on the port impedance matrix.

[0161] After the closed-loop termination, the regional port response is converted into scattering parameters under a unified reference impedance. Based on the interface port mapping relationship and the actual port connection topology, network cascading is performed through multi-port network connection elimination. Passivity check: The maximum singular value of the scattering parameter matrix of the network cascaded result is calculated at each frequency point. The pass rate is determined when the maximum singular value of the scattering parameter matrix is ​​not greater than 1 and the sum of the passivity tolerance given by the simulation task configuration. Causality check: The network cascaded result is converted into an impulse response. The pass rate is determined when the proportion of the response energy before the reference arrival time to the total response energy is not greater than the causality tolerance given by the simulation task configuration. Port reference consistency check: The port number, port voltage reference polarity, port current reference direction, port reference impedance, and port reference plane are compared item by item before and after network cascading. The pass rate is determined when all corresponding items are consistent. After the network cascaded result passes the passivity check, causality check, and port reference consistency check, the signal integrity analysis module injects a high-speed signal excitation into the broadband equivalent circuit model and calculates insertion loss, return loss, crosstalk, and eye diagram parameters.

[0162] Example 1:

[0163] This embodiment uses a ball grid array (BGA) package containing 96 bonding wires to package a high-speed serial chip. The bonding wire material is gold, and the wire diameter is [missing information]. The bond line length is distributed in to The bonding arc height is distributed in to The aforementioned parameters are derived from the chip packaging layout file and bonding process parameter table. The packaging substrate includes eight conductor layers and dielectric layers disposed between adjacent conductor layers. The number of conductor layers and dielectric layer parameters are derived from the packaging substrate stack-up table.

[0164] The target data transmission rate is The upper limit of the common frequency grid is The initial number of bond line spatial segments is 8. The bond line solution region uses the full-wave electromagnetic field solution algorithm, the package substrate solution region uses the quasi-static finite element method, and the pad interface solution region uses the boundary element method.

[0165] After the first round of regional electromagnetic field solving is completed, the interface continuity correction module maps the regional port responses of different solution regions to a common frequency grid, and recovers the port voltages and port currents of adjacent solution regions based on the geometrically calibrated port impedances. The interface continuity residual for the first round is 0.126.

[0166] The closed-loop control module improves performance based on the residual contribution at different frequency points. to The frequency interpolation weights within the range were adjusted, and the number of bond line spatial segments was increased from 8 to 10. After the second round of regional electromagnetic field solving, the interface continuity residual decreased to 0.067, and the total link response change was 0.052.

[0167] In the third round, the number of bond wire spatial segments was increased to 11, and spatial segmentation nodes were added at the bond wire arc apex and pad neck. The interface continuity residual in the third round was 0.032, and the total response change was 0.024. In the fourth round, the interface continuity residual was 0.018, and the total response change was 0.012.

[0168] The interface continuity residual threshold is 0.02, and the end-to-end response change threshold is 0.015. The fourth round simultaneously satisfies two closed-loop termination conditions, and the broadband equivalent circuit construction module constructs a broadband equivalent circuit model based on the regional parasitic parameters and regional port responses formed in the fourth round.

[0169] The signal integrity analysis module injects data transmission rate into the broadband equivalent circuit model. The pseudo-random binary sequence is used to calculate differential insertion loss, differential return loss, near-end crosstalk, far-end crosstalk, eye height, eye width, and total jitter. The frequency interpolation weight, number of bond line spatial segments, interface continuity residual, and end-link response variation are associated with and saved with the signal integrity assessment results.

[0170] Example 2:

[0171] This embodiment, based on Embodiment 1, deploys the region electromagnetic solution module on a computing node with 32 processing cores and shared memory. The region solution task queue stores region solution tasks according to the solution region identifier, iteration round, and task priority. The interface continuity residual, frequency interpolation weight, and number of bond line spatial segments formed in the previous iteration round are written into the region solution task corresponding to the next iteration round as task parameters for the region solution task.

[0172] The bonding wire solving region task, the package substrate solving region task, and the pad interface solving region task are executed in parallel. After the solving tasks for adjacent solving regions are completed, the interface continuity correction module reads the port response of the corresponding region. If any corresponding region solving task is not completed, the interface continuity residual calculation for the current iteration is not performed.

[0173] Ninety-six bond wires form a 96th-order high-frequency parasitic inductance matrix. The high-frequency parasitic inductance matrix includes... There are 2480 off-diagonal positions. Before sparsification, the aforementioned off-diagonal positions all store the mutual inductance of the corresponding bond pairs. After determining the mutual inductance retention threshold based on the bond center distance, parallel coupling length, and upper limit of the common frequency grid, 2480 non-zero mutual inductance elements are retained, and the row sum and difference corresponding to the deleted mutual inductance elements are compensated to the corresponding main diagonal elements.

[0174] The sparsified high-frequency parasitic inductance matrix undergoes symmetry and positive definiteness checks. If the minimum eigenvalue of the matrix is ​​greater than 0, the sparsified high-frequency parasitic inductance matrix is ​​used to construct a broadband equivalent circuit model. If the minimum eigenvalue of the matrix is ​​not greater than 0, the mutual inductance retention threshold is lowered, some mutual inductance elements are recovered, and the main diagonal row and compensation are re-executed.

[0175] If the regional electromagnetic field solution fails to reach the preset solution accuracy, the closed-loop control module will rewrite the corresponding regional solution task into the regional solution task queue. If the preset solution accuracy is not reached twice consecutively, the number of bond line space segments will be restored to the number of bond line space segments in the previous iteration, and the local mesh refinement ratio will be reduced according to the reduction range given by the simulation task configuration before the regional electromagnetic field solution is re-executed.

[0176] Example 3:

[0177] This embodiment uses a data transmission rate of 100%. The high-speed serial transceiver chip package uses a four-level pulse amplitude modulation sequence as the high-speed signal excitation. The four-level pulse amplitude modulation sequence includes four level states and three decision regions.

[0178] The common frequency grid covers the Nyquist frequency, the effective frequency range of higher harmonics, and the package resonant frequency range. The Nyquist frequency neighborhood and the package resonant frequency neighborhood are assigned frequency interpolation weights higher than the low-frequency range.

[0179] The signal integrity analysis module calculates the upper eye height, middle eye height, lower eye height and corresponding eye width of the four-level eye diagram, and calculates differential insertion loss, differential return loss, differential-to-common-mode conversion, near-end crosstalk and far-end crosstalk.

[0180] When the contribution of any frequency range corresponding to a decision region to the interface continuity residual increases, the closed-loop control module increases the frequency interpolation weight within the corresponding frequency range. The updated region port response is used to recalculate the full-link four-level eye diagram, and the number of bond line spatial segments is updated synchronously based on the changes in the interface continuity residual and the full-link response.

[0181] Comparative Example 1:

[0182] Comparative Example 1 uses the same chip packaging structure parameters, initial number of bond line spatial segments, regional electromagnetic field solution method, common frequency grid, high-speed signal excitation, and closed-loop termination threshold as Example 1.

[0183] Comparative Example 1 does not employ a joint closed-loop update mechanism for region port response interpolation and the number of bond line spatial segments driven by interface continuity residuals. Specifically, it does not calculate interface continuity residuals and does not utilize them to update frequency interpolation weights and the number of bond line spatial segments. The region port responses of different solution regions are directly cascaded after linear frequency interpolation, and the number of bond line spatial segments remains at 8.

[0184] The network cascading results were calculated using the port recovery method of Example 1, and the interface continuity residual was 0.094. The maximum change in the insertion loss curve of the neighborhood at adjacent frequency points is The resulting eye height is .

[0185] The interface continuity residual in Example 1 is 0.018. The maximum change in the insertion loss curve of the neighborhood at adjacent frequency points is The resulting eye height is The aforementioned calculation results show that the joint update of the region port response interpolation driven by the interface continuity residual and the number of bond line spatial segments can reduce port discontinuities across the solution region.

[0186] Comparative Example 2:

[0187] Comparative Example 2 uses the same chip packaging structure parameters, initial number of bond line spatial segments, regional electromagnetic field solution method, common frequency grid, high-speed signal excitation, and closed-loop termination threshold as Example 1.

[0188] However, in Comparative Example 2, the port response interpolation and the number of bond line spatial segments are independent. The frequency interpolation weights are updated only based on the response curvature of adjacent frequency sampling points, and the number of bond line spatial segments is updated only based on the effective wavelength corresponding to the upper limit of the target frequency. The interface continuity residual is not used as a common input to the frequency interpolation weights and the number of bond line spatial segments.

[0189] After four rounds of calculations, the number of bond line spatial segments increased to 11, the interface continuity residual was 0.061, the total link response change was 0.029, and the eye height was... The peak value of the far-end crosstalk is .

[0190] In Example 1, the interface continuity residual is 0.018, the end-to-end response change is 0.012, and the eye height is... The peak value of the far-end crosstalk is The aforementioned calculation results show that, when the number of regional port response interpolation and bond line spatial segments is operated independently, a feedback correspondence cannot be established between the location of the frequency response error and the location of the newly added spatial segments.

[0191] In practical implementation, under specific calculation conditions, the bond line length is... The bonding arc height is The basic port impedance is The arc geometry calibration factor is 0.6. The ratio of the bonding arc height to the bonding wire length is 0.2, and the square of the ratio is 0.04. The geometry calibration port impedance is obtained according to the geometry calibration port impedance calculation formula. .

[0192] Taking a pair of adjacent solution regions as an example, at a certain common frequency point, the voltage of the first port is... The voltage at the second port is The current at the first port is The current at the second port is The currents at both the first and second ports have been converted to a unified reference direction flowing into the connection interface according to the interface port mapping relationship. The port voltage continuity error is... The port current conservation error is The product of the port current conservation error and the geometrically calibrated port impedance is: .

[0193] The square of the port voltage continuity error is The square of the product of the geometric calibration port impedance and the port current conservation error is approximately The sum of the two error terms is approximately .

[0194] The square of the voltage at the first port is The product of the first-side port current and the geometrically calibrated port impedance is approximately The square of the product is approximately When the count value is much smaller than the voltage square canonical value of the aforementioned two terms, the normalized denominator is approximately The aforementioned interface port contributes approximately 0.00664 to the local residual at the corresponding frequency point, and the corresponding local normalized error square root is approximately 0.08147.

[0195] The current number of bond line spatial segments is 8, the interface continuity residual is 0.08, the total link response change is 0.03, the segment adjustment coefficient corresponding to the interface continuity residual is 1.2, and the segment adjustment coefficient corresponding to the total link response change is 0.8. The spatial segmentation update factor is... The number of bond line space segments in the next iteration is .

[0196] After re-executing the electromagnetic field solution for the bond line solution region, the interface continuity residual decreased to 0.018, and the change in the entire link response decreased to 0.012. The threshold for the interface continuity residual is 0.02, and the threshold for the change in the entire link response is 0.015. When both conditions are met simultaneously, the closed-loop control module generates a closed-loop termination indicator, and the broadband equivalent circuit construction module constructs a broadband equivalent circuit model based on the region parasitic parameters and region port responses after the closed-loop termination.

[0197] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0198] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. It should be noted that any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for simulating and analyzing signal integrity in chip packaging, characterized in that, include: Obtain chip packaging structure parameters, construct a partitioned three-dimensional electromagnetic simulation model including bonding line solution area, packaging substrate solution area and pad interface solution area based on the chip packaging structure parameters, and establish interface port mapping relationship between adjacent solution areas; Electromagnetic field solutions are performed on the bonding wire solution region, the packaging substrate solution region, and the pad interface solution region respectively to obtain the region parasitic parameters and region port responses; Based on the bonding arc height, bonding wire length, bonding wire diameter, and relative permittivity of the packaging substrate, a geometrically calibrated port impedance is formed, and the port response of the region is converted to a unified reference impedance and mapped to a common frequency grid. Based on the interface port mapping relationship and the regional port response, the port voltage and port current of adjacent solution regions are recovered to form the interface continuity residual characterizing voltage continuity and current conservation. When the closed-loop termination condition is not met, the frequency interpolation weight and the number of bond line spatial segments are jointly updated using the interface continuity residual. The new frequency point is determined based on the updated frequency interpolation weight, and the electromagnetic field solution of the corresponding solution region is re-executed. The electromagnetic field solution of the bond line solution region is re-executed based on the updated number of bond line spatial segments. The change in the whole link response is calculated based on the newly formed regional port response. When the interface continuity residual and the change in the full-link response simultaneously satisfy the closed-loop termination condition, a broadband equivalent circuit model is constructed based on the regional parasitic parameters and regional port responses after the closed-loop termination. A high-speed signal excitation is injected into the broadband equivalent circuit model to obtain the signal integrity evaluation results of the high-speed interconnect of the chip package.

2. The chip package signal integrity simulation and analysis method according to claim 1, characterized in that, The chip packaging structure parameters include the coordinates of the starting point of the bonding wire, the coordinates of the ending point of the bonding wire, the coordinates of the arc apex of the bonding wire, the length of the bonding wire, the diameter of the bonding wire, the arc height of the bonding wire, the conductivity of the bonding wire material, the thickness of the dielectric layer of the packaging substrate, the relative permittivity of the packaging substrate, the dielectric loss tangent of the packaging substrate, the pad size, the pad spacing, the internal trace width, the internal trace spacing, and the position of the internal trace layer. The partitioned three-dimensional electromagnetic simulation model is divided into solution regions according to structural scale, material boundaries, and port connection relationships; The interface port mapping relationship includes the port number of adjacent solution regions, the port voltage reference polarity, the port current reference direction, the port reference impedance, the port connection coordinates, and the port cross-section normal vector.

3. The chip package signal integrity simulation and analysis method according to claim 2, characterized in that, The geometric calibration port impedance is formed based on the ratio of the bonding arc height to the bonding wire length, the bonding wire diameter, and the relative permittivity of the packaging substrate. The arc-shaped geometric calibration coefficient corresponding to the geometric calibration port impedance is selected from a preset set of candidate coefficients. The selection result is the candidate coefficient that minimizes the interface continuity residual of the current iteration. The common frequency grid is formed based on the intersection of the effective frequency ranges of each solution region and the effective spectrum of the high-speed signal excitation, and encrypted frequency points are set in the Nyquist frequency neighborhood, the encapsulated resonant frequency neighborhood, and the higher harmonic frequency neighborhood.

4. The chip package signal integrity simulation and analysis method according to claim 3, characterized in that, The interface continuity residual is calculated according to the following formula: ； in: For the first Interface continuity residuals in round iterations For iteration rounds, This refers to the port number of the interface. This represents the total number of interface port pairs between adjacent solution regions. The frequency point number in the common frequency grid. The total number of frequency points in the common frequency grid. For the first In the first iteration Frequency interpolation weights at each frequency point For the first For the first side port of the adjacent solution region in the interface port, at the... Port voltage at each frequency point For the first For the second side port of the adjacent solution region in the interface port, at the... Port voltage at each frequency point For the first In the first iteration For the interface port at the first Geometric calibration port impedance at each frequency point For the first For the first side port of the adjacent solution region in the interface port, at the... Port current at each frequency point For the first For the second side port of the adjacent solution region in the interface port, at the... Port current at each frequency point It is a squared regularity of voltage.

5. The chip package signal integrity simulation and analysis method according to claim 4, characterized in that, Calculate the voltage continuity error and current conservation error corresponding to each frequency point in the common frequency grid, and use the normalized sum of the voltage continuity error and the current conservation error as the residual contribution of the corresponding frequency point. The frequency interpolation weights of the corresponding frequency points are updated based on the residual contribution. New frequency points are determined based on the updated frequency interpolation weights. The new frequency points are written into the region solution task of the corresponding solution region and electromagnetic field solution is performed. Before the electromagnetic field solution of the new frequency points is completed, complex linear interpolation is performed on the complex form of the region port response. The regional port response obtained by solving the electromagnetic field at the newly added frequency point is used to update the common frequency grid and form the full-link scattering parameter matrix for the current iteration.

6. The chip package signal integrity simulation and analysis method according to claim 5, characterized in that, When the closed-loop termination condition is not met, the number of bond line spatial segments is updated according to the following formula: ； The closed-loop termination condition is: ； in: For the first The number of bond line space segments in each iteration. For the first The number of bond line space segments in each iteration. For floor operations, This is the dimensionless piecewise adjustment coefficient corresponding to the interface continuity residual. This refers to the dimensionless piecewise adjustment coefficient corresponding to the change in the overall response. For the first Interface continuity residuals in round iterations For the first Round iteration and the first The change in end-to-end response between iterations. The threshold for interface continuity residuals. The threshold for end-to-end response change. For logical AND operation.

7. The chip package signal integrity simulation and analysis method according to claim 6, characterized in that, The bonding wire solution region is used to form a high-frequency parasitic inductance matrix, a high-frequency parasitic capacitance matrix, and the port response of the bonding wire region using a full-wave electromagnetic field solution algorithm. The solution region of the packaging substrate is formed by using the quasi-static finite element method to generate distributed transmission line parameters and port responses of the packaging substrate region. The solution region for the pad interface is formed using the boundary element method to generate the port impedance matrix and the port response of the pad interface region.

8. The chip package signal integrity simulation and analysis method according to claim 7, characterized in that, Perform mutual inductance matrix sparsification and main diagonal row sum compensation on the high-frequency parasitic inductance matrix, and the mutual inductance retention threshold satisfies: ； The sparsification of the mutual inductance matrix is ​​performed according to the following formula: ； The main diagonal row and compensation are performed according to the following formula: ； in: For the sparsified first root bond line and the first Mutual inductance between root bond lines For sparsification, the first root bond line and the first Mutual inductance between root bond lines For the first root bond line and the first Mutual inductance retention threshold between root bond lines This is the first bond line number. This is the second bonding line number. For the compensated first Root bond line self-inductance, For the first time before compensation Root bond line self-inductance.

9. The chip package signal integrity simulation and analysis method according to claim 8, characterized in that, The broadband equivalent circuit model includes a bond wire segmented equivalent circuit, a package substrate distributed transmission line circuit, and a pad interface lumped parameter circuit. The regional port response after closed-loop termination is converted into scattering parameters under a unified reference impedance and then network cascaded. Passivity checks, causality checks, and port reference consistency checks are performed on the network cascaded results. The network cascaded results that pass the checks are used for crosstalk, insertion loss, return loss, and eye diagram calculations.

10. A chip package signal integrity simulation and analysis system, used to execute the chip package signal integrity simulation and analysis method according to any one of claims 1-9, characterized in that, It includes a processor, memory, data bus, region solution task queue, structural parameter acquisition module, partition model establishment module, region electromagnetic solution module, interface continuity correction module, closed-loop control module, broadband equivalent circuit construction module, and signal integrity analysis module; The structural parameter acquisition module receives chip packaging layout data and packaging process parameters through the data bus, and outputs the chip packaging structural parameters to the partition model establishment module. The partition model building module constructs a partition three-dimensional electromagnetic simulation model based on the chip packaging structure parameters, forming a solution region identifier, interface port mapping relationship and region solution task, and writes the region solution task into the region solution task queue; The region electromagnetic solution module is executed by the processor, which executes the electromagnetic solution instructions stored in the memory, reads the region solution tasks in the region solution task queue, forms region parasitic parameters and region port responses, writes the region parasitic parameters and the region port responses into the memory according to the solution region identifier and iteration round, and outputs the region port responses to the interface continuity correction module. The interface continuity correction module forms a geometrically calibrated port impedance based on the bonding arc height, bonding wire length, bonding wire diameter, and relative permittivity of the packaging substrate. It converts the port response of the region to a unified reference impedance and maps it to a common frequency grid. Based on the interface port mapping relationship, it recovers the port voltage and port current of adjacent solution regions and forms the interface continuity residual. The closed-loop control module receives the interface continuity residual, forms the full-link response change based on the full-link response of the current iteration round and the previous iteration round, and updates the frequency interpolation weight and the number of bond line spatial segments when the closed-loop termination condition is not met, forming a new region solving task and writing it into the region solving task queue. When the closed-loop termination condition is met, a closed-loop termination identifier is formed. After receiving the closed-loop termination flag, the broadband equivalent circuit construction module reads the regional parasitic parameters and regional port responses after the closed-loop termination from the memory, forms a broadband equivalent circuit model, and outputs the broadband equivalent circuit model to the signal integrity analysis module through the data bus. The signal integrity analysis module injects high-speed signal excitation into the broadband equivalent circuit model to form insertion loss, return loss, crosstalk, and eye diagram parameters.

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