A method for automatically aligning integrated circuit schematic and layout device cross-views

Abstract

The application relates to the technical field of integrated circuit design automation, and discloses an integrated circuit schematic diagram and layout device cross-view automatic alignment method. The method establishes or reads a corresponding group between a schematic diagram device and a layout structure, records the corresponding relationship between a port role and a physical access area; generates an alignment target containing a port role or a topological role and a target space relationship according to an alignment request; calculates a schematic diagram anchor point according to the port role and calculates a layout anchor point according to the physical access area; generates and combines into a pair of adjustment schemes, selects a target scheme from the schemes that meet network topology, physical connectivity, design rules and consistent role relationship and executes the target scheme; submits the modification through double-view transaction coordination, and restores the two sides of the view when the verification fails. The application realizes cross-view collaborative alignment based on design intention, and ensures the consistency of electrical connection and physical implementation.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design automation technology, and in particular to a method for automatically aligning devices across views between schematic and layout views. Background Technology

[0002] In integrated circuit design, schematics describe device symbols and electrical connections, while layouts correspond to the physical implementation, including geometric structures such as diffusion regions, gates, and metal interconnects. As device sizes shrink and circuit complexity increases, a schematic device may expand into multiple effective finger cells, shared diffusion regions, and dummy cells in the layout, forming one-to-many or even many-to-many mapping relationships. Most existing alignment operations in editors are based on the geometric bounding box center or instance origin, only handling graphic arrangements within the same view, and cannot map schematic port symbols to the electrical roles of physical access areas in the layout. When designers need to maintain a symmetrical arrangement of differential pairs or a specific port order, they typically rely on manually adjusting the positions on both sides and repeatedly revising the layout against the schematic. Figure 1 Alignment checks are not only inefficient, but also prone to causing network topology disruption or design rule violations due to unilateral modifications. Some tools attempt to reconstruct alignment relationships by saving device identifiers and historical coordinates, but this object identifier-dependent association often fails after changes in device parameters, the number of finger units, or the hierarchical expansion method, making it impossible to restore the original design intent.

[0003] Therefore, there is an urgent need for an automatic alignment method that can automatically identify the port roles of cross-view devices, establish semantic anchors on both sides, and collaboratively verify electrical and geometric constraints. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of existing technologies and proposes an automatic cross-view alignment method for integrated circuit schematics and layout devices, comprising:

[0005] Establish or read the correspondence group between schematic devices and layout structure, wherein the correspondence group records the correspondence between the port role of the schematic object and the physical access area of ​​the layout object;

[0006] An alignment target is generated based on the alignment request. The alignment target includes at least two port roles or topology roles, and the target spatial relationship between the at least two port roles or topology roles.

[0007] Based on the port role, calculate the schematic anchor point from the schematic view, and based on the physical access area, calculate the layout anchor point from the layout view;

[0008] Generate schematic candidate adjustment schemes and layout candidate adjustment schemes, and combine one set of schematic candidate adjustment schemes and one set of layout candidate adjustment schemes into a pair of adjustment schemes;

[0009] Select a target pair of adjustment schemes from the pair of adjustment schemes that meet common constraints, including schematic network topology preservation, layout physical network connectivity preservation, layout design rule satisfaction, and after the pair of adjustment schemes are executed, the relationship between the at least two port roles or topology roles is consistent with the target spatial relationship;

[0010] Execute the target pairwise adjustment scheme;

[0011] When the result of the target pairwise adjustment scheme is verified, the modifications to the schematic view and the layout view are committed through dual-view transaction coordination; when the result fails verification, the schematic view and the layout view are restored to their state before the target pairwise adjustment scheme was executed.

[0012] Preferably, the process of establishing or reading the correspondence between schematic devices and layout structures includes:

[0013] The corresponding group is established based on at least one of the following information: device type, port connection network, device parameters, and hierarchical position.

[0014] The layout structure corresponding to the schematic device is marked as one of the following: effective device structure, virtual structure, shared structure, array structure, or hierarchical unfolding structure.

[0015] When multiple candidate corresponding groups exist, a matching score is calculated based on at least one of device type, port connection network, device parameters, hierarchical position and adjacency topology, and the candidate corresponding group whose matching score reaches a preset threshold is selected as the corresponding group.

[0016] More preferably, the port role in the alignment target is one of the following: input terminal, output terminal, control terminal, common terminal, gate terminal, differential positive terminal, and differential negative terminal; the topological role in the alignment target is one of the following: gate axis, source boundary, drain boundary, shared node, matching axis, and array center; the target spatial relationship is one or more of the following: direction of action, reference direction, role order, symmetry relationship, grouping relationship, coincidence relationship, collinear relationship, target distance, and allowable error.

[0017] More preferably, the step of calculating the schematic anchor point from the schematic view based on the port role includes:

[0018] Obtain the coordinates and connection network of the device symbol port corresponding to the port role, and use the port coordinates, the weighted center of multiple ports, the intersection of common connections, or a reference point determined according to a preset signal direction as the schematic anchor point; the step of calculating the layout anchor point from the layout view based on the physical access area includes:

[0019] The effective access area of ​​the layout corresponding to the physical access area is determined based on the layout connectivity, and dummy structures and auxiliary geometry that do not carry the port role are excluded. The effective access area of ​​the layout is one of the following: physical pin pattern, local metal access area in the same network as the physical pin, effective gate pattern and source-drain diffusion boundary.

[0020] The center, boundary, main axis, or weighted center of the effective access area of ​​the map is used as the map anchor point.

[0021] More preferably, the step of selecting the target pairwise adjustment scheme from the pairwise adjustment schemes that satisfy the common constraint conditions includes:

[0022] For each pair of adjustment schemes, a schematic diagram relationship signature is generated based on the adjusted schematic diagram anchor point relationship, and a layout relationship signature is generated based on the adjusted layout anchor point relationship. The relationship signature includes role order, symmetrical pairing relationship, overlapping relationship, collinear relationship, grouping relationship and allowable error status.

[0023] When the schematic relationship signature and the layout relationship signature represent the same relationship type and respectively satisfy the allowable error of the corresponding view, the paired adjustment scheme is determined as a paired adjustment scheme that satisfies the common constraint condition.

[0024] More preferably, the step of selecting the target pairwise adjustment scheme from the pairwise adjustment schemes that satisfy the common constraint conditions further includes:

[0025] Based on the evaluation function J, the pairwise adjustment schemes that satisfy the common constraints are calculated, and the scheme with the best calculation result is selected as the target pairwise adjustment scheme.

[0026] The expression for the evaluation function J is as follows: Where J represents the total cost, This represents the displacement cost of objects in the schematic diagram. This represents the cost of displacing a map object. This indicates the cost of modifying the wiring in the schematic diagram. H represents the cost of modifying the interconnection access segment in the layout, where H represents the cost of the change in relationship relative to the saved alignment target. , , , and The weights are non-negative, and at least one weight is greater than zero.

[0027] More preferably, executing the target pairwise adjustment scheme includes:

[0028] While keeping the network to which the schematic port belongs and the physical network of the layout unchanged, adjust the endpoints and inflection points of the schematic wires, as well as the interconnection access segments near the layout port in the local area affected by the mobile port.

[0029] Further preferably, the method further includes: generating a stable identifier for the corresponding group; associating and persistently saving the stable identifier, the port role, the relationship between the at least two port roles or topology roles and the alignment target; when at least one of the device parameters, the number of finger units, the parallel splitting method, the parameterized unit version, the hierarchical expansion method or the number of dummy structures changes, reconstructing the affected corresponding group according to the changed device and network, re-determining the schematic anchor point and the layout anchor point according to the saved alignment target, and regenerating, filtering and verifying the pairwise adjustment scheme.

[0030] More preferably, the method further includes: when there is no pairwise adjustment scheme that simultaneously satisfies all the common constraints, determining the objects and constraints that make the pairwise adjustment scheme infeasible;

[0031] Output the objects and constraints that make the paired adjustment schemes infeasible, and relaxation suggestions for allowable error, search range, locked state, or reserved area, sorted by the cost of constraint relaxation; do not submit any unilateral modifications to any design view before outputting the relaxation suggestions.

[0032] More preferably, the step of coordinating and committing modifications to the schematic view and the layout view through dual-view transactions, so that both the schematic view and the layout view are restored to their state before the execution of the target pairwise adjustment scheme, includes:

[0033] Establish preparation transactions in the schematic database and the layout database respectively, record snapshots of the affected objects and verify the object versions;

[0034] Once both preparation transactions have completed the verification of the execution results, the modifications to the schematic view and the layout view are committed.

[0035] If any preparation transaction, verification process, or commit process fails, the schematic view and the layout view are restored based on the snapshot, provided that the object version matches the version in the snapshot.

[0036] Technical Effects: This invention establishes a correspondence group containing the mapping between port roles and physical access areas, and generates alignment targets that characterize the spatial relationships between port roles or topology roles, enabling cross-view alignment operations to directly reflect the circuit design intent. On the schematic side, schematic anchor points are calculated based on port roles; on the layout side, layout anchor points are calculated based on valid access areas, resolving the issue of inconsistent geometric benchmarks between the two views. Utilizing a pairwise adjustment scheme and a common constraint filtering mechanism, it ensures that adjustments on both sides simultaneously satisfy consistency in network topology, physical connectivity, design rules, and role relationships. Furthermore, atomic commit or rollback of modifications is achieved through dual-view transaction coordination, thereby avoiding data inconsistencies caused by unilateral commits. Attached Figure Description

[0037] Figure 1 This is a flowchart illustrating the overall process of the cross-view collaborative automatic alignment method of the present invention.

[0038] Figure 2 This is a schematic diagram showing the corresponding group quantity relationship between the schematic components and the layout structure of this invention;

[0039] Figure 3 This is a schematic diagram illustrating the alignment of target content, request source, and recovery conditions according to the present invention.

[0040] Figure 4 This is a schematic diagram, layout structure, and anchor point diagram of a single multi-finger MOS device of the present invention;

[0041] Figure 5 This is a schematic diagram illustrating the joint selection of paired adjustment schemes for the schematic and layout of this invention;

[0042] Figure 6 This diagram illustrates the correspondence between the differential pair schematic and the cross-finger layout of the present invention, as well as a schematic diagram of the anchor points.

[0043] Figure 7 This is a schematic diagram illustrating the reconstruction of the corresponding group and restoration of the alignment target after changes in the device structure of the present invention;

[0044] Figure 8 This is a schematic diagram illustrating the dual-view transaction coordination, commit, and failure recovery of the present invention;

[0045] Figure 9 This is a schematic diagram of the module structure of the cross-view automatic alignment device of the present invention. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0047] Please see Figures 1-9The integrated circuit schematic and layout device cross-view automatic alignment method provided in this solution is applied to an electronic design automation (EDA) environment that includes a schematic editor and a layout editor. The execution entity can be a computer device running EDA software, which includes a processor and memory. The memory stores a computer program, and the processor executes the computer program to implement the various steps of the method. In the schematic view, the electrical connections and functional relationships of the circuit are described using device symbols, ports, wires, and net identifiers. In the layout view, the manufacturable geometric implementation is described using device instances, parameterized cells, physical pins, local metal access areas, effective gate patterns, source / drain diffusion boundaries, and auxiliary structures. Before describing the specific implementation method, several technical terms used in this document are explained. The set of schematic objects and layout structures representing the same circuit device or group of devices is called a corresponding group. The port roles or topological roles and their spatial relationships that need to be maintained in the two views are called alignment targets. The reference position used to calculate the device position or role relationship is called an anchor point. The layout geometric area that undertakes the electrical access of the target port is called the physical access area. Parametric cells are layout cells generated by device parameters. Valid finger cells participate in the device's electrical functions, while dummy finger cells are used for matching or process compensation. The gate terminal represents the gate of the MOS device, and the differential positive and negative terminals represent the positive and negative input terminals of the differential signal, respectively. The above terminology is used for ease of description only and does not constitute a limitation on the scope of protection.

[0048] The implementation process begins with acquiring the schematic data, layout data, and alignment requests to be processed. Schematic data can be read from the currently open project database, and layout data is loaded from the corresponding layout cell library. Alignment requests can be generated manually by the designer through a graphical interface, selecting schematic components or layout structures and specifying alignment references; automatically triggered by electronic design automation software based on the current design object status or design rule detection results; parsed from externally specified constraint files; or issued by other functional modules, such as schematic-to-layout comparison tools, based on preset events when component mismatches are detected. The alignment request carries the scope of objects requiring alignment, the desired port correspondences, and preliminary spatial constraint intentions. After acquiring the above data, the system begins establishing or reading the correspondence groups between schematic components and layout structures.

[0049] The process of establishing corresponding groups is based on matching at least one of the following: device type, port connection network, device parameters, and hierarchical position. The system can first read the output of a layout-schematic comparison tool, which typically records the mapping relationship between corresponding devices in the two views in text or database table form. If the comparison tool does not provide a complete mapping, or if the mapping is outdated due to design changes, a matching process based on device source records and parameterized cell generation records is initiated. The device source record records the origin of the schematic device in the layout, while the parameterized cell generation record records which parameter combinations generated the current layout cell. The system iterates through all schematic devices in the current design, extracting the device type string, the list of connection network names for each port, the device parameter list, and the hierarchical path for each device. Correspondingly, on the layout side, it iterates through all layout instances and parameterized cells, extracting their reference cell name, the network name corresponding to the physical pin, the parameter value, and the hierarchical expansion path. For each candidate pairing of schematic devices and layout structure, the system calculates the type matching degree, network name matching degree, parameter value deviation, and hierarchical position matching degree item by item, and obtains a matching score according to preset weights. When multiple layout structures may match the same schematic device, adjacency topology features are also included in the comparison. Adjacency topology features include the type and relative orientation of adjacent devices around the device. Matching accuracy is further improved by comparing the consistency of adjacency relationships on the schematic side and after the layout is expanded. In the presence of multiple candidate matching groups, the system selects the candidate matching group with a matching score reaching a preset threshold or the highest score from those groups that satisfy port role consistency as the final matching group. The preset threshold can be set according to the design process and device type; for example, a higher threshold is used for core transistors to ensure matching accuracy, while the threshold can be appropriately relaxed for passive devices.

[0050] Once the corresponding group is established, it internally records the correspondence between the port roles of schematic objects and the physical access areas of layout objects. Port roles are determined from input, output, control, common, gate, differential positive, and differential negative, automatically identified based on device type and port function. For example, for MOS transistors, the gate is automatically identified as the gate terminal, and the source and drain are identified as source and drain terminals based on the power and ground relationship or current direction in the network connection. For differential pairs, the two input terminals are marked as differential positive and differential negative terminals respectively by detecting the differential flag bit in the port network name or the differential pair attribute set by the designer. The determination of the physical access area is based on layout connectivity and the network to which it belongs. It traces back to the physical pin pattern or effective access structure by searching for metal patterns, contact holes, and vias at the same potential as the corresponding network. When determining the physical access area, the system marks the layout structure as one of the following: effective device structure, dummy structure, shared structure, array structure, or hierarchical unfolding structure, in order to distinguish which layout structures should participate in anchor point calculations later. Virtual structures do not carry electrical functions and will be excluded in subsequent anchor point calculations. Shared diffusion areas are shared by multiple devices; the system determines which port role a region should belong to based on the network connections to that area. When multiple parallel devices in the schematic are combined into a single parameterized unit, the system records the number of parallel devices and the network allocation information for each port in the corresponding group, ensuring that subsequent anchor point calculations can correctly handle many-to-one relationships.

[0051] After the corresponding groups are established, alignment targets are generated based on the alignment requests. Alignment targets include the objects participating in the alignment, at least two port roles or topology roles, and the target spatial relationship between the at least two port roles or topology roles. The objects participating in the alignment are schematic devices and layout structures selected from the corresponding groups that require maintaining specific spatial relationships. Designers can define the scope through interface interaction, or the software can automatically determine it based on design rules, such as automatically including all devices marked as differential pairs within the alignment scope. Port roles and topology roles are used to define the semantic objects of the alignment. Port roles directly correspond to electrical ports, while topology roles correspond to structural features in the layout geometry, such as gate axes, source boundaries, drain boundaries, shared nodes, matching axes, or array centers. Target spatial relationships include the direction of action, reference direction, role order, symmetry, grouping, overlap, collinearity, target distance, and allowable error. The direction of action indicates whether the spatial relationship is applied horizontally or vertically. The reference direction defines the baseline direction for sorting or symmetry. Role order requires several ports to be arranged in a specified order. Symmetry requires two or more groups of ports to be symmetrical about a specified axis or point. Grouping assigns ports to different constraint groups for independent processing. Coincidence requires two anchor points to coincide within a tolerance range. Collinearity requires a group of anchor points to be on the same straight line. Target distance specifies the desired distance between two anchor points, with an allowable error within the acceptable deviation range of this distance value. Alignment targets do not use absolute coordinates between the two views as a basis for correspondence. Instead, schematic coordinates are used for layout constraints within the schematic view, and layout coordinates are used for manufacturing mesh constraints within the layout view. This allows the alignment operation of the two views to be performed independently in their respective coordinate spaces, maintaining semantic consistency only at the role relationship level.

[0052] The generation of alignment targets can be completed interactively by the designer through a graphical interface. The designer selects a group of device ports and then chooses the alignment method, such as symmetry about a common axis or equidistant arrangement at a specified spacing. The system then converts the interactive operation into structured alignment target data. Alternatively, it can be automatically created by electronic design automation software based on differential pair identifiers or current mirror identifiers. For example, when two transistor gate network names are detected to end with "IN_P" and "IN_N" respectively, alignment targets symmetric about a common axis for the differential positive and differential negative terminals are automatically generated. In addition, alignment constraint scripts can be pre-written in a specified file, and the system generates alignment targets in batches after parsing the scripts.

[0053] After the alignment target is generated, the schematic anchor point is calculated from the schematic view based on the port role, and the layout anchor point is calculated from the layout view based on the physical access area. The calculation of the schematic anchor point first obtains the coordinates and connection network of the device symbol port corresponding to the target port role. When the port role corresponds to only a single symbol port, the coordinates of the pin connection point of that port are directly used as the schematic anchor point. When the same port role corresponds to multiple symbol ports, for example, when a transistor is split into multiple parallel sub-devices in the schematic and their sources need to be aligned as a whole, the coordinates of all sub-device ports participating in that port role are obtained, and the weighted center of these coordinates is calculated as the schematic anchor point. The weight can be set based on the channel width ratio of each sub-device, reflecting the contribution ratio of each sub-device to the total current, making the anchor point closer to the electrical effective center. Alternatively, the intersection of the common connections of these ports can be used as the schematic anchor point. This intersection is usually located at the convergence node of the wires connecting these ports and has a clear physical meaning. Reference points can also be determined based on preset signal flow directions. For example, for a signal path from left to right, the leftmost or rightmost port can be taken as the reference point and used as the schematic anchor point. The coordinate units of the schematic anchor point are in schematic page units and are aligned with the schematic grid.

[0054] The calculation of layout anchor points first determines candidate effective access regions based on port role correspondence and layout connectivity. Effective access regions can be one of the following: physical pin patterns, local metal access regions on the same network as physical pins, effective gate patterns, or source / drain diffusion boundaries; the specific choice depends on the type of port role. For gate roles, effective gate patterns or the metal contact region of a polysilicon gate are typically used as effective access regions. For source or drain roles, metal access regions or diffusion region boundaries on the same network as the port are used as effective access regions, excluding dummy structures and auxiliary geometries that do not support the port role. For example, dummy gates used for process matching exist in the layout. Although these dummy gates are connected to the gate metal, they do not actually participate in the channel conduction of the device and are therefore not included in the anchor point calculation for gate roles. The exclusion operation is achieved by reading the structure markers in the corresponding group. When the same port role is shared by multiple discrete physical access areas in the layout, such as the gate of a multi-finger transistor being composed of multiple finger gates connected in parallel via metal busbars, it is necessary to extract the geometric centers of these finger gates and further calculate the weighted center or the principal axis point of the overall boundary frame as the layout anchor point. When calculating the weighted center, the weights can be set according to the width and effective channel length of each finger gate to reflect the contribution of each finger unit to the overall driving capability. The layout anchor point can also be the center of the boundary frame of the entire effective access area or the principal axis point along the signal access direction. The boundary frame center is calculated by taking the circumscribed rectangle of each access area and its geometric center, while the principal axis point is the intersection of the centerlines passing through the area along the current flow direction. The coordinate dimension of the layout anchor point is in layout database units, and after calculation, it needs to be snapped onto the manufacturing grid to meet the basic requirements of the layout design rules.

[0055] After obtaining the schematic anchor points and layout anchor points, the generation and screening of candidate adjustment schemes begins. When generating schematic candidate adjustment schemes, starting from the current position of the schematic anchor point, the target positions for moving schematic device symbols are solved under the guidance of the target spatial relationships defined in the alignment target. Schematic-side adjustments must satisfy symbol locking constraints, meaning the positions of device symbols explicitly locked by the designer cannot be changed; page boundary constraints, ensuring that the moved device symbols do not exceed the effective drawing area of ​​the schematic page; wire orthogonality requirements, ensuring that the routing of port leads conforms to orthogonal routing rules to reduce visual clutter; and readability rules, such as maintaining minimum spacing between device symbols to avoid overlap. The solution process is completed using a geometric constraint solver, establishing equality or inequality constraints for each spatial relationship in the alignment target, while simultaneously adding the aforementioned boundary and locking constraints, to solve for multiple feasible schematic device position schemes. The set of port coordinates of all participating devices in each scheme constitutes a schematic candidate adjustment scheme.

[0056] The generation of layout candidate adjustment schemes also starts from the current position of the layout anchor point, solving for the movement or mirroring scheme of layout instances or parameterized cells based on the alignment target. Layout-side constraints include manufacturing mesh alignment requirements (all vertex coordinates of the moved graphics must fall on the manufacturing mesh); device orientation constraints (the orientation of device instances can only take a few discrete directions allowed by the process rules); reserved area constraints (moved devices cannot intrude into predefined reserved areas, which are typically power / ground traces, sensitive analog circuit areas, or frozen module boundaries); physical network connectivity constraints (movement cannot cause metal interconnects to break or bridge); and layout design rule constraints (the distance, enclosure relationship, width, etc., between moved graphics must meet the process design rules). Under these constraints, the constraint solver generates multiple layout candidate adjustment schemes. Each layout candidate adjustment scheme contains the target position and orientation information of all participating devices.

[0057] A schematic candidate adjustment scheme is combined with a layout candidate adjustment scheme to form a paired adjustment scheme. Since the number of candidate schemes on the schematic side and the layout side may be different, the combination can be performed by using a Cartesian product to generate all possible paired schemes, or by using heuristic rules for pruning, such as only combining schematic schemes and layout schemes with roughly similar displacement directions to reduce the computational load of subsequent screening.

[0058] For each pair of adjustment schemes, the system generates a schematic relationship signature based on the adjusted schematic anchor point relationships and a layout relationship signature based on the adjusted layout anchor point relationships. The relationship signature is a data structure that abstracts the spatial relationships between anchor points into comparable discrete characteristic values, including role order, symmetric pairing, coincidence, collinearity, grouping, and allowable error status. Role order records the arrangement order of port role anchor points in a specified reference direction, such as the arrangement order of port roles from left to right along the horizontal direction in the layout. Symmetric pairing records which anchor points have symmetric constraints and whether the offset of the symmetry axis is within the allowable error range. Coincidence indicates whether two anchor points coincide within a preset tolerance. Collinearity indicates whether a group of anchor points are located on the same straight line, and the straight-line fitting error does not exceed the allowable error. Grouping records which groups the anchor points are assigned to according to the designer's intention, and whether the relationship between anchor points within a group conforms to the group constraints. Allowable error status is a Boolean field vector, where each vector element corresponds to an allowable error check in the alignment target, recording whether the pair of schemes meets the error requirement after execution. Relationship signatures are implemented by encoding the aforementioned relationships into fixed-length strings or bitmaps, with predefined encoding rules. The paired adjustment scheme is retained only when the relationship types represented by the schematic and layout relationship signatures are completely identical, and both satisfy the allowable errors of their respective views—that is, when the role order, symmetry, etc., in the schematic relationship signature match the corresponding items in the layout relationship signature, and all bits in their respective allowable error state vectors are in the pass state. The comparison process of relationship signatures does not compare specific coordinate values, but only semantic relationships, thus avoiding the problem that direct coordinate comparison is meaningless due to different coordinate scales on both sides.

[0059] The retained paired adjustment schemes still need to undergo further screening based on common constraints. These common constraints include maintaining the schematic network topology, maintaining the physical network connectivity in the layout, satisfying layout design rules, and ensuring that the relationship between at least two port roles or topology roles after the paired adjustment scheme is executed is consistent with the target spatial relationship. Maintaining the schematic network topology is achieved by extracting the adjusted schematic netlist and performing a homogeneous comparison with the netlist before adjustment. Netlist extraction involves generating a network connection matrix by traversing all wire connection relationships, and the homogeneous comparison checks whether the port sets contained in each network are consistent. Maintaining the physical network connectivity in the layout involves extracting the adjusted physical network using a layout parasitic parameter extraction tool and checking its correspondence with the schematic netlist to ensure that each network is physically connected and has no redundant short-circuit paths. Satisfying layout design rules involves performing local rule verification on the adjusted area using an incremental design rule checking engine, checking items such as minimum spacing, minimum enclosure, and minimum width. Paired adjustment schemes that simultaneously satisfy these constraints are marked as feasible schemes.

[0060] When there are multiple feasible paired adjustment schemes, the evaluation function J is used to select the best scheme. The expression for the evaluation function J is as follows: , where J represents the overall cost, and the smaller the value, the smaller the overall change and the degree of deviation in the relationship of the scheme. This represents the displacement cost of schematic objects. It is calculated by taking the Euclidean distance before and after the anchor point movement for each of the schematic device symbols involved in the alignment, and then summing the results. The unit is the schematic page unit, typically millimeters or inches, depending on the schematic editor's internal coordinate system. This represents the displacement cost of a layout object. The calculation method is similar. For all layout instances or parameterized units involved in the alignment, the sum of the Euclidean distances before and after the layout anchor point is moved is calculated. The unit is the layout database unit, usually micrometer or nanometer. This represents the cost of modifying schematic wiring. The calculation method is as follows: for all wires whose endpoint positions have changed due to component symbol movement, after rerouting within the local area affected by the moved port, the difference between the total length of the newly added wire paths and the original path length is calculated. Only the positive increments are accumulated, and the units are the same as those on the schematic page. The local area is determined by extending a certain range outward from the moved port; only wires within this range participate in the rerouting. This represents the cost of modifying interconnect access segments in the layout. It is calculated as the total length of newly added metal paths after local modifications to interconnect access segments near ports within the layout correction window. The unit of measurement is the same as that in the layout database. The size of the layout correction window is consistent with the window for local design rule checks to ensure connectivity and compliance with design rules. H represents the cost of relationship changes relative to a saved alignment target, and is dimensionless. When a historically saved alignment target exists, the adjusted role spatial relationships of the current scheme are compared with that historical alignment target, and the deviation of each spatial relationship is calculated. For example, if the historical alignment target requires a horizontal spacing of L between two gate ports with an allowable error of e, while the actual spacing of the current scheme is d, then the spacing deviation cost is defined as... Then take Otherwise, it is zero. Other spatial relationships, such as symmetry offset and collinearity deviation, are also accumulated using a similar method for exceeding the allowable range. H is the weighted sum of the deviation costs of all relationships, and the weight coefficients are determined by the importance of each spatial relationship. When there is no saved alignment target, H is zero. Weight coefficients , , , and These are non-negative real numbers, and at least one of them must be greater than zero. Typically, a1 and a2 are set larger to encourage schemes with small movement amounts, a5 is set larger to emphasize maintaining historical alignment, and a3 and a4 reflect the cost of wiring changes; these can be appropriately increased in designs with limited wiring resources. The weighting coefficients can be adjusted by the designer through the configuration interface or adaptively set by the system based on the current design density and congestion level. After calculating the J-values ​​of all feasible pairwise adjustment schemes, the scheme with the smallest J-value is selected as the target pairwise adjustment scheme. If the designer specifies a scheme number through the interface or specifies a scheme identifier and sorting rules in a designated file, the scheme is selected first according to the specified rules, provided that common constraints are not violated.

[0061] Once the target pairwise adjustment scheme is determined, it is implemented. During execution, the schematic port's network and the physical network of the layout remain unchanged; only the local connections affected by the moved port are updated. On the schematic side, all wires whose port coordinates have changed due to device symbol movement are traversed. For each wire, its endpoint or inflection point connected to the moved port is found, and rerouting is performed within a local rectangular area containing that endpoint. During adjustment, the main body of the wire and the portion connected to other non-moved ports remain unchanged; only the coordinates of the endpoints directly connected to the moved port and the inflection point positions introduced to maintain orthogonality are modified. The size of the local area can be set to twice the movement distance plus a fixed margin. On the layout side, local corrections are performed on interconnect access segments near the port. The method for determining the affected interconnect access segments is to start from the moved layout anchor point, trace the metal pattern along the signal transmission direction, find the junction point of the metal traces in the same network as the port and connected to the external module of the device, and only regenerate the connection pattern from the moved port to the junction point. The generation of the connection pattern satisfies process rules, including metal width, spacing, contact hole size, and enclosure distance. The diagram generation is accomplished using a predefined port header template or a local routing engine. After the local connectivity update is completed, the overall physical network structure on the layout side remains unchanged; only the port header segments are partially reconstructed.

[0062] After executing the paired adjustment scheme and completing the local connectivity update, the verification phase begins. Verification includes schematic network topology, physical network connectivity, layout design rules, and role relationships. Schematic network topology verification is performed by comparing the exported netlist files or internal netlist data structures before and after execution, checking that the node member lists of each network are completely consistent and ensuring no network splits or accidental merging occur. Layout physical network connectivity verification uses a layout-schematic comparison tool to check the correspondence between the adjusted devices and their ports, confirming that each layout physical port is connected to the correct schematic network and that there are no additional parasitic connectivity paths. Layout design rule verification runs incrementally, performing design rule checks only on layout areas affected by the local connectivity update. Checks include metal spacing, via enclosures, and active area boundaries, ensuring that local modifications do not introduce new violations. Role relationship verification recalculates the adjusted schematic anchor relationships and layout anchor relationships, generates new relationship signatures, and compares them with the target space relationships in the alignment target to confirm consistency.

[0063] When all the above verification items pass, the dual-view transaction coordination process is initiated, and the modifications to both views are committed atomically. The specific implementation of dual-view transaction coordination is as follows: A preparation transaction is established in the schematic database, and a preparation transaction is also established in the layout database. In each preparation transaction, a snapshot of all affected objects is recorded. Affected objects include device symbols or instances participating in alignment, adjusted wire endpoints and inflection points, modified layout interconnect access segment graphics, and version metadata. The snapshot content includes the object's position coordinates, connection relationships, graphic boundary data, and the current database version number. When verifying the object version, it is checked whether the version number of these objects in the current database is consistent with the version number recorded when the corresponding group was established. If they are inconsistent, it indicates that other designers or processes have modified the same object during the adjustment process, and the transaction may fail. After both preparation transactions have completed verification, the modifications to the schematic view and the layout view are committed respectively. If, in any step, the preparation transaction of the schematic database fails, or the preparation transaction of the layout database fails, or a conflict error is returned during the commit process, then if the object version is consistent with the version in the snapshot, the corresponding database is restored to the state before the transaction started using the snapshot data. Recovery operations are achieved by writing back the position and connection information recorded in the snapshot. For lightweight databases or file storage systems that do not support native distributed transactions, each operation and its reverse compensation operation are recorded in a write-ahead log. For example, before moving a schematic component, its original position is written to the write-ahead log. If a rollback is needed later, the component is moved back to its original position according to the reverse operation in the write-ahead log. The compensation operation ensures that, from the user's observable state, the modifications to the two views are either fully visible or completely invisible, avoiding an intermediate state where one side is updated while the other is not.

[0064] In engineering practice, device parameters or layout structures frequently undergo design changes. For example, transistor size adjustments may lead to changes in the number of finger cells, parallel splitting methods may change from single-finger to multi-finger, parameterized cell version upgrades may cause changes in the internal hierarchy, or the number of dummy cells may be added or removed to improve matching. To automatically restore the previously set alignment target after these changes, this solution generates a stable identifier for each corresponding group when it is first established. The stable identifier is generated based on a combination of the device's logical design identifier, the topological characteristics of the port connection network, and key attributes of the device parameters. A hash algorithm is used to map this information into a fixed-length string. The stable identifier does not depend on the object's memory address or instance number in the database. Therefore, after the device is regenerated, as long as the logical attributes and network topology have not fundamentally changed, the corresponding historical corresponding group can be re-matched through the stable identifier. The system serializes and persistently saves the stable identifier, port roles, the relationships between port roles or topology roles, and alignment targets to the design database, which can be stored as additional attributes or independent constraint entries. When a design change event is detected, such as parameterized cell regeneration or netlist update, the recovery process is triggered. The system reconstructs the affected corresponding groups based on the changed devices and networks. It searches for matching alignment targets in the saved data using stability identifiers, then re-identifies valid access areas and calculates layout anchor points on the newly generated layout structure. Simultaneously, it re-reads the port coordinates of the corresponding devices from the schematic side and calculates schematic anchor points. Based on the newly calculated anchor points and the read alignment targets, it regenerates schematic and layout candidate adjustment schemes, re-performs relation signature filtering and common constraint filtering, and uses the evaluation function J to select the optimal scheme. Finally, it submits the update through dual-view transaction coordination. If no feasible scheme is found during the regeneration process due to added layout constraints, the system maintains the current state of both views and outputs failure details caused by insufficient space, reserved area conflicts, locked object limitations, or excessively small allowable error settings.

[0065] Under stringent design constraints, no pairwise adjustment schemes may simultaneously satisfy all common constraints. In this case, the system iterates through all rejected schemes, analyzes the specific constraints each scheme fails to meet, and identifies which objects frequently appear on paths where constraints are not met, thus pinpointing the objects and constraints causing infeasibility. For example, a layout device's gate access line might be marked as locked by the designer. Alignment requirements necessitate moving the device to the left to maintain symmetry, but this movement would stretch or break the locked access line. Therefore, all layout schemes involving moving the device to the left are rejected due to the locked constraint. The system identifies this conflict between the locked object and the symmetry constraint as the root cause of infeasibility. After identifying the infeasible objects and constraints, the system outputs a constraint conflict report to the designer, listing the object identifier causing the failure, the type of constraint involved, and suggested relaxation directions. Relaxation recommendations are ranked according to the cost of constraint relaxation, with cost assessment comprehensively considering the additional design rule violation risks, increased routing congestion, and deviation from design intent that may be introduced after relaxation. For example, relaxing symmetry tolerances is less costly because it only results in slight asymmetry that does not affect electrical performance; while relaxing reserved area restrictions is more costly and may intrude into power ground networks or analog circuits, causing serious interference. Designers can choose to relax certain constraints based on recommendations. Upon receiving a relaxation instruction, the system adjusts the tolerances or locking status in the alignment target and restarts the scheme generation and screening process. Before obtaining designer confirmation, the system does not submit any unilateral modifications to any design view, nor does it retain intermediate adjustment results calculated separately on the schematic side, ensuring that the consistency between the two views in the data warehouse is not disrupted by unilateral modifications.

[0066] In the specific embodiments described above, the constraint solver used can be implemented based on linear programming or integer linear programming, or a rule-based iterative search algorithm can be employed. Relationship signature encoding can use a bitmap approach: a fixed bit width is assigned to each relation type; for example, sequential relations are represented by the number of devices multiplied by the index bit width, and symmetric relations are represented by the number of pairs and the symmetry axis offset quantization bits. Cost calculations for each item in the evaluation function J can be obtained in real-time based on the geometric calculation interface. Write-ahead logging of dual-view transactions can be implemented using operating system file locks or database row-level locks. The size of the rectangular region for local connection updates and the layout correction window size can be preset in a configuration file or automatically calculated according to process rules at program startup. When the electronic design automation environment supports script extensions, the above methods can be implemented entirely or partially in a script manner, calling the functions of each engine through interfaces without modifying the core code of the editor itself.

[0067] This solution establishes corresponding groups for the port roles and physical access areas of cross-view devices, giving the alignment operation an electrical semantic foundation. By introducing alignment targets based on role spatial relationships, alignment is transformed into a constrained geometric problem. Independent calculation of schematic and layout anchor points avoids the drawbacks of direct coordinate copying across views. The generation of paired adjustment schemes and relation signature filtering ensures the unified satisfaction of design intent on both sides. The evaluation function J provides quantitative scheme selection criteria, enabling automatic selection of the adjustment scheme with the lowest comprehensive cost among multiple feasible schemes. The dual-view transaction coordination mechanism ensures the atomicity of modifications, avoiding data inconsistencies. The combination of stable identifiers and persistent alignment targets allows for automatic restoration of alignment relationships after design changes. When no solution is found, constraint conflicts and suggestions are output to assist designers in adjusting constraints to obtain feasible solutions. The overall combination of these techniques elevates the alignment between schematic and layout from a single-view geometric arrangement to a cross-view, semantically constrained, verifiable, and recoverable collaborative automatic alignment, thereby establishing a stable and traceable intent maintenance channel between schematic and layout design.

[0068] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments that can be applied to other fields. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A method for automatic cross-view alignment of integrated circuit schematics and layout devices, characterized in that, include: Establish or read the correspondence group between schematic devices and layout structure, wherein the correspondence group records the correspondence between the port role of the schematic object and the physical access area of ​​the layout object; An alignment target is generated based on the alignment request. The alignment target includes at least two port roles or topology roles, and the target spatial relationship between the at least two port roles or topology roles. Based on the port role, calculate the schematic anchor point from the schematic view, and based on the physical access area, calculate the layout anchor point from the layout view; Generate schematic candidate adjustment schemes and layout candidate adjustment schemes, and combine one set of schematic candidate adjustment schemes and one set of layout candidate adjustment schemes into a pair of adjustment schemes; Select a target pair of adjustment schemes from the pair of adjustment schemes that meet common constraints, including schematic network topology preservation, layout physical network connectivity preservation, layout design rule satisfaction, and after the pair of adjustment schemes are executed, the relationship between the at least two port roles or topology roles is consistent with the target spatial relationship; Execute the target pairwise adjustment scheme; When the results of the target pair adjustment scheme are verified, the modifications to the schematic view and layout view are submitted through dual-view transaction coordination. If the result fails verification, both the schematic view and the layout view are restored to their state before the target pairwise adjustment scheme was executed.

2. The method for automatic cross-view alignment of integrated circuit schematics and layout devices according to claim 1, characterized in that, The process of establishing or reading the correspondence between schematic devices and layout structures includes: The corresponding group is established based on at least one of the following information: device type, port connection network, device parameters, and hierarchical position. The layout structure corresponding to the schematic device is marked as one of the following: effective device structure, virtual structure, shared structure, array structure, or hierarchical unfolding structure. When multiple candidate corresponding groups exist, a matching score is calculated based on at least one of device type, port connection network, device parameters, hierarchical position and adjacency topology, and the candidate corresponding group whose matching score reaches a preset threshold is selected as the corresponding group.

3. The method for automatic cross-view alignment of integrated circuit schematics and layout devices according to claim 1, characterized in that, The port role in the alignment target is one of the following: input terminal, output terminal, control terminal, common terminal, gate terminal, differential positive terminal, and differential negative terminal; the topological role in the alignment target is one of the following: gate axis, source boundary, drain boundary, shared node, matching axis, and array center; the target spatial relationship is one or more of the following: direction of action, reference direction, role order, symmetry relationship, grouping relationship, coincidence relationship, collinear relationship, target distance, and allowable error.

4. The method for automatic cross-view alignment of integrated circuit schematics and layout devices according to claim 1, characterized in that, The step of calculating schematic anchor points from the schematic view based on the port role includes: Obtain the coordinates and connection network of the device symbol port corresponding to the port role, and use the port coordinates, the weighted center of multiple ports, the intersection of common connections, or a reference point determined according to a preset signal direction as the schematic anchor point; the step of calculating the layout anchor point from the layout view based on the physical access area includes: The effective access area of ​​the layout corresponding to the physical access area is determined based on the layout connectivity, and dummy structures and auxiliary geometry that do not carry the port role are excluded. The effective access area of ​​the layout is one of the following: physical pin pattern, local metal access area in the same network as the physical pin, effective gate pattern and source-drain diffusion boundary. The center, boundary, main axis, or weighted center of the effective access area of ​​the map is used as the map anchor point.

5. The method for automatic cross-view alignment of integrated circuit schematics and layout devices according to claim 1, characterized in that, The selection of the target pairwise adjustment scheme from the pairwise adjustment schemes that satisfy common constraints includes: For each pair of adjustment schemes, a schematic diagram relationship signature is generated based on the adjusted schematic diagram anchor point relationship, and a layout relationship signature is generated based on the adjusted layout anchor point relationship. The relationship signature includes role order, symmetrical pairing relationship, overlapping relationship, collinear relationship, grouping relationship and allowable error status. When the schematic relationship signature and the layout relationship signature represent the same relationship type and respectively satisfy the allowable error of the corresponding view, the paired adjustment scheme is determined as a paired adjustment scheme that satisfies the common constraint condition.

6. The method for automatic cross-view alignment of integrated circuit schematics and layout devices according to claim 5, characterized in that, The step of selecting the target pairwise adjustment scheme from the pairwise adjustment schemes that satisfy the common constraints further includes: Based on the evaluation function J, the pairwise adjustment schemes that satisfy the common constraints are calculated, and the scheme with the best calculation result is selected as the target pairwise adjustment scheme. The expression for the evaluation function J is as follows: Where J represents the total cost, This represents the displacement cost of objects in the schematic diagram. This represents the cost of displacing a map object. This indicates the cost of modifying the wiring in the schematic diagram. H represents the cost of modifying the interconnection access segment in the layout, where H represents the cost of the change in relationship relative to the saved alignment target. , , , and The weights are non-negative, and at least one weight is greater than zero.

7. The method for automatic cross-view alignment of integrated circuit schematics and layout devices according to claim 1, characterized in that, The execution of the target pairwise adjustment scheme includes: While keeping the network to which the schematic port belongs and the physical network of the layout unchanged, adjust the endpoints and inflection points of the schematic wires, as well as the interconnection access segments near the layout port in the local area affected by the mobile port.

8. The method for automatic cross-view alignment of integrated circuit schematics and layout devices according to claim 1, characterized in that, The method further includes: generating a stable identifier for the corresponding group; associating and persistently saving the stable identifier, the port role, the relationship between the at least two port roles or topology roles and the alignment target; when at least one of the device parameters, number of finger units, parallel splitting method, parameterized unit version, hierarchical expansion method or number of dummy structures changes, reconstructing the affected corresponding group according to the changed device and network, re-determining the schematic anchor point and the layout anchor point according to the saved alignment target, and regenerating, filtering and verifying the pair adjustment scheme.

9. The method for automatic cross-view alignment of integrated circuit schematics and layout devices according to claim 1, characterized in that, The method further includes: when there is no pairwise adjustment scheme that simultaneously satisfies all the common constraints, determining the objects and constraints that make the pairwise adjustment scheme infeasible; Output the objects and constraints that make the paired adjustment schemes infeasible, and relaxation suggestions for allowable error, search range, locked state, or reserved area, sorted by the cost of constraint relaxation; do not submit any unilateral modifications to any design view before outputting the relaxation suggestions.

10. The method for automatic cross-view alignment of integrated circuit schematics and layout devices according to claim 1, characterized in that, The step of coordinating and committing modifications to the schematic view and the layout view through dual-view transactions, restoring both the schematic view and the layout view to their state before executing the target pairwise adjustment scheme, includes: Establish preparation transactions in the schematic database and the layout database respectively, record snapshots of the affected objects and verify the object versions; Once both preparation transactions have completed the verification of the execution results, the modifications to the schematic view and the layout view are committed. If any preparation transaction, verification process, or commit process fails, the schematic view and the layout view are restored based on the snapshot, provided that the object version matches the version in the snapshot.

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