Capacitive digital-to-analog converter array layout automatic routing method and system

Abstract

The application discloses a capacitor digital-to-analog converter array layout automatic layout and wiring method and system, and belongs to the technical field of integrated circuit electronic design automation and analog integrated circuit layout design. The method splits binary weight capacitors into equivalent working unit capacitors, determines an internal layout matrix with an even number of columns, arranges working unit capacitors of continuous low weight bits in the middle two adjacent columns of the matrix, and sets a central virtual capacitor at a position corresponding to the lowest weight bit; arranges high weight bit groups on the outer sides of the two columns, and arranges the highest weight bit capacitor column and the non-highest weight bit capacitor column in an interleaved manner; generates vertical bottom plate lines and horizontal bottom plate lines connected through through holes in different metal layers below the unit capacitors, and generates a top plate interconnection electrically isolated from the bottom plate wiring line, and outputs layout data according to process design rules. The application can reduce the influence of array adjacent parasitics and interconnection parasitics on weight matching, and realizes automatic design of a CDAC array layout.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit electronic design automation and analog integrated circuit layout design technology, specifically relating to an automatic placement and routing method and system for capacitive digital-to-analog converter arrays. Background Technology

[0002] Successive approximation analog-to-digital converters typically employ binary weighted digital-to-analog converter (CDAC) arrays to sample and quantize the input signal. As conversion accuracy increases, the number of capacitors per unit area, array area, and interconnect size also increase. The spatial distribution of capacitor cells and interconnect parasitics affect the array's weight matching. Existing electronic design automation tools do not adequately consider device matching, process gradients, interconnect parasitics, and spatial symmetry in analog layouts, and related arrays still largely rely on manual placement and routing.

[0003] A common centroid layout can mitigate the impact of process gradients on capacitor matching, but for binary weighted CDACs, the highest weight bit corresponds to the largest number of working unit capacitors. When working unit capacitors of the same high weight bit are consecutively adjacent in the horizontal direction, parasitic coupling between their base plates can easily accumulate and affect weight matching. Base plate interconnects also increase trace length and routing channels when they run around the unit capacitors. Although placing base plate traces below the unit capacitors can shorten traces, coupling may still occur between the base plate traces and the top plate. Summary of the Invention

[0004] To address the aforementioned technical issues, this invention proposes an automatic layout and routing method and system for capacitive digital-to-analog converter arrays. By collaboratively optimizing the inter-bit staggered centroid layout and layered baseboard routing, the impact of array adjacency parasitics and interconnect parasitics on weight matching is effectively reduced.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] In a first aspect, the present invention provides an automatic layout and routing method for a capacitive digital-to-analog converter array, comprising the following steps:

[0007] S100. Obtain the layout generation parameters of the binary weighted capacitive digital-to-analog converter array to be generated. The layout generation parameters include the array bit number, unit capacitor layout data and process design rules. Then, according to the capacitor weight of each weight bit, the capacitor of each weight bit is divided into the corresponding number of equivalent working unit capacitors.

[0008] S200. Based on the total number of all working unit capacitors and the total number of central virtual capacitors used for symmetrical arrangement with the lowest weight working unit capacitor, determine the number of rows and columns of the internal layout matrix, so that the number of columns of the internal layout matrix is ​​even; based on the number of working unit capacitors that can be accommodated in two adjacent columns located in the middle of the internal layout matrix, divide a series of consecutive weight positions starting from the lowest weight position into a low weight position group, and divide the remaining weight positions into a high weight position group.

[0009] S300. Arrange the working unit capacitors of the low-weight bit group in the two adjacent columns, arrange the central virtual capacitor at the symmetrical position of the lowest weight bit working unit capacitor about the center of the internal layout matrix, arrange the non-highest weight bit capacitor columns in the high-weight bit group outward from the two adjacent columns, and set at least one highest weight bit capacitor column between the two adjacent columns in the arrangement order of the non-highest weight bit capacitor columns, so that the highest weight bit capacitor columns and the non-highest weight capacitor columns are arranged alternately, and arrange the working unit capacitors that belong to the same weight bit and do not belong to the lowest weight bit in pairs symmetrically about the center of the internal layout matrix.

[0010] S400. A base plate trace is generated below the working unit capacitor. The base plate trace includes vertical base plate lines and horizontal base plate lines located in different metal layers. The base plate of the working unit capacitor is connected to the corresponding vertical base plate line. Vertical base plate lines of the same weight position are connected through the corresponding horizontal base plate line. The vertical base plate line and the horizontal base plate line are connected through a through hole.

[0011] S500. Generate a top plate interconnect that connects the top plates of each working unit capacitor, so that the top plate interconnect is electrically isolated from the bottom plate traces.

[0012] S600: Automatically generate and output capacitive digital-to-analog converter array layout data containing unit capacitor instances, layer graphics, and network connection relationships according to the process design rules.

[0013] In S200, the number of columns in the internal layout matrix is ​​C, and the two adjacent columns are the C / 2th column and the C / 2+1th column. When the specified number of rows and columns can accommodate the working unit capacitor and the central virtual capacitor, and the specified number of columns is even, the internal layout matrix is ​​generated according to the specified values. When the number of rows and columns is not specified, the combination with the smallest absolute value of the difference between the number of rows and the number of columns is selected from the candidate row and column combinations that meet the capacity requirements and have an even number of columns. The positions in the internal layout matrix that are not occupied by the working unit capacitor and the central virtual capacitor are filled by internal filling virtual capacitors.

[0014] In S300, the lowest weight bit working unit capacitor and the central virtual capacitor are arranged in two adjacent columns and are symmetrical about the center of the internal layout matrix; in the two adjacent columns, the remaining weight bits in the low weight bit group are arranged from the center of the matrix to both ends in order of weight from low to high; outside the two adjacent columns, the non-highest weight bit capacitor columns in the high weight bit group are arranged outward in order of weight from low to high.

[0015] In S400, at least a portion of the vertical base plate lines are located within the planar projection range of the working unit capacitor. When multiple vertical base plate lines are set below the same working unit capacitor, the lateral position of each vertical base plate line is allocated according to the estimated wiring length from the connected working unit capacitor to the corresponding lateral base plate line, so that the lateral distance between the vertical base plate line with the larger estimated wiring length and the vertical center line of the working unit capacitor is not greater than the lateral distance between the vertical base plate line with the smaller estimated wiring length and the vertical center line.

[0016] In S500, a strip-shaped shielding metal extending along the gap is generated in the gap between adjacent unit capacitors. The strip-shaped shielding metal is separated from the base plate traces and the top plate interconnect in the layout. It is located on the same metal layer as at least one layer of the base plate traces, and the width of the strip-shaped shielding metal is greater than the width of the adjacent base plate traces, so as to transform part of the parasitic coupling between the base plate traces and the top plate interconnect into coupling between the base plate traces and the strip-shaped shielding metal.

[0017] Secondly, the present invention provides an automatic layout and routing system for capacitive digital-to-analog converter arrays that suppresses parasitic effects, comprising:

[0018] The parameter acquisition module is used to acquire the layout generation parameters of the binary weighted capacitive digital-to-analog converter array to be generated. The layout generation parameters include the array bit number, unit capacitor layout data and process design rules, and the capacitor of each weighted bit is divided into the corresponding number of equivalent working unit capacitors according to the capacitor weight of each weighted bit.

[0019] The size determination module is used to determine the number of rows and columns of the internal layout matrix based on the total number of all working unit capacitors and the total number of central virtual capacitors used for symmetrical arrangement with the lowest weight working unit capacitor, so that the number of columns of the internal layout matrix is ​​even; and based on the number of working unit capacitors that can be accommodated in two adjacent columns located in the middle of the internal layout matrix, it divides a series of consecutive weighted positions starting from the lowest weighted position into a low weighted position group, and divides the remaining weighted positions into a high weighted position group.

[0020] The common centroid layout module is used to arrange the working unit capacitors of the low-weight bit group in the two adjacent columns, arrange the central virtual capacitor in the symmetrical position of the lowest weight bit working unit capacitor about the center of the internal layout matrix, arrange the non-highest weight bit capacitor columns in the high-weight bit group outward from the two adjacent columns, and set at least one highest weight bit capacitor column between the two adjacent columns in the arrangement order of the non-highest weight bit capacitor columns, so that the highest weight bit capacitor columns and the non-highest weight capacitor columns form an alternating arrangement, and arrange the working unit capacitors belonging to the same weight bit but not the lowest weight bit in pairs symmetrically about the center of the internal layout matrix;

[0021] The base plate wiring module is used to generate base plate traces below the working unit capacitor. The base plate traces include vertical base plate lines and horizontal base plate lines located in different metal layers. The base plate of the working unit capacitor is connected to the corresponding vertical base plate line. Vertical base plate lines of the same weight position are connected through the corresponding horizontal base plate lines. The vertical base plate lines and the horizontal base plate lines are connected through through holes.

[0022] The top plate wiring module is used to generate top plate interconnects that connect the top plates of each working unit capacitor, so that the top plate interconnects are electrically isolated from the bottom plate wiring.

[0023] The layout output module is used to automatically generate and output the layout data of the capacitive digital-to-analog converter array, which includes unit capacitor instances, layer patterns, and network connection relationships, according to the process design rules.

[0024] Thirdly, the present invention provides a capacitive digital-to-analog converter array for suppressing parasitic effects, comprising an internal layout matrix, a base plate interconnect network, and a top plate interconnect network:

[0025] The capacitive digital-to-analog converter array is a binary weighted capacitive digital-to-analog converter array. The capacitor of each weight bit is composed of an equivalent number of working unit capacitors corresponding to its weight. The internal layout matrix includes the working unit capacitors and a central virtual capacitor arranged symmetrically with respect to the working unit capacitors of the lowest weight bit. The number of columns in the internal layout matrix is ​​even. The low-weight bit group includes a series of consecutive weight bits starting from the lowest weight bit. The working unit capacitors of the low-weight bit group are located in the middle of the internal layout matrix and in two adjacent columns. The remaining weight bits form the high-weight bit group. The working unit capacitors of the high-weight bit group are located outside the two adjacent columns. In the horizontal arrangement of the non-highest weight bit capacitor columns of the high-weight bit group, at least one highest weight bit capacitor column is provided between two adjacent columns of non-highest weight bit capacitor columns, so that the highest weight bit capacitor columns and the non-highest weight bit capacitor columns are arranged alternately. The lowest weight bit working unit capacitors and the central virtual capacitors are arranged symmetrically with respect to the center of the internal layout matrix, and the working unit capacitors belonging to the same weight bit but not belonging to the lowest weight bit are arranged symmetrically in pairs with respect to the center of the internal layout matrix.

[0026] Each working unit capacitor has a top plate and a bottom plate that are electrically isolated from each other; the bottom plate interconnection network includes vertical bottom plate lines and horizontal bottom plate lines located in different metal layers respectively, at least a portion of the vertical bottom plate lines are located within the planar projection range of the working unit capacitor, the bottom plate of the working unit capacitor is connected to the corresponding vertical bottom plate line, the vertical bottom plate lines of the same weight position are connected through the corresponding horizontal bottom plate lines, and the vertical bottom plate lines and the horizontal bottom plate lines are connected through through holes;

[0027] The top plate interconnection network connects the top plates of each working unit capacitor and is electrically isolated from the bottom plate interconnection network.

[0028] The capacitive digital-to-analog converter array further includes a strip-shaped shielding metal located within the gap between adjacent unit capacitors and extending along the gap. The strip-shaped shielding metal is separated from the base plate interconnect network and the top plate interconnect network in the layout, and is located on the same metal layer as at least one layer of the base plate interconnect network. The width of the strip-shaped shielding metal is greater than the width of the adjacent base plate line, so as to convert part of the parasitic coupling between the base plate interconnect network and the top plate interconnect network into coupling between the base plate interconnect network and the strip-shaped shielding metal.

[0029] Fourthly, the present invention provides an electronic device including at least one processor and a memory communicatively connected to the processor, wherein the memory stores a computer program or instructions executable by the processor, and when the computer program or instructions are executed by the processor, the processor performs the above-described automatic placement and routing method for a capacitive digital-to-analog converter array.

[0030] Fifthly, the present invention provides a computer program product, including a computer program or instructions, which, when executed by a processor, cause the processor to perform the above-described automatic placement and routing method for a capacitive digital-to-analog converter array.

[0031] Compared with the prior art, the beneficial effects of the present invention are:

[0032] By inserting the highest weight capacitor column between two adjacent columns in the arrangement of the non-highest weight capacitor columns of the high weight bit group, the highest weight capacitor column and the non-highest weight capacitor columns are arranged in an alternating manner. This effectively avoids a large number of unit capacitors of the same highest weight bit being continuously adjacent in the horizontal direction, thereby significantly suppressing the cumulative effect of parasitic coupling between the base plates of this weight bit and improving the proportional matching between each weight bit. At the same time, by arranging the vertical base plate lines directly below the unit capacitors and using different metal layers to realize the vertical and horizontal lines, the interconnect length of the base plate is greatly shortened, the occupation of the horizontal wiring channel is reduced, and the parasitic parameters are further balanced through optimized line length allocation. At the same time, electrical isolation is formed with the top plate interconnect, reducing the inter-board coupling.

[0033] This invention also provides a fully automated solution that can automatically complete the entire process from matrix determination, capacitor cell placement, layered routing to layout data output based on input layout generation parameters and process design rules. This avoids time-consuming and error-prone manual operations, significantly improving design efficiency and consistency. In addition, by setting strip-shaped shielding metal of specific width and layers in the gaps between adjacent capacitors, the electric field that might otherwise be coupled to the top plate is guided to the shielding metal, further reducing parasitic interference on critical signal paths. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments are briefly introduced below.

[0035] Figure 1 This is a flowchart illustrating the steps of an embodiment of the automatic placement and routing method for a CDAC array, including virtual capacitors, shielding metal, and design rule checks, according to the present invention.

[0036] Figure 2 This is a schematic diagram of a functional module structure of the electronic device of the present invention when executing the automatic placement and routing program of the CDAC array;

[0037] Figure 3 This is a schematic diagram of the interlayer connection relationship within a unit capacitor used in a specific embodiment of the present invention;

[0038] Figure 4 This is a schematic diagram of the capacitor array layout and base plate layered wiring provided in a specific embodiment of the present invention;

[0039] Figure 5 This is a schematic diagram of the top plate wiring of the capacitor array provided in a specific embodiment of the present invention;

[0040] Figure 6 This is a schematic diagram of the geometric arrangement of the capacitor array strip shielding metal provided in a specific embodiment of the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this invention clearer, the specific embodiments of this invention will be described in detail below with reference to the accompanying drawings. The following embodiments are for illustrative purposes only and should not be considered as limiting the scope of this invention. Those skilled in the art can make various modifications or equivalent substitutions to the embodiments without departing from the concept of this invention, but all such modifications or substitutions should fall within the protection scope of this invention.

[0042] In this specification, the terms "vertical" and "horizontal" are defined relative to the column and row directions of the internal layout matrix. Specifically, vertical refers to the column direction of the internal layout matrix, and horizontal refers to the row direction of the internal layout matrix. When the entire array layout is rotated or mirrored in the plane, the directions of "vertical" and "horizontal" should change accordingly with the transformation of the array coordinate system, and the electrical properties of the top plate interconnects and bottom plate traces do not substitute for each other due to changes in direction. Unless otherwise explicitly stated, the numbering of the steps is for illustrative purposes only and does not constitute a strict limitation on the order of execution.

[0043] Figure 1 The flowchart illustrates the steps of an embodiment of the automatic placement and routing method for a CDAC array that includes virtual capacitors, shielding metal, and design rule checks according to the present invention. Figure 2 An embodiment of an electronic device and program module structure for implementing the method of the present invention is shown. Figures 3 to 6 Taking an eight-bit (bit 0 to bit 7) binary weighted CDAC as an example, the array layout and wiring scheme of a specific embodiment of the present invention are shown. The numbers 0 to 7 are used to refer to weight bits C0 to C7, respectively, and the letter D is used to refer to a virtual capacitor. It should be understood that these markings are only used to distinguish different weight bits and virtual capacitors in this specific embodiment and should not constitute any limitation on the scope of protection of the present invention.

[0044] Example 1

[0045] This embodiment provides an automatic placement and routing method for CDAC arrays to suppress parasitic effects. This method is executed by an electronic device. The electronic device can be a computer, server, or application-specific integrated circuit (ASIC) design workstation running layout design tools, including at least one processor and a memory communicatively connected to the processor. The memory stores computer programs or instructions, and the processor executes the method described in this embodiment when executing the program or instructions.

[0046] Reference Figure 1 The method in this embodiment includes the following steps:

[0047] S100: Parameter Acquisition and Unit Capacitance Splitting

[0048] First, obtain the layout generation parameters for the CDAC array to be generated. These parameters include at least the number of bits in the array, the layout data of the standard unit capacitance, and the process design rules for the target process.

[0049] The number of array bits determines the number of weight bits in a CDAC and the capacitance value corresponding to each weight bit. For an N-bit binary weighted CDAC, there are N weight bits, denoted as C0, C1, ..., C{N-1}, where C0 is the lowest weight bit and C{N-1} is the highest weight bit.

[0050] Unit capacitance layout data includes the unit capacitance's dimensions, the graphics of each metal layer, the locations of the top and bottom plates' lead-out ports, and the interlayer connections. Unit capacitance layout data can be obtained by importing external files, calling from a layout library, or generating from parametric cells; different acquisition methods do not change the subsequent placement and routing process.

[0051] The process design rules should include at least the minimum width, minimum spacing, enclosing amount, unit capacitance boundary, available wiring layers, and interlayer connection relationships of each metal layer and via layer. These can be obtained through process design kits, rule files, or user configuration.

[0052] Subsequently, according to the binary weighting rules, the program splits the capacitor corresponding to each weight bit into a corresponding number of completely equal working unit capacitors. For example, weight bit C0 is split into 1 working unit capacitor, weight bit C1 into 2 working unit capacitors, and weight bit C{N-1} into 2{N-1} working unit capacitors. These working unit capacitors have completely identical layout structure and electrical characteristics, which is the basis for achieving good matching.

[0053] Figure 3 The internal interlayer connections of the unit capacitor in this embodiment are shown. To illustrate the relationship between the baseboard traces and the unit capacitor, this embodiment uses a metal-oxide-metal capacitor as an example. (Refer to...) Figure 3 The unit capacitor forms an electrically isolated top plate metal and a bottom plate metal in the sixth metal layer. The fifth metal layer and the seventh metal layer form a bottom plate metal plate located below and above the sixth metal layer, respectively, and are connected to the bottom plate metal of the sixth metal layer through Via5 and Via6, so that the top plate and the bottom plate have an independent electrical connection relationship.

[0054] It should be noted that the present invention does not limit the specific structure of the unit capacitor. The only requirements are that the top plate and the bottom plate are electrically isolated from each other and can be led out separately, there is a metal layer below the lowest metal layer constituting the unit capacitor that can be used for wiring on the bottom plate, and the bottom plate of the unit capacitor can be connected to the wiring metal layer through through holes. Figure 3 The metal layer numbers and specific graphics shown are only for illustrating this embodiment and do not constitute a limitation on the unit capacitor structure. The specific layer numbers and via combinations of the metal layers used are determined according to the target process.

[0055] S200: Determine the internal layout matrix size and weight grouping.

[0056] This step is used to determine the number of rows R and columns C of the internal layout matrix, excluding the peripheral virtual capacitors.

[0057] First, calculate the total number of all working unit capacitors, and add a central virtual capacitor for center-symmetric arrangement with the lowest-weighted working unit capacitor, resulting in the total number T. The purpose of the central virtual capacitor is to provide a center-symmetric virtual counterpart for the lowest-weighted working unit capacitor in the matrix, thereby improving its matching environment.

[0058] Then, the matrix size is determined according to the following principles: the product of the number of rows R and the number of columns C must be greater than or equal to T, and the number of columns C must be even. Also, let the two adjacent columns located at the center of the matrix be the C / 2th column and the C / 2+1th column.

[0059] In a preferred embodiment, if the user has specified a feasible number of rows and columns, and the above conditions are met, the user-specified values ​​are directly adopted. If the user has not specified a number of rows and columns, the program selects the combination with the smallest absolute value of the difference between the number of rows R and the number of columns C from all candidate combinations that satisfy the condition that the product is greater than or equal to T and the number of columns C is even, in order to obtain a matrix that is closest to a square. This is beneficial for optimizing the spatial distribution uniformity of unit capacitance and reducing the matching error introduced by process gradient.

[0060] The remaining positions in the matrix beyond T are filled with internal virtual capacitors. These internal virtual capacitors are not used as weight capacitors controlled by digital codes; their purpose is to ensure that all working unit capacitors are in a uniform adjacency environment, thus mitigating the impact of edge effects on matching.

[0061] Next, the division of the low-weight bit group is determined based on the total number of working unit capacitors that can be accommodated in the two middle adjacent columns. Specifically, starting from the lowest weight bit C0, the program accumulates all the working unit capacitors of several consecutive weight bits until the accumulated number does not exceed the total capacity of the two middle columns. These weight bits are divided into the low-weight bit group, and the remaining weight bits are divided into the high-weight bit group.

[0062] Figure 2 An embodiment of an electronic device and program module structure for implementing the method of the present invention is shown. (Refer to...) Figure 2 The parameter acquisition module 100 performs the function of S100, the size determination module 200 performs the function of S200, the common centroid layout module 300 performs the function of S300, the virtual capacitor generation module 350 generates various virtual capacitors, the base plate routing module 400 performs the function of S400, the top plate routing module 500 performs the function of S500, the shielding generation module 600 generates strip-shaped shielding metal, and the design rule checking and layout output module 700 performs the function of S600. The above functional division and module names are only for illustrating this embodiment; in actual programs, multiple modules can be merged, split, or implemented according to different calling orders.

[0063] Step S300: Perform inter-bit staggered cocentroid layout

[0064] This is the core layout step of the present invention, the goal of which is to accurately place the working unit capacitors and virtual capacitors symmetrically around their common centroid in the internal layout matrix. For an internal layout matrix of R rows and C columns, the symmetrical positions of the r-th row and c-th column about the center of the matrix are the (R+1-r)-th row and (C+1-c)-th column.

[0065] First, in the central region of the internal layout matrix, the working unit capacitor of the lowest weight bit C0 is placed in columns C / 2 and C / 2+1. Simultaneously, a central virtual capacitor is placed in a position strictly symmetrical to the C0 unit capacitor about the matrix center, ensuring that the C0 unit capacitor is in an optimally centered position.

[0066] Then, in the remaining space of the two adjacent columns in the middle, the working unit capacitors of the other weight bits in the low weight bit group except C0 are arranged symmetrically from the center of the matrix to the top and bottom ends of the matrix in order of weight from low to high, and it is ensured that all working unit capacitors belonging to the same weight bit are symmetrical about the center of the matrix.

[0067] Next, the highest-weighted and non-highest-weighted bits in the high-weighted bit group are arranged in an alternating pattern. Specifically, starting from the two adjacent columns in the middle, the working unit capacitors are placed column by column outwards from the center. During placement, the non-highest-weighted capacitor columns are arranged from the center outwards in ascending order of weight, but at least one highest-weighted capacitor column must be inserted between any two adjacent non-highest-weighted capacitor columns. This creates an alternating layout of the highest-weighted and non-highest-weighted capacitor columns horizontally, effectively preventing all unit capacitors of the highest-weighted bits from being consecutively adjacent in the horizontal direction.

[0068] For all working unit capacitors that have been placed but are not at the lowest weight position, another working unit capacitor belonging to the same weight position must be placed at a position symmetrical about the center of the matrix to ensure the strict central symmetry of the entire array.

[0069] Figure 4 The diagram illustrates the staggered centroid layout and layered wiring structure of the eight-bit embodiment described above. (Refer to...) Figure 4 The working unit capacitors C0 to C2 are arranged in the middle two adjacent columns of the internal layout matrix, with the C0 unit capacitor and the central virtual capacitor arranged symmetrically with it placed close to the center of the matrix. The working unit capacitors C5 to C7 are arranged outwards column by column, with a C7 capacitor column placed between the C5 and C6 capacitor columns, so that the C7 capacitor column is staggered with the C5 and C6 capacitor columns. Peripheral virtual capacitors are placed around the periphery of the internal layout matrix to improve the adjacency environment of the edge unit capacitors.

[0070] The virtual capacitors in this embodiment include the following three types: central virtual capacitors, used to form a centrally symmetrical relationship with the lowest weighted working unit capacitor; internal filling virtual capacitors, used to fill the remaining positions in the internal layout matrix that are not occupied by the working unit capacitors and the central virtual capacitor; and peripheral virtual capacitors, arranged in at least one ring around the internal layout matrix, so that the working unit capacitors near the edge have a similar adjacency environment to the internal unit capacitors of the array. None of the virtual capacitors are used as weighted capacitors controlled by digital codes for switching. The top plates of the central virtual capacitors and internal filling virtual capacitors are connected to the horizontal top plate line of their respective rows, and the bottom plates of all types of virtual capacitors are connected to ground potential. The peripheral virtual capacitors use the same bottom plate wiring layer, line width, routing direction, and via arrangement as the adjacent working unit capacitors.

[0071] S400: Generate layered base plate routing

[0072] After the layout is completed, the program performs automatic routing for the interconnection of the base plates.

[0073] The program scans the internal layout matrix column by column to determine the weight bits in each column. Based on design rules such as unit capacitor size, spacing between adjacent unit capacitors, minimum width of metal wires, and minimum spacing, one or more vertical base plate lines are generated for each weight bit that needs to be connected. These vertical base plate lines extend vertically, and at least a portion of them lie within the planar projection range of the corresponding working unit capacitor. The base plate of the unit capacitor is vertically connected to the corresponding vertical base plate line below it through through holes.

[0074] For a capacitor column containing only one high-weight bit, setting a corresponding vertical base line will connect all unit capacitors of the same weight bit in that column. For two adjacent columns containing multiple low-weight bits, multiple vertical base lines will be set to connect the unit capacitors of each low-weight bit.

[0075] When multiple different vertical base lines need to be arranged below a unit capacitor, the program allocates the lateral positions of these lines based on the estimated length of each vertical base line from its connected unit capacitor to the point where it merges with the corresponding horizontal base line. The longer the estimated length of the vertical base line, the closer it is to the vertical center line of the unit capacitor; the shorter the estimated length of the line, the more it is placed on both sides, thus balancing the parasitic parameters on each line.

[0076] All vertical baseplate lines extend along the column direction to the same end of the matrix. Then, the program generates a horizontal baseplate line for each weight bit in that end region. All vertical baseplate lines for the same weight bit are connected to the corresponding horizontal baseplate line via vias, ultimately converging at a common baseplate exit point. Vertical and horizontal baseplate lines use different metal layers to avoid overlapping and reduce the occupancy of horizontal routing channels.

[0077] Continue to refer to Figure 4 The vertical base plate lines of each weight position extend along the column direction below the capacitor array to the upper end of the array. Then, the horizontal base plate lines connect multiple vertical base plate lines belonging to the same weight position to the corresponding base plate lead-out end.

[0078] S500: Generate Top Plate Interconnection

[0079] Generate a top-plate interconnect network to connect the top plates of all working unit capacitors.

[0080] Reference Figure 5 In the capacitor array, except for the first and last rows, a horizontal top plate line is generated for each row. This horizontal top plate line connects the top plates of all working unit capacitors in that row. At the same time, for load matching considerations, it also connects the top plates of the central virtual capacitor and the internally filled virtual capacitors in the same row. These virtual capacitors constitute the load of the common top plate.

[0081] Then, on the left and right sides of the array, all the horizontal top plate lines are joined together by one or more vertical top plate lines and connected to a common top plate lead-out end.

[0082] The top plates of the working unit capacitors located in the first and last rows of the capacitor array are connected to the common top plate via the corresponding horizontal top plate lines. The top plates of the peripheral virtual capacitors located in the first and last rows are not connected to the horizontal top plate lines, but are instead connected to ground. The bottom plates of all types of virtual capacitors are connected to ground. The top plate interconnect network and the bottom plate routing network are located on different metal layers and are electrically isolated from each other.

[0083] S600: Design Rule Check and Layout Data Output

[0084] Finally, the program invokes the design rule check module to perform a comprehensive design rule check on the generated layout data, ensuring that it meets the requirements of the process design rules regarding minimum width, minimum spacing, and enclosure. For any non-compliance, the program automatically corrects or provides prompts, while simultaneously checking the connectivity of each network connection.

[0085] After all checks are passed, the program automatically generates and outputs a complete CDAC array layout data file according to the standard layout data format. This file contains unit capacitance instances, all layer diagrams, and complete network connections, which can be directly used for subsequent physical verification, parasitic parameter extraction, and chip manufacturing.

[0086] Example 2

[0087] The difference between this embodiment and embodiment 1 is that, in S500, while generating the top plate interconnect, a strip-shaped shielding metal is also generated in the gap between adjacent unit capacitors.

[0088] Reference Figure 6 The program generates a strip of shielding metal extending along the direction of the gap between adjacent unit capacitors. This strip of shielding metal is separated from the baseplate traces and topplate interconnects in the layout and is not directly connected to them. It is located on the same metal layer as at least one of the baseplate traces, and its width is set to be greater than the width of the adjacent vertical baseplate line.

[0089] The aforementioned structural and dimensional design effectively shields and transforms the electric field that might otherwise couple from the base plate traces to the top plate interconnect into coupling between the base plate traces and the strip-shaped shielding metal, thereby further suppressing parasitic interference on critical signal paths.

[0090] exist Figure 6 In the specific embodiment shown, the inter-column strip shielding metal and the shielding strip around the array are geometrically connected, but this continuity is only used to illustrate this embodiment and does not constitute a limitation on other implementations. Figure 6 Used to indicate the geometric position and relative width of a strip of shielding metal, but not to indicate its specific electrical connection state.

[0091] The other steps in this embodiment are the same as in Embodiment 1, and will not be repeated here.

[0092] Example 3

[0093] This embodiment provides an automatic placement and routing system for CDAC arrays to suppress parasitic effects. Its functional module structure is as follows: Figure 2 As shown.

[0094] Reference Figure 2 The system includes:

[0095] The parameter acquisition module 100 is used to acquire the layout generation parameters of the binary weighted capacitive digital-to-analog converter array to be generated. The layout generation parameters include the array bit number, unit capacitor layout data and process design rules, and the capacitor of each weighted bit is divided into a corresponding number of equivalent working unit capacitors according to the capacitor weight of each weighted bit.

[0096] The size determination module 200 is used to determine the number of rows and columns of the internal layout matrix based on the total number of all working unit capacitors and the total number of central virtual capacitors used for centrally symmetrical arrangement with the lowest weight working unit capacitor, so that the number of columns of the internal layout matrix is ​​even; and based on the number of working unit capacitors that can be accommodated in two adjacent columns located in the middle of the internal layout matrix, it divides a series of consecutive weighted positions starting from the lowest weighted position into a low weighted position group, and divides the remaining weighted positions into a high weighted position group.

[0097] The centroid layout module 300 is used to arrange the working unit capacitors of the low-weight bit group in the two adjacent columns, arrange the central virtual capacitor in the symmetrical position of the lowest weight bit working unit capacitor about the center of the internal layout matrix, arrange the non-highest weight bit capacitor columns in the high-weight bit group outward from the two adjacent columns, and set at least one highest weight bit capacitor column between the two adjacent columns in the arrangement order of the non-highest weight bit capacitor columns, so that the highest weight bit capacitor columns and the non-highest weight capacitor columns form an alternating arrangement, and arrange the working unit capacitors belonging to the same weight bit but not the lowest weight bit in pairs symmetrically about the center of the internal layout matrix.

[0098] The virtual capacitor generation module 350 is used to generate a central virtual capacitor, an internal filling virtual capacitor, and a peripheral virtual capacitor.

[0099] The base plate wiring module 400 is used to generate base plate traces below the working unit capacitor. The base plate traces include vertical base plate lines and horizontal base plate lines located in different metal layers. The base plate of the working unit capacitor is connected to the corresponding vertical base plate line. Vertical base plate lines of the same weight position are connected through the corresponding horizontal base plate lines. The vertical base plate lines and the horizontal base plate lines are connected through through holes.

[0100] The top plate wiring module 500 is used to generate top plate interconnects that connect the top plates of each working unit capacitor, so that the top plate interconnects are electrically isolated from the bottom plate wiring.

[0101] The shielding generation module 600 is used to generate a strip of shielding metal extending along the gap between adjacent unit capacitors.

[0102] The design rule checking and layout output module 700 is used to automatically generate and output the layout data of the capacitive digital-to-analog converter array, which includes unit capacitor instances, layer graphics and network connection relationships, according to the process design rules.

[0103] The aforementioned modules are stored in the electronic device's memory as software program modules, and are executed by the processor. The modules exchange layout matrices, layer diagrams, and network connection data through data interfaces. It should be noted that the functional divisions and module names described above are only for illustrating this embodiment. In actual programs, multiple modules can be merged, split, or implemented in different calling orders, and can also be called through the layout tool's script interface, plug-in interface, or application programming interface.

[0104] Example 4

[0105] This embodiment provides a binary weighted CDAC array materialized according to the above method, whose internal structure, interconnection relationship and geometric features are consistent with the layout and routing results described in the above method embodiment.

[0106] The CDAC array comprises an internal layout matrix with an even number of rows and columns, a bottom-plane interconnect network, and a top-plane interconnect network. The capacitance of each weighted bit consists of an equivalent number of working unit capacitors corresponding to its capacitance weight. The internal layout matrix includes the working unit capacitors and a central virtual capacitor arranged symmetrically with respect to the working unit capacitors of the lowest weighted bit.

[0107] The low-weight bit group comprises a series of consecutive weight bits starting from the lowest weight bit. The working unit capacitor of the low-weight bit group is located in the middle of two adjacent columns of the internal layout matrix. The remaining weight bits constitute the high-weight bit group, and the working unit capacitor of the high-weight bit group is located outside the two adjacent columns. In the horizontal arrangement of the non-highest weight capacitor columns of the high-weight bit group, at least one highest weight capacitor column is provided between two adjacent columns of non-highest weight capacitor columns, so that the highest weight capacitor columns and non-highest weight capacitor columns are arranged alternately. The lowest weight working unit capacitor and the central virtual capacitor are arranged symmetrically about the center of the internal layout matrix, and working unit capacitors belonging to the same weight bit but not belonging to the lowest weight bit are arranged symmetrically in pairs about the center of the internal layout matrix.

[0108] Each working unit capacitor has a top plate and a bottom plate that are electrically isolated from each other. The bottom plate interconnection network includes vertical bottom plate lines and horizontal bottom plate lines located on different metal layers. At least a portion of the vertical bottom plate lines lies within the planar projection range of the working unit capacitor. The bottom plate of the working unit capacitor is connected to the corresponding vertical bottom plate line. Vertical bottom plate lines of the same weight position are connected through the corresponding horizontal bottom plate lines, and the vertical and horizontal bottom plate lines are connected through vias. The top plate interconnection network connects the top plates of each working unit capacitor and is electrically isolated from the bottom plate interconnection network.

[0109] The CDAC array also includes a strip of shielding metal located within and extending along the gap between adjacent unit capacitors. The strip of shielding metal is separated from the baseplate interconnect network and the topplate interconnect network in the layout, is located on the same metal layer as at least one layer of the baseplate interconnect network, and has a width greater than the width of the adjacent baseplate line, so as to transform some of the parasitic coupling between the baseplate interconnect network and the topplate interconnect network into coupling between the baseplate interconnect network and the strip of shielding metal.

[0110] This CDAC array can be integrated into a successive approximation analog-to-digital converter to form its core digital-to-analog conversion section. This application method does not change the spatial relationship of unit capacitance, the bottom-plane interconnect hierarchy, the top-plane interconnect relationship, and the geometry of the shielding metal within the CDAC array.

[0111] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not describe all details exhaustively, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification.

Claims

1. An automatic placement and routing method for a capacitive digital-to-analog converter array, characterized in that, Includes the following steps: S100. Obtain the layout generation parameters of the binary weighted capacitive digital-to-analog converter array to be generated. The layout generation parameters include the array bit number, unit capacitor layout data and process design rules. Then, according to the capacitor weight of each weight bit, the capacitor of each weight bit is divided into the corresponding number of equivalent working unit capacitors. S200. Based on the total number of all working unit capacitors and the total number of central virtual capacitors used for symmetrical arrangement with the lowest weight working unit capacitor, determine the number of rows and columns of the internal layout matrix, so that the number of columns of the internal layout matrix is ​​even; based on the number of working unit capacitors that can be accommodated in two adjacent columns located in the middle of the internal layout matrix, divide a series of consecutive weight positions starting from the lowest weight position into a low weight position group, and divide the remaining weight positions into a high weight position group. S300. Arrange the working unit capacitors of the low-weight bit group in the two adjacent columns, arrange the central virtual capacitor at the symmetrical position of the lowest weight bit working unit capacitor about the center of the internal layout matrix, arrange the non-highest weight bit capacitor columns in the high-weight bit group outward from the two adjacent columns, and set at least one highest weight bit capacitor column between the two adjacent columns in the arrangement order of the non-highest weight bit capacitor columns, so that the highest weight bit capacitor columns and the non-highest weight capacitor columns are arranged alternately, and arrange the working unit capacitors that belong to the same weight bit and do not belong to the lowest weight bit in pairs symmetrically about the center of the internal layout matrix. S400. A base plate trace is generated below the working unit capacitor. The base plate trace includes vertical base plate lines and horizontal base plate lines located in different metal layers. The base plate of the working unit capacitor is connected to the corresponding vertical base plate line. Vertical base plate lines of the same weight position are connected through the corresponding horizontal base plate line. The vertical base plate line and the horizontal base plate line are connected through a through hole. S500. Generate a top plate interconnect that connects the top plates of each working unit capacitor, so that the top plate interconnect is electrically isolated from the bottom plate traces. S600: Automatically generate and output capacitive digital-to-analog converter array layout data containing unit capacitor instances, layer graphics, and network connection relationships according to the process design rules.

2. The automatic placement and routing method for capacitive digital-to-analog converter arrays according to claim 1, characterized in that, In S200, the number of columns in the internal layout matrix is ​​C, and the two adjacent columns are the C / 2th column and the C / 2+1th column. When the specified number of rows and columns can accommodate the working unit capacitor and the central virtual capacitor, and the specified number of columns is even, the internal layout matrix is ​​generated according to the specified values. When the number of rows and columns is not specified, the combination with the smallest absolute value of the difference between the number of rows and the number of columns is selected from the candidate row and column combinations that meet the capacity requirements and have an even number of columns. The positions in the internal layout matrix that are not occupied by the working unit capacitor and the central virtual capacitor are filled by internal filling virtual capacitors.

3. The automatic placement and routing method for capacitive digital-to-analog converter arrays according to claim 1, characterized in that, In S300, the lowest weight bit working unit capacitor and the central virtual capacitor are arranged in two adjacent columns and are symmetrical about the center of the internal layout matrix; in the two adjacent columns, the remaining weight bits in the low weight bit group are arranged from the center of the matrix to both ends in order of weight from low to high; outside the two adjacent columns, the non-highest weight bit capacitor columns in the high weight bit group are arranged outward in order of weight from low to high.

4. The automatic placement and routing method for a capacitive digital-to-analog converter array according to claim 1, characterized in that, In S400, at least a portion of the vertical base plate lines are located within the planar projection range of the working unit capacitor. When multiple vertical base plate lines are set below the same working unit capacitor, the lateral position of each vertical base plate line is allocated according to the estimated wiring length from the connected working unit capacitor to the corresponding lateral base plate line, so that the lateral distance between the vertical base plate line with the larger estimated wiring length and the vertical center line of the working unit capacitor is not greater than the lateral distance between the vertical base plate line with the smaller estimated wiring length and the vertical center line.

5. The automatic placement and routing method for a capacitive digital-to-analog converter array according to claim 1, characterized in that, In S500, a strip-shaped shielding metal extending along the gap is generated in the gap between adjacent unit capacitors. The strip-shaped shielding metal is separated from the base plate traces and the top plate interconnect in the layout. It is located on the same metal layer as at least one layer of the base plate traces, and the width of the strip-shaped shielding metal is greater than the width of the adjacent base plate traces, so as to transform part of the parasitic coupling between the base plate traces and the top plate interconnect into coupling between the base plate traces and the strip-shaped shielding metal.

6. An automatic placement and routing system for capacitive digital-to-analog converter arrays to suppress parasitic effects, characterized in that: The parameter acquisition module is used to acquire the layout generation parameters of the binary weighted capacitive digital-to-analog converter array to be generated. The layout generation parameters include the array bit number, unit capacitor layout data and process design rules, and the capacitor of each weighted bit is divided into the corresponding number of equivalent working unit capacitors according to the capacitor weight of each weighted bit. The size determination module is used to determine the number of rows and columns of the internal layout matrix based on the total number of all working unit capacitors and the total number of central virtual capacitors used for symmetrical arrangement with the lowest weight working unit capacitor, so that the number of columns of the internal layout matrix is ​​even; and based on the number of working unit capacitors that can be accommodated in two adjacent columns located in the middle of the internal layout matrix, it divides a series of consecutive weighted positions starting from the lowest weighted position into a low weighted position group, and divides the remaining weighted positions into a high weighted position group. The common centroid layout module is used to arrange the working unit capacitors of the low-weight bit group in the two adjacent columns, arrange the central virtual capacitor in the symmetrical position of the lowest weight bit working unit capacitor about the center of the internal layout matrix, arrange the non-highest weight bit capacitor columns in the high-weight bit group outward from the two adjacent columns, and set at least one highest weight bit capacitor column between the two adjacent columns in the arrangement order of the non-highest weight bit capacitor columns, so that the highest weight bit capacitor columns and the non-highest weight capacitor columns form an alternating arrangement, and arrange the working unit capacitors belonging to the same weight bit but not the lowest weight bit in pairs symmetrically about the center of the internal layout matrix; The base plate wiring module is used to generate base plate traces below the working unit capacitor. The base plate traces include vertical base plate lines and horizontal base plate lines located in different metal layers. The base plate of the working unit capacitor is connected to the corresponding vertical base plate line. Vertical base plate lines of the same weight position are connected through the corresponding horizontal base plate lines. The vertical base plate lines and the horizontal base plate lines are connected through through holes. The top plate wiring module is used to generate top plate interconnects that connect the top plates of each working unit capacitor, so that the top plate interconnects are electrically isolated from the bottom plate wiring. The layout output module is used to automatically generate and output the layout data of the capacitive digital-to-analog converter array, which includes unit capacitor instances, layer patterns, and network connection relationships, according to the process design rules.

7. A capacitive digital-to-analog converter array for suppressing parasitic effects, characterized in that, This includes the internal layout matrix, the bottom plate interconnection network, and the top plate interconnection network; The capacitive digital-to-analog converter array is a binary weighted capacitive digital-to-analog converter array. The capacitor of each weight bit is composed of an equivalent number of working unit capacitors corresponding to its weight. The internal layout matrix includes the working unit capacitors and a central virtual capacitor arranged symmetrically with respect to the working unit capacitors of the lowest weight bit. The number of columns in the internal layout matrix is ​​even. The low-weight bit group includes a series of consecutive weight bits starting from the lowest weight bit. The working unit capacitors of the low-weight bit group are located in the middle of the internal layout matrix and in two adjacent columns. The remaining weight bits form the high-weight bit group. The working unit capacitors of the high-weight bit group are located outside the two adjacent columns. In the horizontal arrangement of the non-highest weight bit capacitor columns of the high-weight bit group, at least one highest weight bit capacitor column is provided between two adjacent columns of non-highest weight bit capacitor columns, so that the highest weight bit capacitor columns and the non-highest weight bit capacitor columns are arranged alternately. The lowest weight bit working unit capacitors and the central virtual capacitors are arranged symmetrically with respect to the center of the internal layout matrix, and the working unit capacitors belonging to the same weight bit but not belonging to the lowest weight bit are arranged symmetrically in pairs with respect to the center of the internal layout matrix. Each working unit capacitor has a top plate and a bottom plate that are electrically isolated from each other; the bottom plate interconnection network includes vertical bottom plate lines and horizontal bottom plate lines located in different metal layers respectively, at least a portion of the vertical bottom plate lines are located within the planar projection range of the working unit capacitor, the bottom plate of the working unit capacitor is connected to the corresponding vertical bottom plate line, the vertical bottom plate lines of the same weight position are connected through the corresponding horizontal bottom plate lines, and the vertical bottom plate lines and the horizontal bottom plate lines are connected through through holes; The top plate interconnection network connects the top plates of each working unit capacitor and is electrically isolated from the bottom plate interconnection network.

8. The capacitive digital-to-analog converter array for suppressing parasitic effects according to claim 7, characterized in that, It also includes a strip-shaped shielding metal located within the gap between adjacent unit capacitors and extending along the gap. The strip-shaped shielding metal is separated from the base plate interconnect network and the top plate interconnect network in the layout, is located on the same metal layer as at least one layer of the base plate interconnect network, and the width of the strip-shaped shielding metal is greater than the width of the adjacent base plate line, so as to transform part of the parasitic coupling between the base plate interconnect network and the top plate interconnect network into coupling between the base plate interconnect network and the strip-shaped shielding metal.

9. An electronic device, characterized in that, The method includes at least one processor and a memory communicatively connected to the processor, the memory storing a computer program or instructions executable by the processor, wherein when the computer program or instructions are executed by the processor, the processor performs the automatic placement and routing method for a capacitive digital-to-analog converter array as described in any one of claims 1 to 5.

10. A computer program product, comprising a computer program or instructions, characterized in that, When the computer program or instructions are executed by the processor, the processor performs the automatic placement and routing method for the capacitive digital-to-analog converter array as described in any one of claims 1 to 5.

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