Verification method and related apparatus

Abstract

The application discloses a verification method and related devices, which converts a graphic merging verification problem into a consistency comparison problem of point position relations, and realizes high-precision, automatic and positionable verification of a geometric graphic merging operation by combining intersection segmentation sampling, bidirectional offset detection and mapping rules of internal and external position relations. The application can reduce the cost of layout verification, improve verification efficiency and reliability, and enhance user experience.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a verification method and related apparatus. Background Technology

[0002] In the fields of electronic design automation (EDA) and computer-aided design (CAD), geometric merging is a fundamental operation in layout data processing. Whether in integrated circuit (IC) layout design, printed circuit board (PCB) design, or micro-electro-mechanical system (MEMS) and flat panel display device design, Boolean logic processing such as unioning, clipping, or stitching is involved in merging polygons, line segments, and filled regions to generate target graphic data that conforms to manufacturing rules.

[0003] For example, in the PCB design process, after designers complete the circuit layout and routing, they typically need to convert the design data into Gerber files or other standard format data to drive the manufacturing equipment used to physically process the PCB. A Gerber file is essentially a data representation of the geometry in the PCB design layout. During this process, due to differences in data format conversion, graphic simplification, arc discretization, and the implementation of Boolean operation engines, discretization may occur between the geometry in the Gerber file and the original PCB design data. Summary of the Invention

[0004] This application discloses a verification method and related apparatus, which can reduce the cost of layout verification, improve verification efficiency and reliability, and enhance user experience.

[0005] In a first aspect, embodiments of this application provide a verification method. This method can be applied to an electronic device, which can be independent software, or a module integrated into an EDA (e.g., verification is performed internally within the EDA before outputting a photoplot file) (wherein, the modules in the electronic device include communication modules and computing modules), or a circuit or chip in the electronic device responsible for verification functions (such as a modem chip, also known as a baseband chip, or a system-on-chip (SoC) chip containing a modem core, or a system-in-package (SIP) chip), or the electronic device can also be a logic module or software capable of implementing all or part of the verification functions. The method includes: determining multiple intersection points of any two geometric figures in a design layout that have an intersection relationship, wherein the multiple intersection points are located on the contour of each of the two geometric figures; determining multiple candidate points, wherein the multiple candidate points correspond one-to-one with multiple reference contours, each candidate point being any point on the corresponding reference contour, and the multiple reference contours including the contour between any two adjacent intersection points on the contour of each of the two geometric figures. Offset each of the plurality of candidate points along at least one of a first direction and a second direction to obtain multiple sets of detection points after offset, wherein each set of detection points corresponds one-to-one with the plurality of candidate points, and each set of detection points includes at least one detection point, wherein the at least one detection point is located within or outside the geometry of any two geometric figures containing the candidate point corresponding to the at least one detection point; for each candidate point, the first direction is directed towards the geometry containing the candidate point, and the second direction is directed towards the geometry containing the candidate point. A first positional relationship and a second positional relationship are determined for each detection point. The first positional relationship indicates whether the detection point is an internal or external detection point in the design layout, and the second positional relationship indicates whether the detection point is an internal or external detection point in the actual layout. The actual layout includes the geometric shape formed by merging any two geometric shapes in the design layout. The position of the multiple sets of detection points in the actual layout is the same as the position of the multiple sets of detection points in the design layout. For each detection point in the design layout, if the detection point is located within any two geometric shapes, it is an internal detection point; if the detection point is located outside any two geometric shapes, it is an external detection point. Similarly, for each detection point in the actual layout, if the detection point is located within any one of the geometric shapes, it is an internal detection point; if the detection point is not located within any one of the geometric shapes, it is an external detection point.Based on the comparison results of the first positional relationship and the second positional relationship, verify whether the merging is correct.

[0006] In this embodiment, the detection interval is first divided based on multiple intersection points on the contours of any two geometric figures. On the contours of two intersecting geometric figures, multiple intersection points are used as dividing points to extract the contours between adjacent intersection points as reference contours. This division method covers potential topological change areas, especially boundary overlap areas, coincident areas, and areas near intersection points that are prone to errors in merging operations.

[0007] Secondly, this application associates candidate points with boundary paths. Candidate points are selected on each reference contour, and multiple sets of detection points are generated by offsetting them in the directions inside and outside the geometry. This ensures that the detection points are distributed in locations where the geometric contours may change before and after merging, reducing invalid sampling.

[0008] Then, the coordinate positions of the same detection point are recorded in the design layout before merging (e.g., two independent geometric shapes) and the actual layout after merging (e.g., a merged geometric shape). Since the position of the detection point in the physical coordinate system remains unchanged, only the graphic object it refers to may change. Therefore, by comparing whether the "internal or external" attributes of the detection point are consistent before and after merging, the correctness of the merging operation can be determined, thus improving the efficiency and reliability of verification.

[0009] In summary, this application transforms the graphic merging verification problem into a consistency comparison problem of point position relationships. By combining intersection point segmentation sampling, bidirectional offset detection, and mapping rules for internal and external position relationships, it achieves high-precision, automated, and location-based verification of geometric graphic merging operations. This application can reduce the cost of layout verification, improve verification efficiency and reliability, and enhance the user experience.

[0010] In one possible implementation, determining multiple intersection points of any two intersecting geometric shapes among a plurality of geometric shapes in the design layout includes: traversing the outline of each of the plurality of geometric shapes; calculating the intersection relationship between the outline of each of the plurality of geometric shapes and the outline of every other geometric shape in the plurality of geometric shapes to determine the arbitrary two geometric shapes; and determining all intersection points between the outline of one of the arbitrary two geometric shapes and the outline of the other geometric shape to obtain the plurality of intersection points.

[0011] In the above implementation, by traversing all geometric figures, determining intersections by contour-to-contour method, and solving all intersection points, a complete, accurate, orderly, and scalable intersection point input is provided for merging and verification. This systematically solves the problems of incomplete identification of intersecting figures, inaccurate intersection point positioning, and low computational efficiency in large-scale layouts, thereby improving the verification efficiency and reliability of the entire geometric figure merging and verification method.

[0012] In another possible implementation, verifying the correctness of the merging based on the comparison results of the first positional relationship and the second positional relationship includes: for each detection point, if the first positional relationship of the detection point is different from the second positional relationship of the detection point, determining that the merging is incorrect; for each detection point, if the first positional relationship of the detection point is the same as the second positional relationship of the detection point, determining that the merging is correct.

[0013] In the above implementation, this solution can associate the verification results with the meaning of the merged topology. By establishing a simple judgment rule that "if the positional relationship of the detection points before and after the merge is consistent, the merge is correct; if it is inconsistent, the merge is incorrect," it can not only capture various topological errors in the merging process, but also achieve the accuracy, diagnosability, and efficiency of the verification logic.

[0014] In another possible implementation, after determining the merging error for each detection point when the first positional relationship of the detection point differs from the second positional relationship of the detection point, the method further includes: determining reference information for each of one or more detection points, wherein the first positional relationship of each of the one or more detection points is inconsistent with the second positional relationship of the detection point, wherein the reference information for each detection point is used to indicate that the reference contour where the candidate point corresponding to the detection point is located is not correctly displayed in the actual layout, and the reference information for each detection point includes at least one of the following: an identifier for indicating the incorrectly displayed reference contour, the position of the detection point corresponding to the incorrectly displayed reference contour, and the position of the candidate point corresponding to the incorrectly displayed reference contour. The reference information is then output.

[0015] In the above implementation, based on the inconsistency in the positional relationship of the detection points before and after merging and the determination of merging errors, reference information corresponding to the erroneous detection points is further extracted and output. This reference information points to the location information of the reference contours that are not correctly displayed in the actual layout and the corresponding detection points or candidate points. In this way, merging errors can be transformed from abstract logical inconsistencies into specific, traceable, and semantic contour-level fault descriptions, which are provided to users or automation tools in a visual form. This enables rapid error location, improves the coordination between merging verification and backend geometric processing, and enhances the practicality of layout merging verification.

[0016] In another possible implementation, if any one of the plurality of reference contours includes only one vertex of the geometry corresponding to that reference contour, then the candidate point corresponding to that reference contour is that vertex. If any one of the plurality of reference contours is a line segment, then the candidate point corresponding to that reference contour is the midpoint of the line segment. If any one of the plurality of reference contours includes at least two vertices of the geometry corresponding to that reference contour, and the reference contour is not a line segment, then the candidate point corresponding to that reference contour is any one of the at least two vertices.

[0017] For example, the reference profile is a straight line segment or an arc segment.

[0018] In the above embodiments, for example, when the geometric figures simply intersect, the vertices of the geometric figures corresponding to the reference contour can be preferentially selected as candidate points. When the geometric figures share edges, the midpoints of the geometric figures corresponding to the reference contour can be selected as candidate points. In this way, the selection of candidate points can be deterministic, reducing the possibility that random points may fall into unreasonable areas or coincide with intersection points, leading to inaccurate verification results, thereby effectively improving the stability and feasibility of the verification method.

[0019] In yet another possible implementation, the merging method includes Boolean union operations.

[0020] In another possible implementation, the offsetting of each candidate point among the plurality of candidate points along at least one of a first direction and a second direction to obtain the offset set of multiple detection points includes at least one of a first method and a second method: the first method is to offset each candidate point among the plurality of candidate points along the first direction using a first offset value. The second method is to offset each candidate point among the plurality of candidate points along the second direction using a second offset value, wherein the first offset value and the second offset value are determined based on the minimum local feature size of the plurality of geometric shapes.

[0021] In the above implementation, by using the smallest local feature size of the geometric shape as a reference, first and second offset values ​​are determined along the inner and outer directions of the shape. Flexible execution modes are supported, allowing offsetting only along the first direction, only along the second direction, or both. This ensures that the generated set of detection points matches the layout's own process features in scale. In this way, while reducing floating-point noise misjudgments, merge boundary errors of the same order of magnitude as minimum linewidth and minimum spacing can be identified. Furthermore, no fixed offset constant needs to be manually set, and the system automatically adapts to different process nodes and mixed-scale layouts, improving the practicality and flexibility of the offset sampling process.

[0022] In another possible implementation, the first offset value is less than the minimum local feature size, so that the detection points inside the geometry where each candidate point is located do not exceed the boundary of the geometry; the second offset value is less than the minimum local feature size, so that the detection points outside the geometry where each candidate point is located, and corresponding to the candidate point, do not fall into the geometry adjacent to the geometry.

[0023] In the above implementation, the range constraint on the offset value can effectively reduce the situation where the inner point goes out of bounds or the outer point falls into another geometric shape due to the offset value being too large, and at the same time reduce the interference of floating point error due to the offset value being too small, thereby improving the accuracy and robustness of the verification results.

[0024] In another possible implementation, the design layout is an integrated circuit board layout, and the actual layout is the manufacturing data file of the integrated circuit board layout.

[0025] In another possible implementation, the first positional relationship and the second positional relationship are determined by the ray method or the number of turns method.

[0026] In the above embodiments, possible definitions were provided for determining the first positional relationship and the second positional relationship. For example, the ray method has high computational efficiency, and the wrap-around number method is more robust to non-convex and self-intersecting polygons. In this solution, the verification method can be flexibly selected according to actual application requirements, thereby improving the versatility and engineering applicability of the verification method.

[0027] In another possible implementation, the two geometric figures are the same, or the two geometric figures are different.

[0028] In the above embodiments, there is no limitation on whether any two geometric figures are the same, which has wide applicability.

[0029] In another possible implementation, one of the two geometric figures includes any one of the shape combinations, and the other geometric figure includes any one of the shape combinations, wherein the shape combinations include polygons, circles, ellipses, and figures resulting from combinations of different geometric figures.

[0030] In the above embodiments, there are no restrictions on the specific shapes of any two geometric figures (any two geometric figures can be the same, for example, both can be polygons, circles or ellipses, and any two geometric figures can also be different, for example, different figures among polygons, circles or ellipses, or combinations of different figures), which has wide applicability.

[0031] Secondly, embodiments of this application provide a verification device that can be applied to the electronic device of the first aspect. For example, the electronic device can be independent software, verification software integrated into EDA, a device (e.g., a chip, a chip system, or a circuit) in the verification software, or a device that can be used in conjunction with the verification software, or a logic module or software that can perform all or part of the verification functions.

[0032] In one possible implementation, the verification device may include modules or units that perform the methods / operations / steps / actions described in the first aspect. These modules or units may be hardware circuits, software, or a combination of hardware circuits and software.

[0033] Thirdly, embodiments of this application provide an electronic device including at least one processor and a communication interface; the communication interface is used for inputting and / or outputting information, and the at least one processor is used to call a computer program stored in at least one memory to implement the method described in any of the embodiments of the first aspect.

[0034] In one possible implementation, the electronic device further includes at least one of the aforementioned memories. Optionally, the memory and processor are integrated together.

[0035] Fourthly, embodiments of this application provide a computer-readable storage medium for storing instructions or computer programs; when the instructions or computer programs are executed, they implement the method of any of the embodiments of the first aspect.

[0036] Fifthly, this application provides a computer program product including computer instructions that, when executed on at least one processor, can implement the method described in any aspect or any possible implementation of the first aspect. Exemplarily, the computer program product can be a software installation package, which can be downloaded and executed on a computing device when the aforementioned method is required.

[0037] The beneficial effects of the technical solutions provided in the second to fifth aspects of this application can be referred to the beneficial effects of the technical solutions in the first aspect, and will not be repeated here. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application; Figure 2 A flowchart illustrating a verification method provided in an embodiment of this application; Figure 3 A schematic diagram illustrating any two geometric figures that intersect, as provided in an embodiment of this application; Figure 4 A schematic diagram of the intersection point between two intersecting geometric figures provided in this application embodiment; Figure 5 This is a schematic diagram of a detection point corresponding to a candidate point provided in an embodiment of this application; Figure 6 A schematic diagram illustrating the positional relationship between detection points in the design layout and the actual layout, provided for an embodiment of this application; Figure 7 A schematic diagram illustrating the positional relationship between a detection point in the design layout and the actual layout, as provided in an embodiment of this application; Figure 8 This is a schematic structural diagram of an electronic device provided in an embodiment of this application.

[0040] Explanation of reference numerals in the attached figures: 100 - Electronic device; 11 - Processor; 12 - Memory; 13 - Transceiver. Detailed Implementation

[0041] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings. In the description of the embodiments of this application, unless otherwise stated, " / " means "or," for example, A / B can mean A or B; the word "and / or" in the text is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Furthermore, in the description of the embodiments of this application, "multiple" refers to two or more than two.

[0042] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as implying or suggesting relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature, and in the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0043] In the fields of EDA and CAD, merging geometric shapes is a fundamental operation in layout data processing. Whether in IC layout design, PCB design, or MEMS and flat panel display device design, Boolean logic processing such as merging, trimming, or stitching polygons, line segments, and filled areas is involved to generate target graphic data that conforms to manufacturing rules.

[0044] For example, in the PCB design process, after designers complete the circuit layout and routing, they usually need to convert the design data into photoplot files or other standard format data to drive the manufacturing equipment used to produce the PCB for physical processing. A photoplot file is essentially a data-driven representation of the geometry in the PCB design layout. During this process, due to differences in data format conversion, graphic simplification, arc discretization, and the implementation of Boolean operation engines, discretization may occur between the geometry in the photoplot file and the original PCB design data.

[0045] Most solutions in related technologies focus on optimizing the geometric Boolean operation algorithms themselves, such as using scan-line algorithms, boundary representation methods, or extracting contours after pixelation filling, to improve computational speed or reduce memory usage. For example, taking the merging operation as an example, a filled image of the geometric shape is drawn, and then the contour of the filled image is extracted to obtain the merged outer contour point set. However, the solutions in related technologies mainly focus on how to solve the merging result, without providing a verification mechanism for whether the merging result is correct, thus failing to meet the verification requirements of the design layout.

[0046] Therefore, how to automatically and efficiently verify the consistency between the geometry in the photoplot file and the original design data after obtaining the photoplot file, improve verification efficiency and reliability, and enhance user experience is a hot topic that those skilled in the art are currently researching.

[0047] This application proposes a verification method for electronic devices. First, the electronic device can divide the detection interval based on multiple intersection points on the contours of any two geometric figures. On the contours of two intersecting geometric figures, multiple intersection points are used as dividing points, and the contour between adjacent intersection points is extracted as a reference contour segment. This division method covers potential topological change areas, especially boundary overlap areas, coincident areas, and areas near intersection points that are prone to errors in merging operations.

[0048] Secondly, the electronic device can associate candidate points with boundary paths. Candidate points are selected on each reference contour segment, and multiple sets of detection points are generated by offsetting them inward and outward directions of the geometry. This ensures that the detection points are distributed in locations where the contour of the graphic may change before and after merging, reducing invalid sampling.

[0049] Then, the electronic device can record the coordinate position relationship of the same detection point in the design layout before merging (e.g., two independent geometric shapes) and the actual layout after merging (e.g., a merged geometric shape). Since the position of the detection point in the physical coordinate system remains unchanged, only the graphic object it refers to may change. Therefore, by comparing whether the "internal or external" attributes of the detection point are consistent before and after merging, the correctness of the merging operation can be determined, thereby improving the efficiency and reliability of verification.

[0050] In summary, this application transforms the graphic merging verification problem into a consistency comparison problem of point position relationships. By combining intersection point segmentation sampling, bidirectional offset detection, and mapping rules for internal and external position relationships, it achieves high-precision, automated, and location-based verification of geometric graphic merging operations. This application can reduce the cost of layout verification, improve verification efficiency and reliability, and enhance the user experience.

[0051] In this application embodiment, the electronic device may be, but is not limited to, a mobile phone, tablet computer, handheld computer, desktop computer, laptop computer, ultra-mobile personal computer (UMPC), netbook, cellular phone, personal digital assistant (PDA), as well as smart home devices such as smart TVs and smart cameras, wearable devices such as smart bracelets, smartwatches, and smart glasses, extended reality (XR) devices such as augmented reality (AR), virtual reality (VR), and mixed reality (MR), in-vehicle devices, or smart city devices. This application embodiment does not impose any special restrictions on the specific type of electronic device.

[0052] The structure of the electronic device provided by the exemplary embodiments of this application will be described below.

[0053] It is understood that the structures illustrated in the embodiments of this application do not constitute a specific limitation on the electronic device 100. In other embodiments of this application, the electronic device 100 may include more or fewer components than illustrated, or combine some components, or split some components, or have different component arrangements. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

[0054] Figure 1 An exemplary schematic diagram of the structure of an electronic device 100 is shown.

[0055] like Figure 1As shown, the electronic device 100 may include hardware and software components. The hardware component may include a central processing unit (CPU), memory, and external devices, while the software component may include EDA software and verification software.

[0056] The following section, using the design layout verification process as an example, illustrates the working process of each module in the software portion of the electronic device 100. The design layout verification process can include a design layout merging stage and a design layout verification stage; the specific implementation process of these two stages is described below.

[0057] As one possible implementation, during the design layout merging stage, EDA software can respond to user input operations, receiving multiple geometric shapes from the design layout. For example, the user inputs multiple geometric shapes via an external device (e.g., a click operation via a mouse, keyboard, microphone, etc.), and performs a merging operation on these multiple geometric shapes. This involves identifying any two intersecting geometric shapes in the design layout, determining all intersection points between any two adjacent intersection points on the contours of each of the two geometric shapes, then using these intersection points as a reference, extracting the contours between adjacent intersection points as reference contours, selecting candidate points on each reference contour, and generating multiple sets of detection points by offsetting them inwards and outwards, ensuring that the detection points are distributed at locations where the contours of the shapes may change before and after merging. This yields the merged actual design layout, which can contain one or more geometric shapes. For example, if multiple geometric shapes include two geometric shapes, the merged actual design layout of the two geometric shapes is one geometric shape; if multiple geometric shapes include more than two geometric shapes, the merged actual design layout of the more than two geometric shapes is multiple geometric shapes.

[0058] As one possible implementation, during the design layout verification stage, the verification software can respond to the user's verification operation (e.g., the verification operation can be a double-click operation via mouse, keyboard, microphone, etc.), and compare the positional relationship of the actual design layout (i.e., the merged geometry) with the positional relationship of the original design layout (i.e., the geometry before merging) based on the verification algorithm, obtain the comparison result, and verify whether the merging is correct based on the comparison result.

[0059] Each module of the hardware part in the above electronic device 100 can be implemented in hardware, and each module of the software part in the electronic device 100 can be implemented in software or a combination of software and hardware. For example, the above EDA software and verification software can both be implemented in software, or the above EDA software and verification software can both be implemented in a combination of software and hardware.

[0060] In this embodiment, "implemented through software" means that the processor reads and executes program instructions stored in memory to implement the functions corresponding to the above-mentioned modules or units. The processor refers to a processing circuit capable of executing program instructions, including but not limited to at least one of the following: a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a microcontroller unit (MCU), or an artificial intelligence processor, etc., and other processing circuits capable of running program instructions. In other embodiments, the processor may also include circuits with other processing functions (such as hardware circuits for hardware acceleration, bus and interface circuits, etc.). The processor can be presented as an integrated chip, for example, as an integrated chip whose processing function only includes executing software instructions, or it can also be presented as a SoC (system on a chip), that is, on a single chip, in addition to the processing circuit capable of running program instructions (usually referred to as the "core"), it also includes other hardware circuits for implementing specific functions (of course, these hardware circuits can also be implemented separately based on ASIC or FPGA). Correspondingly, the processing functions, in addition to executing software instructions, may also include various hardware acceleration functions (such as AI calculation, encoding / decoding, compression / decompression, etc.).

[0061] In this embodiment, "implemented in hardware" means that the functions of the above-mentioned modules or units are implemented through hardware processing circuits that do not have program instruction processing capabilities. These hardware processing circuits can be composed of discrete hardware components or integrated circuits. To reduce power consumption and size, integrated circuits are typically used. The hardware processing circuits can include ASICs (application-specific integrated circuits) or PLDs (programmable logic devices); PLDs can include FPGAs (field-programmable gate arrays), CPLDs (complex programmable logic devices), and so on. These hardware processing circuits can be a single packaged semiconductor chip (e.g., packaged as an ASIC); or they can be integrated with other circuits (e.g., CPUs, DSPs) and packaged into a single semiconductor chip. For example, multiple hardware circuits and a CPU can be formed on a silicon substrate and packaged into a single chip; this type of chip is also called a SoC. Alternatively, circuits for implementing FPGA functions and a CPU can be formed on a silicon substrate and packaged into a single chip; this type of chip is also called a SoPC (system on a programmable chip).

[0062] It should be noted that when the embodiments of this application are implemented through software, hardware, or a combination of both, different software or hardware can be used, and it is not limited to using only one type of software or hardware. For example, one module or unit can be implemented using a CPU, while another module or unit can be implemented using a DSP. Similarly, when implemented using hardware, one module or unit can be implemented using an ASIC, while another module or unit can be implemented using an FPGA. Of course, it is not limited to using the same software (e.g., all through a CPU) or the same hardware (e.g., all through an ASIC) to implement some or all modules or units. Furthermore, those skilled in the art will understand that software is generally more flexible but less performant than hardware, while hardware is the opposite. Therefore, those skilled in the art can choose software, hardware, or a combination of both based on actual needs.

[0063] The following is combined with Figure 1The embodiments of this application are described in detail below. It is understood that this application uses an electronic device 100 as an example to illustrate the execution of the verification method, but this application does not limit the illustrated execution subject. For example, the method executed by the electronic device 100 in this application can also be implemented by modules in the electronic device 100 (such as verification software, circuits, chips, or chip systems), or by logic nodes, logic modules, or software capable of implementing all or part of the verification functions, or by circuits or chips (such as GPUs, AI processors, NPUs, or ASICs) in the electronic device 100 responsible for communication and / or computing functions.

[0064] Please see Figure 2 , Figure 2 This is a flowchart illustrating a verification method provided in an embodiment of this application. Optionally, this method can be applied to... Figure 1 The electronic device 100 shown.

[0065] like Figure 2 The method shown may include steps S201-S205. It should be understood that this application describes the steps in the order of S201-S205 for ease of description, and is not intended to limit the execution to this specific order. This application's embodiments do not limit the order of execution, the execution time, or the number of executions of one or more of the above steps. Steps S201-S205 are as follows: Step S201: Electronic device 100 determines multiple intersection points of any two geometric shapes that have an intersection relationship in the design layout.

[0066] As one possible scenario, the design layout is an integrated circuit board layout, while the actual layout is a manufacturing data file of the integrated circuit board layout.

[0067] For example, the integrated circuit board layout includes PCB layout and MEMS layout, and the manufacturing data file includes the photoplot file corresponding to the PCB layout and the actual physical layout corresponding to the MEMS layout.

[0068] As one possible scenario, multiple intersection points lie on the outline of each of any two geometric figures.

[0069] Alternatively, any two geometric figures can be identical, or any two geometric figures can be different.

[0070] For example, one of the two geometric figures includes any one of the shapes in a shape combination, and the other geometric figure includes any one of the shapes in a shape combination, including polygons, circles, ellipses, and shapes resulting from combinations of different geometric figures.

[0071] As one possible implementation, please see Figure 3, Figure 3 This is a schematic diagram of any two geometric figures that intersect, as provided in the embodiments of this application. Figure 3 As shown in (a), for example, when multiple geometric figures include only two geometric figures, taking the two geometric figures (e.g., geometric figure A and geometric figure B) as being the same, geometric figure A and geometric figure B can both be rectangles or triangles in polygons, or geometric figure A and geometric figure B can both be circles, or geometric figure A and geometric figure B can both be ellipses, etc.

[0072] like Figure 3 As shown in (b), for example, when multiple geometric figures include three geometric figures (e.g., geometric figure A, geometric figure B and geometric figure C), taking the example that any two geometric figures (e.g., geometric figure A and geometric figure B, geometric figure A and geometric figure C, geometric figure B and geometric figure C) are the same, geometric figure A, geometric figure B and geometric figure C can all be circles.

[0073] As another possible implementation, such as Figure 3 As shown in (c), for example, when multiple geometric figures include only two geometric figures, taking the two geometric figures (e.g., geometric figure A and geometric figure B) as different as possible, geometric figure A can be a rectangle in a polygon, and geometric figure B can be a triangle in a polygon.

[0074] like Figure 3 As shown in (d), for example, when multiple geometric figures include three geometric figures (e.g., geometric figure A, geometric figure B and geometric figure C), taking any two geometric figures (e.g., geometric figure A and geometric figure B, geometric figure A and geometric figure C, geometric figure B and geometric figure C) as different as an example, geometric figure A is a rectangle in a polygon, geometric figure B is a triangle in a polygon, and geometric figure C is a circle.

[0075] It should be noted that the above possible implementations are merely several possible examples provided for ease of understanding and should not be construed as limiting the embodiments of this application.

[0076] For ease of description, the embodiments of this application will be further described below using the case where only two geometric figures are included among multiple geometric figures. However, this should not be construed as a limitation of this application, and will not be repeated hereafter.

[0077] The following is an exemplary description of the process by which an electronic device 100 determines multiple intersection points of any two geometric shapes that have an intersection relationship in a design layout: As one possible implementation, the electronic device 100 traverses the contour of each geometric shape in a plurality of geometric shapes, calculates the intersection relationship between the contour of each geometric shape in the plurality of geometric shapes and the contour of each geometric shape in the plurality of geometric shapes other than the geometric shape, to determine any two geometric shapes, and determines all intersection points between the contour of one geometric shape and the contour of the other geometric shape in any two geometric shapes, so as to obtain multiple intersection points.

[0078] For example, please see Figure 4 , Figure 4 This is a schematic diagram of the intersection point between two intersecting geometric figures provided in an embodiment of this application, such as... Figure 4 As shown in (a), when geometric figures A and B have a simple intersection relationship and the same shape (e.g., both are rectangles in polygons), the intersection points between geometric figures A and B are 1 and 3, and intersection points 1 and 3 are both located on the outlines of geometric figures A and B.

[0079] Another example is, such as Figure 4 As shown in (b), when geometric figures A and B have a common edge and the same shape (e.g., both are rectangles in a polygon), the intersection points between geometric figures A and B are 1 and 2, and intersection points 1 and 2 are both located on the outlines of geometric figures A and B.

[0080] Another example is, such as Figure 4 As shown in (c), when geometric figures A and B have a simple intersection relationship and different shapes (for example, geometric figure A is a rectangle in a polygon and geometric figure B is a triangle in a polygon), the intersection points between geometric figures A and B are 1, 2, 3 and 4. Intersection points 1, 2, 3 and 4 are all located on the outlines of geometric figures A and B.

[0081] Step S202: Electronic device 100 determines multiple candidate points.

[0082] Among them, multiple candidate points correspond one-to-one with multiple reference contours. Each candidate point is any point on the corresponding reference contour. The multiple reference contours include the contour between any two adjacent intersection points on the contours of each of any two geometric figures.

[0083] The following examples illustrate several possible correspondences between candidate points and reference contours: Case 1: If any one of the multiple reference contours includes only one vertex of the geometry corresponding to that reference contour, then the candidate point corresponding to that reference contour is a single vertex.

[0084] For example, combined Figure 4 In (a), the intersection points between geometric figures A and B are 1 and 3. For geometric figure A, looking counter-clockwise, the contour between intersection points 1 and 3 includes a first contour (1-4-3) and a second contour (1-10-5-6-3). Therefore, candidate points for geometric figure A include any point on the first contour and any point on the second contour. When selecting, electronic device 100 may prefer to select any vertex in the first contour and any vertex in the second contour. For example... Figure 4 As shown in (a), the candidate point of the first contour of geometric figure A can be 4, and the candidate point of the second contour can be any vertex among 10, 5, and 6.

[0085] Optionally, the first and second contours can be determined by a pathfinding algorithm (which can be understood as, at a point of intersection, there are two directions along the contour that can be explored).

[0086] Another example is the combination of Figure 4 In (a), for geometric figure B, viewed counterclockwise, the contour between intersection point 1 and intersection point 3 includes the first contour (1-2-3) and the second contour (3-7-8-9-1). Therefore, candidate points for geometric figure B include any point on the first contour and any point on the second contour. When selecting, electronic device 100 may prefer to select any vertex in the first contour and any vertex in the second contour. Figure 4 As shown in (a), the candidate point of the first contour of geometric figure B can be 2, and the candidate point of the second contour can be any one of the vertices 7, 8, and 9.

[0087] Scenario 2: If any one of the multiple reference contours is a line segment, the candidate point corresponding to that reference contour is the midpoint of the line segment.

[0088] For example, the line segment can be a straight line segment or an arc segment.

[0089] For example, combined Figure 4 In (b), the intersection points between geometric figures A and B are 1 and 2. The reference contour includes the two vertices (1 and 2) of geometric figures A and B corresponding to the reference contour, i.e., intersection point 1 and intersection point 2. The contour between intersection point 1 and intersection point 2 includes a first contour (1-2) and a second contour (1-3-4-2), where the first contour is a straight line segment and the second contour is a polyline. Therefore, candidate points for geometric figures A or B include any point on the first contour and any point on the second contour. When making a selection, electronic device 100 may prefer to select the midpoint of the first contour and any vertex of the second contour. Figure 4As shown in (b), the candidate point of the first contour of geometric figure A or geometric figure B can be the midpoint of the line segment composed of 1 and 2, and the candidate point of the second contour can be any vertex of 3 and 4.

[0090] Case 3: If any one of the multiple reference contours includes at least two vertices of the geometry corresponding to the reference contour, and the reference contour is not a line segment, then the candidate point corresponding to the reference contour is any one of the at least two vertices.

[0091] For example, combined Figure 4 In (c), the intersection points between geometric figures A and B are 1, 2, 3, and 4. For geometric figure A, the contour between intersection point 1 and intersection point 2 includes the first contour (1-5-2), which is a polyline; the contour between intersection point 1 and intersection point 3 includes the second contour (1-3), which is a straight line segment; the contour between intersection point 3 and intersection point 4 includes the third contour (3-6-7-4), which is a polyline; and the contour between intersection point 4 and intersection point 2 includes the fourth contour (4-2), which is a straight line segment. Therefore, the candidate points for geometric figure A include any point on the first contour, any point on the second contour, any point on the third contour, and any point on the fourth contour. When selecting points, electronic device 100 may prefer to select any vertex in the first contour, the midpoint of the straight line segment formed by 1 and 3 in the second contour, any vertex in the third contour, and the midpoint of the straight line segment formed by 4 and 2 in the fourth contour. Figure 4 As shown in (c), the candidate point of the first contour of geometric figure A can be 5, the candidate point of the second contour can be the midpoint of the line segment formed by 1 and 3, the candidate point of the third contour can be any vertex between 6 and 7, and the candidate point of the fourth contour can be the midpoint of the line segment formed by 4 and 2.

[0092] Another example is the combination of Figure 4In (c), for geometric figure B, the contour between intersection point 1 and intersection point 2 includes the first contour (1-2), which is a straight line segment; the contour between intersection point 1 and intersection point 3 includes the second contour (1-8-10-3), which is a broken line; the contour between intersection point 3 and intersection point 4 includes the third contour (3-4), which is a straight line segment; and the contour between intersection point 4 and intersection point 2 includes the fourth contour (4-11-9-2), which is a broken line. Therefore, the candidate points for geometric figure B include any point on the first contour, any point on the second contour, any point on the third contour, and any point on the fourth contour. When selecting, electronic device 100 may prefer to select the midpoint of the straight line segment formed by 1 and 2 in the first contour, any vertex in the second contour, the midpoint of the straight line segment formed by 3 and 4 in the third contour, and any vertex in the fourth contour. Figure 4 As shown in (c), the candidate points of the first contour of geometric figure B can be the midpoint of the line segment formed by 1 and 2, the candidate points of the second contour can be any vertex between 8 and 10, the candidate points of the third contour can be the midpoint of the line segment formed by 3 and 4, and the candidate points of the fourth contour can be any vertex between 11 and 9.

[0093] Step S203: The electronic device 100 offsets each of the multiple candidate points along at least one of the first and second directions to obtain multiple sets of detection points after offset.

[0094] Among them, multiple sets of detection points correspond one-to-one with multiple candidate points. Each set of detection points includes at least one detection point. The at least one detection point is located within or outside the geometric figure where the candidate point corresponding to the at least one detection point is located in any two geometric figures.

[0095] For each candidate point, the first direction is towards the inside of the geometry where the candidate point is located, and the second direction is towards the outside of the geometry where the candidate point is located.

[0096] As one possible implementation, when at least one detection point is a single detection point, the detection point is located inside or outside the geometry of the candidate point corresponding to the set of detection points in which the detection point is located.

[0097] For example, please see Figure 5 , Figure 5 This is a schematic diagram of a detection point corresponding to a candidate point provided in an embodiment of this application, such as... Figure 5 As shown in (a) in the figure, combined with Figure 4In example (a), taking candidate points 4 and 6 of geometric figure A and candidate points 2 and 9 of geometric figure B as an example, if at least one detection point is a detection point, detection point 11 is located outside of geometric figure A where candidate point 4, corresponding to detection point 11, is located in geometric figure A; detection point 12 is located inside of geometric figure A where candidate point 6, corresponding to detection point 12, is located in geometric figure A; detection point 13 is located outside of geometric figure B where candidate point 2, corresponding to detection point 13, is located in geometric figure A; and detection point 14 is located inside of geometric figure B where candidate point 9, corresponding to detection point 14, is located in geometric figure A.

[0098] As another possible implementation, when at least one detection point is multiple detection points, the multiple detection points are located inside and outside the geometry of the candidate point corresponding to the set of multiple detection points in the two geometry.

[0099] For example, such as Figure 5 As shown in (b) in the figure, combined with Figure 4 In example (a), taking candidate points 4 and 6 of geometric figure A and candidate points 2 and 9 of geometric figure B as an example, if at least one detection point is two detection points, detection points a and b are located inside and outside of geometric figure A, where candidate point 4, corresponding to detection points a and b, is located, respectively; detection points c and d are located inside and outside of geometric figure A, where candidate point 6, corresponding to detection points c and d, is located, respectively; detection points e and f are located outside and inside of geometric figure B, where candidate point 2, corresponding to detection points e and f, is located, respectively; and detection points g and h are located inside and outside of geometric figure B, where candidate point 9, corresponding to detection points g and h, is located, respectively.

[0100] As one possible implementation, each candidate point among a plurality of candidate points is offset along at least one of a first direction and a second direction to obtain a plurality of sets of detection points after offset, including at least one of a first method and a second method: the first method is to offset each candidate point among a plurality of candidate points along a first direction using a first offset value, and the second method is to offset each candidate point among a plurality of candidate points along a second direction using a second offset value.

[0101] The first offset value and the second offset value are different, and the first offset value and the second offset value can be determined based on the minimum local feature size of multiple geometric figures.

[0102] Optionally, the first offset value is less than the minimum local feature size, so that the detection points inside the geometry where each candidate point is located do not exceed the boundary of the geometry; the second offset value is less than the minimum local feature size, so that the detection points outside the geometry where each candidate point is located, and corresponding to the candidate point, do not fall into the geometry adjacent to the geometry.

[0103] Alternatively, the first offset value and the second offset value can be the same.

[0104] Step S204: Electronic device 100 determines the first positional relationship of each detection point and the second positional relationship of each detection point.

[0105] The first positional relationship of each detection point indicates whether it is an internal or external detection point in the design layout, and the second positional relationship of each detection point indicates whether it is an internal or external detection point in the actual layout.

[0106] The actual layout includes the geometric shape formed by merging any two geometric shapes in the design layout; the positions of multiple sets of detection points in the actual layout are the same as the positions of multiple sets of detection points in the design layout.

[0107] In one possible implementation, for each detection point in the design layout, if the detection point is located within any two geometric shapes, the detection point is an internal detection point; if the detection point is located outside any two geometric shapes, the detection point is an external detection point.

[0108] It should be noted that the case where the detection point is located within any two geometric figures means that the detection point is located inside any one of the two geometric figures.

[0109] For example, please see Figure 6 , Figure 6 This is a schematic diagram illustrating the positional relationship between detection points in the design layout and the actual layout, as provided in an embodiment of this application. Figure 6 As shown in (a), for example, detection points a and b are located inside geometric figure B, which contains candidate points 4 corresponding to detection points a and b, respectively. That is, in the design layout, detection points a and b are both internal detection points.

[0110] For example, detection points c and d are located inside and outside geometric figure A, respectively, where candidate point 6, which corresponds to detection points c and d, is located. That is, in the design layout, detection point c is an internal detection point and detection point d is an external detection point.

[0111] For example, detection points e and f are located inside geometric figure A, which contains candidate point 2 corresponding to detection points e and f, respectively. In other words, in the design layout, detection points e and f are both internal detection points.

[0112] For example, detection points g and h are located inside and outside geometric figure B, respectively, where candidate point 9, which corresponds to detection points g and h, is located. That is, in the design layout, detection point g is an internal detection point and detection point h is an external detection point.

[0113] In one possible implementation, for each detection point in the actual layout, if the detection point is located within any geometric shape, the detection point is an internal detection point; if the detection point is not located within any geometric shape, the detection point is an external detection point.

[0114] For example, such as Figure 6 As shown in (b), for example, detection points a and b are located inside the merged geometry C, that is, in the actual layout, detection points a and b are both internal detection points.

[0115] For example, detection points c and d are located inside and outside the merged geometric figure C, respectively. That is, in the actual layout, detection point c is an internal detection point and detection point d is an external detection point.

[0116] For example, detection points e and f are located inside the merged geometry C, meaning that in the actual layout, detection points e and f are both internal detection points.

[0117] For example, detection points g and h are located inside and outside the merged geometric figure C, respectively. That is, in the actual layout, detection point g is an internal detection point and detection point h is an external detection point.

[0118] In one possible implementation, the first positional relationship and the second positional relationship are determined by ray casting.

[0119] Specifically, the ray method works as follows: draw a horizontal ray to the right from a detection point, and calculate the number of valid intersections between the detection point and the directed edge (without limiting the direction) of the geometric figure. If the number of valid intersections is odd, the detection point is an internal detection point; if the number of valid intersections is even, the detection point is an external detection point.

[0120] For example, combined Figure 6For example, in (a), taking detection point c as an example, if a horizontal ray is drawn to the right from detection point c, and the number of valid intersections between detection point c and the directed edge (without limiting the direction) of the geometric figure is calculated to be 1 (odd), then detection point c is an internal detection point. Similarly, taking detection point d as an example, if a horizontal ray is drawn to the right from detection point d, and the number of valid intersections between detection point d and the directed edge (without limiting the direction) of the geometric figure is calculated to be 0 (even), then detection point d is an external detection point.

[0121] In another possible implementation, the first positional relationship and the second positional relationship are determined by the wrap number method.

[0122] Specifically, the wrap count method works as follows: treat the edges of the geometric figure as directed edges (in vertex order), draw a horizontal ray to the right from a detection point, and each time an edge crosses this ray, if the edge crosses from bottom to top (from right to left in left-to-right view), the wrap count wn+1, and if the edge crosses from top to bottom, the wrap count wn-1; when wn≠0, it means that the detection point is an internal detection point; when wn=0, it means that the detection point is an external detection point.

[0123] For example, combined Figure 6 In example (a), taking detection point c as an example, if a horizontal ray is drawn to the right from detection point c, there exists a line segment (e.g., a straight line segment or an arc segment) composed of 4 and 6 that crosses the horizontal ray drawn from detection point c. Therefore, the wrapping number is 1. Since the wrapping number ≠ 0, detection point c is an internal detection point. As another example, taking detection point d as an example, if a horizontal ray is drawn to the right from detection point d, there is no edge that crosses the horizontal ray drawn from detection point d. Therefore, the wrapping number is -1. Since the wrapping number ≠ 0, detection point d is an external detection point.

[0124] Optionally, the merging methods include Boolean union, Boolean intersection, or Boolean difference operations.

[0125] Step S205: The electronic device 100 verifies whether the merging is correct based on the comparison results of the first position relationship and the second position relationship.

[0126] As one possible implementation, the electronic device 100 determines that the merging is correct for each detection point if the first positional relationship of the detection point is the same as the second positional relationship of the detection point.

[0127] For example, the case where the first positional relationship and the second positional relationship of the detection point are the same can be: the first positional relationship and the second positional relationship are such that the detection point is located inside any two geometric shapes before merging, and the detection point is located inside the geometric shape after merging. For example, combining Figure 6Taking detection point c as an example, detection point c is located inside both the original geometric figures A and B, and also inside the merged geometric figure C. Therefore, the first positional relationship is the same as the second positional relationship.

[0128] Another example is that the first positional relationship and the second positional relationship of the detection point are the same, which can also be: the first positional relationship and the second positional relationship are that the detection point is located outside any two geometric shapes before merging, and the detection point is located outside the geometric shape after merging. For example, combining Figure 6 Taking detection point d as an example, detection point d is located outside of geometric figures A and B before merging, and outside of geometric figure C after merging. Therefore, the first positional relationship is the same as the second positional relationship.

[0129] As another possible implementation, the electronic device 100 determines a merging error for each detection point if the first positional relationship of the detection point is different from the second positional relationship of the detection point.

[0130] For example, the first positional relationship and the second positional relationship of the detection point may differ as follows: the first positional relationship is that the detection point is located inside any two geometric shapes before merging, and the second positional relationship is that the detection point is located outside the merged geometric shape. For example, please see... Figure 7 , Figure 7 This is a schematic diagram illustrating the positional relationship between detection points in the design layout and the actual layout, as provided in another embodiment of this application. Figure 7 As shown in (a), taking detection point g as an example, detection point g is located inside the geometry B before merging, but Figure 7 In (b), the detection point g is located outside the merged geometry C. Therefore, the first positional relationship is different from the second positional relationship.

[0131] Another example is that the first positional relationship of the detection point is different from the second positional relationship, which can be: the first positional relationship is that the detection point is located outside any two geometric figures before merging, and the second positional relationship is that the detection point is located inside the geometric figures after merging.

[0132] Optionally, for each detection point, if the first positional relationship of the detection point is different from the second positional relationship of the detection point, after determining the merging error, the electronic device 100 can also determine the reference information of each detection point in one or more detection points and output the reference information.

[0133] In this scenario, the first positional relationship of each detection point among one or more detection points is inconsistent with its second positional relationship. The reference information for each detection point indicates that the reference contour of the candidate point corresponding to that detection point is not correctly displayed in the actual layout. For example, the reference contour of the candidate point corresponding to that detection point is shifted in the actual layout, or the reference contour of the candidate point corresponding to that detection point is not displayed in the actual layout.

[0134] The reference information for each detection point includes at least one of the following: an identifier for indicating a reference contour that is not displayed correctly, the location of the detection point corresponding to the reference contour that is not displayed correctly, and the location of the candidate point corresponding to the reference contour that is not displayed correctly.

[0135] For example, the identifier used to indicate a reference outline that is not displayed correctly can be a highlight identifier or other identifier that is easy to remind the user.

[0136] Optionally, the electronic device 100 may output reference information by highlighting it in the user interface (UI) or by outputting it to a log.

[0137] exist Figure 2 In the method shown, the electronic device first divides the detection interval based on multiple intersection points on the contours of any two geometric figures. On the contours of two intersecting geometric figures, multiple intersection points are used as dividing points to extract the contour between adjacent intersection points as a reference contour. This division method covers potential topological change areas, especially boundary overlap areas, coincident areas, and areas near intersection points that are prone to errors in merging operations.

[0138] Secondly, the electronic device associates candidate points with boundary paths. Candidate points are selected on each reference contour, and multiple sets of detection points are generated by offsetting them inward and outward directions of the geometry. This ensures that the detection points are distributed in locations where the contours of the graphics may change before and after merging, reducing invalid sampling.

[0139] Then, the electronic device records the coordinate position relationship of the same detection point in the design layout before merging (e.g., two independent geometric shapes) and the actual layout after merging (e.g., a merged geometric shape). Since the position of the detection point in the physical coordinate system remains unchanged, only the graphic object it refers to may change. Therefore, by comparing whether the "internal or external" attributes of the detection point are consistent before and after merging, the correctness of the merging operation can be determined, thereby improving the verification efficiency and reliability.

[0140] In summary, this application transforms the graphic merging verification problem into a consistency comparison problem of point position relationships. By combining intersection point segmentation sampling, bidirectional offset detection, and mapping rules for internal and external position relationships, it achieves high-precision, automated, and location-based verification of geometric graphic merging operations. This application can reduce the cost of layout verification, improve verification efficiency and reliability, and enhance the user experience.

[0141] The methods of the embodiments of this application have been described in detail above, and the apparatus of the embodiments of this application is provided below.

[0142] This application also proposes a verification apparatus. In some embodiments, the verification apparatus includes a module for performing the verification method of any of the above embodiments.

[0143] As some implementations, the verification device includes a first determining module, a second determining module, an offset module, a third determining module, and a verification module.

[0144] The first determining module is configured to: determine multiple intersection points of any two geometric figures that have an intersection relationship in the design layout, wherein the multiple intersection points are located on the outline of each of the two geometric figures.

[0145] The second determining module is configured to: determine multiple candidate points, wherein the multiple candidate points correspond one-to-one with multiple reference contours, each candidate point is any point of the corresponding reference contour, and the multiple reference contours include the contour between any two adjacent intersection points on the contours of each of any two geometric figures.

[0146] The offset module is configured to offset each of the plurality of candidate points along at least one of a first direction and a second direction to obtain multiple sets of offset detection points, wherein the multiple sets of detection points correspond one-to-one with the plurality of candidate points, and each set of detection points includes at least one detection point, wherein the at least one detection point is located within or outside the geometry of any two geometric figures where the candidate point corresponding to the at least one detection point is located; for each candidate point, the first direction is directed toward the geometry where the candidate point is located, and the second direction is directed toward the geometry where the candidate point is located.

[0147] The third determining module is configured to: determine the first positional relationship and the second positional relationship of each detection point. The first positional relationship of each detection point indicates whether the detection point is an internal or external detection point in the design layout, and the second positional relationship of each detection point indicates whether the detection point is an internal or external detection point in the actual layout. The actual layout includes the geometric shape formed by merging any two geometric shapes in the design layout. The positions of multiple sets of detection points in the actual layout are the same as the positions of multiple sets of detection points in the design layout. For each detection point in the design layout, if the detection point is located within any two geometric shapes, the detection point is an internal detection point; if the detection point is located outside any two geometric shapes, the detection point is an external detection point. For each detection point in the actual layout, if the detection point is located within any one of the geometric shapes, the detection point is an internal detection point; if the detection point is not located within any one of the geometric shapes, the detection point is an external detection point.

[0148] The verification module is configured to verify whether the merging is correct based on the comparison results of the first positional relationship and the second positional relationship.

[0149] In some embodiments, the verification apparatus may further include other modules to perform the verification method of any of the above embodiments.

[0150] Figure 8 This is a schematic structural diagram of the electronic device provided in this application. For example, such as Figure 8 As shown, the electronic device 100 includes a processor 11, which is coupled to a memory 12. The memory 12 is used to store computer programs or instructions and / or data. The processor 11 is used to execute the computer programs or instructions stored in the memory 12, or to read the data stored in the memory 12, in order to perform the methods in the above method embodiments.

[0151] Optionally, there may be one or more processors 11.

[0152] Optionally, the memory 12 may be one or more.

[0153] Alternatively, the memory 12 can be integrated with the processor 11, or it can be set separately.

[0154] Optionally, the electronic device 100 also includes a transceiver 13 for receiving and / or transmitting signals. For example, the processor 11 controls the transceiver 13 to receive and / or transmit data.

[0155] In addition, this application also provides a computer-readable storage medium storing computer instructions that, when executed on a computer, cause the methods in the various method embodiments of this application to be performed.

[0156] This application also provides a computer program product, which includes computer program code or instructions, such that when the computer program code or instructions are run on a computer, the methods in the various method embodiments of this application are executed.

[0157] Furthermore, this application also provides a chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory to perform the methods in the various method embodiments of this application.

[0158] Furthermore, the chip may also include a communication interface. The communication interface may be an input / output interface or an interface circuit, etc. Furthermore, the chip may also include a memory.

[0159] This application also provides a verification system, which includes the electronic device 100 described in the above embodiments. The electronic device 100 is used to perform some or all of the operations performed by the electronic device 100 in the above method embodiments.

[0160] It should be understood that the processor in the embodiments of this application can be an integrated circuit chip with the ability to process signals. In implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. A general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of this application can be directly implemented by a hardware encoding processor, or implemented by a combination of hardware and software modules in the encoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above method.

[0161] The memory in this application embodiment can be volatile memory or non-volatile memory, or it can include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), and synchronous link dynamic memory (SLDRAM).

[0162] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA, or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component, the memory can be integrated into the processor.

[0163] It should also be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0164] The above embodiments further illustrate the purpose, technical solution, and advantages of this application. It should be understood that the above descriptions are merely embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A verification method, characterized in that, include: Identify multiple intersection points of any two geometric figures that have an intersection relationship in the design layout, wherein the multiple intersection points are located on the outline of each of the two geometric figures; Multiple candidate points are determined, wherein each candidate point corresponds one-to-one with a multiple reference contour, and each candidate point is any point of the corresponding reference contour. The multiple reference contours include the contour between any two adjacent intersection points on the contour of each of the two geometric figures. Offset each of the plurality of candidate points along at least one of a first direction and a second direction to obtain multiple sets of detection points after offset, wherein each set of detection points corresponds one-to-one with the plurality of candidate points, and each set of detection points includes at least one detection point, wherein the at least one detection point is located either inside or outside the geometry containing the candidate point corresponding to the at least one detection point in any two geometry; for each candidate point, the first direction is directed towards the geometry containing the candidate point, and the second direction is directed towards the geometry containing the candidate point. A first positional relationship and a second positional relationship are determined for each detection point. The first positional relationship indicates whether the detection point is an internal or external detection point in the design layout, and the second positional relationship indicates whether the detection point is an internal or external detection point in the actual layout. The actual layout includes the geometric shape formed by merging any two geometric shapes in the design layout. The position of the multiple sets of detection points in the actual layout is the same as the position of the multiple sets of detection points in the design layout. For each detection point in the design layout, if the detection point is located within any two geometric shapes, it is an internal detection point; if the detection point is located outside any two geometric shapes, it is an external detection point. Similarly, for each detection point in the actual layout, if the detection point is located within any one of the geometric shapes, it is an internal detection point; if the detection point is not located within any one of the geometric shapes, it is an external detection point. Based on the comparison results of the first positional relationship and the second positional relationship, verify whether the merging is correct.

2. The method according to claim 1, characterized in that, The determination of multiple intersection points of any two geometric figures that have an intersection relationship in the design layout includes: Traverse the outline of each of the multiple geometric figures; Calculate the intersection relationship between the outline of each of the plurality of geometric figures and the outline of each of the plurality of geometric figures except the geometric figure itself, in order to determine any two geometric figures; Determine all intersection points between the outlines of one of the two geometric figures and the outline of the other geometric figure to obtain the plurality of intersection points.

3. The method according to claim 1, characterized in that, The step of verifying the correctness of the merging based on the comparison results of the first positional relationship and the second positional relationship includes: For each detection point, if the first positional relationship of the detection point is different from the second positional relationship of the detection point, the merging is determined to be incorrect; if the first positional relationship of the detection point is the same as the second positional relationship of the detection point, the merging is determined to be correct.

4. The method according to claim 3, characterized in that, After determining the merging error for each detection point when the first positional relationship of the detection point differs from the second positional relationship of the detection point, the method further includes: Determine reference information for each of one or more detection points, wherein a first positional relationship of each detection point is inconsistent with a second positional relationship of the detection point, wherein the reference information for each detection point is used to indicate that the reference contour where the candidate point corresponding to the detection point is located is not correctly displayed in the actual layout, and the reference information for each detection point includes at least one of the following: an identifier for indicating the incorrectly displayed reference contour, the position of the detection point corresponding to the incorrectly displayed reference contour, and the position of the candidate point corresponding to the incorrectly displayed reference contour; Output the reference information.

5. The method according to any one of claims 1-4, characterized in that, If any one of the plurality of reference contours includes only one vertex of the geometry corresponding to the reference contour, then the candidate point corresponding to the reference contour is the vertex. If any one of the plurality of reference contours is a line segment, the candidate point corresponding to that reference contour is the midpoint of the line segment. If any one of the plurality of reference contours includes at least two vertices of the geometry corresponding to the reference contour, and the reference contour is not a line segment, then the candidate point corresponding to the reference contour is any one of the at least two vertices.

6. The method according to any one of claims 1-4, characterized in that, The merging method includes Boolean union operations.

7. The method according to any one of claims 1-4, characterized in that, The process involves offsetting each candidate point among the plurality of candidate points along at least one of a first direction and a second direction to obtain a set of multiple sets of detection points after offsetting, including at least one of the first and second methods: The first method involves offsetting each of the plurality of candidate points along the first direction using a first offset value; The second method involves offsetting each of the plurality of candidate points along the second direction using a second offset value, wherein the first offset value and the second offset value are determined based on the minimum local feature size of the plurality of geometric figures.

8. The method according to claim 7, characterized in that, The first offset value is less than the minimum local feature size, so that the detection points inside the geometry where each candidate point is located do not exceed the boundary of the geometry; the second offset value is less than the minimum local feature size, so that the detection points outside the geometry where each candidate point is located, and corresponding to the candidate point, do not fall into the geometry adjacent to the geometry.

9. The method according to any one of claims 1-4, characterized in that, The design layout is an integrated circuit board layout, and the actual layout is the manufacturing data file of the integrated circuit board layout.

10. The method according to any one of claims 1-4, characterized in that, The first positional relationship and the second positional relationship are determined by the ray method or the number of turns method.

11. The method according to any one of claims 1-4, characterized in that, The two geometric figures are the same, or the two geometric figures are different.

12. The method according to claim 11, characterized in that, One of the two geometric figures includes any one of the shape combinations, and the other geometric figure includes any one of the shape combinations. The shape combinations include polygons, circles, ellipses, and figures resulting from combinations of different geometric figures.

13. An electronic device, characterized in that, The electronic device includes a processor; When the processor executes instructions, it causes the electronic device to implement the method as described in any one of claims 1-12.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store instructions or computer programs that, when executed, cause the method as described in any one of claims 1-12 to be performed or implemented.

15. A computer program product, characterized in that, include: Instructions or computer programs; When the instructions or the computer program are executed, the method as described in any one of claims 1-12 is performed or implemented.

Images