A method for integrated circuit layout design physical verification and rule checking

Abstract

The present application belongs to the technical field of integrated circuit design automation, and relates to a kind of integrated circuit layout design physical verification and rule checking method.The present application writes node attribute field by allocating electrical node name, generates module level and physical coordinate mapping index by parsing layout level tree;According to the index, execute hierarchical netlist extraction, compare the top interconnection netlist with the reference netlist to preliminarily screen abnormal modules;For abnormal modules, perform topological consistency comparison and output difference node list, and finally retrieve attribute field with node name to obtain graphic layer attribute and grid point coordinate.The method solves the problem of existing global flattening mode, which causes memory occupation to increase sharply, low spatial locality utilization, high redundancy of overall comparison without distinction, and error positioning and layout disconnection.The effect of reducing analysis memory peak, improving extraction flow efficiency, reducing comparison search range, and automatically tracing to physical coordinates to improve error correction closed loop response speed is achieved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design automation technology, and relates to a method for physical verification and rule checking of integrated circuit layout design. Background Technology

[0002] Before chip manufacturing and tape-out, physical verification and rule checking of integrated circuit layout design are crucial steps to ensure the correctness of chip functionality. Among these, comparing the connection relationships of the actual geometric shapes on the layout with the design schematic is the core task of verification. Existing physical verification and rule checking methods for integrated circuit layout design mostly adopt a global flattening approach, which involves directly performing a one-time overall analysis of the entire chip's layout data, extracting the global connection network, and then comparing it with the design source file. This process has the following specific problems in practical applications: First, the number of geometric shapes in the layout of very large-scale integrated circuits can reach tens of billions. A one-time overall analysis and extraction operation significantly increases memory usage and processing time, thus affecting the overall efficiency of the verification process.

[0003] Second, the global flattening mode disrupts the original spatial combination relationship of the layout data, and the memory scheduling strategy fails to make full use of the physical layout structure of the layout entities, resulting in low spatial locality utilization of computing resources.

[0004] Third, existing methods perform an overall comparison of all extracted connection relationships with the design source files without any difference. When there are connection differences in local areas, the comparison engine still needs to search and verify within the entire data range, resulting in high redundancy in comparison calculations.

[0005] Fourth, after identifying the connection differences, it is found that the abstract logical identifiers output by the verification system are disconnected from the specific layers and spatial orientations of the actual layout geometry. Designers need to manually search the layout database a second time to determine the error location, which results in a long error localization cycle and reduces the closed-loop response speed of physical verification and rule checking of integrated circuit layout design. Summary of the Invention

[0006] In view of this, in order to solve the problems mentioned in the background technology, a physical verification and rule checking method for integrated circuit layout design is proposed.

[0007] The objective of this invention can be achieved through the following technical solution: a method for physical verification and rule checking of integrated circuit layout design, comprising: S1, in the layout editing environment, assigning electrical node names according to the electrical connectivity of polygonal geometry and writing them into their node attribute fields.

[0008] S2. Based on GDS data, the unit hierarchy structure parsing layer-level tree identifies the physical bounding boxes of standard units, macro modules, and IP cores, and generates a mapping index between module hierarchy and physical coordinates.

[0009] S3. Perform hierarchical netlist extraction on each module based on the mapping index to generate a module-level netlist and a top-level interconnect netlist. The module-level netlist contains the internal device connection relationships of the module, and the top-level interconnect netlist contains the port connection relationships between modules. Compare the top-level interconnect netlist with the circuit schematic reference netlist to identify abnormal modules with connection differences.

[0010] S4. For abnormal modules, perform a topology consistency comparison based on module port constraints only between the module-level netlist of the abnormal module and the corresponding sub-module netlist in the reference netlist, and output a list of differing nodes.

[0011] S5. Using the name of the electrical node in the difference node list as the search key, query the node attribute field to obtain the layer attributes and grid coordinates of the polygon geometry that has the node attribute field.

[0012] Compared with the prior art, the beneficial effects of the present invention are as follows: (1) The present invention analyzes the layout layer hierarchy tree based on the unit hierarchy structure of GDS data, identifies the physical bounding boxes of standard units, macro modules and IP cores, and performs layered netlist extraction accordingly, avoiding the need to directly perform a one-time overall analysis and extraction of all polygonal geometric figures. This method solves the problem of memory consumption surge and processing time being too long due to the large number of layout geometric figures in VLSI, effectively reducing the memory peak of a single analysis, thereby improving the flow efficiency of layout data extraction.

[0013] (2) This invention generates a mapping index between module hierarchy and physical coordinates, and uses this mapping index to locate the physical bounding box of each module to extract the internal polygonal geometry, thus establishing a modular spatial layout structure. This method solves the problems of the original global flattening mode destroying the spatial combination relationship of the layout data and the memory scheduling strategy failing to utilize the physical layout structure, enabling the memory scheduling strategy to perform localized data loading according to the physical bounding box, thereby improving the spatial locality utilization rate of computing resources.

[0014] (3) This invention identifies abnormal modules by comparing the top-level interconnection netlist with the reference netlist, and performs topology consistency comparison based on module port constraints only on the module-level netlist of the abnormal module and the corresponding sub-module netlist. This method solves the problem in existing methods where the comparison engine searches and verifies the entire data range due to connection differences in local areas when performing an indiscriminate overall comparison of all connection relationships with the design source file. This reduces the search range and data volume of the comparison, and lowers the redundancy of the comparison calculation.

[0015] (4) This invention obtains the layer attributes and grid coordinates of polygonal geometric figures with the specified node attribute field by querying the node attribute field using the name of the electrical node in the difference node list as the search key. This method solves the problem of the disconnect between the abstract logical identifier output by the verification system and the specific layer and spatial orientation of the actual layout geometry, avoids the need for designers to manually search the layout database to determine the error location, and improves the closed-loop response speed of physical verification. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart of a physical verification and rule checking method for integrated circuit layout design in this invention;

[0018] Figure 2 This is a flowchart of the module-level netlist generation method in this invention;

[0019] Figure 3 This is a flowchart of step S4 in this invention;

[0020] Figure 4 This is a comparison chart of memory peak values ​​for the present invention;

[0021] Figure 5 This is a graph showing the relationship between the number of objects extracted and the comparison time in this invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0024] The specific scheme of the physical verification and rule checking method for integrated circuit layout design provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0025] Please see Figure 1As shown, the implementation of the present invention includes S1 to S5: In response to the technical problems of low efficiency in anomaly location and difficulty in error tracing caused by the large layout size and complex hierarchical structure in the physical verification of integrated circuit layout design, the present invention provides a verification method from geometric figures to electrical nodes, from global netlists to local differences, and finally back to graphic coordinates.

[0026] First, electrical node names are assigned and written based on electrical connectivity on the bottom-level polygonal geometry of the map, completing the electrical labeling of the physical geometry. Simultaneously, the cell hierarchy tree of the GDS data is parsed to construct a mapping index between module levels and physical coordinates. Guided by this mapping index, hierarchical netlist extraction is performed, transforming the physical geometry data into module-level netlists and top-level interconnection netlists. Subsequently, abnormal modules are initially screened by comparing the top-level interconnection netlist with a reference netlist, and a topology consistency comparison based on module port constraints is performed on the abnormal modules to output a list of differing nodes. Finally, using the electrical node names in the differing node list as search keys, the previously established node attribute fields are queried in reverse order, directly tracing back to the layer attributes and grid coordinates of the bottom-level polygonal geometry.

[0027] This technical solution starts from the underlying graphic electrical markers and hierarchical coordinate mapping, and through netlist extraction, anomaly screening and topology difference depth comparison, it finally traces the difference nodes back to the physical map coordinates and automatically highlights them, thus opening up the data closed loop from logical verification to physical location, improving the error-checking efficiency and coordinate positioning accuracy of map verification.

[0028] S1. In the layout editing environment, assign electrical node names based on the electrical connectivity of the polygon geometry and write them into its node attribute field.

[0029] Considering that there are electrical connections between polygonal geometries on the conductive layer in the integrated circuit layout due to geometric intersections, inclusions, or vias, and that the layout data itself only records the layer affiliation and vertex coordinates of each polygonal geometries and does not directly represent their electrical connection status, if a mapping between electrical nodes and geometries is not established, subsequent netlist extraction, connection comparison, and difference localization cannot be performed using electrical nodes as indexes, resulting in the physical verification process lacking a traceable electrical identification basis.

[0030] Therefore, this step involves traversing the polygonal geometry in the layout data layer by layer, filtering out conductive layer graphics based on the set of conductive layer identifiers in the process document, identifying the electrical connectivity between graphics based on edge intersection and inclusion determination, and using a depth-first search algorithm to merge connected graphics into the same node group and assign a unique electrical node name to each group and write it into the node attribute field, thereby providing a data foundation for subsequent steps to retrieve geometry by electrical node name.

[0031] In one specific embodiment, within the layout editing environment, the polygonal geometries in the layout data are traversed layer by layer. The layer identifier of each polygonal geometries is read, and the character sequence of the layer identifier is compared item by item with the character sequence of each element in the conductive layer identifier set in the process file. If the two character sequences are completely identical, it is determined that the layer identifier exists in the conductive layer identifier set, and the polygonal geometries are marked as conductive layer geometries; otherwise, the polygonal geometries are skipped. The process file is a technical configuration file that records the identifiers, conductive properties, and electrical connectivity rules of each mask layer in the integrated circuit manufacturing process, and it contains at least a conductive layer identifier set and a via layer identifier set.

[0032] Subsequently, for all polygonal geometric figures marked as conductive layer graphics, the endpoint coordinates of each edge of each polygonal geometric figure are extracted. Any two polygonal geometric figures under the same layer identifier are taken as the first figure and the second figure, respectively. The intersection points of each edge of the first figure and each edge of the second figure are calculated. If there is an intersection point, the first figure and the second figure are determined to intersect and are marked as having an electrical connection. If there is no intersection point, the coordinates of all vertices of the second figure are substituted into the boundary equation of the first figure. If all vertices of the second figure are located inside the first figure, the first figure is determined to completely contain the second figure and are marked as having an electrical connection.

[0033] For conductive layer graphics belonging to different layer identifiers, read the through hole graphics on the layer corresponding to the through hole layer identifier in the process file, calculate the intersection area of ​​the through hole graphics and the first layer conductive layer graphics, and the intersection area of ​​the through hole graphics and the second layer conductive layer graphics. If both intersection areas are greater than zero, it is determined that the first layer conductive layer graphics and the second layer conductive layer graphics are connected across layers, and the two are marked as having an electrical connection relationship.

[0034] Furthermore, all polygonal geometric figures marked with electrical connectivity are used as vertices of the graph, and electrical connectivity is used as edges of the graph to construct an undirected graph. The undirected graph is traversed using a depth-first search algorithm. All vertices connected by edges during the traversal are merged into the same set as the same group, and vertices without edge connections are divided into different groups.

[0035] Finally, electrical node names are assigned to each group in the order they were created. Each electrical node name is prefixed with the letter N followed by an integer number starting from 1, ensuring the uniqueness of each name in the netlist and meeting the naming requirements for expanding the number of nodes in large-scale integrated circuits. This electrical node name is then written into the node attribute field of each polygon geometry within the corresponding group. This node attribute field represents the mapping relationship between the electrical node name and the polygon geometry, and is used in subsequent differential node localization steps to look up the corresponding geometry using the electrical node name as the search key.

[0036] Simultaneously, all electrical node names belonging to the same electrical connectivity group and connected by metal interconnect graphics are merged into the same electrical network, a network name is assigned to the electrical network, and the network name is written into the attribute field of each polygon geometry in the corresponding group. This attribute field is different from the node attribute field and is used to store the network identifier.

[0037] S2. Based on GDS data, the unit hierarchy structure parsing layer-level tree identifies the physical bounding boxes of standard units, macro modules, and IP cores, and generates a mapping index between module hierarchy and physical coordinates.

[0038] Given that integrated circuit layouts adopt a hierarchical design approach, GDS data expresses a multi-level hierarchy from the top-level chip to the bottom-level standard unit through the nested calling relationship of structural units. However, the geometric shapes in the layout are scattered within each level of structural units, lacking a unified description of module boundaries and coordinate space. If the hierarchical calling relationship is not parsed and the physical boundary box and coordinate information of each module are not extracted, it is impossible to divide the scope of the geometric shapes according to the module. Subsequent hierarchical netlist extraction will be unable to locate the graphic data within each module due to the lack of module space index.

[0039] Therefore, this step recursively constructs a layer-level tree by reading the structural unit definitions and SREF call records in the GDS data. Based on the node attributes and sub-unit instance information, the structural units are labeled as standard units, macro modules, and IP cores. The bounding rectangles of all polygonal geometric figures within each module are calculated as physical bounding boxes, and the module level names and physical coordinates are combined into a mapping index.

[0040] In one specific embodiment, the structural unit definition and unit call record in the GDS data are read, the structural unit in the GDS data that is not called by any other structural unit is located as the top-level structural unit, the top-level structural unit is taken as the root node, the names of the lower-level structural units referenced by the SREF record in the root node and the coordinate transformation parameters are read, each lower-level structural unit is attached as a child unit instance under the root node, and the root node is marked as the parent node.

[0041] Subsequently, the above operation of reading SREF records is repeated for each sub-unit instance, and the process is recursively expanded layer by layer according to the nesting depth of the call relationship. The recursion is terminated when the sub-unit instance does not contain SREF records. In this way, a tree data structure is constructed with the root node as the starting point and the structural unit without SREF records as the ending point as the page layer-level tree.

[0042] In the page-level tree, structural unit nodes that do not contain sub-unit instances are marked as leaf nodes, and structural unit nodes that contain sub-unit instances are marked as non-leaf nodes; read the ATTRIB attribute field of each structural unit in the GDS data, and mark structural units that contain the string "LIB" in the ATTRIB attribute field as units carrying library identifier attributes.

[0043] In the layout hierarchy tree, leaf nodes that do not contain sub-unit instances are labeled as standard units, non-leaf nodes that contain sub-unit instances are labeled as macro modules, and units carrying library identifier attributes are labeled as IP cores. Standard units are indivisible basic logical units, macro modules are combined functional modules containing sub-unit instances, and IP cores are pre-verified reusable modules carrying library identifiers.

[0044] Read the vertex coordinates of all polygonal geometric figures in the standard unit, macro module, and IP core. Traverse all vertex coordinates to extract the minimum and maximum values ​​in the X-axis direction and the Y-axis direction. Use the minimum value in the X-axis and the minimum value in the Y-axis to form the lower left vertex, and use the maximum value in the X-axis and the maximum value in the Y-axis to form the upper right vertex. Construct an outer rectangle from the lower left and upper right vertices, and use this outer rectangle as the physical bounding box.

[0045] Extract the coordinates of the lower left and upper right vertices of the physical bounding box as physical coordinates. Combine the physical coordinates with the corresponding standard unit, macro module, and IP core module level names in the layout layer hierarchy tree to form a key-value pair structure, where the module level name is the key and the physical coordinates are the value, to generate a mapping index between module level and physical coordinates.

[0046] Before performing hierarchical netlist extraction, the physical bounding boxes of each module are located based on the mapping index. The polygonal geometries located on the active region layer, gate layer, and contact hole layer within the physical bounding box are combined and determined according to their relative positional relationships: the active region pattern combined with the gate pattern that crosses the active region pattern is identified as a transistor device; the area on the active region pattern that covers the contact hole pattern is extracted as the source or drain pin of the transistor; the gate extension portion outside the overlapping area of ​​the gate pattern and the active region pattern is extracted as the gate pin; the combination of the well region pattern and the injection layer pattern is identified as a resistor or capacitor device, and its end connection area is extracted as the device pin; a unique device identifier is assigned to each identified device.

[0047] like Figure 4 As shown, for a map size of 1 million to 100 million graphics, the peak memory usage of the hierarchical extraction method of this invention is significantly lower than that of existing global flattening methods, with a reduction of approximately 6.3 times at a map size of 100 million graphics. This result verifies that the strategy of constructing a mapping index based on the GDS unit hierarchy tree and performing localized data loading according to the physical bounding box can effectively alleviate the problem of soaring memory usage caused by the global flattening mode.

[0048] S3. Perform hierarchical netlist extraction on each module based on the mapping index to generate a module-level netlist and a top-level interconnect netlist. The module-level netlist contains the internal device connection relationships of the module, and the top-level interconnect netlist contains the port connection relationships between modules. Compare the top-level interconnect netlist with the circuit schematic reference netlist to identify abnormal modules with connection differences.

[0049] Considering that the core objective of physical layout verification is to detect the connection differences between the layout implementation and the circuit design, and that layout data only contains the layers and coordinate information of geometric figures and does not directly express the electrical connection topology between devices, if the overlapping, adjacency and cross-layer connectivity relationships between geometric figures are not converted into a connection description in the form of a netlist, it is impossible to perform a structured comparison with the circuit schematic reference netlist. Furthermore, the interconnection relationships between modules cross physical boundary boxes, and port connections need to be extracted independently to form a complete netlist.

[0050] Therefore, this step filters the internal graphics according to the mapping index by the module boundary box, extracts the connection relationship of the internal components of the module by calculating the intersection area and determining the shortest distance, generates a module-level netlist, extracts the intersection relationship between the metal connection lines crossing the boundary box and the ports, generates a top-level interconnect netlist, and compares the top-level interconnect netlist with the reference netlist by network name and port connection path strings to identify abnormal modules.

[0051] In one specific embodiment, please refer to Figure 2 As shown, the steps of the module-level netlist generation method are as follows: S201, locate the physical bounding box of each module according to the physical coordinates in the mapping index, read the coordinates of the lower left and upper right vertices of the physical bounding box, traverse the vertex coordinates of all polygonal geometric figures in the layout data, determine the interval between the X-axis component of each vertex coordinate and the X-axis coordinates of the lower left and upper right vertices of the physical bounding box, determine the interval between the Y-axis component and the Y-axis coordinates of the lower left and upper right vertices of the physical bounding box, and determine the interval between the Y-axis component and the Y-axis coordinates of the lower left and upper right vertices of the physical bounding box. If all vertices of the polygonal geometric figure are located within the coordinate interval of the physical bounding box, then mark the polygonal geometric figure as a netlist extraction object.

[0052] S202. For any two netlist extraction objects belonging to the same layer identifier within the same module, calculate the intersection polygon using a polygon clipping algorithm, and then calculate the area of ​​the intersection polygon using the Gaussian area formula, as follows: .

[0053] in, The first one is arranged in counterclockwise or clockwise order for the intersection polygons. The coordinates of the vertices, The total number of vertices of the intersecting polygon. If the area... If the two overlap, then it is determined that they overlap.

[0054] S203. For two netlist extraction objects that belong to the same layer identifier and have an intersection area of ​​zero within the same module, calculate the shortest distance between each edge of the first netlist extraction object and each edge of the second netlist extraction object. Take the minimum value among all the shortest distances as the shortest distance between their boundary lines. If the shortest distance is equal to zero, then the two are determined to be adjacent.

[0055] S204. For netlist extraction objects belonging to different layer identifiers within the same module, read the through hole pattern on the layer corresponding to the through hole layer identifier in the process file, calculate the intersection area between the through hole pattern and the first layer netlist extraction object, and the intersection area between the through hole pattern and the second layer netlist extraction object. If both intersection areas are greater than zero, it is determined that the first layer netlist extraction object and the second layer netlist extraction object are connected across layers.

[0056] S205. Organize the connection relationships between netlist extraction objects that overlap, are adjacent, or have cross-layer connectivity into module-level device connection relationships, generating a module-level netlist. This module-level netlist represents the electrical connection topology between the pins of devices within each module, and is used for comparison with the corresponding sub-modules in the reference netlist.

[0057] Since the module-level netlist only describes the internal device connections within a module, and signal transmission between modules at the top level of the layout depends on interconnects that cross the physical boundary of the modules, it is necessary to further extract the port connectivity between modules to form a complete layout netlist. The generation method of the top-level interconnect netlist is as follows: Traverse the physical boundary of standard cells, macro modules, and IP cores in the layout layer hierarchy tree. Mark the polygonal geometry located on the metal interconnect layer with vertex coordinates crossing the physical boundary as metal interconnect geometry. Mark the polygonal geometry located on the port layer with vertex coordinates on the edge of the physical boundary as port geometry. Use a polygon clipping algorithm to calculate the intersection polygon of the metal interconnect geometry and the port geometry. Calculate the area of ​​the intersection polygon using the Gaussian area formula. If the area is greater than zero, it is determined that the metal interconnect geometry and the port geometry intersect.

[0058] The network names stored in the attribute fields of intersecting metal interconnection patterns are extracted, and the port names stored in the attribute fields of intersecting port patterns are read. The mapping relationship between port names and network names is used as the port connection relationship between modules, and a top-level interconnection table is generated. This top-level interconnection table represents the attribution correspondence between each module port and the top-level network signal, and is used for top-level connection comparison. The mapping relationship indicates the top-level network signal name corresponding to each port name, meaning that all ports under the same network name are electrically interconnected.

[0059] Since the top-level interconnect netlist and the schematic reference netlist are extracted independently from the layout data and circuit design data, respectively, the connection differences between the two are the characteristics of the layout implementation deviating from the circuit design. Therefore, it is necessary to identify abnormal modules by comparison, as follows: Read the network lists in the top-level interconnect netlist and the schematic reference netlist, extract the port connection path strings of the network with the same name from the top-level interconnect netlist and the schematic reference netlist using the network name as the matching key, and compare the port connection path strings of the two one by one according to the character position. If there is a character inconsistency at the corresponding position, the module to which the network name belongs is marked as an abnormal module.

[0060] S4. For abnormal modules, perform a topology consistency comparison based on module port constraints only between the module-level netlist of the abnormal module and the corresponding sub-module netlist in the reference netlist, and output a list of differing nodes.

[0061] If an abnormal module is identified by comparing the port connection path strings between the top-level interconnection netlist and the reference netlist, but the connection topology differences between the devices inside the module have not been refined to the specific electrical nodes, and if the topology structure inside the abnormal module is not further compared position by position, the difference location will remain at the module level and will not be able to indicate the specific defect node, resulting in the inability to accurately locate the physical error location in the layout.

[0062] Therefore, this step starts with the port pin of the abnormal module, traverses the device path along the connection edge in the module-level netlist and the sub-module netlist respectively, and records the device identification sequence. The two device identification sequences are compared position by position, and the electrical nodes corresponding to the inconsistent positions are recorded as difference nodes and summarized into a difference node list.

[0063] In one specific embodiment, please refer to Figure 3 As shown, step S4 is as follows: S301, read the port name of each port pin and the list of device pin identifiers connected to it from the module-level netlist of the abnormal module. At the same time, read the list of device pin identifiers connected to the same port name from the sub-module netlist with the same name as the abnormal module in the circuit schematic reference netlist. Use the above two lists of device pin identifiers as module port constraints to limit the target device pins connected to the port inside the module, and use them as the starting positioning basis for topology comparison.

[0064] S302. In the module-level netlist, starting from the port pin, read the pin identifier of the first device connected to the port pin, jump along the connection edge in the module-level netlist to the next device connected to the pin identifier, record the device identifier of the device, continue to read the next connected device pin identifier along the connection edge and jump, until another port pin is reached or there is no subsequent connection edge, arrange all the device identifiers recorded in the traversal process according to the traversal order to form a device identifier sequence, which is the module-level topology.

[0065] S303. In the submodule netlist, starting from the pin with the same name, jump sequentially to the connected device along the connection edge in the submodule netlist, and record the device identification sequence on the traversal path as a reference topology.

[0066] S304. According to the traversal order, compare the device identifier sequence in the module-level topology with that in the reference topology position by position. If the device identifiers at the same position are inconsistent, it means that the actual device at that position in the layout implementation does not match the expected device in the schematic design. Then, the electrical node corresponding to the device identifier at that position is recorded as a difference node.

[0067] If the number of device identifiers in the module-level topology is inconsistent with the number of device identifiers in the reference topology, it indicates that there are redundant or missing devices in the device connection paths in the layout implementation compared to the schematic design. In this case, the electrical nodes corresponding to the device identifiers at the extra locations are recorded as difference nodes, and all difference nodes are summarized to form a difference node list.

[0068] like Figure 5 As shown, the statistical results of topology comparison time for samples of three types of modules—standard units, macro modules, and IP cores—show a positive correlation between the number of objects extracted from the netlist within a module and the topology comparison time. Specifically, standard units have a lower comparison time due to the smaller number of extracted objects; macro modules have a lower time; and IP cores have a relatively higher time due to the larger number of extracted objects. The overall regression trend line and confidence band indicate a stable linear relationship between the number of extracted objects and the comparison time. Based on this linear relationship, only abnormal modules identified through the initial screening of the top-level netlist are subjected to local topology comparison based on module port constraints. Since the number of abnormal modules is less than the total number of all modules, and the number of extracted objects for a single abnormal module is less than the total number of extracted objects for the complete chip, this mechanism can effectively reduce the comparison search range and data volume, thereby reducing the redundancy of the comparison calculation.

[0069] S5. Using the name of the electrical node in the difference node list as the search key, query the node attribute field to obtain the layer attributes and grid coordinates of the polygon geometry that has the node attribute field.

[0070] Considering that the output list of difference nodes only contains the names of electrical nodes, while the physical defect location and repair operations in the layout editing environment need to be performed on the corresponding positions of the layout screen based on layer attributes and grid coordinates, if the electrical identifiers of the difference nodes are not mapped back to the geometric entities in the layout, only the abstract node differences can be known, and the actual layout graphics that need to be modified cannot be located, resulting in the physical verification results being unable to guide layout repair.

[0071] Therefore, this step searches the node attribute fields of polygonal geometric figures in the layout one by one by the electrical node names in the difference node list, marks the figures with completely matching character sequences as matching figures, reads their layer attributes and grid coordinates, and thus transforms the difference positioning at the electrical level into the figure positioning at the physical level of the layout.

[0072] In one specific embodiment, the names of electrical nodes are read one by one from the list of differences in order. The node attribute fields of all polygonal geometries in the layout are traversed, and the strings stored in the node attribute fields are extracted. The character sequence of the electrical node name is compared character by character with the character sequence of the extracted string. If the lengths of the two character sequences are equal and the characters at corresponding positions are exactly the same, the polygonal geometries are marked as matching geometries.

[0073] Read the layer attributes corresponding to the layer identifier of the layer to which the matched graphic belongs, and read the coordinate values ​​of all vertices of the matched graphic as grid coordinates.

[0074] Since the matching graphics corresponding to the difference nodes have obtained layer attributes and grid coordinates, in order to intuitively locate the physical defect location in the layout, the viewport range is set with the grid coordinates as the center in the layout editing environment, the display color of the matching graphics is changed to the highlight color, and the layer attributes and grid coordinates are written to a text file to generate a verification report.

[0075] The above embodiments can be implemented, in whole or in part, by software, hardware, firmware, or any other combination thereof. When implemented using software, the above embodiments can be implemented, in whole or in part, in the form of a computer program product.

[0076] Those skilled in the art will recognize that the algorithmic steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0077] In addition, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module.

[0078] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0079] Finally, the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An integrated circuit layout design physical verification and rule checking method, characterized by, include: S1. In the layout editing environment, assign electrical node names based on the electrical connectivity of polygon geometry and write them into their node attribute fields; S2. Based on GDS data, the unit hierarchical structure parsing layer-level tree identifies the physical bounding boxes of standard units, macro modules and IP cores, and generates a mapping index between module hierarchy and physical coordinates; S3. Perform hierarchical netlist extraction on each module based on the mapping index to generate a module-level netlist and a top-level interconnect netlist. The module-level netlist contains the internal device connection relationship of the module, and the top-level interconnect netlist contains the port connection relationship between modules. Compare the top-level interconnect netlist with the circuit schematic reference netlist to identify abnormal modules with connection differences. S4. For abnormal modules, perform a topology consistency comparison based on module port constraints only between the module-level netlist of the abnormal module and the corresponding sub-module netlist in the reference netlist, and output a list of differences in nodes. S5. Using the name of the electrical node in the difference node list as the search key, query the node attribute field to obtain the layer attributes and grid coordinates of the polygon geometry that has the node attribute field. Step S2 includes: In the page layer hierarchy tree, leaf nodes that do not contain sub-unit instances are marked as standard units, non-leaf nodes that contain sub-unit instances are marked as macro modules, and units carrying library identifier attributes are marked as IP cores. Read the vertex coordinates of all polygonal geometric figures in the standard unit, macro module and IP core, extract the minimum vertex coordinate values ​​and the maximum vertex coordinate values ​​in the X and Y directions respectively, combine them to form the lower left vertex and the upper right vertex to construct the bounding rectangle, and use the bounding rectangle as the physical bounding box; Extract the coordinates of the bottom left and top right vertices of the physical bounding box as physical coordinates; The physical coordinates are combined with the corresponding standard units, macro modules, and IP cores in the layout hierarchy tree to form a key-value pair structure, generating a mapping index between the module hierarchy and the physical coordinates. The S4 step includes: Extract the device pin list connected to the port pins in the module-level netlist of the abnormal module, and the device pin list connected to the port pins of the same name in the sub-module netlist. Use the above device pin list as the module port constraint. In the module-level netlist, starting from the port pin, the connected devices and internal connections are traversed sequentially according to the path indicated by the device pin list, and the device identifier sequence on the traversal path is recorded as the module-level topology. In the submodule netlist, starting from the pin of the same port, the connected devices and internal connections are traversed in sequence along the same path, and the device identification sequence on the traversal path is recorded as a reference topology. The module-level topology is compared one by one with the device identifier sequence in the reference topology according to the traversal order. If the device identifiers at the same position are inconsistent or the number of device identifiers is inconsistent, the node corresponding to the device identifier at that position is recorded as a difference node, and a list of difference nodes is formed. Step S5 includes: Read the electrical node names from the list of differences in order, traverse the node attribute fields of the polygonal geometry in the layout, and extract the strings stored in the node attribute fields. The character sequence of the electrical node name is compared with the character sequence of the extracted string. If the lengths of the two character sequences are equal and the characters at corresponding positions are exactly the same, the polygonal geometric figure is marked as a matching figure. Read the layer attributes of the layer identifier corresponding to the matched graphic, and read the vertex coordinates of the matched graphic as grid point coordinates.

2. The method for physical verification and rule checking of integrated circuit layout design as described in claim 1, characterized in that, Step S1 includes: In the layout editing environment, the polygonal geometry on each layer is traversed, the layer identifier is read and compared with the set of conductive layer identifiers in the process file. If the layer identifier exists in the set of conductive layer identifiers, the polygonal geometry is identified as belonging to the conductive layer. For polygonal geometries belonging to the conductive layer, calculate whether the edges of any two polygonal geometries intersect or whether one completely contains the other. If they intersect or contain each other, mark them as having an electrical connection. A graph traversal algorithm is used to merge polygonal geometric figures with electrical connectivity into the same set as a group, and to divide those that are not merged into different groups. Assign electrical node names to each group of polygonal geometries and write them into the node attribute fields of each polygonal geometries in the corresponding group.

3. The method for physical verification and rule checking of integrated circuit layout design as described in claim 1, characterized in that, The page layout hierarchy tree specifically includes: Read the structural unit definitions and unit call records in the GDS data; take the top-level structural unit as the root node, take the lower-level structural units called by the root node as child unit instances, and take the structural unit that calls the child unit instance as the parent node; The nesting depth of the call relationship is recursively expanded layer by layer to construct a tree data structure as a page-level tree; In a tree data structure, a structural unit node that does not contain a child unit instance is defined as a leaf node, and a structural unit node that contains a child unit instance is defined as a non-leaf node. Read the attribute fields of the structural units in the GDS data, and define the structural units that contain library identifier characters in the attribute fields as units that carry library identifier attributes.

4. The method for physical verification and rule checking of integrated circuit layout design as described in claim 1, characterized in that, The method for generating the module-level netlist includes: Based on the mapping index, locate the physical bounding box corresponding to the physical coordinates of each module, and use the polygonal geometry inside the physical bounding box as the netlist extraction object; Calculate the intersection area of ​​any two polygonal geometric figures belonging to the same layer identifier. If the intersection area is greater than zero, the two are determined to overlap. Calculate the shortest distance between the boundary lines of two polygonal geometric figures belonging to the same layer identifier. If the shortest distance is zero and the intersection area is zero, then the two are determined to be adjacent. Find through-hole graphics located in different layer identifiers and with overlapping areas, and determine the polygonal geometric shapes in different layers with overlapping through-hole graphics as cross-layer connected; The connection relationships between overlapping, adjacent, or cross-layer connected polygonal geometries are organized into the internal device connection relationships of the module, generating a module-level netlist.

5. The method for physical verification and rule checking of integrated circuit layout design as described in claim 1, characterized in that, The method for generating the top-level interconnection table includes: Extract the metal connection graphics and port graphics that cross the physical boundary box from the layer hierarchy tree, calculate the intersection area of ​​the metal connection graphics and port graphics, and determine that the metal connection graphics and port graphics intersect if the intersection area is greater than zero. Extract the network name and port name stored in the attribute fields of the intersecting metal connection graphs, use the mapping relationship between port name and network name as the port connection relationship between modules, and summarize to generate a top-level interconnection table.

6. The method for physical verification and rule checking of integrated circuit layout design as described in claim 1, characterized in that, The method for identifying the abnormal module includes: Read the network list from the top-level interconnection netlist and the circuit schematic reference netlist, and compare the port connection path strings under the same network name one by one. If the port connection path strings are inconsistent, mark the module corresponding to the network name as an abnormal module.

7. The method for physical verification and rule checking of integrated circuit layout design as described in claim 1, characterized in that, Following step S5, the method further includes: in the layout editing environment, automatically locating and highlighting the matching graphic based on the grid coordinates, and simultaneously generating a verification report containing layer attributes and grid coordinates.

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