A mapping method of a quantum circuit and a related device

Abstract

The application discloses a quantum circuit mapping method and related device, and the method comprises the following steps: obtaining an initial mapping relationship between logical bits of a quantum circuit and physical bits of a real quantum chip; based on the initial mapping relationship, determining a pre-sequence gate as an unexecutable gate, wherein the pre-sequence gate is a two-bit quantum logic gate without bit entanglement in two-bit quantum logic gates which are first executed in the quantum circuit, and the physical bits of the pre-sequence gate are not connected and the distance between the physical bits is less than a target threshold; obtaining a first score of all current SWAP exchange schemes of each unexecutable gate, and obtaining a second score of all current SWAP exchange schemes of each unexecutable gate; determining a SWAP exchange scheme with the highest sum of the first score and the second score as a target scheme; the application introduces the first score and the second score mechanism, aiming to reduce the depth of the quantum circuit and improve the execution efficiency of the quantum circuit.

Description

Technical Field

[0001] This invention belongs to the field of quantum computing technology, specifically a mapping method and related apparatus for quantum circuits. Background Technology

[0002] In the process of mapping quantum circuits, the depth of the quantum circuit directly affects the execution efficiency and result quality of quantum computing. As the circuit depth increases, the execution time becomes longer, affecting the feasibility of actual computation. Excessively deep circuits may also increase the complexity of error correction and optimization, requiring more resources for error correction and compilation optimization, and placing higher demands on quantum computing hardware resources.

[0003] Therefore, the urgent technical problem to be solved is to propose a new mapping method for quantum circuits, which aims to reduce the depth of quantum circuits and improve the execution efficiency of quantum circuits. Summary of the Invention

[0004] The purpose of this invention is to provide a quantum circuit mapping method and related apparatus, which aims to reduce the depth of quantum circuits and improve the execution efficiency of quantum circuits.

[0005] One embodiment of the present invention provides a mapping method for quantum circuits, the method comprising:

[0006] Obtain the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the real quantum chip;

[0007] Based on the initial mapping relationship, the preorder gates that are not connected to the physical bits mapped to the real quantum chip and whose physical bit distance is less than the target threshold are determined as non-executable gates; wherein, the preorder gates are the two-bit quantum logic gates that are not entangled among the first two-bit quantum logic gates executed by the quantum circuit;

[0008] Obtain the first score of all current SWAP swap schemes for each non-executable gate, and obtain the second score of all current SWAP swap schemes for each non-executable gate. Determine the SWAP swap scheme with the highest sum of the first and second scores as the target scheme. Here, a SWAP swap scheme includes only one SWAP gate. The first score and the second score respectively characterize the distance change of all physical bits of the non-executable gate and the depth change of the quantum circuit after performing a SWAP swap scheme on a non-executable gate.

[0009] Using the exchange results of the qubits in the target scheme, it is determined that all non-executable gates can obtain the final mapping relationship based on all target schemes when executed on the real quantum chip.

[0010] Optionally, obtaining the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the actual quantum chip includes:

[0011] For each first topological subgraph, a second topological subgraph with a number of bits greater than or equal to and closest to the number of bits of the first topological subgraph is determined, and a matching relationship is established between the first topological subgraph and the determined second topological subgraph. The first topological subgraph is a topological subgraph of a quantum circuit, and there is no bit entanglement between the first topological subgraphs. The second topological subgraph is a topological subgraph of a real quantum chip, and there is no bit coupling between the second topological subgraphs.

[0012] Using the established matching relationship, the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the real quantum chip is obtained.

[0013] Optionally, obtaining the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the real quantum chip using the established matching relationship includes:

[0014] By using a random number method, a mapping between logical bits and physical bits corresponding to each matching relationship is established to obtain the initial mapping relationship.

[0015] Optionally, the target threshold is the threshold used when determining an inoperable gate through threshold update.

[0016] Optionally, obtaining the first score of all current SWAP switching schemes for each non-executable gate includes:

[0017] Calculate the distance change difference of physical bits for each non-executable gate after executing the SWAP switching scheme, and obtain the sum of the distance changes of all non-executable gates as the first score; wherein, the distance change difference is recorded as -1 if the topological distance of the shortest path between the two physical bits corresponding to each non-executable gate increases after executing the SWAP switching scheme, and +1 if the topological distance of the shortest path between the two physical bits corresponding to each non-executable gate decreases.

[0018] Optionally, obtaining the second score of all current SWAP switching schemes for each non-executable gate includes:

[0019] Determine the first line depth and the second line depth corresponding to each SWAP scheme of each non-executable gate, wherein the first line depth is the quantum line depth of the non-executable gate, and the second line depth is the quantum line depth of the logical bit exchanged by the non-executable gate after executing a SWAP scheme;

[0020] The second score for each SWAP switching scheme is obtained based on the maximum value between the first line depth and the second line depth corresponding to each SWAP switching scheme and each non-executable gate.

[0021] Optionally, the method for calculating the second score of each SWAP switching scheme for each non-executable gate based on the maximum value of the first line depth and the second line depth corresponding to each SWAP switching scheme is as follows:

[0022] Second score = r*(depth-max(depth1,depth2))

[0023] Where r is the weight value, depth is the quantum circuit depth of the non-executable gate, and depth1 and depth2 are the quantum circuit depths of the logical bits swapped by the non-executable gate after executing a SWAP scheme.

[0024] Optionally, when determining that all non-executable gates can be executed on the real quantum chip using the exchange results of the target scheme for qubits, the final mapping relationship is obtained based on all target schemes, including:

[0025] Based on the result of the qubit exchange according to the target scheme, the target scheme for each non-executable gate is updated in the next iteration. The update is iteratively updated until the physical bits of any non-executable gate in the set of non-executable gates are connected. The set of non-executable gates in the quantum circuit is obtained again. The target scheme is iteratively updated until any two-bit quantum logic gates in the quantum circuit can be executed on a real quantum chip. Based on all target schemes, the final mapping relationship is obtained.

[0026] Another embodiment of the present invention provides a quantum circuit mapping device, the device comprising:

[0027] The initial mapping acquisition unit is used to obtain the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the real quantum chip;

[0028] The determining unit is used to determine, based on the initial mapping relationship, a pre-order gate that is not connected to the physical bits of the real quantum chip and whose physical bit distance is less than a target threshold as an unexecutable gate; wherein, the pre-order gate is the two-bit quantum logic gate without bit entanglement among the first two-bit quantum logic gates executed by the quantum circuit;

[0029] The target scheme acquisition unit is used to obtain the first score of all current SWAP exchange schemes for each non-executable gate, and the second score of all current SWAP exchange schemes for each non-executable gate, and determine the SWAP exchange scheme with the highest sum of the first score and the second score as the target scheme. Here, a SWAP exchange scheme includes only one SWAP gate. The first score and the second score respectively characterize the distance change of all non-executable gate physical bits and the depth change of quantum circuit after performing a SWAP exchange scheme on a non-executable gate.

[0030] The final mapping acquisition unit is used to determine, based on all target schemes, the final mapping relationship when all non-executable gates can be executed on the real quantum chip, by utilizing the exchange results of the qubits in the target scheme.

[0031] Another embodiment of the present invention provides an electronic device, wherein the computer-readable storage medium stores a computer program, the computer program including program instructions, which, when executed by a processor, perform the methods described in any of the above embodiments.

[0032] Another embodiment of the present invention provides a computer-readable storage medium storing a computer program, the computer program including program instructions that, when executed by a processor, perform the methods described in any of the above embodiments.

[0033] Another embodiment of the present invention provides a quantum computer operating system, which implements quantum circuit mapping according to the method described in any of the above embodiments.

[0034] Compared with existing technologies, this invention first obtains an initial mapping relationship between the logical bits of a quantum circuit and the physical bits of a real quantum chip. Then, based on this initial mapping relationship, it identifies pre-order gates whose physical bits mapped to the real quantum chip are not connected and whose physical bit distance is less than a target threshold as non-executable gates. The pre-order gates are the two unentangled quantum logic gates among the first two quantum logic gates executed by the quantum circuit. Next, by obtaining the first score of all current SWAP exchange schemes for each non-executable gate and the second score of all current SWAP exchange schemes for each non-executable gate, it determines the SWAP exchange scheme with the highest sum of the first and second scores as the target scheme. Each SWAP exchange scheme includes only one SWAP gate, and the first and second scores respectively characterize the change in the distance between the physical bits of all non-executable gates and the change in the depth of the quantum circuit after performing a SWAP exchange scheme on a non-executable gate. Finally, using the qubit exchange results of the target scheme, it is determined that all non-executable gates can be executed on the real quantum chip, and based on all target schemes, a final mapping relationship is obtained.

[0035] This invention first establishes an initial mapping relationship between the logical bits of a quantum circuit and the physical bits of a real quantum chip. Logical bits in a quantum circuit need to be mapped to physical bits of the real quantum chip to be executed. The initial mapping relationship is the starting point of the entire mapping method, clarifying the initial state, upon which subsequent optimization operations are performed. Then, based on the initial mapping relationship, pre-order gates whose physical bits mapped to the real quantum chip are not connected and whose physical bit distance is less than a target threshold are identified as non-executable gates. The pre-order gates are the two-bit quantum logic gates without bit entanglement that are executed first in the quantum circuit. By clearly defining the non-executable gates, the invention ensures accurate identification of quantum logic gates that cannot be directly executed under the current initial mapping relationship, focusing the problem on key points. Secondly, by obtaining the first score of all current SWAP exchange schemes for each non-executable gate and the second score of all current SWAP exchange schemes for each non-executable gate, the SWAP exchange scheme with the highest sum of the first and second scores is identified as the target gate. The target scheme is defined as follows: a SWAP scheme includes only one SWAP gate. The first score and the second score represent the changes in the distance between the physical bits of all non-executable gates and the changes in the depth of the quantum circuit after performing a SWAP scheme on a non-executable gate, respectively. The first score and the second score take into account the changes in the distance between the physical bits and the changes in the depth of the quantum circuit, respectively. This comprehensive approach ensures that the distance between the physical bits meets the requirements of quantum operation while minimizing the increase in the depth of the quantum circuit caused by inserting SWAP gates. This improves the efficiency of quantum computing while ensuring the executability of the quantum circuit. Finally, using the qubit swapping results of the target scheme, it is determined that all non-executable gates can be executed on the real quantum chip. Based on all target schemes, the final mapping relationship is obtained. From the iterative update of the first swap scheme to the determination of the final mapping relationship of the circuit, the quantum circuit can better adapt to the physical characteristics of the real quantum chip, reducing errors and noise caused by improper mapping and improving the reliability and stability of quantum computing. Attached Figure Description

[0036] Figure 1 This is a network block diagram of a quantum circuit mapping system provided in an embodiment of the present invention.

[0037] Figure 2 This is a flowchart of a quantum circuit mapping method provided in an embodiment of the present invention.

[0038] Figure 3 This is a schematic diagram of a quantum circuit topology provided in an embodiment of the present invention.

[0039] Figure 4 This is a schematic diagram of the initial mapping of a quantum circuit provided in an embodiment of the present invention.

[0040] Figure 5 This is a structural diagram of a quantum circuit mapping device provided in an embodiment of the present invention.

[0041] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0042] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0043] Figure 1 This is a network block diagram of a quantum circuit mapping system provided in an embodiment of the present invention. The quantum circuit mapping system may include a network 110, a server 120, a wireless device 130, a client 140, a storage 150, a classical computing unit 160, a quantum computing unit 170, and may also include additional memory, a classical processor, a quantum processor, and other devices not shown.

[0044] Network 110 is a medium used to provide communication links between various devices and computers connected together within a quantum circuit mapping system, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof, and the connection method can be wired, wireless communication links, or fiber optic cables.

[0045] Server 120, wireless device 130, and client 140 are conventional data processing systems that may contain data and application programs or software tools that perform conventional computational processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 120. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0046] The classical computing unit 160 (quantum computing unit 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application program 163 (application program 173). The application program 163 (application program 173) may be used to implement a quantum algorithm compiled by the quantum circuit mapping method provided in the embodiments of the present invention.

[0047] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application executed therein can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0048] It should be noted that a true quantum computer has a hybrid structure, which includes at least... Figure 1 The system consists of two main parts: the classical computing unit 160, which is responsible for performing classical calculations and control; and the quantum computing unit 170, which is responsible for running quantum programs to achieve quantum computing.

[0049] The aforementioned classical computing unit 160 and quantum computing unit 170 can be integrated into a single device or distributed across two different devices. For example, a first device including the classical computing unit 160 runs a classical computer operating system, providing quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum programs using the quantum application development tools and services on the second device, and send these quantum programs to a second device including the quantum computing unit 170 via the network services. The second device runs a quantum computer operating system, which parses and compiles the quantum program's code into instructions that the quantum processor 170 can recognize and execute. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.

[0050] The computing units of the classic processor 161 within the classic computing unit 160 are based on CMOS transistors on a silicon chip. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of such computing units in a silicon chip is sufficient; currently, a single classic processor 161 contains tens of thousands of computing units. Given this sufficient number and the fixed selectable computing logic of the CMOS transistors (e.g., AND logic), computational performance is achieved by combining a large number of CMOS transistors with a limited set of logic functions during operation.

[0051] In the quantum computing unit 170, the basic computing unit of the quantum processor 171 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logical functions. Given the limited number of qubits and the diverse logical functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), X gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse logical function combinations to achieve computational effects.

[0052] Based on these differences, the design of classical logic functions applied to CMOS transistors and the design of quantum logic functions applied to qubits are significantly and fundamentally different. The design of classical logic functions applied to CMOS transistors does not need to consider the individuality of CMOS transistors. For example, the representation of a CMOS transistor in a silicon chip is its individual identifier, location, and usable time of each CMOS transistor. Therefore, classical algorithms composed of classical logic functions only express the operational relationship of the algorithm, not the algorithm's dependence on individual CMOS transistors.

[0053] Quantum logic functions applied to qubits need to consider the individuality of each qubit, such as its position within the quantum chip, its relationship with surrounding qubits, and the duration of its usable time. Therefore, quantum algorithms composed of quantum logic functions not only express the computational relationships within the algorithm but also its dependence on the individual qubits.

[0054] A quantum chip can include qubits and channels for controlling them. Quantum logic gates are implemented using analog signals. Different combinations of analog signals are applied to the qubits through these channels, thereby creating quantum circuits with different functions to process data. Therefore, the design of quantum logic functions in the qubits (including the design of whether qubits are used and the design of the efficiency of each qubit) is crucial for improving the computational performance of quantum computers and requires special design. This is the unique characteristic of quantum algorithms based on quantum logic functions, and it is fundamentally and significantly different from classical algorithms based on classical logic functions. The aforementioned design considerations for qubits are technical problems that ordinary computing devices do not need to consider or address.

[0055] In the field of quantum computing, the depth of quantum circuits directly affects the execution efficiency and result quality of quantum computing during the mapping process. As the circuit depth increases, the execution time becomes longer, affecting the feasibility of actual computation. Excessively deep circuits may also increase the complexity of error correction and optimization, requiring more resources for error correction and compilation optimization, thus placing higher demands on quantum computing hardware resources.

[0056] Therefore, the urgent technical problem to be solved is to propose a new mapping method for quantum circuits, which aims to reduce the depth of quantum circuits and improve the execution efficiency of quantum circuits.

[0057] See Figure 2 , Figure 2 A quantum circuit mapping method provided in this embodiment of the invention includes the following steps:

[0058] Step S201: Obtain the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the real quantum chip.

[0059] Step S202: Based on the initial mapping relationship, determine the pre-order gates that are not connected to the physical bits of the real quantum chip and whose physical bit distance is less than the target threshold as non-executable gates; wherein, the pre-order gates are the two-bit quantum logic gates that are not entangled among the first two-bit quantum logic gates executed by the quantum circuit.

[0060] Specifically, non-executable gates are first identified. The determination of non-executable gates requires that, under the initial mapping relationship, the physical topology is not connected, and the topological distance between the two corresponding physical bits is less than a preset threshold for two-bit quantum logic gates.

[0061] For example, see Figure 3 , Figure 3 This is a schematic diagram of a quantum circuit topology provided in an embodiment of the present invention. It is assumed that the preorder gates G1, G2, and G3 are first determined. After initial mapping, the physical topologies of gates G1, G2, and G3 are not connected. See [link to documentation]. Figure 4 , Figure 4 This is a schematic diagram of the initial mapping of a quantum circuit provided in an embodiment of the present invention. The topological distance between the two corresponding physical bits is less than a preset threshold unit of 5. Therefore, the {G1, G2, G3} gates are determined to be a set of non-executable gates.

[0062] Step S203: Obtain the first score of all current SWAP switching schemes for each non-executable gate, and obtain the second score of all current SWAP switching schemes for each non-executable gate. Determine the SWAP switching scheme with the highest sum of the first and second scores as the target scheme. Herein, a SWAP switching scheme includes only one SWAP gate. The first score and the second score respectively characterize the distance change of all physical bits of the non-executable gate and the depth change of the quantum circuit after performing a SWAP switching scheme on a non-executable gate.

[0063] Specifically, for the set of non-executable gates {G1, G2, G3} obtained through the above steps, all swap schemes are listed for each non-executable gate. The first score of all current swap schemes for each non-executable gate and the second score of all current swap schemes for each non-executable gate are calculated. The swap scheme with the highest sum of the first and second scores is determined and used as the target swap scheme.

[0064] For example, see Figure 4 , Figure 4 This is a schematic diagram of the initial mapping of a quantum circuit provided in an embodiment of the present invention. The (q3, q4) corresponding to gate G1 is mapped to (Q0, Q4), and the exchange schemes for gate G1 are listed as Q0-Q7, Q0-Q1, Q4-Q3, Q4-Q5. The (q5, q6) corresponding to gate G2 is mapped to (Q1, Q3), and the exchange schemes for gate G2 are listed as Q1-Q0, Q1-Q2, Q3-Q2, Q3-Q4. The (q0, q1) corresponding to gate G3 is mapped... For (Q5, Q7), the switching schemes for gate G3 are listed as Q5-Q4, Q5-Q6, Q7-Q0, Q7-Q6, a total of 12 switching schemes. First, calculate the first score of all current SWAP switching schemes for each non-executable gate, and then calculate the second score of all current SWAP switching schemes for each non-executable gate. Assume that the switching path of the SWAP switching scheme with the highest sum of the first and second scores is determined to be Q0-Q1, and this is used as the target switching scheme.

[0065] Step S204: Using the exchange results of the qubits in the target scheme, determine that all non-executable gates can be executed in the real quantum chip, and obtain the final mapping relationship based on all target schemes.

[0066] Specifically, the target exchange scheme is used to find the exchange results of the qubits, so as to determine all target schemes when all non-executable gates can be executed on a real quantum chip, and the final mapping relationship is determined based on all target schemes.

[0067] In summary, this invention first obtains an initial mapping relationship between the logical bits of a quantum circuit and the physical bits of a real quantum chip. Logical bits in a quantum circuit need to be mapped to physical bits of a real quantum chip to be executed. The initial mapping relationship is the starting point of the entire mapping method, clarifying the initial state, upon which subsequent optimization operations are performed. Then, based on the initial mapping relationship, pre-order gates whose physical bits mapped to the real quantum chip are not connected and whose physical bit distance is less than a target threshold are identified as non-executable gates. The pre-order gates are the two-bit quantum logic gates without bit entanglement among the first two-bit quantum logic gates executed by the quantum circuit. By clearly defining the non-executable gates, it ensures accurate identification of quantum logic gates that cannot be directly executed under the current initial mapping relationship, focusing the problem on key points. Secondly, by obtaining the first score of all current SWAP exchange schemes for each non-executable gate and the second score of all current SWAP exchange schemes for each non-executable gate, the SWAP exchange scheme with the highest sum of the first and second scores is determined as the... The target scheme is defined as follows: a SWAP scheme includes only one SWAP gate. The first score and the second score represent the changes in the distance between the physical bits of all non-executable gates and the changes in the depth of the quantum circuit after performing a SWAP scheme on a non-executable gate, respectively. The first score and the second score consider the changes in the distance between the physical bits and the changes in the depth of the quantum circuit, respectively. This comprehensive approach ensures that the distance between the physical bits meets the requirements of quantum operations while minimizing the increase in the depth of the quantum circuit caused by inserting SWAP gates. This improves the efficiency of quantum computing while ensuring the executability of the quantum circuit. Finally, using the qubit swapping results of the target scheme, it is determined that all non-executable gates can be executed on the real quantum chip. Based on all target schemes, the final mapping relationship is obtained. From the iterative update of the first swap scheme to the determination of the final mapping relationship of the circuit, the quantum circuit can better adapt to the physical characteristics of the real quantum chip, reducing errors and noise caused by improper mapping and improving the reliability and stability of quantum computing.

[0068] In one embodiment of the present invention, obtaining the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the real quantum chip includes:

[0069] For each first topological subgraph, a second topological subgraph with a number of bits greater than or equal to and closest to the number of bits in the first topological subgraph is determined, and a matching relationship is established between the first topological subgraph and the determined second topological subgraph. The first topological subgraph is a topological subgraph of a quantum circuit, and there is no bit entanglement between the first topological subgraphs. The second topological subgraph is a topological subgraph of a real quantum chip, and there is no bit coupling between the second topological subgraphs.

[0070] Specifically, the topological subgraphs of the quantum circuit and the topological subgraphs of the real quantum chip are first arranged in ascending order. For each quantum circuit's topological subgraph, a topological subgraph of the real quantum chip with a number of qubits greater than or equal to that of the quantum circuit's topological subgraph is found and matched one by one. The matching results are then placed into a matching result set.

[0071] For example, suppose there are three topological subgraphs of quantum circuits, Gcir1, Gcir2, and Gcir3, with 3, 4, and 6 qubits respectively after ascending order. At the same time, there are three topological subgraphs of real quantum chips, Gchip1, Gchip2, and Gchip3, with 4, 7, and 8 qubits respectively after ascending order. For each topological subgraph of a quantum circuit, find the topological subgraph of a real quantum chip with a qubit count greater than or equal to that of the topological subgraph of the quantum circuit. Suppose the matching result set is {(Gcir1:Gchip1)(Gcir2:Gchip2)(Gcir3:Gchip3)}.

[0072] Using the established matching relationship, the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the real quantum chip is obtained.

[0073] Specifically, the matching relationships established through the above steps determine the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the real quantum chip in each matching relationship.

[0074] In summary, by matching the topology of the quantum circuit (first topological subgraph) and the quantum chip (second topological subgraph), the physical subgraph with the closest number of bits is selected first, and the physical bit resources of the quantum chip are allocated more rationally. Through subgraph-level matching, rather than global one-time mapping, multiple logical subgraphs can avoid competing for the resources of the same physical subgraph, thus improving the flexibility of the mapping process.

[0075] In one embodiment of the present invention, obtaining the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the real quantum chip using the established matching relationship includes:

[0076] By using a random number method, a mapping between logical bits and physical bits corresponding to each matching relationship is established to obtain the initial mapping relationship.

[0077] Specifically, by setting a random number method, the corresponding logical bits and physical bits between each matching subgraph are randomly mapped to obtain the mapping relationship of all matching subgraphs.

[0078] In one embodiment of the present invention, the target threshold is the threshold used when determining an inoperable gate through threshold update.

[0079] Specifically, the target threshold is the threshold corresponding to the non-executable gate determined by each threshold update. When the preceding gate is determined, an initial threshold is set, a set of non-executable gates is searched, and swaps are performed in these sets of non-executable gates. After all non-executable gates have been swapped, the threshold is incremented by 1 to set the next threshold. Under this threshold, the next set of non-executable gates to be swapped is searched.

[0080] In one embodiment of the present invention, obtaining the first score of all current SWAP switching schemes for each non-executable gate includes:

[0081] Calculate the distance change difference of physical bits for each non-executable gate after executing the SWAP switching scheme, and obtain the sum of the distance changes of all non-executable gates as the first score; wherein, the distance change difference is recorded as -1 if the topological distance of the shortest path between the two physical bits corresponding to each non-executable gate increases after executing the SWAP switching scheme, and +1 if the topological distance of the shortest path between the two physical bits corresponding to each non-executable gate decreases.

[0082] Specifically, the difference in physical bit distance for each non-executable gate after executing the SWAP scheme is calculated, and the sum of the distance changes of all non-executable gates is used as the first score.

[0083] For example, see Figure 4 , Figure 4 This is a schematic diagram of the initial mapping of a quantum circuit provided by an embodiment of the present invention. In step S203, a total of 12 exchange schemes for gates G1, G2, and G3 are listed. Assuming that an exchange scheme is selected, namely Q0-Q1 corresponding to G1, Q0 and Q1 are exchanged. Then, the shortest exchange path unit of gate G1, which is 4, becomes 3, and its topological distance decreases, which is recorded as +1. Based on this, looking at gate G2, the shortest exchange path unit of G2 becomes 2, which becomes 3, and its topological distance decreases, which is recorded as -1. Looking at G3, the shortest exchange path unit of G3 does not change, and its topological distance change is recorded as 0. The first score is obtained by adding the sum of the distance changes calculated above.

[0084] In summary, by introducing dynamic difference calculation and a global optimization perspective, the calculation of the first score is made more refined and systematic. The first score directly reflects the comprehensive impact of the SWAP scheme on the physical bit connectivity, providing a clear direction for algorithm optimization, ensuring the improvement of global mapping quality, and thus improving algorithm efficiency and mapping quality.

[0085] In one embodiment of the present invention, obtaining the second score of all current SWAP switching schemes for each non-executable gate includes:

[0086] Determine the first line depth and the second line depth corresponding to each SWAP scheme of each non-executable gate, wherein the first line depth is the quantum line depth of the non-executable gate, and the second line depth is the quantum line depth of the logical bits obtained by the non-executable gate after executing a SWAP scheme.

[0087] Specifically, determine the first line depth and the second line depth corresponding to each SWAP switching scheme for each non-executable gate.

[0088] The second score for each SWAP switching scheme is obtained based on the maximum value between the first line depth and the second line depth corresponding to each SWAP switching scheme and each non-executable gate.

[0089] Specifically, for each SWAP switching scheme, the maximum value between the first line depth and the second line depth can be used to obtain the second score for each SWAP switching scheme with each non-executable gate.

[0090] In one embodiment of the present invention, the method for calculating the second score of each SWAP switching scheme for each non-executable gate based on the maximum value of the first line depth and the second line depth corresponding to each SWAP switching scheme is as follows:

[0091] Second score = r*(depth-max(depth1,depth2))

[0092] Where r is the weight value, depth is the quantum circuit depth of the non-executable gate, and depth1 and depth2 are the quantum circuit depths of the logical bits swapped by the non-executable gate after executing a SWAP scheme.

[0093] Specifically, r is the weight value, which is a constant and is usually set to 0.1.

[0094] For example, suppose there are 12 possible swap schemes G1, G2, and G3. Assume we select one swap scheme, specifically the one corresponding to G3, and calculate the second score. r is the weight value, typically set to 0.1, and depth is the quantum circuit depth of the non-executable gate. See [link to relevant documentation]. Figure 3The line depth corresponding to G3 is 2, which means it is in the second execution sequence. depth1 and depth2 are the quantum line depths of the logical bits swapped after the non-executable gate executes a SWAP scheme. Assuming that the two qubits corresponding to G3 are q0 and q1, and that q1 is swapped to q2 after the SWAP scheme, the depth1 and depth2 change from 2,1 to 2,2. Then, according to the above formula, the second score of the SWAP scheme executed by the corresponding G3 gate can be calculated.

[0095] In one embodiment of the present invention, the step of determining that all non-executable gates can be executed on the real quantum chip by utilizing the exchange results of the qubits using the target scheme, and obtaining the final mapping relationship based on all target schemes, includes:

[0096] Based on the result of the qubit exchange according to the target scheme, the target scheme for each non-executable gate is updated in the next iteration. The update is iteratively updated until the physical bits of any non-executable gate in the set of non-executable gates are connected. The set of non-executable gates in the quantum circuit is obtained again. The target scheme is iteratively updated until any two-bit quantum logic gates in the quantum circuit can be executed on a real quantum chip. Based on all target schemes, the final mapping relationship is obtained.

[0097] Specifically, based on the exchange results of the target scheme for qubits, the exchange path of qubits is obtained. Based on the first exchange result, the target scheme for each non-executable gate is updated for the next time. The search is iterated until the physical bits of any non-executable gate in the set of non-executable gates are connected. Then, the set of non-executable gates in the quantum circuit is obtained, and the search for the target scheme for the exchange of non-executable gates continues. The target scheme is iteratively updated until any two qubits of quantum logic gates in the quantum circuit can be executed on a real quantum chip. All target schemes are obtained, and based on all target schemes, the final mapping relationship is obtained.

[0098] See Figure 5 , Figure 5 A quantum circuit mapping device is provided in an embodiment of the present invention. The device includes an initial mapping acquisition unit 501, a determination unit 502, a target scheme acquisition unit 503, and a final mapping acquisition unit 504, wherein:

[0099] The initial mapping acquisition unit 501 is used to obtain the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the real quantum chip.

[0100] Specifically, obtaining the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the actual quantum chip includes:

[0101] For each first topological subgraph, a second topological subgraph with a number of bits greater than or equal to and closest to the number of bits in the first topological subgraph is determined, and a matching relationship is established between the first topological subgraph and the determined second topological subgraph. The first topological subgraph is a topological subgraph of a quantum circuit, and there is no bit entanglement between the first topological subgraphs. The second topological subgraph is a topological subgraph of a real quantum chip, and there is no bit coupling between the second topological subgraphs.

[0102] Using the established matching relationship, the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the real quantum chip is obtained.

[0103] Specifically, obtaining the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the real quantum chip using the established matching relationship includes:

[0104] By using a random number method, a mapping between logical bits and physical bits corresponding to each matching relationship is established to obtain the initial mapping relationship.

[0105] The determining unit 502 is used to determine, based on the initial mapping relationship, a pre-order gate that is not connected to the physical bits of the real quantum chip and whose physical bit distance is less than a target threshold as an unexecutable gate; wherein, the pre-order gate is a two-bit quantum logic gate without bit entanglement among the first two-bit quantum logic gates executed by the quantum circuit.

[0106] Specifically, the target threshold is the threshold used to determine an inoperable gate through threshold update.

[0107] The target scheme acquisition unit 503 is used to obtain the first score of all current SWAP exchange schemes for each non-executable gate, and the second score of all current SWAP exchange schemes for each non-executable gate, and determine the SWAP exchange scheme with the highest sum of the first score and the second score as the target scheme. Here, a SWAP exchange scheme includes only one SWAP gate. The first score and the second score respectively characterize the distance change of all physical bits of the non-executable gate and the depth change of the quantum circuit after performing a SWAP exchange scheme on a non-executable gate.

[0108] Specifically, obtaining the first score of all current SWAP schemes for each non-executable gate includes:

[0109] Calculate the distance change difference of physical bits for each non-executable gate after executing the SWAP switching scheme, and obtain the sum of the distance changes of all non-executable gates as the first score; wherein, the distance change difference is recorded as -1 if the topological distance of the shortest path between the two physical bits corresponding to each non-executable gate increases after executing the SWAP switching scheme, and +1 if the topological distance of the shortest path between the two physical bits corresponding to each non-executable gate decreases.

[0110] Specifically, obtaining the second score of all current SWAP switching schemes for each non-executable gate includes:

[0111] Determine the first line depth and the second line depth corresponding to each SWAP switching scheme of each non-executable gate, wherein the first line depth is the quantum line depth of the non-executable gate, and the second line depth is the quantum line depth of the logical bits swapped by the non-executable gate after executing a SWAP switching scheme.

[0112] The second score for each SWAP switching scheme is obtained based on the maximum value between the first line depth and the second line depth corresponding to each SWAP switching scheme and each non-executable gate.

[0113] Specifically, the method for calculating the second score of each SWAP switching scheme for each non-executable gate based on the maximum value of the first line depth and the second line depth corresponding to each SWAP switching scheme is as follows:

[0114] Second score = r*(depth-max(depth1,depth2))

[0115] Where r is the weight value, depth is the quantum circuit depth of the non-executable gate, and depth1 and depth2 are the quantum circuit depths of the logical bits swapped by the non-executable gate after executing a SWAP scheme.

[0116] The final mapping acquisition unit 504 is used to determine, based on all target schemes, the final mapping relationship when all non-executable gates can be executed on the real quantum chip by using the exchange results of the qubits in the target scheme.

[0117] Specifically, the step of using the target scheme to exchange qubits and determining that all non-executable gates can be executed on the real quantum chip, based on all target schemes, to obtain the final mapping relationship includes:

[0118] Based on the result of the qubit exchange according to the target scheme, the target scheme for each non-executable gate is updated in the next iteration. The update is iteratively updated until the physical bits of any non-executable gate in the set of non-executable gates are connected. The set of non-executable gates in the quantum circuit is obtained again. The target scheme is iteratively updated until any two-bit quantum logic gates in the quantum circuit can be executed on a real quantum chip. Based on all target schemes, the final mapping relationship is obtained.

[0119] The specific functions and effects of the quantum circuit mapping device described above can be explained by referring to other embodiments in this specification, and will not be repeated here. Each module in the quantum circuit mapping device can be implemented entirely or partially through software, hardware, or a combination thereof. Each module can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0120] Please see Figure 6 This specification also provides an electronic device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the quantum circuit mapping method in any of the above embodiments. Please refer to [link to documentation]. Figure 6 The electronic device can be a classical computer or a quantum computer.

[0121] This specification also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the quantum circuit mapping method of any of the above embodiments.

[0122] This invention also provides a quantum computer operating system, which implements quantum circuit mapping according to any of the above-described method embodiments provided in this invention.

[0123] It is understood that the specific examples in this specification are only intended to help those skilled in the art better understand the implementation methods described herein, and are not intended to limit the scope of the invention.

[0124] It is understood that in the various embodiments of this specification, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this specification in any way.

[0125] It is understood that the various implementation methods described in this specification can be implemented individually or in combination, and the implementation methods in this specification are not limited in this respect.

[0126] Unless otherwise stated, all technical and scientific terms used in the embodiments of this specification have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this specification. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0127] It is understood that the processor in the embodiments of this specification can be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method embodiments can be completed by integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this specification. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this specification can be directly implemented by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software modules can reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above methods.

[0128] It is understood that the memory in the embodiments of this specification may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0129] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this specification.

[0130] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0131] In the several embodiments provided in this specification, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0132] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0133] In addition, the functional units in the various embodiments of this specification can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0134] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of this specification, in essence, or the parts that contribute to the prior art, or parts of the technical solutions, can be embodied in the form of software products. These computer software products are stored in a storage medium and include several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this specification. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0135] The above description is merely a specific embodiment of this specification, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this specification should be included within the scope of protection of this specification. Therefore, the scope of protection of this invention should be determined by the scope of the claims.

Claims

1. A mapping method for quantum circuits, characterized in that, The method includes: Obtain the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the real quantum chip; Based on the initial mapping relationship, the preorder gates that are not connected to the physical bits mapped to the real quantum chip and whose physical bit distance is less than the target threshold are determined as non-executable gates; wherein, the preorder gates are the two-bit quantum logic gates that are not entangled among the first two-bit quantum logic gates executed by the quantum circuit; Obtain the first score of all current SWAP swap schemes for each non-executable gate, and obtain the second score of all current SWAP swap schemes for each non-executable gate. Determine the SWAP swap scheme with the highest sum of the first and second scores as the target scheme. Here, a SWAP swap scheme includes only one SWAP gate. The first score and the second score respectively characterize the distance change of all physical bits of the non-executable gate and the depth change of the quantum circuit after performing a SWAP swap scheme on a non-executable gate. Using the exchange results of the qubits in the target scheme, it is determined that all non-executable gates can obtain the final mapping relationship based on all target schemes when executed on the real quantum chip.

2. The method according to claim 1, characterized in that, The initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the real quantum chip is obtained, including: For each first topological subgraph, a second topological subgraph with a number of bits greater than or equal to and closest to the number of bits of the first topological subgraph is determined, and a matching relationship is established between the first topological subgraph and the determined second topological subgraph. The first topological subgraph is a topological subgraph of a quantum circuit, and there is no bit entanglement between the first topological subgraphs. The second topological subgraph is a topological subgraph of a real quantum chip, and there is no bit coupling between the second topological subgraphs. Using the established matching relationship, the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the real quantum chip is obtained.

3. The method according to claim 2, characterized in that, The process of obtaining the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the real quantum chip using the established matching relationship includes: By using a random number method, a mapping between logical bits and physical bits corresponding to each matching relationship is established to obtain the initial mapping relationship.

4. The method according to claim 1, characterized in that, The target threshold is the threshold used when determining an inoperable gate through threshold updates.

5. The method according to claim 1, characterized in that, The process of obtaining the first score of all current SWAP switching schemes for each non-executable gate includes: Calculate the distance change difference of physical bits for each non-executable gate after executing the SWAP switching scheme, and obtain the sum of the distance changes of all non-executable gates as the first score; wherein, the distance change difference is recorded as -1 if the topological distance of the shortest path between the two physical bits corresponding to each non-executable gate increases after executing the SWAP switching scheme, and +1 if the topological distance of the shortest path between the two physical bits corresponding to each non-executable gate decreases.

6. The method according to claim 1, characterized in that, The second score for obtaining all current SWAP switching schemes for each non-executable gate includes: Determine the first line depth and the second line depth corresponding to each SWAP scheme of each non-executable gate, wherein the first line depth is the quantum line depth of the non-executable gate, and the second line depth is the quantum line depth of the logical bit exchanged by the non-executable gate after executing a SWAP scheme; The second score for each SWAP switching scheme is obtained based on the maximum value between the first line depth and the second line depth corresponding to each SWAP switching scheme and each non-executable gate.

7. The method according to claim 6, characterized in that, The method for calculating the second score of each SWAP switching scheme for each non-executable gate based on the maximum value of the first line depth and the second line depth corresponding to each SWAP switching scheme is as follows: Second score = r*(depth-max(depth1,depth2)) Where r is the weight value, depth is the quantum circuit depth of the non-executable gate, and depth1 and depth2 are the quantum circuit depths of the logical bits swapped by the non-executable gate after executing a SWAP scheme.

8. The method according to claim 1, characterized in that, The process of using the target scheme to exchange qubits determines that all non-executable gates can be executed on the real quantum chip. Based on all target schemes, the final mapping relationship is obtained, including: Based on the result of the qubit exchange according to the target scheme, the target scheme for each non-executable gate is updated in the next iteration. The update is iteratively updated until the physical bits of any non-executable gate in the set of non-executable gates are connected. The set of non-executable gates in the quantum circuit is obtained again. The target scheme is iteratively updated until any two-bit quantum logic gates in the quantum circuit can be executed on a real quantum chip. Based on all target schemes, the final mapping relationship is obtained.

9. A quantum circuit mapping device, characterized in that, The device includes: The initial mapping acquisition unit is used to obtain the initial mapping relationship between the logical bits of the quantum circuit and the physical bits of the real quantum chip; The determining unit is used to determine, based on the initial mapping relationship, a pre-order gate that is not connected to the physical bits of the real quantum chip and whose physical bit distance is less than a target threshold as an unexecutable gate; wherein, the pre-order gate is a two-bit quantum logic gate without bit entanglement among the first two-bit quantum logic gates executed by the quantum circuit; The target scheme acquisition unit is used to obtain the first score of all current SWAP exchange schemes for each non-executable gate, and the second score of all current SWAP exchange schemes for each non-executable gate, and determine the SWAP exchange scheme with the highest sum of the first score and the second score as the target scheme. Here, a SWAP exchange scheme includes only one SWAP gate. The first score and the second score respectively characterize the distance change of all non-executable gate physical bits and the depth change of quantum circuit after performing a SWAP exchange scheme on a non-executable gate. The final mapping acquisition unit is used to determine, based on all target schemes, the final mapping relationship when all non-executable gates can be executed on the real quantum chip, by utilizing the exchange results of the qubits in the target scheme.

10. An electronic device, characterized in that, include: Processor and memory; The processor is connected to a memory, wherein the memory is used to store a computer program, and the processor is used to invoke the computer program to execute the method as described in claims 1-8.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, the computer program including program instructions that, when executed by a processor, perform the method as described in claims 1-8.

12. A quantum computer operating system, characterized in that, The quantum computer operating system implements quantum circuit mapping according to any one of claims 1-8.

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