A three-dimensional resonant cavity, an operation bit, a computing unit and a preparation method

Abstract

The application provides a three-dimensional resonant cavity, an operation bit, a computing unit and a preparation method. The three-dimensional resonant cavity comprises a lumped capacitance and a lumped inductance, and the lumped capacitance and the lumped inductance are connected in parallel. The lumped capacitance and the lumped inductance are arranged on the sidewall of a first through silicon via, and the first through silicon via is arranged on an adapter plate. The first through silicon via is prepared by wet etching. The three-dimensional resonant cavity, the operation bit, the computing unit and the preparation method provided by the application reduce the planar area of a silicon wafer occupied by the three-dimensional resonant cavity, and improve the planar area utilization efficiency of the silicon wafer.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, specifically to a three-dimensional resonant cavity, operational bits, a quantum computing unit, and a method for its fabrication. Background Technology

[0002] In the field of superconducting quantum computing, the integrated structure of resonant cavity and qubit is a key component for achieving high-fidelity readout and high-density expansion.

[0003] In existing technologies, for quantum circuits with measurement and control frequencies between 4 and 8 GHz, superconducting quantum processors employ distributed LC resonant cavities in a meandering line configuration. These cavities are on the order of millimeters in size, far larger than the size of the Josephson junction, the core computing element. As superconducting quantum processors move towards the scale of tens of thousands of qubits, the size of the resonant cavity limits the upper limit of the integration density of planar quantum computing units on a single silicon chip. Therefore, how to reduce the size of the resonant cavity to improve the utilization efficiency of the planar silicon region has become a crucial issue that urgently needs to be addressed in this field. Summary of the Invention

[0004] To address the problems in the prior art, embodiments of the present invention provide a three-dimensional resonant cavity, operational bits, computing units, and a fabrication method, which can at least partially solve the problems existing in the prior art.

[0005] In a first aspect, the present invention proposes a three-dimensional resonant cavity, comprising a lumped capacitance and a lumped inductance, wherein: The lumped capacitor is connected in parallel with the lumped inductor; The lumped capacitor and the lumped inductor are disposed on the sidewall of the first through-silicon via (TSV), which is disposed on the adapter plate; wherein the first TSV is prepared by wet etching.

[0006] Furthermore, the lumped capacitor is positioned near the first opening of the first through-silicon via, and the lumped inductor is positioned near the second opening of the first through-silicon via.

[0007] Furthermore, the lumped capacitor and the lumped inductor are disposed around the sidewall of the first through-silicon via.

[0008] Furthermore, the size of the first opening of the first through-silicon via is different from the size of the second opening.

[0009] Secondly, the present invention proposes a method for fabricating a three-dimensional resonant cavity, comprising: Hard masks are deposited on two surfaces of a substrate to obtain a first mask layer and a second mask layer; wherein the substrate is a double-polished silicon wafer with a (100) crystal plane; A first aperture pattern of the first through-silicon via is formed on the first mask layer, and a second aperture pattern of the first through-silicon via is formed on the second mask layer; Based on the first aperture pattern and the second aperture pattern, a first through-silicon via is formed by wet etching; Remove the remaining first mask layer and second mask layer on both surfaces of the substrate; A superconducting material is deposited on the sidewall of the first through-silicon via to form a superconducting layer; A lumped capacitor and a lumped inductor are sequentially fabricated on the superconducting layer on the sidewall of the first through-silicon via.

[0010] Thirdly, this invention proposes an operational bit, comprising a Josephson junction and a capacitor, wherein: The Josephson junction is connected in parallel with the capacitor; The Josephson junction is disposed on an adapter plate, and a groove or a second through-silicon via is provided on the adapter plate. The capacitor is disposed in the groove or the second through-silicon via. The second through-silicon via is prepared by wet etching, and the sidewall of the groove is inclined to facilitate the preparation of the capacitor.

[0011] Furthermore, the capacitor includes a first plate, an intermediate dielectric layer, and a second plate, wherein: The intermediate dielectric layer is disposed between the first electrode plate and the second electrode plate; The first electrode and the second electrode are disposed on the sidewall of a second through-silicon via; The first electrode or the second electrode is connected to the Josephson junction through another second through-silicon via.

[0012] Furthermore, the capacitor is disposed on the sidewall of the groove, or on the sidewall and bottom of the groove.

[0013] Fourthly, this invention proposes a method for preparing operational bits, comprising: A groove is formed on the substrate or a second through-silicon via is formed by wet etching; wherein the substrate is a double-polished silicon wafer with a (100) crystal plane; the sidewalls of the groove are inclined; A capacitor is formed within the groove or the second through-silicon via; A Josephson junction is fabricated on the substrate and connected in parallel with the capacitor.

[0014] Furthermore, the wet etching process for forming the second through-silicon via includes: Hard masks are deposited on two surfaces of the substrate to obtain a third mask layer and a fourth mask layer; A third opening pattern of the second through-silicon via is formed on the third mask layer, and a fourth opening pattern of the second through-silicon via is formed on the fourth mask layer; Based on the third and fourth aperture patterns, a second through-silicon via (TSV) is formed by wet etching.

[0015] Further, forming the groove on the substrate includes: A hard mask is deposited on the surface of the substrate to obtain a fifth mask layer; A groove pattern is formed on the fifth mask layer; The groove is formed based on the groove pattern.

[0016] Fifthly, this invention proposes a 0-π operation bit, comprising two capacitors, wherein: The adapter board is provided with two grooves or multiple third through-silicon vias, and each capacitor is disposed in the groove or the third through-silicon via; wherein, the third through-silicon via is prepared by wet etching, and the sidewall of the groove is inclined to facilitate the preparation of the capacitor.

[0017] Furthermore, the capacitor is a metal-insulator-metal capacitor, which includes a first plate and a second plate, wherein: The first electrode plate includes a first common electrode and a plurality of first sheet electrodes, and the second electrode plate includes a second common electrode and a plurality of second sheet electrodes. The plurality of first sheet electrodes and the plurality of second sheet electrodes are interleaved and interspersed, and an intermediate dielectric layer is disposed between adjacent first sheet electrodes and second sheet electrodes. The plurality of first sheet electrodes and the plurality of second sheet electrodes are disposed on the sidewall of a third through-silicon via; The first common electrode or the second common electrode is disposed on the sidewall of another third through-silicon via.

[0018] Furthermore, the capacitor is disposed on the sidewall of the groove, or on the sidewall and bottom of the groove.

[0019] In a sixth aspect, the present invention proposes a computing unit, including the operational bits described in any of the above embodiments, or the 0-π operational bits described in any of the above embodiments, and the three-dimensional resonant cavity described in any of the above embodiments.

[0020] The three-dimensional resonant cavity, operational bits, computing unit, and fabrication method provided in this invention include a lumped capacitor and a lumped inductor, wherein the lumped capacitor and the lumped inductor are connected in parallel; the lumped capacitor and the lumped inductor are disposed on the sidewall of a first through-silicon via (TSV), which is disposed on an adapter plate and is fabricated by wet etching; the area occupied by the three-dimensional resonant cavity is on the order of hundreds of micrometers, which reduces the planar area of ​​the silicon wafer occupied by the three-dimensional resonant cavity, thereby improving chip integration and increasing the planar area utilization efficiency of the silicon wafer. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1a This is a schematic cross-sectional view of a three-dimensional resonant cavity provided in an embodiment of the present invention.

[0023] Figure 1b This is a schematic diagram of the lumped capacitance structure of a three-dimensional resonant cavity provided in an embodiment of the present invention.

[0024] Figure 1c This is a schematic diagram of the lumped inductance structure of a three-dimensional resonant cavity provided in an embodiment of the present invention.

[0025] Figure 2 This is a schematic flowchart of a method for fabricating a three-dimensional resonant cavity according to an embodiment of the present invention.

[0026] Figure 3a This is a schematic diagram of the structure after the mask layer is formed, according to an embodiment of the present invention.

[0027] Figure 3b This is a schematic diagram of the structure after forming the opening pattern according to an embodiment of the present invention.

[0028] Figure 3c This is a schematic diagram of the structure after forming the first through-silicon via according to an embodiment of the present invention.

[0029] Figure 3d This is a schematic diagram of the structure after removing the remaining mask layer according to an embodiment of the present invention.

[0030] Figure 3e This is a schematic diagram of the structure after the formation of the superconducting layer according to an embodiment of the present invention.

[0031] Figure 4a This is a top view of the operational bits provided in an embodiment of the present invention.

[0032] Figure 4b This is a schematic cross-sectional view of the operational bits provided in an embodiment of the present invention.

[0033] Figure 5a This is a top view of the operational bits provided in another embodiment of the present invention.

[0034] Figure 5b This is a cross-sectional structural diagram of the operational bits provided in another embodiment of the present invention.

[0035] Figure 6 This is a cross-sectional structural diagram of the operational bits provided in another embodiment of the present invention.

[0036] Figure 7 This is a schematic flowchart of a method for preparing operational bits according to an embodiment of the present invention.

[0037] Figure 8 This is a flowchart illustrating a method for preparing operational bits according to another embodiment of the present invention.

[0038] Figure 9 This is a flowchart illustrating a method for preparing operational bits according to another embodiment of the present invention.

[0039] Figure 10 This is a flowchart illustrating a method for preparing operational bits according to another embodiment of the present invention.

[0040] Figure 11 This is a schematic diagram of the circuit structure of 0-π operation bits provided in an embodiment of the present invention.

[0041] Figure 12a This is a top view of a capacitor provided in an embodiment of the present invention.

[0042] Figure 12b This is a schematic cross-sectional view of a capacitor provided in an embodiment of the present invention.

[0043] Figure 13a This is a top view of the capacitor provided in another embodiment of the present invention.

[0044] Figure 13b This is a cross-sectional structural diagram of a capacitor provided in another embodiment of the present invention.

[0045] Figure 14 This is a schematic cross-sectional view of a parallel plate capacitor provided in an embodiment of the present invention. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Here, the illustrative embodiments and descriptions of the present invention are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be arbitrarily combined with each other. The acquisition, storage, use, and processing of data in the technical solutions of this application all comply with the relevant provisions of laws and regulations. The user information in the embodiments of this application is obtained through legal and compliant means, and the acquisition, storage, use, and processing of user information have been agreed upon by the customer.

[0047] To facilitate understanding of the technical solution provided in this application, the relevant content of the technical solution in this application will be explained below.

[0048] To address the issue that existing quantum resonant cavities employ a distributed LC meandering line design, which occupies a large planar area on the silicon wafer, this patent proposes to replace the distributed design with a lumped discrete inductor (L) and capacitor (C) design. Furthermore, the L and C components are directly fabricated on the sidewalls of a smooth through-silicon via (TSV), enabling independent design optimization of the L and C components and reducing the resonant cavity from the millimeter level to the hundred-micrometer level.

[0049] Figure 1a This is a schematic cross-sectional view of a three-dimensional resonant cavity provided in an embodiment of the present invention. Figure 1b This is a schematic diagram of the lumped capacitance structure of a three-dimensional resonant cavity provided in an embodiment of the present invention. Figure 1c This is a schematic diagram of the lumped inductor structure of a three-dimensional resonant cavity provided in an embodiment of the present invention. Figure 1b for Figure 1a Diagram of direction A in the middle. Figure 1c For example Figure 1a A schematic diagram of direction B is shown below. Figure 1a , Figure 1b and Figure 1c As shown, the three-dimensional resonant cavity provided in this embodiment of the invention includes a lumped capacitance 101 and a lumped inductance 102, wherein: The lumped capacitor 101 and the lumped inductor 102 are connected in parallel; The lumped capacitor 101 and the lumped inductor 102 are disposed on the sidewall of the first through-silicon via 103, which is disposed on the adapter plate 100; wherein the first through-silicon via 103 is prepared by wet etching.

[0050] Specifically, the three-dimensional resonant cavity proposed in this application can be applied to a computing unit. A lumped capacitor 101 and a lumped inductor 102 are disposed on the sidewall of the first through-silicon via 103, and the lumped capacitor 101 and lumped inductor 102 are connected in parallel. By placing the lumped capacitor 101 and lumped inductor 102 within the first through-silicon via 103, and since the sidewall of the first through-silicon via 103 is inclined, the planar area of ​​the silicon wafer occupied by the three-dimensional resonant cavity is reduced. This allows the resonant cavity, previously in the millimeter range, to be reduced to the hundreds of micrometer range, significantly reducing the size by 1-2 orders of magnitude and greatly improving the planar area utilization efficiency of the silicon wafer. Simultaneously, the resonant frequency can be maintained within the ideal quantum measurement and control frequency range, such as 4.37 GHz, while the intrinsic quality factor remains at a high-performance level greater than 3500.

[0051] To accommodate the lumped capacitance 101 and lumped inductance 102 within the first through-silicon via (TSV) 103, superconducting material needs to be deposited within it. The wet-etched TSV 103 has smooth and angled sidewalls (54.7°), which facilitates superconducting material deposition and significantly expands the compatibility of superconducting TSVs with various material systems. It also exhibits high compatibility with superconducting materials obtained through physical vapor deposition (PVD) and chemical vapor deposition (CVD), enabling a very wide range of sputtered superconducting material system compatibility. In contrast, TSVs formed by conventional dry deep reactive ion etching (DRIE) have steep sidewalls with pronounced scalloped edges, typically requiring atomic layer deposition (ALD) for electrical connections. However, there are currently no commercially available superconducting pure metal ALD (Alternating Current Discharge) devices. Most technologies use nitrides (such as TiN, NbN, and TaN) as superconducting sidewall fillers. However, the superconducting properties of these nitrides are highly sensitive to changes in stoichiometry; even small compositional deviations can lead to significant changes in the critical temperature (Tc), thus greatly limiting process repeatability and superconducting consistency. The superconducting transition of nitrides is strongly dependent on the atomic dose ratio, which is unfavorable for long-term and repeated use under extreme conditions. Furthermore, the Tc of the aforementioned nitride materials is typically lower than that of Nb. As one of the most widely used superconducting materials, Nb can achieve stable and reliable superconducting properties through mature magnetron sputtering processes. Simultaneously, under ambient pressure, Nb has the highest superconducting critical temperature among all elemental metals and exhibits strong resistance to thermal fluctuations at low temperatures, demonstrating good compatibility with other quantum device processes. Therefore, under the current technical conditions, this application proposes to set lumped capacitance and lumped inductance in the wet-etched TSV, providing a convenient and effective implementation path for realizing a miniaturized resonant cavity structure based on sputtered Nb.

[0052] In one embodiment, the lumped capacitor 101 can be an interdigitated capacitor (IDC), and the lumped inductor 102 can be a meander inductor. By changing parameters such as the linewidth, spacing, and total length of the interdigitated capacitor and the meander inductor, the intrinsic mode frequency can be flexibly adjusted to the required readout and control frequency band, facilitating the adjustment of the resonant frequency and quality factor.

[0053] The three-dimensional resonant cavity provided in this embodiment of the invention includes a lumped capacitor and a lumped inductor, which are connected in parallel. The lumped capacitor and the lumped inductor are disposed on the sidewall of a first through-silicon via (TSV), which is disposed on an adapter plate. The first TSV is prepared by wet etching. The occupied area of ​​the three-dimensional resonant cavity is on the order of hundreds of micrometers, reducing the planar area of ​​the silicon wafer occupied by the three-dimensional resonant cavity, which is beneficial to improving chip integration and increasing the planar area utilization efficiency of the silicon wafer. Furthermore, the TSV prepared by wet etching has tilted sidewalls, enabling full compatibility with mainstream superconducting thin film fabrication processes such as PVD and CVD, significantly broadening the selection boundaries of superconducting thin film fabrication processes.

[0054] Based on the above embodiments, the lumped capacitor 1 is further disposed near the first opening of the first through-silicon via 103, and the lumped inductor 102 is disposed near the second opening of the first through-silicon via 103.

[0055] In one embodiment, such as Figure 1a As shown, the first through-silicon via 103 has an upper opening (first opening) and a lower opening (second opening). The lumped capacitor 1 is disposed on the side wall near the upper opening of the first through-silicon via 103, and the lumped inductor 102 is disposed on the side wall near the lower opening of the first through-silicon via 103.

[0056] Based on the above embodiments, the lumped capacitor 101 and the lumped inductor 102 are further arranged around the sidewall of the first through-silicon via 103.

[0057] In one embodiment, the sidewalls of the first through-silicon via 103 are sequentially arranged in a clockwise direction as a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall. A lumped capacitor 101 is disposed on the first and second sidewalls of the first through-silicon via 103, and a lumped inductor 102 is disposed on the third and fourth sidewalls of the first through-silicon via 103.

[0058] In one embodiment, the sidewalls of the first through-silicon via 103 are sequentially arranged in a clockwise direction as a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall. A lumped capacitor 101 is disposed on the first sidewall of the first through-silicon via 103, and a lumped inductor 102 is disposed on the second, third, and fourth sidewalls of the first through-silicon via 103.

[0059] Based on the above embodiments, the size of the first opening of the first through-silicon via 103 is different from the size of the second opening.

[0060] Specifically, the size of the first opening of the first through-silicon via 103 is different from the size of the second opening, making the first through-silicon via 103 an asymmetrical double-funnel structure, which is beneficial for realizing flexible configuration and discrete design of lumped inductors and lumped capacitors.

[0061] Since wet etching of through-silicon vias is essentially formed by the intersection of two funnel-shaped contours at the top and bottom of the substrate, corresponding to a central opening greater than 0, an asymmetric TSV structure can be naturally achieved by designing different diameters for the first and second openings. This allows for independent optimization of the ratio of lumped capacitance to lumped inductance, thereby further improving the utilization efficiency of the silicon wafer's planar area.

[0062] Figure 2 This is a schematic flowchart of a method for fabricating a three-dimensional resonant cavity according to an embodiment of the present invention, as shown below. Figure 2 As shown, the method for fabricating a three-dimensional resonant cavity provided in this embodiment of the invention includes: S201. Hard masks are deposited on the two surfaces of the substrate respectively to obtain a first mask layer and a second mask layer; wherein the substrate is a double-polished silicon wafer with a (100) crystal plane; Specifically, a hard mask is deposited on one surface of the substrate to obtain a first mask layer, and a hard mask is deposited on the other surface of the substrate to obtain a second mask layer. The substrate is a double-polished silicon wafer with a (100) crystal plane. The silicon wafer can be a high-resistivity silicon wafer (HR-Si High Resistivity Silicon) or a regular silicon wafer. The resistivity of the substrate is selected according to actual needs, and is not limited in this embodiment of the invention. The hard mask includes, but is not limited to, silicon nitride, silicon oxide, etc.

[0063] Understandably, the two surfaces of the substrate are chemically and mechanically polished (CMP) to facilitate subsequent photolithography and thin film deposition; the oxide layer on the surface is removed by hydrofluoric acid cleaning and then cleaned with acetone-isopropanol (IPA)-DI deionized water.

[0064] In one embodiment, the resistivity of the substrate is greater than 10,000 Ω. cm.

[0065] In one embodiment, low-pressure chemical vapor deposition (LPCVD) can be used to deposit hard masks on two surfaces of the substrate to obtain a first mask layer and a second mask layer.

[0066] S202. A first opening pattern of the first through-silicon via is formed on the first mask layer, and a second opening pattern of the first through-silicon via is formed on the second mask layer; Specifically, photolithography is performed on the first mask layer to form a first aperture photoresist pattern for the first through-silicon via (TSV). Using the first aperture photoresist pattern as a mask, the first mask layer is etched to expose the substrate. The first aperture photoresist pattern is then transferred onto the first mask layer to form the first aperture pattern of the TSV. The remaining photoresist on the first mask layer is then removed. Photolithography is performed on the second mask layer to obtain a second aperture photoresist pattern for the first TSV. Using the second aperture photoresist pattern as a mask, the second mask layer is etched to expose the substrate. The second aperture photoresist pattern is then transferred onto the second mask layer to form the second aperture pattern of the first TSV. The remaining photoresist on the second mask layer is then removed. The first aperture pattern and the second aperture pattern are fabricated separately; the first aperture pattern can be fabricated first, followed by the second aperture pattern, or vice versa. This embodiment of the invention does not limit the specific fabrication process.

[0067] In this invention, photolithography can be performed using either spray lithography or spin lithography, depending on the specific requirements. The etching process can be dry etching, and the etching gas can be SF6. The size of the first aperture corresponding to the first aperture pattern and the size of the second aperture corresponding to the second aperture pattern can be equal or unequal, depending on the specific requirements. The size of the second aperture corresponding to the second aperture pattern is not limited in this invention.

[0068] S203. Based on the first aperture pattern and the second aperture pattern, a first through-silicon via is formed by wet etching. Specifically, a substrate having the first and second aperture patterns is immersed in an etching solution, and the substrate is wet-etched to form a first through-silicon via (TSV). The substrate with the first TSV formed is called an adapter board. The etching solution can be potassium hydroxide (KOH) solution, tetramethylammonium hydroxide (TMAH) solution, or a mixture of KOH and isopropanol, etc., selected according to actual needs; this embodiment of the invention does not limit the choice.

[0069] Understandably, after wet etching, deionized water can be used to thoroughly remove any remaining etching solution.

[0070] The first through-silicon via (TSV) obtained by wet etching exhibits high performance, with high coverage of the superconducting thin film and photoresist, and no open circuits appearing in the tip region. The superconducting transition temperature of 9.3K is close to that of Nb bulk material, and it can withstand 22 thermal cycles at a wide field speed (±20K / min) of 300-1.68-300K without performance degradation, showing high consistency in the cumulative distribution function (CDF). The critical current reaches 354mA, while the current requirement for conventional flux modulation is only a few mA. The critical current for typical flip-chip bonding in existing technologies is 20-30mA. This application significantly increases the critical current by one order of magnitude, which helps to enhance the current-carrying capacity and stability of superconducting interconnects, reduce parasitic nonideal stress, and realize a more reliable, low-loss three-dimensional interconnect structure for quantum chips.

[0071] S204. Remove the remaining first mask layer and second mask layer on the two surfaces of the substrate; Specifically, after forming the first through-silicon via, the remaining first and second mask layers on the two surfaces of the substrate are removed to expose the two surfaces of the substrate.

[0072] In one embodiment, double-sided reactive ion etching is used to remove the remaining first and second mask layers.

[0073] In one embodiment, a double-polished silicon wafer is used. After removing the remaining first and second mask layers on both surfaces of the substrate, a dielectric layer is thermally oxidized or deposited on both surfaces of the substrate and the sidewalls of the first through-silicon via (TSV), before subsequent superconducting material deposition. The dielectric layer serves to insulate the substrate from the subsequently deposited superconducting layer.

[0074] S205. Deposit superconducting material on the sidewall of the first through-silicon via to form a superconducting layer; Specifically, a superconducting material is deposited on the sidewall of the first through-silicon via (TSV) to form a superconducting layer. Simultaneously, superconducting materials are also deposited on both surfaces of the substrate. The superconducting material can be selected according to actual needs, such as niobium (Nb), and this embodiment of the invention does not limit its application. The deposition process can be physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), selected according to actual needs, and this embodiment of the invention does not limit its application.

[0075] In one embodiment, Nb is deposited on both surfaces of the substrate, and Nb is grown on the sidewalls of the first through-silicon via (TSV) to form a superconducting layer covering the sidewalls of the TSV.

[0076] S206. A lumped capacitor and a lumped inductor are sequentially fabricated on the superconducting layer on the sidewall of the first through hole.

[0077] Specifically, photolithography is performed on the superconducting layer to form a photoresist pattern of lumped capacitance on the superconducting layer on the sidewall of the first through-silicon via (TSV). Then, the superconducting layer is etched based on the photoresist pattern of lumped capacitance to obtain a lumped capacitor. Photolithography is performed on the superconducting layer to form a photoresist pattern of lumped inductance on the superconducting layer on the sidewall of the first TSV. Then, the superconducting layer is etched based on the photoresist pattern of lumped inductance to obtain a lumped inductor.

[0078] One approach is to first fabricate the lumped capacitor and then the lumped inductor; or, to first fabricate the lumped inductor and then the lumped capacitor.

[0079] Among them, photolithography can be carried out by spray photolithography, which can significantly improve the coverage of photoresist on the sidewalls inside the first through-silicon via compared with spin-coating photolithography.

[0080] In one embodiment, photoresist is first sprayed onto the first surface of the substrate and the superconducting layer within the first through-silicon via (TSV). Then, photolithography is used to obtain a wiring pattern and a photoresist pattern for the lumped capacitance on the first surface. Based on the wiring pattern and the photoresist pattern for the lumped capacitance on the first surface, the superconducting layer is etched to obtain the wiring and lumped capacitance on the first surface. Next, photoresist is sprayed onto the second surface of the substrate and the superconducting layer within the first TSV. Then, photolithography is used to obtain a wiring pattern and a photoresist pattern for the lumped inductance on the second surface. Based on the wiring pattern and the photoresist pattern for the lumped inductance on the second surface, the superconducting layer is etched to obtain the wiring and lumped inductance on the second surface. The wiring on the first and second surfaces includes, but is not limited to, signal lines, transmission lines, and pads, and is configured according to actual needs; this embodiment of the invention does not impose limitations.

[0081] The following specific embodiment illustrates the fabrication process of the three-dimensional resonant cavity provided in this invention.

[0082] Step 1: Deposit hard mask. Silicon oxide is deposited on the upper surface of substrate 300 to obtain the first mask layer 301, and silicon oxide is deposited on the lower surface of substrate 300 to obtain the second mask layer 302, as shown below. Figure 3a As shown. The substrate 300 is a double-polished high-resistivity silicon wafer with a (100) crystal plane; the resistivity of the substrate 300 is greater than 10,000 Ω. cm.

[0083] The second step is to obtain the aperture pattern. Photoresist is sprayed onto the first mask layer 301 to form a first photoresist layer. The first photoresist layer is aligned, exposed, and developed to obtain the first aperture photoresist pattern. Using the first aperture photoresist pattern as a mask, the first mask layer 301 is etched to expose the substrate 300. The first aperture photoresist pattern is transferred onto the first mask layer 301 to form the first aperture pattern. Then, the remaining photoresist on the first mask layer 301 is removed.

[0084] Photoresist is sprayed onto the second mask layer 302 to form a second photoresist layer. The second photoresist layer is aligned, exposed, and developed to obtain a second aperture photoresist pattern. Using the second aperture photoresist pattern as a mask, the second mask layer 302 is etched to expose the substrate 300. The second aperture photoresist pattern is then transferred onto the second mask layer 302 to form a second aperture pattern. Finally, the remaining photoresist on the second mask layer 302 is removed. The structure after obtaining the aperture pattern is as follows: Figure 3b As shown.

[0085] Step 3: Forming the first through-silicon via (TSV). The substrate with the first and second aperture patterns is immersed in a potassium hydroxide solution, and the substrate is wet-etched to form the first TSV 306 on the substrate 300. Figure 3c As shown, the sidewalls of the first through-silicon via 306 are inclined.

[0086] Step 4: Remove the remaining mask layers. After forming the first through-silicon via 306, remove the remaining first mask layer 301 and second mask layer 302 from the two surfaces of the substrate 300, exposing the two surfaces of the substrate 300, as shown below. Figure 3d As shown.

[0087] Step 5: Deposit superconducting material. Nb is deposited on both surfaces of the substrate 300, growing on the sidewalls of the first through-silicon via 306 to form a superconducting layer 307 covering the sidewalls of the first through-silicon via 306 and both surfaces of the substrate 300, as shown below. Figure 3e As shown.

[0088] Step 6: Fabrication of the lumped capacitor. Photoresist is sprayed onto the upper surface of the substrate 300 and the superconducting layer 307 within the first through-silicon via 306. Then, photolithography is used to obtain the wiring pattern on the upper surface and the photoresist pattern for the lumped capacitor. Based on the wiring pattern on the first surface and the photoresist pattern for the lumped capacitor, the superconducting layer 307 is etched to obtain the wiring and lumped capacitor on the upper surface. The lumped capacitor is fabricated on the upper half of the sidewall of the first through-silicon via 306.

[0089] Step 7: Fabrication of the lumped inductor. Photoresist is sprayed onto the lower surface of the substrate 300 and the superconducting layer 307 within the first through-silicon via 306. Then, photolithography is used to obtain the wiring pattern on the lower surface and the photoresist pattern for the lumped inductor. Based on the wiring pattern and the photoresist pattern for the lumped inductor, the superconducting layer 307 is etched to obtain the wiring and the lumped inductor on the lower surface. The lumped inductor is fabricated on the lower half of the sidewall of the first through-silicon via 306.

[0090] Figure 4a This is a top view schematic diagram of the operational bits provided in an embodiment of the present invention. Figure 4b This is a schematic cross-sectional view of the operational bits provided in an embodiment of the present invention. Figure 4b yes Figure 4a A schematic diagram of the CC section, as shown below. Figure 4a and 4b As shown, the operational bits provided in this embodiment of the invention include a Josephson junction 401 and a capacitor 402, wherein: Josephson junction 401 is connected in parallel with capacitor 402; Josephson junction 401 is disposed on adapter plate 400, and a groove 403 is provided on adapter plate 400, and capacitor 402 is disposed in groove 403; wherein, the sidewall of groove 403 is inclined to facilitate the fabrication of capacitor 402.

[0091] Specifically, a capacitor 402 is disposed within the groove 403. The capacitor 402 can be electrically connected to the Josephson junction 401 via a first interconnect 404 and a second interconnect 405. Since the sidewalls of the groove 403 are inclined, the planar area of ​​the silicon wafer occupied by the capacitor 402 is reduced, which is beneficial to improving the planar area utilization efficiency of the silicon wafer. To dispose of the capacitor 402 within the groove 403, superconducting material needs to be deposited on the sidewalls of the groove 403. The inclined sidewalls of the groove 403 facilitate the deposition of superconducting material, significantly expanding the compatibility material system for superconducting TSVs. The computational bits in this application can also be referred to as quantum bits.

[0092] In one embodiment, capacitor 402 includes a first electrode plate 4021, a second electrode plate 4022, and an intermediate dielectric layer 4023. The first electrode plate 4021 is electrically connected to a Josephson junction 401 via a first interconnect 404, and the second electrode plate 4022 is electrically connected to the Josephson junction 401 via a second interconnect 405. The first electrode plate 4021 and the second electrode plate 4022 are made of superconducting material, and the intermediate dielectric layer 4023 is made of insulating material, serving to insulate the first electrode plate 4021 and the second electrode plate 4022.

[0093] The operational bits provided in this embodiment of the invention, by placing capacitors within the grooves, reduce the area occupied by the capacitors, which is beneficial for improving integration density and increasing the planar area utilization efficiency of the silicon wafer. Furthermore, the inclined sidewalls of the grooves enable full compatibility with mainstream thin film fabrication processes such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), significantly broadening the selection boundaries for superconducting thin film fabrication processes.

[0094] Figure 5a This is a top view schematic diagram of the operational bits provided in another embodiment of the present invention. Figure 5b This is a cross-sectional structural diagram of the operational bits provided in another embodiment of the present invention. Figure 5b yes Figure 5a Schematic diagram of the cross-sectional structure of DD, as shown below Figure 5a and Figure 5b As shown, the operational bits provided in this embodiment of the invention include a Josephson junction 501 and a capacitor 502, wherein: Josephson junction 501 is connected in parallel with capacitor 502; Josephson junction 501 is disposed on adapter plate 500, and second through silicon via 503 is disposed on adapter plate 500. Capacitor is disposed in second through silicon via 503; wherein, second through silicon via 503 is prepared by wet etching.

[0095] Specifically, a capacitor 502 is disposed within the second through-silicon via (TSV) 503. The capacitor 502 can be electrically connected to the Josephson junction 501 via the third interconnect 505 and the fourth interconnect 504. Since the second TSV 503 is fabricated by wet etching and has inclined sidewalls, the planar area occupied by the capacitor 502 is reduced, which is beneficial for improving the planar area utilization efficiency of the silicon wafer. To accommodate the capacitor 502 within the second TSV 503, superconducting material needs to be deposited within it. The wet-etched second TSV 503 has smooth sidewalls and an inclination angle of 54.7°, which is conducive to the deposition of superconducting materials. This significantly expands the compatibility of superconducting TSVs with various materials, including PVD and CVD deposited superconducting materials, and enables a very wide range of sputtered superconducting material system compatibility.

[0096] The operational bits provided in this embodiment of the invention, by incorporating a capacitor within the second through-silicon via 503, reduce the area occupied by the capacitor, which is beneficial for improving integration density and increasing the planar area utilization efficiency of the silicon wafer. Furthermore, the inclined sidewalls of the second through-silicon via 503 enable full compatibility with mainstream thin film fabrication processes such as physical vapor deposition (PVD) and chemical vapor deposition (CVD), significantly broadening the selection boundaries for superconducting thin film fabrication processes.

[0097] like Figure 5a and Figure 5bAs shown, capacitor 502 includes a first electrode 5021, an intermediate dielectric layer 5023, and a second electrode 5022, wherein: An intermediate dielectric layer 5023 is disposed between the first electrode plate 5021 and the second electrode plate 5022; The first electrode plate 5021 and the second electrode plate 5022 are disposed on the sidewall of a second silicon through-hole 503; The first electrode 5021 or the second electrode 5022 is connected to the Josephson junction 501 through another second through-silicon via.

[0098] Specifically, the first electrode 5021 is connected to the Josephson junction 501 via the third interconnect 505, and the second electrode 5022 is connected to the Josephson junction 501 via the fourth interconnect 504, which passes through the sidewall of another second through-silicon via 503. The first electrode 5021 and the second electrode 5022 are made of superconducting material, and the intermediate dielectric layer 5023 is made of insulating material. The intermediate dielectric layer 5023 is used to achieve insulation between the first electrode 5021 and the second electrode 5022.

[0099] like Figure 4b As shown, based on the above embodiments, capacitor 402 is further disposed on the side wall and bottom of groove 403.

[0100] Figure 6 This is a cross-sectional structural diagram of the operational bits provided in another embodiment of the present invention. Figure 6 yes Figure 4a Another structural schematic diagram of the CC section, as shown below. Figure 6 As shown, capacitor 402 is disposed on the side wall of groove 403.

[0101] Figure 7 This is a schematic flowchart of a method for preparing operational bits according to an embodiment of the present invention, as shown below. Figure 7 As shown, the method for preparing operational bits provided in this embodiment of the invention includes: S701. A groove is formed on a substrate; wherein the substrate is a double-polished silicon wafer with a (100) crystal plane; the sidewalls of the groove are inclined. Specifically, grooves are formed on the substrate. The substrate is a double-polished silicon wafer with a (100) crystal plane. The resistivity of the substrate is selected according to actual needs, and is not limited in this embodiment of the invention. Hard masks include, but are not limited to, silicon nitride, silicon oxide, etc.

[0102] Understandably, the two surfaces of the substrate are chemically and mechanically polished to facilitate subsequent photolithography and thin film deposition; the oxide layer on the surface is removed by cleaning with hydrofluoric acid and then cleaned with acetone-isopropanol (IPA)-DI deionized water.

[0103] S702, A capacitor is formed in the groove; Specifically, a superconducting material is deposited on the sidewall of the groove to form a superconducting layer, and then a capacitor is fabricated on the superconducting layer on the sidewall of the groove. The superconducting material is selected according to actual needs, such as niobium (Nb), and this embodiment of the invention is not limited thereto. The deposition process can be physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), selected according to actual needs, and this embodiment of the invention is not limited thereto.

[0104] In one embodiment, Nb is deposited on the surface of a substrate with grooves, allowing Nb to grow on the sidewalls and bottom of the grooves to form a superconducting layer covering the sidewalls and bottom of the grooves. Then, photoresist is sprayed onto the substrate and the superconducting layer on the grooves, followed by photolithography to obtain wiring patterns on the substrate surface and photoresist patterns for the capacitor. Based on the wiring patterns on the substrate surface and the photoresist patterns for the capacitor, the superconducting layer is etched to obtain wiring on the substrate surface and the lower electrode of the capacitor within the grooves. Then, photoresist is sprayed onto the substrate and a dielectric is deposited, followed by photoresist spraying and photolithography to deposit the upper electrode on the dielectric, thus obtaining a complete metal-insulator-metal (MIM) capacitor. The wiring on the substrate surface includes, but is not limited to, signal lines, transmission lines, and pads, and is configured according to actual needs; this embodiment of the invention does not impose limitations.

[0105] S703. A Josephson junction is formed on the substrate and connected in parallel with the capacitor.

[0106] Specifically, a Josephson junction is fabricated on the substrate, and the resulting Josephson junction can be connected in parallel with the capacitor through wiring on the substrate surface.

[0107] Figure 8 This is a flowchart illustrating a method for preparing operational bits according to another embodiment of the present invention, as shown below. Figure 8 As shown, the method for preparing operational bits provided in this embodiment of the invention includes: S801. A second through-silicon via is formed by wet etching on the substrate; wherein the substrate is a double-polished silicon wafer with a crystal plane (100). Specifically, a second through-silicon via (TSV) is formed on the substrate by wet etching. The substrate is a double-polished silicon wafer with a crystal plane of 100°. The resistivity of the substrate is selected according to actual needs, and is not limited in this embodiment of the invention. The hard mask includes, but is not limited to, silicon nitride, silicon oxide, etc.

[0108] Understandably, the two surfaces of the substrate are chemically and mechanically polished (CMP) to facilitate subsequent photolithography and thin film deposition; the oxide layer on the surface is removed by hydrofluoric acid cleaning and then cleaned with acetone-isopropanol (IPA)-DI deionized water.

[0109] S802. A capacitor is formed within the second through-silicon via; Specifically, a superconducting material is deposited on the sidewall of the second through-silicon via (TSV) to form a superconducting layer, and then a capacitor is fabricated on the superconducting layer on the sidewall of the TSV. The superconducting material can be selected according to actual needs, such as niobium (Nb), and this embodiment of the invention is not limited thereto. The deposition process can be physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD), selected according to actual needs, and this embodiment of the invention is not limited thereto.

[0110] In one embodiment, Nb is deposited on both surfaces of the substrate, and Nb grows on the sidewalls of the second through-silicon via (TSV) to form a superconducting layer covering the sidewalls of the TSV. Photoresist is sprayed onto one surface of the substrate and the superconducting layer within the TSV, and then photolithography is performed to obtain wiring patterns on the substrate surface and photoresist patterns for capacitors. Based on the wiring patterns and photoresist patterns on the substrate surface, the superconducting layer is photolithographically lithographically processed to obtain wiring and capacitors on the substrate surface. The wiring on the substrate surface includes, but is not limited to, signal lines, transmission lines, and pads, and is configured according to actual needs; this embodiment of the invention does not impose limitations.

[0111] S803. A Josephson junction is formed on the substrate and connected in parallel with the capacitor.

[0112] Specifically, a Josephson junction is fabricated on the substrate, and the resulting Josephson junction can be connected in parallel with the capacitor through wiring on the substrate surface.

[0113] Figure 9 This is a flowchart illustrating a method for preparing operational bits according to another embodiment of the present invention, as shown below. Figure 9 As shown, based on the above embodiments, the wet etching process for forming the second through-silicon via further includes: S901. Deposit hard masks on two surfaces of the substrate respectively to obtain a third mask layer and a fourth mask layer; Specifically, a hard mask is deposited on one surface of the substrate to obtain a third mask layer, and a hard mask is deposited on the other surface of the substrate to obtain a fourth mask layer. The specific implementation process of this step is similar to that of step S201, and will not be described in detail here.

[0114] S902, A third opening pattern of the second through-silicon via is formed on the third mask layer, and a fourth opening pattern of the second through-silicon via is formed on the fourth mask layer; Specifically, photolithography is performed on the third mask layer to form a third aperture photoresist pattern for the second through-silicon via (TSV). Using this third aperture photoresist pattern as a mask, the third mask layer is etched to expose the substrate. The third aperture photoresist pattern is then transferred onto the third mask layer to form the third aperture pattern for the second TSV. The remaining photoresist on the third mask layer is then removed. Photolithography is performed on the fourth mask layer to obtain a fourth aperture photoresist pattern for the fourth TSV. Using this fourth aperture photoresist pattern as a mask, the fourth mask layer is etched to expose the substrate. The fourth aperture photoresist pattern is then transferred onto the fourth mask layer to form the fourth aperture pattern for the second TSV. The remaining photoresist on the fourth mask layer is then removed. The third and fourth aperture patterns are fabricated separately; the third aperture pattern can be fabricated first, followed by the fourth aperture pattern; or the fourth aperture pattern can be fabricated first, followed by the third aperture pattern. This embodiment of the invention does not limit the specific fabrication process.

[0115] S903. Based on the third and fourth aperture patterns, a second through-silicon via is formed by wet etching.

[0116] Specifically, the substrate having the third and fourth opening patterns is immersed in an etching solution, and the substrate is wet-etched to form a second through-silicon via (TSV). The substrate with the second TSV is referred to as an adapter board in this application. The etching solution can be potassium hydroxide (KOH) solution, tetramethylammonium hydroxide (TMAH), or a mixture of KOH and isopropanol, selected according to actual needs; this embodiment of the invention does not limit the choice.

[0117] Understandably, after wet etching, deionized water can be used to thoroughly remove any remaining etching solution.

[0118] Figure 10 This is a flowchart illustrating a method for preparing operational bits according to another embodiment of the present invention, as shown below. Figure 10 As shown, based on the above embodiments, further, forming a groove on the substrate includes: S1001. Deposit a hard mask on the surface of the substrate to obtain the fifth mask layer; Specifically, a hard mask is deposited on one surface of the substrate to obtain a fifth mask layer. The hard mask includes, but is not limited to, silicon nitride and silicon oxide.

[0119] S1002. A groove pattern is formed on the fifth mask layer; Specifically, photolithography is performed on the fifth mask layer to form a groove photoresist pattern on the fifth mask layer, and then the remaining photoresist on the fifth mask layer is removed. Using the groove photoresist pattern as a mask, the fifth mask layer is etched to expose the substrate, and the groove photoresist pattern is transferred onto the fifth mask layer to form a groove pattern.

[0120] S1003. Based on the groove pattern, form the groove.

[0121] Specifically, the substrate with the groove pattern is immersed in an etching solution, and the substrate is wet-etched to form grooves on the substrate. The substrate with the grooves formed is referred to as an adapter plate in this application. The etching solution can be potassium hydroxide (KOH) solution, tetramethylammonium hydroxide (TMAH), or a mixture of KOH and isopropanol, selected according to actual needs; this embodiment of the invention does not limit the choice.

[0122] Understandably, after wet etching, deionized water can be used to thoroughly remove any remaining etching solution.

[0123] Figure 11 This is a top view schematic diagram of the 0-π operation bits provided in an embodiment of the present invention, as shown below. Figure 11 As shown, the 0-π operands include two Josephson junctions 1101, two capacitors 1102, two superinductors 1104, and four superconducting nodes 1105. Each Josephson junction 1101 is connected to a capacitor 1102 via a superconducting node. Each superinductor 1104 includes multiple Josephson junctions connected in series. The superconducting nodes 1105 are coupling connection regions for different components. The 0-π operands in this application can also be referred to as 0-π quantum bits.

[0124] In existing technologies, the two capacitors for the 0-π operands are planar interdigitated capacitors, occupying a large amount of silicon wafer space, far exceeding the size of a Josephson junction. Josephson junctions are typically on the order of hundreds of nanometers, resulting in a large overall area for the 0-π operands, making effective miniaturization and high-density scaling impossible. Since the interdigitated capacitors and the Josephson junction are on the same plane, ports need to be led out from the four superconducting nodes for their arrangement, leading to the fabrication of long, unused interconnects outside the junction region, wasting silicon wafer space and increasing uncertainty in meeting the stringent performance design specifications of the 0-π operands. Therefore, this application proposes miniaturizing the capacitors. While maintaining the original symmetry of the 0-π operands, the capacitors are placed within grooves or through-silicon vias (TSVs), reducing the planar area occupied by the capacitors and shrinking the physical size of the 0-π operands, thereby improving the utilization rate of the silicon wafer's planar space.

[0125] Figure 12a This is a schematic diagram of a planar structure of a capacitor provided in an embodiment of the present invention. Figure 12b This is a schematic cross-sectional view of a capacitor provided in an embodiment of the present invention. Figure 12b yes Figure 12a Schematic diagram of the EE cross section, as shown Figure 11 , Figure 12a and Figure 12b As shown, the 0-π operation bits provided in this embodiment of the invention include two capacitors 1102, wherein: Two grooves 1103 are provided on the adapter plate 1100, and each capacitor is disposed in the groove 1103; wherein, the sidewall of the groove 1103 is inclined to facilitate the fabrication of the capacitor 1102.

[0126] Specifically, a capacitor 1102 is disposed within the recess 1103, and the capacitor 1102 can be electrically connected to the Josephson junction 1101 through the superconducting node 1105. Since the sidewalls of the recess 1103 are inclined, the planar area of ​​the silicon wafer occupied by the capacitor 1102 is reduced, which is beneficial to improving the planar area utilization efficiency of the silicon wafer. To dispose of the capacitor 1102 within the recess 1103, superconducting material needs to be deposited within the recess 1103. The inclined sidewalls of the recess 1103 facilitate the deposition of superconducting material, which can significantly expand the compatible material system for superconducting TSVs.

[0127] In one embodiment, capacitor 1102 is a metal-insulator-metal (MIM) capacitor, including a first electrode 11021 and a second electrode 11022. The first electrode 11021 includes a first common electrode 110211 and two first sheet electrodes 110212, and the second electrode 11022 includes a second common electrode 110221 and two second sheet electrodes 110222. The two first sheet electrodes 110212 and the two second sheet electrodes 110222 are alternately interleaved, and an intermediate dielectric layer 11023 is disposed between adjacent first sheet electrodes 110212 and second sheet electrodes 110222. The first electrode 11021 and the second electrode 11022 are made of superconducting material, and the intermediate dielectric layer 11023 is used to achieve insulation between the first sheet electrodes 110212 and the second sheet electrodes 110222.

[0128] Figure 13a This is a top view of a capacitor provided in another embodiment of the present invention. Figure 13b This is a cross-sectional structural diagram of a capacitor provided in another embodiment of the present invention. Figure 13b yes Figure 13a Schematic diagram of the FF cross section, as shown Figure 11 , Figure 13a and Figure 13b As shown, the 0-π operation bits provided in this embodiment of the invention include two capacitors 1102, wherein: The adapter board 1100 is provided with multiple third through silicon vias 1106, and each capacitor 1102 is disposed in the third through silicon via 1106; wherein, the third through silicon via 1106 is prepared by wet etching.

[0129] Specifically, a capacitor 1102 is placed within the third through-silicon via 1106, and the capacitor 1102 can be connected to the Josephson junction 1101 through a superconducting node 1105. Since the third through-silicon via 1106 is fabricated by wet etching and has inclined sidewalls, the planar area of ​​the silicon wafer occupied by the capacitor 1102 is reduced, which is beneficial to improving the planar area utilization efficiency of the silicon wafer. To place the capacitor 1102 within the third through-silicon via 1106, superconducting material needs to be deposited within the third through-silicon via 1106. The wet-etched third through-silicon via 1106 has smooth sidewalls and an inclination angle of 54.7°, which is conducive to the deposition of superconducting materials. This significantly expands the compatible material system of superconducting TSVs and also has high compatibility with superconducting materials deposited by PVD and CVD, achieving a very wide range of sputtered superconducting material system compatibility.

[0130] like Figure 13a and Figure 13b As shown, based on the above embodiments, capacitor 1102 is further defined as a MIM capacitor, which includes a first plate 11021 and a second plate 11022, wherein: The first electrode plate 11021 includes a first common electrode 110211 and a plurality of first sheet electrodes 110212, and the second electrode plate 11022 includes a second common electrode 110221 and a plurality of second sheet electrodes 110222. The plurality of first sheet electrodes 110212 and the plurality of second sheet electrodes 110222 are arranged alternately, and an intermediate dielectric layer 11023 is provided between adjacent first sheet electrodes 110212 and second sheet electrodes 110222.

[0131] The plurality of first sheet electrodes 110212 and the plurality of second sheet electrodes 110222 are disposed on the sidewall of a third through-silicon via 1106.

[0132] The first common electrode 110211 or the second common electrode 110221 is disposed on the sidewall of another third through-silicon via 1106.

[0133] This application reduces the planar area of ​​the silicon wafer occupied by the MIM capacitor by placing the sheet electrode and the common electrode on the sidewall of the third through-silicon via.

[0134] In one embodiment, the capacitor is disposed on the sidewall of the groove 1103, or on the sidewall and bottom of the groove 1103.

[0135] In one embodiment, the capacitors included in the 0-π operation bits are deep trench capacitors, which are disposed on the adapter plate 1100, and the adapter plate 1100 has trenches that can accommodate the deep trench capacitors.

[0136] like Figure 14As shown, the capacitors included in the 0-π operation bits are flat plate capacitors 1401, and silicon vias 1402 are provided on the adapter board 1400. The flat plate capacitors 1401 are located in the fourth silicon via 1402.

[0137] Specifically, two electrode plates of a planar capacitor 1401 are disposed on the sidewall of the fourth silicon via 1402.

[0138] The present invention provides a computing unit comprising the operational bits described in any of the above embodiments, and the three-dimensional resonant cavity described in any of the above embodiments.

[0139] Specifically, the operation bits and the three-dimensional resonant cavity are coupled. Since the capacitor of the operation bits is set in the groove or the second through-silicon via, and the three-dimensional resonant cavity is set in the first through-silicon via, the planar area of ​​the silicon wafer occupied by the operation bits and the three-dimensional resonant cavity can be reduced, thereby reducing the planar area of ​​the silicon wafer occupied by the computing unit, thereby improving the utilization rate of the planar area of ​​the silicon wafer and improving the integration of the computing unit.

[0140] The present invention provides a computing unit comprising 0-π operation bits as described in any of the above embodiments, and a three-dimensional resonant cavity as described in any of the above embodiments.

[0141] Specifically, the operation bits and the three-dimensional resonant cavity are coupled. Since the capacitors of the 0-π operation bits are set in the groove or the second through-silicon via, and the three-dimensional resonant cavity is set in the first through-silicon via, the planar area of ​​the silicon wafer occupied by the operation bits and the three-dimensional resonant cavity can be reduced, thereby reducing the planar area of ​​the silicon wafer occupied by the computing unit, thereby improving the utilization rate of the planar area of ​​the silicon wafer and improving the integration of the computing unit.

[0142] This invention provides a superconducting quantum processor that employs the computing unit described in the above embodiments.

[0143] In the description of this specification, the references to terms such as "an embodiment," "a specific embodiment," "some embodiments," "for example," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0144] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A three-dimensional resonant cavity, characterized in that, Includes lumped capacitance and lumped inductance, where: The lumped capacitor is connected in parallel with the lumped inductor; The lumped capacitor and the lumped inductor are disposed on the sidewall of the first through-silicon via (TSV), which is disposed on the adapter plate; wherein the first TSV is prepared by wet etching.

2. The three-dimensional resonant cavity according to claim 1, characterized in that, The lumped capacitor is located near the first opening of the first through-silicon via, and the lumped inductor is located near the second opening of the first through-silicon via.

3. The three-dimensional resonant cavity according to claim 1, characterized in that, The lumped capacitor and the lumped inductor are disposed around the sidewall of the first through-silicon via.

4. The three-dimensional resonant cavity according to any one of claims 1 to 3, characterized in that, The size of the first opening of the first through-silicon via is different from the size of the second opening.

5. A method for fabricating a three-dimensional resonant cavity, characterized in that, include: Hard masks are deposited on two surfaces of a substrate to obtain a first mask layer and a second mask layer; wherein the substrate is a double-polished silicon wafer with a (100) crystal plane; A first aperture pattern of the first through-silicon via is formed on the first mask layer, and a second aperture pattern of the first through-silicon via is formed on the second mask layer; Based on the first aperture pattern and the second aperture pattern, a first through-silicon via is formed by wet etching; Remove the remaining first mask layer and second mask layer on both surfaces of the substrate; A superconducting material is deposited on the sidewall of the first through-silicon via to form a superconducting layer; A lumped capacitor and a lumped inductor are sequentially fabricated on the superconducting layer on the sidewall of the first through-silicon via.

6. An operational bit, characterized in that, Including Josephson junctions and capacitors, where: The Josephson junction is connected in parallel with the capacitor; The Josephson junction is disposed on an adapter plate, and a groove or a second through-silicon via is provided on the adapter plate. The capacitor is disposed in the groove or the second through-silicon via. The second through-silicon via is prepared by wet etching, and the sidewall of the groove is inclined to facilitate the preparation of the capacitor.

7. The operational bits according to claim 6, characterized in that, The capacitor includes a first plate, an intermediate dielectric layer, and a second plate, wherein: The intermediate dielectric layer is disposed between the first electrode plate and the second electrode plate; The first electrode and the second electrode are disposed on the sidewall of a second through-silicon via; The first electrode or the second electrode is connected to the Josephson junction through another second through-silicon via.

8. The operational bits according to claim 6, characterized in that, The capacitor is disposed on the side wall of the groove, or on the side wall and bottom of the groove.

9. A method for preparing operational bits, characterized in that, include: A groove is formed on the substrate or a second through-silicon via is formed by wet etching; wherein the substrate is a double-polished silicon wafer with a (100) crystal plane; the sidewalls of the groove are inclined; A capacitor is formed within the groove or the second through-silicon via; A Josephson junction is fabricated on the substrate and connected in parallel with the capacitor.

10. The method according to claim 9, characterized in that, The wet etching process for forming the second through-silicon via includes: Hard masks are deposited on two surfaces of the substrate to obtain a third mask layer and a fourth mask layer; A third opening pattern of the second through-silicon via is formed on the third mask layer, and a fourth opening pattern of the second through-silicon via is formed on the fourth mask layer; Based on the third and fourth aperture patterns, a second through-silicon via (TSV) is formed by wet etching.

11. The method according to claim 9, characterized in that, The process of forming a groove on the substrate includes: A hard mask is deposited on the surface of the substrate to obtain a fifth mask layer; A groove pattern is formed on the fifth mask layer; The groove is formed based on the groove pattern.

12. A 0-π operation bit, characterized in that, Includes two capacitors, wherein: The adapter board is provided with two grooves or multiple third through-silicon vias, and each capacitor is disposed in the groove or the third through-silicon via; wherein, the third through-silicon via is prepared by wet etching, and the sidewall of the groove is inclined to facilitate the preparation of the capacitor.

13. The 0-π operation bits according to claim 12, characterized in that, The capacitor is a metal-insulator-metal capacitor, which includes a first plate and a second plate, wherein: The first electrode plate includes a first common electrode and a plurality of first sheet electrodes, and the second electrode plate includes a second common electrode and a plurality of second sheet electrodes. The plurality of first sheet electrodes and the plurality of second sheet electrodes are interleaved and interspersed, and an intermediate dielectric layer is disposed between adjacent first sheet electrodes and second sheet electrodes. The plurality of first sheet electrodes and the plurality of second sheet electrodes are disposed on the sidewall of a third through-silicon via; The first common electrode or the second common electrode is disposed on the sidewall of another third through-silicon via.

14. The 0-π operation bits according to claim 12, characterized in that, The capacitor is disposed on the side wall of the groove, or on the side wall and bottom of the groove.

15. A computing unit, characterized in that, It includes the operational bits as described in any one of claims 6 to 8, or the 0-π operational bits as described in any one of claims 12 to 14, and the three-dimensional resonant cavity as described in any one of claims 1 to 4.

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