Display device and display control method

Abstract

The application discloses a display device and a display control method, relates to the display field, and discloses the display device which comprises a time sequence controller, a power manager, a line frequency detection module, a power frequency detection module and a comparison control module. The line frequency detection module is used for receiving a display time sequence signal output by the time sequence controller to obtain a line frequency detection value. The power frequency detection module is used for collecting a frequency signal of the power manager to obtain a power frequency detection value. The comparison control module is used for adjusting the working frequency of the power manager when the absolute difference between the detection ratio and the preset integer multiple is less than the preset offset, wherein the detection ratio is the ratio between the line frequency detection value and the power frequency detection value. The application solves the problem of poor display quality caused by water ripples.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to display devices and display control methods. Background Technology

[0002] For display devices such as LCD (Liquid Crystal Display) and OLED (Organic Light-Emitting Diode), during the horizontal scanning process, the power supply rails (such as AVDD (Analog VDD) and AVEE (Analog VEE)) of the display panel exhibit regular dynamic current changes. The power management system (PMIC) that supplies power to the display panel in the display device typically adopts a switching DC-DC (DC-DC Converter) architecture. When the PMIC is working, it inevitably introduces ripple related to the PMIC's operating frequency onto the power supply rails.

[0003] During use, it was found that in some cases, the frequency of dynamic current changes and the operating frequency of the PMIC can affect each other, resulting in a significant amplification of ripples. This can cause water ripples on the display screen, such as slowly moving stripes or local brightness fluctuations, which affect the display quality.

[0004] The above content is only used to help understand the technical solutions of the embodiments of this application, and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this application is to provide a display device and a display control method, which aims to solve the technical problem of poor display quality caused by water ripples.

[0006] To achieve the above objectives, embodiments of this application provide a display device, which includes a timing controller, a power manager, a horizontal frequency detection module, a power frequency detection module, and a comparison control module; The first output terminal of the timing controller is connected to the input terminal of the line frequency detection module, and the output terminal of the line frequency detection module is connected to the first input terminal of the comparison control module. The input terminal of the power frequency detection module is connected to the frequency detection terminal of the power manager, the output terminal of the power frequency detection module is connected to the second input terminal of the comparison control module, and the output terminal of the comparison control module is connected to the frequency control terminal of the power manager. The line frequency detection module is used to receive the display timing signal output by the timing controller in order to detect the line frequency detection value; The power frequency detection module is used to collect the frequency signal of the power manager in order to detect the power frequency detection value. The comparison control module is used to adjust the operating frequency of the power manager when the absolute difference between the detection ratio and a preset integer multiple is less than a preset offset, wherein the detection ratio is the ratio between the horizontal frequency detection value and the power frequency detection value.

[0007] In one embodiment, the line frequency detection module further includes a first pulse shaping unit, a charge conversion unit, and an integral filtering unit connected in sequence; The input terminal of the first pulse shaping unit is connected to the first output terminal of the timing controller, and the output terminal of the integral filtering unit is connected to the first input terminal of the comparison control module. The first pulse shaping unit is used to shape the display timing signal into a first standard pulse signal with a preset first stable width; The charge conversion unit is used to convert the first standard pulse signal into charge. The integral filtering unit is used to integrate the charge output by the charge conversion unit and output the line frequency detection value.

[0008] In one embodiment, the charge conversion unit includes a first switching transistor, a current source, and a first capacitor; the integral filtering unit includes a first operational amplifier, a second operational amplifier, a second capacitor, and a first resistor. The control terminal of the first switching transistor is connected to the output terminal of the first pulse shaping unit, the first terminal of the first switching transistor is used to connect to a preset power supply terminal, and the second terminal of the first switching transistor is connected to the first terminal of the current source. The second end of the current source is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to a preset low voltage terminal. The first end of the first capacitor is connected to the first end of the first resistor, the second end of the first resistor is connected to the negative input terminal of the first operational amplifier, and the positive input terminal of the first operational amplifier is connected to the preset low voltage terminal. The second capacitor is disposed between the negative input terminal and the output terminal of the first operational amplifier; The output terminal of the first operational amplifier is connected to the positive input terminal of the second operational amplifier, the negative input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier outputs the line frequency detection value.

[0009] In one embodiment, the power frequency detection module includes an input filtering unit, a second pulse shaping unit, and a frequency conversion unit connected in sequence. The input filtering unit is connected to the frequency detection terminal, and the output terminal of the frequency conversion unit is connected to the second input terminal of the comparison control module. The input filtering unit is used to filter the frequency signal sampled at the frequency detection terminal, and the second pulse shaping unit is used to shape the signal output by the input filtering unit into a second standard pulse signal with a preset second stable width. The frequency conversion unit is used to output the power frequency detection value based on the second standard pulse signal.

[0010] In one embodiment, the input filtering unit includes a filter resistor, a filter capacitor, a first diode, and a second diode; the frequency conversion unit includes a second switch, a second resistor, a third resistor, a third capacitor, and a third operational amplifier. The first end of the filter resistor is connected to the frequency detection terminal, the second end of the filter resistor is connected to the first end of the filter capacitor, and the second end of the filter capacitor is connected to the preset low voltage terminal. The anode of the first diode is connected to a preset power supply terminal, the cathode of the first diode is connected to the second terminal of the filter resistor, the cathode of the second diode and the input terminal of the second pulse shaping unit, and the anode of the second diode is connected to a preset low voltage terminal. The output terminal of the second pulse shaping unit is connected to the control terminal of the second switching transistor. The first terminal of the second switching transistor is connected to the first terminal of the second resistor, the first terminal of the third capacitor, and the positive input terminal of the third operational amplifier. The second terminal of the third capacitor is connected to a preset low voltage terminal. The second terminal of the second switch is connected to the first terminal of the third resistor, and the second terminal of the third resistor is connected to a preset low voltage terminal. The negative input terminal of the third operational amplifier is connected to the output terminal of the third operational amplifier, and the output terminal of the third operational amplifier outputs the power supply frequency detection value.

[0011] In one embodiment, the comparison control module includes a comparison unit and a frequency control unit; The first comparison terminal of the comparison unit is used as the first input terminal of the comparison control module, and the second comparison terminal of the comparison unit is used as the second input terminal of the comparison control module. The output terminal of the comparison unit is connected to the input terminal of the frequency control unit, and the control terminal of the frequency control unit is connected to the second output terminal of the timing controller. The comparison unit is used to output a comparison level based on the line frequency detection value and the power frequency detection value. When the absolute difference between the ratio of the line frequency detection value and the power frequency detection value and a preset integer multiple is less than a preset offset, the comparison level output by the comparison unit is a preset risk level. The frequency control unit is used to adjust the operating frequency of the power manager during the blanking phase when the comparison level output by the comparison unit is a preset risk level.

[0012] In one embodiment, the comparison unit includes an interval generation circuit and a judgment circuit; The first reference terminal of the judgment circuit is used as the first comparison terminal of the comparison unit, and the second reference terminal of the interval generation circuit is used as the second comparison terminal of the comparison unit. The output terminal of the interval generation circuit is connected to the input terminal of the judgment circuit, and the judgment circuit is used to output a comparison level.

[0013] In one embodiment, the comparison unit includes an interval generation circuit and a judgment circuit, wherein the interval generation circuit includes an offset generation branch and at least one interval generation branch; The first reference terminal of the judgment circuit is used as the first comparison terminal of the comparison unit, and the second reference terminal of the interval generation circuit is used as the second comparison terminal of the comparison unit; the judgment circuit is used to output the comparison level. The input terminal of the offset generation branch is connected to a preset interval width control voltage, and the offset generation branch is used to output the offset amount based on the preset interval width control voltage. For each interval generation branch, the branch input terminal of the interval generation branch is connected to the second reference terminal, the offset input terminal of the interval generation branch is connected to the output terminal of the offset generation branch, and the first and second output terminals of the interval generation branch are both connected to the input terminal of the judgment circuit. The first output terminal of the interval generation branch is used to output the upper limit value of the multiple interval corresponding to the preset integer multiple, and the second output terminal of the interval generation branch is used to output the lower limit value of the multiple interval. The preset integer multiples corresponding to the branch generated in each interval are different.

[0014] In one embodiment, the offset generation branch includes a first-width resistor, a second-width resistor, and a first voltage buffer; The interval generation branch includes a multiple generation sub-branch, an adder, and a subtractor. The multiple generation sub-branch is used to generate a preset integer multiple voltage that is a preset integer multiple of the power supply frequency detection value. The first end of the first width resistor is connected to a preset interval width control voltage, the second end of the first width resistor is connected to the first end of the second width resistor, and the second end of the second width resistor is connected to a preset low voltage end. The input terminal of the first voltage buffer is connected to the second terminal of the first width resistor, and the output terminal of the first voltage buffer serves as the output terminal of the offset generation branch. The multiplier generation sub-branch includes a first branch resistor, a second branch resistor, and a second voltage buffer; The first end of the first branch resistor is connected to the power frequency detection value, the second end of the first branch resistor is connected to the first end of the second branch resistor, and the second end of the second branch resistor is connected to a preset low level. The input terminal of the second voltage buffer is connected to the second terminal of the first branch resistor, and the output terminal of the second voltage buffer is connected to the first terminal of the adder and the first terminal of the subtractor. The offset input terminal of the interval generation branch includes the second terminal of the adder and the second terminal of the subtractor, and the offset input terminal is connected to the output terminal of the offset generation branch.

[0015] In one embodiment, the determination circuit includes an OR gate and at least one determination branch. The first reference terminal of the determination circuit includes the first input terminal of the determination branch, and the input terminal of the determination circuit includes the second input terminal of the determination branch. The determination branch includes an upper limit comparator, a lower limit comparator, and an AND gate. The first input terminal of the decision branch includes the negative input terminal of the upper limit comparator and the positive input terminal of the lower limit comparator; the second input terminal of the decision branch includes the positive input terminal of the upper limit comparator and the negative input terminal of the lower limit comparator. For each decision branch, the positive input of the upper limit comparator in the decision branch is connected to the first output of the interval generation branch in the interval generation circuit, and the negative input of the lower limit comparator in the decision branch is connected to the second output of the interval generation branch. Different decision branches are connected to different interval generation branches. The output of the upper limit comparator is connected to the first terminal of the AND gate, the output of the lower limit comparator is connected to the second terminal of the AND gate, the output of the AND gate is connected to the input of the OR gate, and the output of the OR gate outputs a comparison level.

[0016] Furthermore, to achieve the above objectives, embodiments of this application also provide a display control method, which is applied to the display device described above, and the display control method further includes: The horizontal frequency detection value and the power frequency detection value of the display device are obtained, and the detection ratio value is calculated based on the ratio of the horizontal frequency detection value to the power frequency detection value. If the absolute difference between the detection ratio and a preset integer multiple is less than a preset offset, the target frequency is determined from multiple preset frequency levels based on the power frequency detection value. Control the power manager to operate at the target frequency to adjust the operating frequency of the power manager.

[0017] One or more technical solutions proposed in this application have at least the following technical effects: The display device of this application includes a timing controller, a power manager, a horizontal frequency detection module, a power frequency detection module, and a comparison control module. Since the dynamic current change on the power supply rail is generated along with the horizontal scanning process, the dynamic current change is related to the horizontal frequency. Therefore, by detecting the display timing signal through the horizontal frequency detection module, a horizontal frequency detection value that reflects the horizontal frequency can be obtained in real time. Then, the horizontal frequency detection value and the power frequency detection value detected by the power frequency detection module can be used to determine whether the operating frequency of the power manager needs to be adjusted. In the research process, this application found that when the horizontal frequency is an integer multiple of the power manager's operating frequency, the ripple will be significantly amplified, resulting in a water ripple. Therefore, this application obtains the horizontal frequency detection value through the horizontal frequency detection module and the power frequency detection value through the power frequency detection module. The comparison control module accurately determines whether the horizontal frequency detection value and the power frequency detection value are integer multiples or close to integer multiples, thereby improving the reliability of the judgment.

[0018] In this embodiment, when the absolute difference between the detection ratio (the ratio between the horizontal frequency detection value and the power frequency detection value) and a preset integer multiple is less than a preset offset, the operating frequency of the power manager can be adjusted to disrupt the integer multiple relationship between the horizontal frequency and the operating frequency of the power manager. This can suppress the significant amplification of ripple, eliminate or reduce water ripple phenomena such as slowly moving stripes and local brightness fluctuations in the display screen, thereby improving display quality. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of the embodiments of this application.

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a module of a display device according to an embodiment of this application; Figure 2 This is a schematic diagram of the line frequency detection module in the display device according to an embodiment of this application; Figure 3 This is a circuit diagram of the line frequency detection module in the display device according to an embodiment of this application; Figure 4 This is a schematic diagram of the power frequency detection module in the display device according to an embodiment of this application; Figure 5 This is a circuit diagram of the power frequency detection module in the display device according to an embodiment of this application; Figure 6 This is a schematic diagram of a comparison control module in a display device according to an embodiment of the present application, which includes a comparison unit and a frequency control unit; Figure 7 This is a schematic diagram of a comparison unit in a display device according to an embodiment of the present application, including an interval generation circuit and a judgment circuit; Figure 8 This is a schematic diagram of the interval generation circuit in the display device according to an embodiment of this application; Figure 9 This is a circuit diagram of the offset generation branch in the display device according to an embodiment of this application; Figure 10 This is a circuit diagram of the offset generation branch and multiple interval generation branches in the display device of the present application embodiment; Figure 11 This is a circuit diagram of the judgment circuit in the display device according to an embodiment of this application; Figure 12 This is a flowchart illustrating one embodiment of the control method in this application. Figure 13 This is a flowchart illustrating an example of a control method in an embodiment of this application.

[0022] Explanation of icon numbers: 100. Timing Controller; 200. Power Manager; 300. Horizontal Frequency Detection Module; 400. Power Frequency Detection Module; 500. Comparison Control Module; 310. First Pulse Shaping Unit; 320. Charge Conversion Unit; 330. Integrating Filter Unit; SW1. First Switch; VDD. Preset Power Supply Terminal; VSS. Preset Low Voltage Terminal; R1. First Resistor; C1. First Capacitor; C2. Second Capacitor; op1. First Operational Amplifier; op2. Second Operational Amplifier; Is. Current Source; HSYC. Horizontal Synchronization Signal; VFH. Horizontal Frequency Voltage; 410 Input filtering unit; 420 Second pulse shaping unit; 430 Frequency conversion unit; Ra, filter resistor; Ca, filter capacitor; D1, first diode; D2, second diode; SW2, second switch; R2, second resistor; R3, third resistor; op3, third operational amplifier; C3, third capacitor; VSW, power supply frequency voltage; 510 Comparison unit; 520 Frequency control unit; 511 Interval generation circuit; 512 Judgment circuit; VREF, preset interval width control voltage; 60 Offset generation branch; 61~6m, multiple interval generation branches; Rk1, first width resistor; Rk2, second width resistor; BUF1, first voltage buffer; 611, multiple generation sub-branch in interval generation branch 61; 612, multiple generation sub-branch in interval generation branch 62; 613, multiple generation sub-branch in interval generation branch 63; 2Rb1, the first branch resistor of the multiplier generation sub-branch 611; Rb1, the second branch resistor of the multiplier generation sub-branch 611; BUF21, the second voltage buffer of the multiplier generation sub-branch 611; AP1, the adder in the interval generation branch 61; AM1, the subtractor in the interval generation branch 61; 3Rb2, the first branch resistor of the multiplier generation sub-branch 621; Rb2, the second branch resistor of the multiplier generation sub-branch 621; BUF22, the second voltage buffer of the multiplier generation sub-branch 621; AP2, the adder in the interval generation branch 62; AM2, the subtractor in the interval generation branch 62; 4Rb3, the first branch resistor of the multiplier generation sub-branch 631; Rb3, the second branch resistor of the multiplier generation sub-branch 631; BUF23, the second voltage buffer of the multiplier generation sub-branch 631; AP3, the adder in the interval generation branch 63; AM3, the subtractor in the interval generation branch 63; 71~73, multiple decision branches; CMPH1, upper limit comparator in decision branch 71; CMPL1, lower limit comparator in decision branch 71; Y1, AND gate in decision branch 71; CMPH2, upper limit comparator in decision branch 72; CMPL2, lower limit comparator in decision branch 72; Y2, AND gate in decision branch 72; CMPH3, upper limit comparator in decision branch 73; CMPL3, lower limit comparator in decision branch 73; Y3, AND gate in decision branch 73; OR, OR gate.

[0023] The objectives, features, and advantages of the embodiments described in this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0024] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of the embodiments of this application and are not intended to limit the embodiments of this application.

[0025] To better understand the technical solutions of the embodiments of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0026] For display devices such as LCD and OLED, during the horizontal scanning process of the display panel, the power supply rails (such as AVDD and AVEE) of the display panel will show regular dynamic current changes. The power management system (PMIC) that supplies power to the display panel in the display device usually adopts a switching DC-DC architecture. When the PMIC is working, it will inevitably introduce ripple related to the operating frequency of the PMIC onto the power supply rails.

[0027] During use, it was found that in some cases, the frequency of dynamic current changes and the operating frequency of the PMIC can affect each other, resulting in a significant amplification of ripples. This can cause water ripples on the display screen, such as slowly moving stripes or local brightness fluctuations, which affect the display quality.

[0028] The display device in this embodiment includes a timing controller, a power manager, a horizontal frequency detection module, a power frequency detection module, and a comparison control module. Since the dynamic current change on the power supply rail is generated during the horizontal scanning process, the dynamic current change is related to the horizontal frequency. Therefore, by detecting the display timing signal through the horizontal frequency detection module, a horizontal frequency detection value reflecting the horizontal frequency can be obtained in real time. Then, the horizontal frequency detection value and the power frequency detection value detected by the power frequency detection module can be used to determine whether the operating frequency of the power manager needs to be adjusted. During the research process, this embodiment found that when the horizontal frequency and the power manager's operating frequency are integer multiples, the ripple is significantly amplified, resulting in a water ripple effect. Therefore, this embodiment uses the horizontal frequency detection module to detect the horizontal frequency detection value, the power frequency detection module to detect the power frequency detection value, and the comparison control module to accurately determine whether the horizontal frequency detection value and the power frequency detection value are integer multiples or close to integer multiples, thereby improving the reliability of the judgment.

[0029] In this embodiment, when the absolute difference between the detection ratio (the ratio between the horizontal frequency detection value and the power frequency detection value) and a preset integer multiple is less than a preset offset, the operating frequency of the power manager can be adjusted to disrupt the integer multiple relationship between the horizontal frequency and the operating frequency of the power manager. This can suppress the significant amplification of ripple, eliminate or reduce water ripple phenomena such as slowly moving stripes and local brightness fluctuations in the display screen, thereby improving display quality.

[0030] Based on this, embodiments of this application provide a display device, referring to... Figure 1 , Figure 1 This is a schematic diagram of the display device modules according to an embodiment of this application.

[0031] The display device includes a timing controller 100, a power manager 200, a horizontal frequency detection module 300, a power frequency detection module 400, and a comparison control module 500. The first output terminal of the timing controller 100 is connected to the input terminal of the line frequency detection module 300, and the output terminal of the line frequency detection module 300 is connected to the first input terminal of the comparison control module 500. The input terminal of the power frequency detection module 400 is connected to the frequency detection terminal of the power manager 200, the output terminal of the power frequency detection module 400 is connected to the second input terminal of the comparison control module 500, and the output terminal of the comparison control module 500 is connected to the frequency control terminal of the power manager 200. The line frequency detection module 300 is used to receive the display timing signal output by the timing controller 100 in order to detect the line frequency detection value; The power frequency detection module 400 is used to collect the frequency signal of the power manager 200 in order to detect the power frequency detection value. The comparison control module 500 is used to adjust the operating frequency of the power manager 200 when the absolute difference between the detection ratio and a preset integer multiple is less than a preset offset, wherein the detection ratio is the ratio between the horizontal frequency detection value and the power frequency detection value.

[0032] It should be noted that the timing controller 100 can be a TCON, and the first output terminal of the timing controller 100 is a port used to output display timing signals. These display timing signals can be horizontal synchronization signals, data enable signals, frame start signals, etc. This embodiment does not impose specific limitations on these signals; they can be set based on actual conditions. The horizontal synchronization signal can be an HSYC signal, and the frequency of the HSYC signal is the horizontal frequency. When the display timing signal is a data enable signal or a frame start signal, the horizontal frequency detection module 300 can convert the data enable signal or frame start signal into the corresponding horizontal frequency. For example, the horizontal frequency detection module 300 can determine the current refresh rate of the display device through the data enable signal or frame start signal, and then calculate the horizontal frequency based on the product of the current refresh rate and the number of effective display lines in one frame.

[0033] The power manager 200 can be a PMIC. In this embodiment, the horizontal frequency detection module 300, the power frequency detection module 400, and the comparison control module 500 can be set in the PMIC. In other embodiments, they can also be set out of the PMIC. This embodiment does not make specific limitations on this. The specific settings can be based on the actual situation.

[0034] The horizontal frequency detection value can be the horizontal frequency voltage corresponding to the horizontal frequency of the display device. In other embodiments, the horizontal frequency detection value can also be the frequency value of the horizontal frequency of the display device, where the horizontal frequency is the frequency of the horizontal synchronization signal. For example, when the horizontal frequency detection value is the frequency value of the horizontal frequency of the display device, the horizontal frequency detection module 300 can be a counter, which detects the frequency of the horizontal synchronization signal.

[0035] The power frequency detection value is the voltage corresponding to the operating frequency of the power manager 200. In other embodiments, the power frequency detection value can also be the operating frequency of the power manager 200. When the horizontal frequency detection value is the horizontal frequency value, the power frequency detection value is also the operating frequency of the power manager 200; similarly, when the horizontal frequency detection value is the horizontal voltage value, the power frequency detection value is also the voltage value, to ensure that the two detection values ​​used by the comparison control module 500 for ratio calculation are in the same physical dimension. The frequency signal of the power manager 200 is output from the frequency detection terminal of the power manager 200 and is an electrical signal that reflects its operating frequency. The frequency detection terminal can be an LX node, an SW node, or the internal clock node of the PMIC, etc. This embodiment does not specifically limit this, and it can be set according to the actual situation.

[0036] When the power frequency detection value is the operating frequency of the power manager 200, the power frequency detection module 400 can also be a counter. The counter counts the frequency of the signal output from the frequency detection terminal of the power manager 200 to obtain the operating frequency value. For example, when the frequency detection terminal outputs a high level, the count value of the power frequency detection module 400 can be incremented by 1.

[0037] In this embodiment, both the horizontal frequency detection value and the power frequency detection value are detected in real time, which can improve the accuracy of subsequent judgment on whether the operating frequency of the power manager 200 needs to be adjusted.

[0038] The preset integer multiple is a pre-set multiple. In this embodiment, there can be multiple different preset integer multiples. When the absolute difference between the ratio between the horizontal frequency detection value and the power frequency detection value and any preset integer multiple is less than a preset offset, the operating frequency of the power manager 200 is adjusted.

[0039] The preset offset is a small tolerance value set in advance, used to determine whether the horizontal frequency detection value and the power frequency detection value are integer multiples or close to integer multiples.

[0040] To better understand this embodiment, a 23.8-inch display device with a resolution of 1920×1080 and a refresh rate of 165Hz is used as an example. The effective number of display lines (Vtotal) of this display device is approximately 1125, corresponding to a horizontal frequency of approximately 165×1125=185.6kHz. During the test, the set switching frequency of the power manager 200 was approximately 750kHz, while the actual detected operating frequency of the power manager 200 was approximately 742.3kHz. At this time, the ratio between the horizontal frequency and the operating frequency is approximately 742.3 / 185.6≈4. Under these circumstances, obvious moving stripes appear on the display screen, and low-frequency ripple enhancement is observed on the power supply rail and some reference voltage nodes. This indicates that when the ratio of the horizontal frequency to the PMIC's operating frequency is close to a preset integer multiple, the ripple introduced into the power supply rail by the power manager 200 is significantly amplified, thus causing a water ripple phenomenon.

[0041] Furthermore, in actual product operation, the operating frequency of the power manager 200 is not constant. During power-on heating and continuous operation, the actual operating frequency of the power manager 200 drifts. For example, under certain test conditions, the power frequency detection value during the startup phase is approximately 743.2kHz, which drops to 722.5kHz after about 5 minutes of continuous operation. This change causes the PMIC's operating frequency, which was originally not an integer multiple of the horizontal frequency, to once again approach an integer multiple of the horizontal frequency, resulting in the water ripple effect gradually appearing over time. In addition, with the widespread adoption of multi-refresh-rate displays, display devices may need to switch between multiple refresh rates such as 60Hz, 120Hz, 144Hz, and 165Hz, and the horizontal frequency will change accordingly with the refresh rate. Traditionally, this is usually mitigated by fixing the power frequency or manually modifying parameters, but this requires separate adjustments for different operating modes, which is costly and cannot continuously adapt to frequency drift and changes in operating status caused by temperature variations.

[0042] The display device provided in this application embodiment obtains the horizontal frequency detection value in real time through the horizontal frequency detection module 300 and the power frequency detection value in real time through the power frequency detection module 400. When the absolute difference between the detection ratio and a preset integer multiple is less than a preset offset, the comparison control module 500 actively adjusts the operating frequency of the power manager 200 through the frequency control terminal of the power manager 200, thereby disrupting the above-mentioned integer multiple frequency correspondence, suppressing ripple amplification, and eliminating the water ripples appearing in the display screen. Therefore, this embodiment can sense changes in horizontal frequency and power frequency in real time, automatically adapt to frequency drift and multi-refresh rate switching, improve display stability, and reduce maintenance costs.

[0043] The display device in this embodiment includes a timing controller 100, a power manager 200, a horizontal frequency detection module 300, a power frequency detection module 400, and a comparison control module 500. Since the dynamic current change on the power supply rail is generated during the horizontal scanning process, the dynamic current change is related to the horizontal frequency. Therefore, by detecting the display timing signal through the horizontal frequency detection module 300, a horizontal frequency detection value reflecting the horizontal frequency can be obtained in real time. Then, the horizontal frequency detection value and the power frequency detection value detected by the power frequency detection module 400 can be used to determine whether the operating frequency of the power manager 200 needs to be adjusted. During the research process, this embodiment found that when the horizontal frequency is an integer multiple of the operating frequency of the power manager 200, the ripple is significantly amplified, resulting in a water ripple effect. Therefore, this embodiment uses the horizontal frequency detection module 300 to detect the horizontal frequency detection value and the power frequency detection module 400 to detect the power frequency detection value. The comparison control module accurately determines whether the horizontal frequency detection value and the power frequency detection value are integer multiples or close to integer multiples, thereby improving the reliability of the determination.

[0044] This embodiment adjusts the operating frequency of the power manager when the absolute difference between the detection ratio (the ratio between the horizontal frequency detection value and the power frequency detection value) and a preset integer multiple is less than a preset offset. This can disrupt the integer multiple relationship between the horizontal frequency and the operating frequency of the power manager 200, thereby suppressing the significant amplification of ripples and eliminating or reducing water ripple phenomena such as slowly moving stripes and local brightness fluctuations in the display screen, thus improving display quality.

[0045] In one embodiment, please refer to Figure 2 The line frequency detection module 300 also includes a first pulse shaping unit 310, a charge conversion unit 320 and an integral filtering unit 330 connected in sequence. The input terminal of the first pulse shaping unit 310 is connected to the first output terminal of the timing controller 100, and the output terminal of the integral filtering unit 330 is connected to the first input terminal of the comparison control module 500. The first pulse shaping unit 310 is used to shape the display timing signal into a first standard pulse signal with a preset first stable width; The charge conversion unit 320 is used to convert the first standard pulse signal into charge; The integral filter unit 330 is used to integrate the charge output by the charge conversion unit 320 and output the line frequency detection value.

[0046] It should be noted that the first pulse shaping unit 310 is used to shape the horizontal synchronization signal into a first standard pulse signal with a fixed and stable width. The preset first stable width is a fixed width that each high level in the horizontal synchronization signal should reach in advance.

[0047] The first standard pulse signal is output after being processed by the first pulse shaping unit 310, and the width of each pulse is constant as a preset first stable width.

[0048] The charge conversion unit 320 converts the input first standard pulse signal into a corresponding charge. The integration and filtering unit 330 integrates the input charge and outputs the line frequency detection value. Figure 2 The line frequency detection module 300 shown outputs a line frequency detection value of line frequency voltage, and the display timing signal received by the line frequency detection module 300 is a line synchronization signal. When the display timing signal is a data enable signal or a frame start signal, a signal conversion circuit can be added before the first pulse shaping unit 310 to convert the data enable signal or frame start signal into a line synchronization signal.

[0049] The first pulse shaping unit 310 can be a monostable pulse shaping unit. This unit only responds to the edge triggering of the input signal (horizontal synchronization signal) and outputs a first standard pulse signal with a preset first stable width. This ensures that the width of the first standard pulse signal remains constant within each signal cycle, regardless of changes in the duty cycle of the horizontal synchronization signal. In this way, the amount of charge injected into the integrating filter unit 330 through the charge conversion unit 320 remains fixed within each horizontal cycle. This makes the output horizontal frequency detection value primarily reflect changes in the horizontal frequency, while mitigating the impact of changes in the duty cycle of the horizontal synchronization signal on the horizontal frequency voltage, thus improving the accuracy of the horizontal frequency voltage.

[0050] In other embodiments, the horizontal frequency detection module 300 can also be a module composed of a counter and a voltage mapping unit. The counter detects the horizontal frequency value, and the voltage mapping unit determines the horizontal frequency voltage corresponding to the horizontal frequency value in a first preset frequency-voltage mapping relationship between a preset horizontal frequency and a preset first voltage, and outputs the horizontal frequency voltage. The voltage mapping unit can be a software functional unit implemented by a preset program, or a hardware lookup table unit composed of logic circuits. This embodiment does not specifically limit this. When implemented as a software functional unit, the voltage mapping unit stores program instructions for the first preset frequency-voltage mapping relationship. By executing these program instructions, the conversion and output from the frequency value to the horizontal frequency voltage is completed.

[0051] The first preset frequency voltage mapping relationship can also be expressed as a function, for example, as shown in Formula 1: VFH=KH×fH (Formula 1); Wherein, VFH is the horizontal frequency voltage, KH is the first conversion coefficient, fH is the horizontal frequency value, and KH can be obtained by fitting multiple preset first voltages with their respective preset horizontal frequency.

[0052] In one feasible embodiment, please refer to Figure 3 The charge conversion unit 320 includes a first switch SW1, a current source Is, and a first capacitor C1; the integral filter unit 330 includes a first operational amplifier op1, a second operational amplifier op2, a second capacitor C2, and a first resistor R1. The control terminal of the first switching transistor SW1 is connected to the output terminal of the first pulse shaping unit 310. The first terminal of the first switching transistor SW1 is used to connect to the preset power supply terminal VDD. The second terminal of the first switching transistor SW1 is connected to the first terminal of the current source Is. The second terminal of the current source Is is connected to the first terminal of the first capacitor C1, and the second terminal of the first capacitor C1 is connected to the preset low voltage terminal VSS. The first terminal of the first capacitor C1 is connected to the first terminal of the first resistor R1, the second terminal of the first resistor R1 is connected to the negative input terminal of the first operational amplifier op1, and the positive input terminal of the first operational amplifier op1 is connected to the preset low voltage terminal VSS. The second capacitor C2 is placed between the negative input terminal of the first operational amplifier op1 and the output terminal of the first operational amplifier op1. The output of the first operational amplifier op1 is connected to the positive input of the second operational amplifier op2, and the negative input of the second operational amplifier op2 is connected to the output of the second operational amplifier op2. The output of the second operational amplifier op2 outputs the line frequency detection value.

[0053] It should be noted that the first switch SW1 can be an NMOS transistor, or other types of switches in other embodiments; this embodiment does not specifically limit it. When the control terminal of the first switch SW1 receives a high level, the first switch SW1 is turned on; when the control terminal of the first switch SW1 receives a low level, the first switch SW1 is turned off.

[0054] The current source Is is a circuit unit used to provide a constant charging current, ensuring that the amount of charge injected into the first capacitor C1 is consistent each time it is turned on. The first capacitor C1 is used to receive the charge injected by the current source Is.

[0055] The first operational amplifier op1, together with the second capacitor C2 and the first resistor R1, constitutes an integrator. The second operational amplifier op2 is a voltage follower, which can isolate the voltage output by the first operational amplifier op1 from the circuit connected to the output of the second operational amplifier op2, ensuring the stability and accuracy of the line frequency detection value output.

[0056] In other embodiments, the integral filter unit 330 may not include the second operational amplifier op2, or the first operational amplifier op1 may directly output the line frequency detection value. This embodiment does not impose specific limitations on this, and the specific configuration can be based on actual conditions.

[0057] The second capacitor C2 is placed between the negative input and output terminals of the first operational amplifier op1, serving as an integrating capacitor. The first resistor R1 is connected between the first capacitor C1 and the negative input terminal of the first operational amplifier op1. The preset power supply terminal VDD provides a constant supply voltage. The preset low voltage terminal VSS provides a reference zero potential or low potential, such as ground.

[0058] In this embodiment, the frequency of the horizontal synchronization signal can be output as a voltage, which facilitates subsequent comparison of the horizontal frequency voltage with the voltage value corresponding to the operating frequency of the power manager 200 via hardware circuitry. This improves the accuracy of determining whether the power supply frequency needs adjustment and increases the efficiency of comparing the horizontal frequency voltage with the voltage value corresponding to the operating frequency. For example, refer to... Figure 3 , Figure 3 Taking the horizontal synchronization signal HSYC as an example and the horizontal frequency detection value as the horizontal frequency voltage as an example, a circuit diagram of the horizontal frequency detection module is given. Figure 3 As can be seen, the horizontal synchronization signal HSYC is input to the first pulse shaping unit. Figure 3 In the middle, the horizontal frequency voltage VFH is output through the second operational amplifier op2.

[0059] In one feasible embodiment, please refer to Figure 4 The power frequency detection module 400 includes an input filtering unit 410, a second pulse shaping unit 420, and a frequency conversion unit 430 connected in sequence. The input filtering unit 410 is connected to the frequency detection terminal, and the output terminal of the frequency conversion unit 430 is connected to the second input terminal of the comparison control module 500. The input filtering unit 410 is used to filter the frequency signal sampled at the frequency detection end, and the second pulse shaping unit 420 is used to shape the signal output by the input filtering unit 410 into a second standard pulse signal with a preset second stable width. The frequency conversion unit 430 is used to output the power frequency detection value based on the second standard pulse signal.

[0060] It should be noted that the input filtering unit 410 is used to filter the frequency signal acquired from the frequency detection terminal to attenuate or filter out high-frequency noise and interference in the frequency signal. The second pulse shaping unit 420 is a circuit unit used to convert the filtered frequency signal into a second standard pulse signal with a fixed and stable width. The preset second stable width is a pre-set width that each pulse in the frequency signal of the power manager 200 should reach. In this embodiment, the second pulse shaping unit 420 may be a Schmitt trigger unit.

[0061] The second standard pulse signal is output after being processed by the second pulse shaping unit 420, and each pulse width is a constant preset second stable width. The frequency conversion unit 430 is used to convert the input second standard pulse signal into a voltage value that can characterize the operating frequency of the power manager 200.

[0062] In this embodiment, the actual operating frequency of the PMIC or the voltage value corresponding to the actual operating frequency is detected by the power frequency detection module 400, rather than reading the set value of the PMIC operating frequency. This is because the operating frequency of the PMIC may drift, so comparing the set value of the PMIC operating frequency with the horizontal frequency detection value would be less accurate.

[0063] Figure 4 The power frequency detection module 400 shown outputs a power frequency detection value that corresponds to the voltage value of the PMIC's operating frequency. For ease of description, the voltage value corresponding to the PMIC's operating frequency will be described as a power frequency voltage. Converting the actual operating frequency of the power manager 200 to a power frequency voltage reduces the complexity of frequency judgment and control in the subsequent comparison and control module 500.

[0064] In this embodiment, the input filtering unit 410 ensures that the width of the second standard pulse signal output in each signal cycle remains constant regardless of the duty cycle of the PMIC's operating frequency. This makes the output power frequency detection value mainly reflect the change in the operating frequency of the power manager 200, while weakening the influence of the input signal duty cycle change on the power frequency voltage, thereby improving the accuracy of the power frequency voltage.

[0065] In other embodiments, the power frequency detection module 400 may be implemented using the same structure as the line frequency detection module 300. For example, the power frequency detection module 400 may also refer to... Figure 2 The module structure shown can eliminate errors caused by the different structures of the two detection modules, and improve the accuracy and reliability of the comparison control module 500 in judging the absolute difference between the ratio of the line frequency detection value and the power frequency detection value and the preset integer multiple.

[0066] In other embodiments, the power frequency detection module 400 can also be a module composed of a counter and a voltage mapping unit. The counter detects the operating frequency of the power manager 200, and the voltage mapping unit determines the power frequency voltage corresponding to the operating frequency of the power manager 200 in a second preset frequency-voltage mapping relationship between a preset power frequency and a preset second voltage, and outputs the power frequency voltage. The voltage mapping unit can be a software functional unit implemented by a preset program, or a hardware lookup table unit composed of logic circuits. This embodiment does not specifically limit this. When implemented as a software functional unit, the voltage mapping unit stores program instructions for the second preset frequency-voltage mapping relationship. By executing these program instructions, the conversion and output from the frequency value to the power frequency voltage is completed.

[0067] The second preset frequency voltage mapping relationship can also be expressed as a function, for example, as shown in Formula 2: VSW=KS×fS (Formula 2); Where VSW is the power supply frequency voltage, KS is the second conversion coefficient, fS is the operating frequency of the PMIC, and KS can be obtained by fitting multiple preset second voltages with their respective preset power supply frequencies.

[0068] In one feasible embodiment, please refer to Figure 5 The input filtering unit 410 includes a filter resistor Ra, a filter capacitor Ca, a first diode D1, and a second diode D2; the frequency conversion unit 430 includes a second switch SW2, a second resistor R2, a third resistor R3, a third capacitor C3, and a third operational amplifier op3. The first end of the filter resistor Ra is connected to the frequency detection terminal, the second end of the filter resistor Ra is connected to the first end of the filter capacitor Ca, and the second end of the filter capacitor Ca is connected to the preset low voltage terminal VSS. The anode of the first diode D1 is connected to the preset power supply terminal VDD, the cathode of the first diode D1 is connected to the second terminal of the filter resistor Ra, the cathode of the second diode D2 and the input terminal of the second pulse shaping unit 420, and the anode of the second diode D2 is connected to the preset low voltage terminal VSS. The output terminal of the second pulse shaping unit 420 is connected to the control terminal of the second switching transistor SW2. The first terminal of the second switching transistor SW2 is connected to the first terminal of the second resistor R2, the first terminal of the third capacitor C3, and the positive input terminal of the third operational amplifier op3. The second terminal of the third capacitor C3 is connected to the preset low voltage terminal VSS. The second terminal of the second switch SW2 is connected to the first terminal of the third resistor R3, and the second terminal of the third resistor R3 is connected to the preset low voltage terminal VSS. The negative input terminal of the third operational amplifier op3 is connected to the output terminal of the third operational amplifier op3, and the output terminal of the third operational amplifier op3 outputs the power supply frequency detection value.

[0069] It should be noted that the filter resistor Ra and the filter capacitor Ca together form a low-pass filter network, used to attenuate or filter out high-frequency noise and interference in the frequency signal. The first diode D1 is a clamping diode connected between the preset power supply terminal VDD and the second terminal of the filter resistor Ra; the second diode D2 is a diode connected between the second terminal of the filter resistor Ra and the input terminal of the second pulse shaping unit 420, together with the first diode D1, forming an input protection network.

[0070] The second switch SW2 can be an NMOS transistor, or other types of switches in other embodiments; this embodiment does not specifically limit it. When the control terminal of the second switch SW2 receives a high level, the second switch SW2 is turned on; when the control terminal receives a low level, the second switch SW2 is turned off. When the second standard pulse signal is high, the third capacitor C3 can be charged, and the power supply frequency voltage can be determined through the third capacitor C3. The third operational amplifier op3 is a voltage follower, used to isolate the voltage on the third capacitor C3 and output the power supply frequency detection value, thereby improving the accuracy and reliability of the power supply frequency detection value output.

[0071] This embodiment effectively suppresses high-voltage spike interference and high-frequency noise at the frequency detection terminal output through a low-pass filter network composed of a filter resistor Ra and a filter capacitor Ca, and an input protection network composed of a first diode D1 and a second diode D2. The second pulse shaping unit 420 then shapes the filtered signal into a second standard pulse signal with a constant pulse width, eliminating the influence of input signal duty cycle variations. The second standard pulse signal frequency is then converted to the power supply frequency voltage through the second switch SW2, the third capacitor C3, etc., and buffered by the third operational amplifier op3, thereby improving the stability of the power supply frequency voltage output.

[0072] For example, refer to Figure 5 , Figure 5 Taking the frequency detection terminal as the LX node and the power supply frequency detection value as the power supply frequency voltage as an example, a circuit diagram of the power supply frequency detection module is given. Figure 5 As can be seen, the power frequency detection module can detect the operating frequency of the power manager at the LX node, and finally output the power frequency voltage VSW through the third operational amplifier op3.

[0073] In one feasible embodiment, please refer to Figure 6 The comparison control module 500 includes a comparison unit 510 and a frequency control unit 520; The first comparison terminal of the comparison unit 510 is used as the first input terminal of the comparison control module 500, and the second comparison terminal of the comparison unit 510 is used as the second input terminal of the comparison control module 500. The output of the comparison unit 510 is connected to the input of the frequency control unit 520, and the control terminal of the frequency control unit 520 is connected to the second output of the timing controller 100. The comparison unit 510 is used to output a comparison level based on the line frequency detection value and the power supply frequency detection value. When the absolute difference between the detection ratio and a preset integer multiple is less than a preset offset, the comparison level output by the comparison unit 510 is a preset risk level. The frequency control unit 520 is used to adjust the operating frequency of the power manager 200 during the blanking phase when the comparison level output by the comparison unit 510 is a preset risk level.

[0074] It should be noted that the comparison unit 510 can receive the horizontal frequency detection value and the power frequency detection value, and output a comparison level based on the horizontal frequency detection value and the power frequency detection value. The comparison level is used to characterize whether the horizontal frequency detection value and the power frequency detection value constitute or are close to any preset integer multiple.

[0075] The frequency control unit 520 receives the comparison level output by the comparison unit 510 and generates a frequency adjustment signal to adjust the operating frequency of the power manager 200 when the comparison level is a preset risk level. The preset risk level is a pre-set level value used to indicate that the horizontal frequency detection value and the power frequency detection value have entered or approached a preset integer multiple. For example, the preset risk level can be a high level, and in other embodiments, it can also be a low level. This embodiment does not specifically limit this, and it can be set according to the actual situation.

[0076] The blanking phase is the time interval during which the display panel in a display device does not write valid display data to the pixels during the line scan or frame scan process. For example, the blanking phase can be the line blanking period and / or the frame blanking period.

[0077] The comparison unit 510 can determine the multiple range corresponding to each preset integer multiple based on the power frequency detection value and the preset offset. The comparison unit 510 can also be used to detect whether the horizontal frequency detection value falls into any multiple range. If the horizontal frequency detection value falls into any multiple range, the comparison unit 510 outputs a preset risk level.

[0078] In other embodiments, the comparison unit 510 includes an analog-to-digital converter (ADC) and a digital comparison logic circuit. The ADC converts the line frequency detection value and the power supply frequency detection value into digital quantities, and the digital comparison logic circuit calculates the ratio between the two values ​​and compares it with a pre-stored preset integer multiple and a preset offset. When the absolute difference between the ratio and the preset integer multiple is less than the offset, a preset risk level is output.

[0079] The frequency control unit 520 is also used to adjust the operating frequency of the power manager 200 to the target frequency during the blanking phase when the comparison unit 510 outputs a preset risk level. For example, the frequency control unit 520 can output a signal including the target frequency and input the signal including the target frequency to the frequency control terminal of the power manager 200 to instruct the power manager 200 to adjust the operating frequency to the target frequency.

[0080] The target frequency can be determined from multiple preset frequency levels. These preset frequency levels refer to several pre-set selectable frequency values ​​for the safe operation of the power manager 200, each avoiding frequency points that are integer multiples of common horizontal frequencies. When determining the target frequency, if the power frequency detection value is the power frequency voltage, the frequency control unit 520 can first obtain the operating frequency of the power manager 200 corresponding to the power frequency voltage based on the correspondence between the power frequency voltage and the operating frequency of the power manager 200. Then, it determines the preset frequency with the smallest absolute value of the difference between the power frequency voltage and the operating frequency of the power manager 200 from the multiple preset frequency levels, and uses this as the target frequency.

[0081] In another embodiment, when the power frequency detection value is itself the operating frequency of the power manager 200, the frequency control unit 520 can directly determine the preset frequency with the smallest absolute value of the difference between the power manager 200 and the operating frequency of the power manager 200 from among multiple preset frequency settings, and use it as the target frequency. Determining the target frequency by using the method with the smallest absolute value of the difference minimizes the adjustment range of the power manager 200's operating frequency, thereby reducing disturbances during frequency switching and ensuring display stability.

[0082] In other embodiments, the frequency control unit 520 can adjust the operating frequency of the power manager 200 using a continuous frequency adjustment method. For example, the frequency control unit 520 can calculate the frequency adjustment amount based on the degree to which the ratio of the horizontal frequency detection value to the power supply frequency detection value deviates from a preset integer multiple, and use the sum of the frequency adjustment amount and the operating frequency corresponding to the power supply frequency voltage as the target frequency.

[0083] The frequency control unit 520 adopts a gear-based adjustment method that determines the target frequency from multiple preset gear frequencies. Since the target frequency is a pre-set discrete frequency value, the frequency control unit 520 only needs to select from a limited number of preset gear frequencies, without performing complex frequency calculations. This method has a simpler circuit, higher frequency switching efficiency, more accurate and reliable adjustment results, and a lower operating load on the frequency control unit 520.

[0084] Upon receiving a preset risk level, the frequency control unit 520 does not immediately adjust the PMIC's operating frequency. Instead, it combines this with a timing signal provided by the second output of the timing controller 100 (e.g., a DE signal, i.e., a data enable signal) to adjust the power manager 200's operating frequency during the blanking phase. Because the frequency switching action is controlled to be performed during the blanking phase, the display panel does not write valid pixel data at this time. Therefore, any transient power supply fluctuations that may occur during frequency adjustment will not cause visible interference to the display screen. This suppresses ripple amplification to eliminate water ripples while ensuring the instantaneous stability of the display screen, further improving display quality.

[0085] In one feasible embodiment, please refer to Figure 7 and Figure 8 The comparison unit 510 includes an interval generation circuit 511 and a judgment circuit 512. The interval generation circuit 511 includes an offset generation branch 60 and includes at least one interval generation branch. The first reference terminal of the judgment circuit 512 is used as the first comparison terminal of the comparison unit 510, and the second reference terminal of the interval generation circuit 511 is used as the second comparison terminal of the comparison unit 510; the judgment circuit 512 is used to output the comparison level. The input terminal of the offset generation branch 60 is connected to the preset interval width control voltage VREF, and the offset generation branch 60 is used to output the offset based on the preset interval width control voltage VREF. For each interval generation branch, the branch input terminal of the interval generation branch is connected to the second reference terminal, the offset input terminal of the interval generation branch is connected to the output terminal of the offset generation branch 60, and the first and second output terminals of the interval generation branch are both connected to the input terminal of the judgment circuit 512. The first output terminal of the interval generation branch is used to output the upper limit value of the multiple interval corresponding to the preset integer multiple, and the second output terminal of the interval generation branch is used to output the lower limit value of the multiple interval. The preset integer multiples corresponding to the branch paths generated in each interval are different.

[0086] It should be noted that the interval generation circuit 511 is used to generate at least one multiple interval based on the power supply frequency detection value. A multiple interval refers to an interval centered on the ratio of the power supply frequency detection value to a preset integer multiple, determined by a preset offset. When multiple intervals exist, the preset integer multiples corresponding to different multiple intervals are different.

[0087] The judgment circuit 512 receives the multiple range output by the interval generation circuit 511 and determines whether the horizontal frequency detection value falls within the multiple range, thereby outputting the corresponding comparison level. The first reference terminal of the judgment circuit 512 is connected to the horizontal frequency detection value, and the second reference terminal of the interval generation circuit 511 is connected to the power supply frequency detection value. The judgment circuit 512 outputs a preset risk level when the horizontal frequency detection value falls within any multiple range.

[0088] In this embodiment, the interval generation circuit 511 can generate multiple multiple intervals in parallel for different preset integer multiples, and the judgment circuit 512 can simultaneously complete the risk judgment of multiple integer multiple relationships, improving the detection speed and detection range. This ensures that the preset risk level can still be output in a timely and accurate manner when the horizontal frequency or power frequency changes rapidly, thereby facilitating timely adjustment of the operating frequency of the power manager 200 and reducing or eliminating the occurrence of water ripples. Furthermore, in this embodiment, the determination of whether the horizontal frequency detection value falls within any multiple interval corresponding to the power frequency detection value can be realized through hardware circuitry, without the need for software calculation. This improves the real-time performance of the detection and the accuracy of determining whether the operating frequency of the power manager 200 needs to be adjusted.

[0089] It should also be noted that the offset generation branch 60 is used to generate an offset based on the preset interval width control voltage VREF. The offset can be expressed as a voltage, for example, an offset voltage. The preset interval width control voltage VREF is a pre-set reference voltage value used to control the width of the multiple interval. The magnitude of the preset interval width control voltage VREF determines the magnitude of the offset. The offset is an electrical signal output by the offset generation branch 60, representing half the width of the multiple interval.

[0090] The interval generation branch is used to generate the upper and lower limits of a multiple interval corresponding to a preset integer multiple, based on the power frequency detection value and the offset. Different interval generation branches correspond to different preset integer multiples. For example, the multiple interval corresponding to the preset integer multiple 'a' is [VSW / a-Vd, VSW / a+Vd], where VSW is the power frequency detection value, 'a' is the preset integer multiple, and Vd is the offset. For the same power frequency detection value, different preset integer multiples result in different multiple intervals corresponding to that power frequency detection value. In this embodiment, there can be one or more interval generation branches, for example, refer to... Figure 8 , Figure 8The diagram shows a module schematic of an interval generation circuit including multiple interval generation branches, where 61~6m refers to multiple interval generation branches, and m is a positive integer greater than 1. m can be determined based on the actual situation, and this embodiment does not make a specific limitation on it.

[0091] The branch input terminal is the input port on the interval generation branch used to receive the power frequency detection value. The offset input terminal is the input port on the interval generation branch used to receive the offset output from offset generation branch 60.

[0092] Since the interval generation branches work in parallel, the judgment circuit 512 can simultaneously complete the judgment of all preset integer multiple intervals within one row cycle, avoiding the risk of ripple amplification due to the omission of other integer multiples caused by the judgment of a single integer multiple. In turn, the comprehensiveness and response speed of the detection are improved by the parallel generation of multiple interval branches, so that the comparison unit 510 can quickly and accurately detect the relationship between any preset integer multiple between the row frequency and the power supply frequency.

[0093] In other embodiments, when the interval generation circuit 511 includes multiple interval generation branches, the offset generation branch 60 can be one or more. When there are multiple offset generation branches 60, different interval generation branches can be connected to different offset generation branches 60. The offsets generated by different offset generation branches 60 can be the same or different, thereby configuring the same or different offsets for each interval generation branch, which facilitates setting differentiated offsets for different preset integer multiples. For example, for preset integer multiples that are prone to causing water ripples over a wide frequency deviation range, a larger offset can be configured to expand the corresponding multiple range and improve detection sensitivity; for preset integer multiples that only generate water ripples when the frequency deviation is extremely small, a smaller offset can be configured to narrow the corresponding multiple range and avoid triggering unnecessary frequency adjustment operations due to an excessively wide range.

[0094] In one feasible embodiment, please refer to Figure 9 and Figure 10 The offset generation branch 60 includes a first width resistor, a second width resistor, and a first voltage buffer; The interval generation branch includes a multiple generation sub-branch, an adder, and a subtractor. The multiple generation sub-branch is used to generate a preset integer multiple voltage that is an integer multiple of the power supply frequency detection value. The first end of the first width resistor is connected to the preset interval width control voltage VREF, the second end of the first width resistor is connected to the first end of the second width resistor, and the second end of the second width resistor is connected to the preset low voltage end VSS. The input terminal of the first voltage buffer is connected to the second terminal of the first width resistor, and the output terminal of the first voltage buffer serves as the output terminal of the offset generation branch 60. The multiplier generating sub-branch includes a first branch resistor, a second branch resistor, and a second voltage buffer; The first terminal of the first branch resistor is connected to the power frequency detection value, the second terminal of the first branch resistor is connected to the first terminal of the second branch resistor, and the second terminal of the second branch resistor is connected to a preset low level. The input terminal of the second voltage buffer is connected to the second terminal of the first branch resistor, and the output terminal of the second voltage buffer is connected to the first terminal of the adder and the first terminal of the subtractor. The offset input of the interval generation branch includes the second end of the adder and the second end of the subtractor, and the offset input is connected to the output of the offset generation branch 60.

[0095] It should be noted that the first-width resistor and the second-width resistor refer to two resistive elements that constitute the resistive voltage divider network. They are connected in series and divide the preset interval width control voltage VREF to obtain the required offset voltage at the series node. The first voltage buffer refers to a unity-gain amplifier, which is used to impedance isolate the output offset voltage at the voltage divider node, thus avoiding the impact of subsequent load changes on the voltage divider accuracy.

[0096] Both the first and second width resistors are fixed-value resistors. The preset interval width control voltage VREF is divided by the two resistors in a fixed ratio to output a fixed offset. This method has a simple circuit structure and is suitable for applications where the offset does not need to be adjusted.

[0097] In other embodiments, the first width resistor and / or the second width resistor are adjustable resistors. By adjusting the resistance value of the adjustable resistor, the voltage division ratio can be changed, thereby flexibly setting the size of the offset to adapt to different requirements for the width of the interval in different application scenarios.

[0098] The offset generation branch 60 divides the preset interval width control voltage VREF through a first width resistor and a second width resistor, obtaining the offset voltage (offset amount) at the second terminal of the first width resistor. This offset voltage is then impedance-isolated by a first voltage buffer before being output to each interval generation branch. Using a resistor divider to generate the offset amount results in a simple circuit implementation and low power consumption. For example, refer to... Figure 9 ,exist Figure 9 In the first voltage buffer, the output terminal outputs the offset Vd.

[0099] It should also be noted that the multiplier generation sub-branch is used to proportionally divide the power supply frequency detection value according to a preset integer multiple, and generate a preset integer multiple voltage that is an integer multiple of the power supply frequency detection value.

[0100] The preset integer multiple voltage is the voltage output by the multiple generation sub-branch, which is equal to the power supply frequency detection value divided by a preset integer multiple. The preset integer multiple voltage serves as the center voltage of the multiple range corresponding to the preset integer multiple.

[0101] The first branch resistor and the second branch resistor are two resistive elements that constitute a resistive voltage divider network. The ratio of their resistance values ​​determines the specific value of a preset integer multiple, wherein the resistance value of the first branch resistor is one less than the preset integer multiple of the second branch resistor.

[0102] The second voltage buffer provides a stable voltage for the subsequent adders and subtractors. An adder is a device that adds two input voltages and outputs the sum. A subtractor is a device that subtracts two input voltages and outputs the difference.

[0103] Both the first and second branch resistors can be resistors with fixed resistance values. The resistance of the first branch resistor is a preset integer multiple of the second branch resistor minus one. For example, when the preset integer multiple is N, N is a positive integer. The voltage divider output is 1 / N of the power supply frequency detection value, which is then buffered by the second voltage buffer before being output as a preset integer multiple voltage. In other words, the resistance ratio of the first and second branch resistors is configured such that the voltage output at the second terminal of the first branch resistor is one-tenth of the preset integer multiple of the power supply frequency detection value.

[0104] The interval generation branch forms a voltage divider network with the first and second branch resistors in the multiple generation sub-branch. Using these resistors, the power frequency detection value is divided into preset integer multiples N to obtain a preset integer multiple voltage VSW / N. After being buffered by the second voltage buffer, this voltage is simultaneously output to the adder and subtractor. The adder adds this preset integer multiple voltage to the offset Vd output from the offset generation branch 60 to obtain the upper limit value VSW / N+Vd of the multiple interval corresponding to the preset integer multiple. The subtractor subtracts this preset integer multiple voltage from the offset Vd to obtain the lower limit value VSW / N-Vd. This circuit achieves proportional scaling of the power frequency detection value through resistor voltage division, and generates the upper and lower limits of the multiple interval in parallel through the adder and subtractor, eliminating the need for complex division circuits. The circuit is simple to implement and has a fast response speed. Each interval generates a branch that is designed for different preset integer multiples. The first branch resistor and the second branch resistor are respectively used with corresponding resistance ratios. This allows for the synchronous generation of multiple intervals corresponding to different preset integer multiples, which are then compared and judged in parallel by the judgment circuit 512, thus improving the comprehensiveness and real-time performance of the detection.

[0105] For example, refer to Figure 10 , Figure 10Taking an interval generation circuit with three interval generation branches (interval generation branch 61, interval generation branch 62, and interval generation branch 63) and multiple preset integer multiples of 3, 4, and 5 as an example, a circuit diagram of the interval generation circuit is given. Figure 10 The diagram shows the multiple generation sub-branch 611 in interval generation branch 61, the multiple generation sub-branch 621 in interval generation branch 62, and the multiple generation sub-branch 631 in interval generation branch 63. Figure 10 The diagram also shows the first branch resistor 2Rb1, the second branch resistor Rb1, and the second voltage buffer BUF21 in the multiplier generation sub-branch 611; the first branch resistor 3Rb2, the second branch resistor Rb3, and the second voltage buffer BUF22 in the multiplier generation sub-branch 621; and the first branch resistor 4Rb3, the second branch resistor Rb3, and the second voltage buffer BUF23 in the multiplier generation sub-branch 631. The resistance values ​​of Rb1, Rb2, and Rb3 can be the same. In the multiple generation sub-branch 611, the voltage value output by BUF21 is VSW / 3. The preset integer multiple corresponding to the multiple generation sub-branch 611 is 3 times. The first output terminal of the interval generation sub-branch 611 is the output terminal of adder AP1, and the second output terminal of the interval generation sub-branch 611 is the output terminal of subtractor AM1. The upper limit value output by the first output terminal of the interval generation sub-branch 61 is VSW / 3+Vd, and the lower limit value output by the second output terminal of the interval generation sub-branch 611 is VSW / 3-Vd. VSW / 3+Vd and VSW / 3-Vd constitute a multiple interval. Figure 10 In the interval generation branch 62, the upper limit of the output is VSW / 4+Vd, and the lower limit is VSW / 4-Vd; the upper limit of the output of the interval generation branch 63 is VSW / 5+Vd, and the lower limit is VSW / 5-Vd. Figure 10 Adder AP2 in interval generation branch 62 and subtractor AM2 in interval generation branch 62 are also shown.

[0106] In one embodiment, please refer to Figure 11 The judgment circuit 512 includes an OR gate and at least one judgment branch. The first reference terminal of the judgment circuit 512 includes the first input terminal of the judgment branch. The input terminal of the judgment circuit 512 includes the second input terminal of the judgment branch. The judgment branch includes an upper limit comparator, a lower limit comparator, and an AND gate. The first input terminal of the decision branch includes the negative input terminal of the upper limit comparator and the positive input terminal of the lower limit comparator. The second input terminal of the decision branch includes the positive input terminal of the upper limit comparator and the negative input terminal of the lower limit comparator. For each decision branch, the positive input of the upper limit comparator in the decision branch is connected to the first output of the interval generation branch in the interval generation circuit 511, and the negative input of the lower limit comparator in the decision branch is connected to the second output of the interval generation branch. Different decision branches are connected to different interval generation branches. The output of the upper limit comparator is connected to the first terminal of the AND gate, the output of the lower limit comparator is connected to the second terminal of the AND gate, the output of the AND gate is connected to the input of the OR gate, and the output of the OR gate outputs the comparison level.

[0107] It should be noted that the judgment circuit 512 is used to receive the line frequency detection value and the upper and lower limits of each multiple interval output by the interval generation circuit 511, and to determine whether the line frequency detection value falls into any multiple interval.

[0108] A decision branch refers to a circuit sub-unit that generates a branch corresponding to a specific interval and is used to independently determine whether the line frequency detection value falls within a multiple of the output interval of that branch. An upper limit comparator is a comparator that compares the line frequency detection value with the upper limit of the multiple interval; its output signal indicates whether the line frequency detection value is lower than the upper limit. A lower limit comparator is a comparator that compares the line frequency detection value with the lower limit of the multiple interval; its output signal indicates whether the line frequency detection value is higher than the lower limit.

[0109] An AND gate is a logic gate circuit that performs a logical AND operation on the output signals of the upper limit comparator and the lower limit comparator. When the horizontal frequency detection value is simultaneously lower than the upper limit value and higher than the lower limit value, the AND gate outputs a valid level, indicating that the horizontal frequency detection value falls within the multiple range corresponding to the judgment branch.

[0110] An OR gate is a logic gate circuit that performs a logical OR operation on the outputs of the AND gates of each decision branch. As long as any decision branch determines that the line frequency detection value falls within its corresponding multiple range, the OR gate will output a preset risk level.

[0111] The judgment circuit 512 includes an OR gate and at least one judgment branch. Each judgment branch corresponds to an interval generation branch; that is, each judgment branch receives the upper and lower limits of a multiple interval output by an interval generation branch. The judgment branch is used to independently determine whether the line frequency detection value falls within the multiple interval output by that interval generation branch. In one optional embodiment, both the upper limit comparator and the lower limit comparator are implemented using high-speed voltage comparators, which facilitates direct input to the OR gate after the AND gate outputs of multiple judgment branches. In another optional embodiment, the upper limit comparator and the lower limit comparator are implemented using hysteresis comparators, avoiding frequent level switching when the line frequency detection value fluctuates slightly near the interval boundary, thereby improving the stability of the comparison level output and reducing unnecessary frequency adjustment triggering.

[0112] The judgment circuit 512 consists of an OR gate and multiple judgment branches, realizing parallel and fast determination of whether the line frequency detection value falls within the multiple range corresponding to any preset integer multiple. In this embodiment, the multiple preset integer multiples can be set based on actual conditions. For example, the multiple preset integer multiples can be 3 times, 4 times, or 5 times, etc. This embodiment does not make a specific limitation on this.

[0113] Each decision branch receives the line frequency detection value and the upper and lower limits of the multiple interval output by the corresponding interval generation branch. Within each decision branch, the upper limit comparator compares the line frequency detection value with the upper limit value connected to its negative input. When the line frequency detection value is lower than the upper limit value, the upper limit comparator outputs a high level. The lower limit comparator compares the line frequency detection value with the lower limit value connected to its positive input. When the line frequency detection value is higher than the lower limit value, the lower limit comparator outputs a high level. An AND gate receives the outputs of the upper and lower limit comparators. The AND gate outputs a high level only when the line frequency detection value simultaneously meets the conditions of being lower than the upper limit value and higher than the lower limit value, i.e., the line frequency detection value falls entirely within the multiple interval. The AND gate outputs of each decision branch are connected to different inputs of an OR gate. As long as any decision branch outputs a high level, the OR gate outputs a preset risk level. Furthermore, in this embodiment, the judgment circuit 512 can synchronously complete the window comparison of all preset integer multiples corresponding to multiple intervals within one row cycle, realizing parallel detection of multiple intervals, significantly improving the comprehensiveness and response speed of detection, and providing a reliable trigger signal for the subsequent frequency control unit 520 to adjust the operating frequency of the power manager 200 in a timely manner during the blanking stage, thereby effectively suppressing water ripples.

[0114] For example, refer to Figure 11 , Figure 11 Taking a judgment circuit that includes three judgment branches (judgment branch 71, judgment branch 72, and judgment branch 73) and multiple preset integer multiples of 3, 4, and 5 as an example, a circuit diagram of the judgment circuit is given; the number of judgment branches is the same as the number of interval generation branches. Figure 11 The diagram also shows the upper limit comparator CMPH1 in decision branch 71, the lower limit comparator CMPL1 in decision branch 71, and the AND gate Y1 in decision branch 71; the upper limit comparator CMPH2 in decision branch 72, the lower limit comparator CMPL2 in decision branch 72, and the AND gate Y2 in decision branch 72; the upper limit comparator CMPH3 in decision branch 73, the lower limit comparator CMPL3 in decision branch 73, and the AND gate Y3 in decision branch 73. When the horizontal frequency voltage VFH falls within the multiple range formed by VSW / 3-Vd and VSW / 3+Vd, the AND gate Y1 will output a high level, and the OR gate OR will also output a high level, which is the preset risk level. Figure 11 The Risk_flag in the OR gate is the comparison level of the OR gate output.

[0115] Furthermore, based on the above embodiments of this application, in another embodiment of this application, the same or similar content as the above embodiments can be referred to the above description, and will not be repeated hereafter. On this basis, this embodiment also provides a display control method applied to the above-mentioned display device, the display control method including steps S10 to S30: Step S10: Obtain the horizontal frequency detection value and the power frequency detection value of the display device, and calculate the detection ratio based on the ratio of the horizontal frequency detection value to the power frequency detection value. Step S20: If the absolute difference between the detection ratio and a preset integer multiple is less than a preset offset, the target frequency is determined from multiple preset frequency levels based on the power frequency detection value. It should be noted that the horizontal frequency detection value is a voltage or frequency value that is detected by the horizontal frequency detection module of the display device and can characterize the current horizontal scanning frequency (the frequency of the horizontal synchronization signal). The power frequency detection value is a voltage or frequency value that is detected by the power frequency detection module of the display device and can characterize the current operating frequency of the power manager.

[0116] The detection ratio is the ratio between the horizontal frequency detection value and the power supply frequency detection value. When both are voltage values, the detection ratio reflects the voltage ratio; when both are frequency values, the detection ratio reflects the frequency ratio.

[0117] The preset integer multiple is a pre-set and stored integer value. The preset offset is used to determine whether the ratio of the horizontal frequency detection value to the power frequency detection value is close to the preset integer multiple. The preset gear frequency is a set of preset discrete power manager operating frequency values, and each preset gear frequency can avoid forming an integer multiple relationship with the horizontal frequency as much as possible.

[0118] For example, in this embodiment, the ratio between the horizontal frequency detection value and the power frequency detection value can be determined by the comparison control module in the display device. In other embodiments, the ratio can also be calculated by running a preset software program. The preset software program can be used to calculate the ratio between the horizontal frequency detection value and the power frequency detection value.

[0119] When the absolute difference between the ratio and a preset integer multiple is less than a preset offset, the preset frequency with the smallest absolute difference between the power manager's operating frequency and the power frequency detection value is selected from a plurality of preset frequency levels stored in advance as the target frequency, and the operating frequency of the power manager is switched to the target frequency during the blanking phase.

[0120] When the absolute difference between the ratio and a preset integer multiple is less than a preset offset, the frequency adjustment amount is calculated based on the direction and degree of the ratio deviating from the preset integer multiple. The sum of the frequency adjustment amount and the operating frequency of the power manager corresponding to the power frequency detection value is used as the target frequency. During the blanking phase, the operating frequency of the power manager is switched to the target frequency.

[0121] If, after adjusting to the target frequency, the horizontal frequency detection value and the power frequency detection value are still detected to be in any preset integer multiple relationship, or close to any preset integer multiple relationship, then other preset frequency levels can be selected for switching until the absolute difference between the ratio of the horizontal frequency detection value and the power frequency detection value and the preset integer multiple is less than the preset offset.

[0122] In this embodiment, a horizontal frequency detection value reflecting the horizontal frequency can be obtained in real time. Then, the need to adjust the power manager's operating frequency can be determined by combining the horizontal frequency detection value with the power frequency detection value detected by the power frequency detection module. During the research process, this application discovered that when the horizontal frequency and the power manager's operating frequency are integer multiples, the ripple is significantly amplified, resulting in a water ripple effect. Therefore, this application obtains the horizontal frequency detection value through the horizontal frequency detection module and the power frequency detection value through the power frequency detection module. The comparison control module accurately determines whether the horizontal frequency detection value and the power frequency detection value are integer multiples or nearly integer multiples, thereby improving the reliability of the determination.

[0123] This embodiment adjusts the operating frequency of the power manager when the absolute difference between the ratio of the horizontal frequency detection value and the power frequency detection value and a preset integer multiple is less than a preset offset. This can disrupt the integer multiple relationship between the horizontal frequency and the operating frequency of the power manager, thereby suppressing the significant amplification of ripples and eliminating or reducing water ripple phenomena such as slowly moving stripes and local brightness fluctuations in the display screen, thus improving display quality.

[0124] Step S30: Control the power manager to run at the target frequency to adjust the operating frequency of the power manager.

[0125] It should be noted that the target frequency refers to the frequency selected from multiple preset frequency ranges when the ratio of the current horizontal frequency detection value to the power frequency detection value falls within a multiple range. The adjusted power manager will then operate at this target frequency.

[0126] For example, multiple preset frequency levels are sorted according to their frequency values, and the previous or next frequency level adjacent to the current power supply frequency is selected as the target frequency, thereby reducing the impact of frequency switching on the power manager's output stability. The current power supply frequency is the operating frequency of the power manager corresponding to the power supply frequency detection value. In other embodiments, any preset frequency level can be selected as the target frequency from multiple preset frequency levels.

[0127] This embodiment uses a pre-set multiple preset frequency levels to ensure that the working frequency after switching is no longer an integer multiple or close to the current horizontal frequency, thereby suppressing the resonance amplification of ripples, eliminating the water ripple phenomenon in the display screen, and improving display quality.

[0128] In a feasible embodiment, the display control method further includes steps A10 to A30: Step A10: Obtain the ripple voltage of the display device; Step A20: Generate an offset voltage based on the ripple voltage and a preset conversion ratio; Step A30: Use the offset voltage as the offset amount.

[0129] It should be noted that ripple voltage is the amplitude of the AC fluctuation voltage generated on the power rail of the display device due to the switching action of the power manager. Ripple voltage reflects the degree of coupling between the horizontal scanning frequency and the operating frequency of the power manager. The larger the ripple voltage, the stronger the coupling, and the higher the risk of water ripples. It also indicates that the horizontal scanning frequency and the operating frequency of the power manager are integer multiples or close to integer multiples. In this embodiment, the ripple voltage of the display device can be detected by a ripple detection circuit.

[0130] The preset conversion ratio refers to a pre-set proportional coefficient used to convert ripple voltage into a corresponding offset voltage. The preset conversion ratio defines the mapping relationship between ripple voltage and offset. The preset conversion ratio can be set based on actual conditions; this embodiment does not impose specific limitations on this. For example, the preset conversion ratio can be obtained through experimental calibration. During the development or production line testing phase of the display device, the power manager's operating frequency is manually set so that the ratio of the horizontal frequency detection value to the power frequency detection value gradually approaches a preset integer multiple. Simultaneously, the ripple voltage on the power supply rail and the visibility of the water ripples on the display screen are monitored. The ripple voltage corresponding to when the water ripples first reach a level perceptible to the human eye is recorded as the critical ripple voltage. The deviation between this ratio and the preset integer multiple is recorded as the critical deviation. The ratio of the critical deviation to the critical ripple voltage is used as the preset conversion ratio.

[0131] Offset voltage refers to the voltage signal generated by converting ripple voltage through a preset conversion ratio. This voltage signal can be directly provided as an offset to the interval generation circuit to determine the width of the multiple interval.

[0132] In other embodiments, the offset may also be set based on the experience of the display device developer, and this embodiment does not specifically limit it.

[0133] This embodiment acquires the ripple voltage on the power supply rail of the display device and generates an offset voltage based on the ripple voltage and a preset conversion ratio. This offset voltage is then used as the offset in the comparison control module to determine the frequency coupling relationship. When the ripple voltage increases, the offset voltage also increases, widening the multiplier range and enabling more timely triggering of the power manager's operating frequency adjustment. Conversely, when the ripple voltage is low, the offset voltage decreases, narrowing the multiplier range and preventing frequent unnecessary frequency adjustments due to excessive offset, thus ensuring stable operation of the display device. By correlating the offset with the ripple voltage in real time, adaptive dynamic adjustment of the offset is achieved, effectively suppressing ripples while maintaining the stability of the display device.

[0134] In a feasible embodiment, the display control method further includes step B10 and / or step B30: Step B10: If the refresh rate of the display device is greater than the preset high refresh rate threshold, decrease the offset; if the refresh rate of the display device is less than the preset low refresh rate threshold, increase the offset. It should be noted that the preset high refresh rate threshold is a pre-set refresh rate threshold used to determine whether the display device is in a high refresh rate working state. When the refresh rate of the display device is higher than the preset high refresh rate threshold, it indicates that the display device is currently in high refresh rate mode.

[0135] The preset low refresh rate threshold is a pre-set refresh rate threshold used to determine whether the display device is in a low refresh rate working state. When the refresh rate of the display device is lower than the preset low refresh rate threshold, it indicates that it is currently in low refresh rate mode.

[0136] The refresh rate of the display device is divided into a high refresh rate range, a normal refresh rate range, and a low refresh rate range. When the refresh rate is greater than a preset high refresh rate threshold, the offset is decreased by a preset step size; when the refresh rate is less than a preset low refresh rate threshold, the offset is increased by a preset step size; when the refresh rate is between the preset high refresh rate and the preset low refresh rate threshold, the offset remains unchanged. The preset step size can be determined based on actual conditions, and this embodiment does not impose a specific limitation on it; it can be set according to actual conditions.

[0137] When the refresh rate is low, the single-frame scan cycle is longer, and the voltage attenuation on the pixel electrodes is relatively greater, resulting in a decrease in the average brightness of the actual displayed image, making the overall image darker. In low refresh rate scenarios with darker images, the human eye's sensitivity to brightness fluctuations increases significantly. Therefore, the water ripple effect will be more pronounced in low refresh rate mode, and even weak ripple amplification is easily perceived by the human eye. Therefore, when the refresh rate is less than a preset low refresh rate threshold, the offset is increased to expand the multiple range corresponding to each preset integer multiple, making the comparison control module more sensitive to comparison values ​​close to integer multiples, thus achieving a more reliable water ripple suppression effect in low refresh rate mode. Conversely, when the refresh rate is greater than a preset high refresh rate threshold, the single-frame scan cycle is shorter, the overall brightness of the displayed image tends to increase, the human eye's sensitivity to brightness fluctuations is relatively reduced, and the visibility of water ripples decreases. At this point, by reducing the offset to narrow the multiplier range, the detection sensitivity can be reduced, avoiding unnecessary frequency adjustment operations when the ripple amplification is insufficient to cause visible water ripples. This reduces the frequency of power manager frequency switching, which is beneficial for maintaining the stability of the display at high refresh rates.

[0138] When the offset is determined based on the ripple voltage and the preset conversion ratio, the offset can be further adjusted when the display device is detected to be in high refresh rate mode or low refresh rate mode.

[0139] Specifically, based on the offset determined by the ripple voltage and a preset conversion ratio, if the refresh rate of the display device is greater than a preset high refresh rate threshold, the offset can be further reduced; if the refresh rate of the display device is less than a preset low refresh rate threshold, the offset can be further increased. This allows the offset to both adaptively change with the ripple voltage and be further adjusted according to the refresh rate, ensuring that both ripple suppression and display device stability are maintained at different refresh rates.

[0140] Step B20: If the temperature of the display device is detected to be greater than a preset high temperature threshold, increase the offset.

[0141] It should be noted that the preset high temperature threshold is a pre-set temperature threshold used to determine whether the internal temperature of the display device is too high. When the temperature of the display device is greater than the preset high temperature threshold, it indicates that the power manager is at greater risk of operating frequency drift due to temperature rise.

[0142] For example, a temperature sensor can be used to detect the temperature inside the display device or near the power manager in real time. When the detected temperature exceeds a preset high-temperature threshold, the offset is increased by a preset change amount to widen the range of multiples, compensating for the judgment deviation caused by changes in the power manager's operating frequency due to temperature drift. The preset change amount can be set based on actual conditions, and this embodiment does not impose specific limitations on it.

[0143] When the refresh rate of the display device is greater than a preset high refresh rate threshold and the detected temperature is greater than a preset high temperature threshold, an adjustment priority can be set. For example, when the temperature of the display device is greater than a preset high temperature threshold, regardless of whether the current refresh rate is greater than or less than a preset low refresh rate threshold, step B20 is executed. In other embodiments, an adjustment priority based on the refresh rate adjustment offset can be set to be higher than the adjustment priority based on the temperature adjustment offset. This embodiment does not specifically limit this, and the specific setting can be based on the actual situation.

[0144] In other embodiments, when the refresh rate of the display device is greater than a preset high refresh rate threshold and the detected temperature is greater than a preset high temperature threshold, a first adjustment amount that the offset of the display device needs to be reduced when it is at a high refresh rate can be obtained, and a second adjustment amount that the offset of the display device needs to be increased when the temperature is greater than a preset high temperature threshold can be obtained. The sum of the reduced first adjustment amount and the increased second adjustment amount can be calculated to obtain the target adjustment amount, and the offset can be adjusted based on the target adjustment amount.

[0145] When the temperature rises and the risk of power manager operating frequency drift increases, the offset is increased to expand the multiple range corresponding to each preset integer multiple. This can effectively compensate for the judgment deviation that may be caused by PMIC operating frequency drift, and prevent the operating frequency that has already avoided integer multiple relationships from drifting back into the risk range and not being detected due to temperature changes. Thus, it can still maintain reliable suppression of water ripples under high temperature conditions.

[0146] To better understand this embodiment, please refer to Figure 13The process of this embodiment is briefly described, including at least steps W1 to W5. Step W1: Obtain the horizontal frequency detection value; Step W2: Obtain the power frequency detection value; Step W3: Based on the power frequency detection value, a preset offset, and at least one preset integer multiple, construct a multiple interval corresponding to each preset integer multiple; for example, for each preset integer multiple, determine the ratio of the power frequency detection value to the preset integer multiple to obtain the interval center voltage, add the offset to the interval center voltage to obtain the upper limit of the multiple interval corresponding to the preset integer multiple, and subtract the offset from the interval center voltage to obtain the lower limit of the multiple interval. Step W4: Determine whether the horizontal frequency detection value falls within any multiple interval; if the horizontal frequency detection value falls within any multiple interval, execute step W5 to adjust the operating frequency of the power manager during the blanking phase. If the horizontal frequency detection value does not fall within any multiple interval, return to execute step W1. After step W5, the following can also be performed: wait for a preset stabilization period, and then return to step W1 after waiting for the preset stabilization period. The preset stabilization period can be set based on the actual situation. This embodiment does not make a specific limitation on this. The purpose of waiting for the preset stabilization period is to wait for the operating frequency adjusted by the power manager to stabilize before obtaining the power frequency detection value and the horizontal frequency detection value. This will help improve the reliability of obtaining the power frequency detection value and improve the accuracy of determining whether to adjust the operating frequency of the power manager.

[0147] The above are merely preferred embodiments of the present application and do not limit the patent scope of the present application. Any equivalent structural or procedural transformations made using the description and drawings of the present application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present application.

Claims

1. A display device, characterized in that, The display device includes a timing controller, a power manager, a horizontal frequency detection module, a power frequency detection module, and a comparison control module; The first output terminal of the timing controller is connected to the input terminal of the line frequency detection module, and the output terminal of the line frequency detection module is connected to the first input terminal of the comparison control module. The input terminal of the power frequency detection module is connected to the frequency detection terminal of the power manager, the output terminal of the power frequency detection module is connected to the second input terminal of the comparison control module, and the output terminal of the comparison control module is connected to the frequency control terminal of the power manager. The line frequency detection module is used to receive the display timing signal output by the timing controller in order to detect the line frequency detection value; The power frequency detection module is used to collect the frequency signal of the power manager in order to detect the power frequency detection value. The comparison control module is used to adjust the operating frequency of the power manager when the absolute difference between the detection ratio and a preset integer multiple is less than a preset offset, wherein the detection ratio is the ratio between the horizontal frequency detection value and the power frequency detection value.

2. The display device as claimed in claim 1, characterized in that, The line frequency detection module also includes a first pulse shaping unit, a charge conversion unit, and an integral filtering unit connected in sequence. The input terminal of the first pulse shaping unit is connected to the first output terminal of the timing controller, and the output terminal of the integral filtering unit is connected to the first input terminal of the comparison control module. The first pulse shaping unit is used to shape the display timing signal into a first standard pulse signal with a preset first stable width; The charge conversion unit is used to convert the first standard pulse signal into charge. The integral filtering unit is used to integrate the charge output by the charge conversion unit and output the line frequency detection value.

3. The display device as claimed in claim 2, characterized in that, The charge conversion unit includes a first switching transistor, a current source, and a first capacitor; the integral filtering unit includes a first operational amplifier, a second operational amplifier, a second capacitor, and a first resistor. The control terminal of the first switching transistor is connected to the output terminal of the first pulse shaping unit, the first terminal of the first switching transistor is used to connect to a preset power supply terminal, and the second terminal of the first switching transistor is connected to the first terminal of the current source. The second end of the current source is connected to the first end of the first capacitor, and the second end of the first capacitor is connected to a preset low voltage terminal. The first end of the first capacitor is connected to the first end of the first resistor, the second end of the first resistor is connected to the negative input terminal of the first operational amplifier, and the positive input terminal of the first operational amplifier is connected to the preset low voltage terminal. The second capacitor is disposed between the negative input terminal and the output terminal of the first operational amplifier; The output terminal of the first operational amplifier is connected to the positive input terminal of the second operational amplifier, the negative input terminal of the second operational amplifier is connected to the output terminal of the second operational amplifier, and the output terminal of the second operational amplifier outputs the line frequency detection value.

4. The display device as claimed in claim 1, characterized in that, The power frequency detection module includes an input filtering unit, a second pulse shaping unit, and a frequency conversion unit connected in sequence. The input filtering unit is connected to the frequency detection terminal, and the output terminal of the frequency conversion unit is connected to the second input terminal of the comparison control module. The input filtering unit is used to filter the frequency signal sampled at the frequency detection terminal, and the second pulse shaping unit is used to shape the signal output by the input filtering unit into a second standard pulse signal with a preset second stable width. The frequency conversion unit is used to output the power frequency detection value based on the second standard pulse signal.

5. The display device as claimed in claim 4, characterized in that, The input filtering unit includes a filter resistor, a filter capacitor, a first diode, and a second diode; the frequency conversion unit includes a second switch, a second resistor, a third resistor, a third capacitor, and a third operational amplifier. The first end of the filter resistor is connected to the frequency detection terminal, the second end of the filter resistor is connected to the first end of the filter capacitor, and the second end of the filter capacitor is connected to the preset low voltage terminal. The anode of the first diode is connected to a preset power supply terminal, the cathode of the first diode is connected to the second terminal of the filter resistor, the cathode of the second diode and the input terminal of the second pulse shaping unit, and the anode of the second diode is connected to a preset low voltage terminal. The output terminal of the second pulse shaping unit is connected to the control terminal of the second switching transistor. The first terminal of the second switching transistor is connected to the first terminal of the second resistor, the first terminal of the third capacitor, and the positive input terminal of the third operational amplifier. The second terminal of the third capacitor is connected to a preset low voltage terminal. The second terminal of the second switch is connected to the first terminal of the third resistor, and the second terminal of the third resistor is connected to a preset low voltage terminal. The negative input terminal of the third operational amplifier is connected to the output terminal of the third operational amplifier, and the output terminal of the third operational amplifier outputs the power supply frequency detection value.

6. The display device as claimed in claim 1, characterized in that, The comparison control module includes a comparison unit and a frequency control unit; The first comparison terminal of the comparison unit is used as the first input terminal of the comparison control module, and the second comparison terminal of the comparison unit is used as the second input terminal of the comparison control module. The output terminal of the comparison unit is connected to the input terminal of the frequency control unit, and the control terminal of the frequency control unit is connected to the second output terminal of the timing controller. The comparison unit is used to output a comparison level based on the line frequency detection value and the power frequency detection value, wherein, when the absolute difference between the detection ratio and a preset integer multiple is less than a preset offset, the comparison level output by the comparison unit is a preset risk level. The frequency control unit is used to adjust the operating frequency of the power manager during the blanking phase when the comparison level output by the comparison unit is a preset risk level.

7. The display device as claimed in claim 6, characterized in that, The comparison unit includes an interval generation circuit and a judgment circuit. The interval generation circuit includes an offset generation branch and at least one interval generation branch. The first reference terminal of the judgment circuit is used as the first comparison terminal of the comparison unit, and the second reference terminal of the interval generation circuit is used as the second comparison terminal of the comparison unit. The judgment circuit is used to output a comparison level; The input terminal of the offset generation branch is connected to a preset interval width control voltage, and the offset generation branch is used to output the offset amount based on the preset interval width control voltage. For each interval generation branch, the branch input terminal of the interval generation branch is connected to the second reference terminal, the offset input terminal of the interval generation branch is connected to the output terminal of the offset generation branch, and the first and second output terminals of the interval generation branch are both connected to the input terminal of the judgment circuit. The first output terminal of the interval generation branch is used to output the upper limit value of the multiple interval corresponding to the preset integer multiple, and the second output terminal of the interval generation branch is used to output the lower limit value of the multiple interval. The preset integer multiples corresponding to the branch generated in each interval are different.

8. The display device as claimed in claim 7, characterized in that, The offset generation branch includes a first-width resistor, a second-width resistor, and a first voltage buffer; The interval generation branch includes a multiple generation sub-branch, an adder, and a subtractor. The multiple generation sub-branch is used to generate a preset integer multiple voltage that is a preset integer multiple of the power supply frequency detection value. The first end of the first width resistor is connected to a preset interval width control voltage, the second end of the first width resistor is connected to the first end of the second width resistor, and the second end of the second width resistor is connected to a preset low voltage end. The input terminal of the first voltage buffer is connected to the second terminal of the first width resistor, and the output terminal of the first voltage buffer serves as the output terminal of the offset generation branch. The multiplier generation sub-branch includes a first branch resistor, a second branch resistor, and a second voltage buffer; The first end of the first branch resistor is connected to the power frequency detection value, the second end of the first branch resistor is connected to the first end of the second branch resistor, and the second end of the second branch resistor is connected to a preset low level. The input terminal of the second voltage buffer is connected to the second terminal of the first branch resistor, and the output terminal of the second voltage buffer is connected to the first terminal of the adder and the first terminal of the subtractor. The offset input terminal of the interval generation branch includes the second terminal of the adder and the second terminal of the subtractor, and the offset input terminal is connected to the output terminal of the offset generation branch.

9. The display device as claimed in claim 7, characterized in that, The judgment circuit includes an OR gate and at least one judgment branch. The first reference terminal of the judgment circuit includes the first input terminal of the judgment branch, and the input terminal of the judgment circuit includes the second input terminal of the judgment branch. The judgment branch includes an upper limit comparator, a lower limit comparator, and an AND gate. The first input terminal of the decision branch includes the negative input terminal of the upper limit comparator and the positive input terminal of the lower limit comparator; the second input terminal of the decision branch includes the positive input terminal of the upper limit comparator and the negative input terminal of the lower limit comparator. For each decision branch, the positive input of the upper limit comparator in the decision branch is connected to the first output of the interval generation branch in the interval generation circuit, and the negative input of the lower limit comparator in the decision branch is connected to the second output of the interval generation branch. Different decision branches are connected to different interval generation branches. The output of the upper limit comparator is connected to the first terminal of the AND gate, the output of the lower limit comparator is connected to the second terminal of the AND gate, the output of the AND gate is connected to the input of the OR gate, and the output of the OR gate outputs a comparison level.

10. A display control method, characterized in that, The display control method is applied to the display device as described in claim 1, and the display control method further includes: The horizontal frequency detection value and the power frequency detection value of the display device are obtained, and the detection ratio value is calculated based on the ratio of the horizontal frequency detection value to the power frequency detection value. If the absolute difference between the detection ratio and a preset integer multiple is less than a preset offset, the target frequency is determined from multiple preset frequency levels based on the power frequency detection value. Control the power manager to operate at the target frequency to adjust the operating frequency of the power manager.

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