Driving circuit of double-gate transistor and display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a driving circuit of a double-gate transistor and a display panel. The driving circuit comprises: a first negative voltage module configured to generate a first negative voltage in a frame interval period in response to a first trigger signal; a second negative voltage module configured to generate a second negative voltage in the frame interval period in response to a second trigger signal; wherein the second negative voltage is smaller than the first negative voltage; and an output module connected with the first negative voltage module, the second negative voltage module and a top gate of the double-gate transistor respectively, and configured to output the first negative voltage to the top gate of the double-gate transistor in a first interval sub-period and output the second negative voltage to the top gate of the double-gate transistor in a second interval sub-period, so as to turn off the double-gate transistor; wherein the frame interval period comprises the first interval sub-period and the second interval sub-period. The application improves the reliability of turning off the double-gate transistor.

Description

Technical Field

[0001] This disclosure belongs to the field of display technology, specifically relating to a driving circuit for a dual-gate transistor and a display panel. Background Technology

[0002] Oxide TFTs (Oxide Thin-Film Transistors) are widely used in LCDs (Liquid Crystal Displays), OLEDs (Organic Light-Emitting Diodes), electronic paper, Micro-LEDs (Micro Light-Emitting Diodes), and automotive displays due to their advantages such as high mobility, good uniformity, and low leakage current. In related technologies, the driving circuits for dual-gate transistor structures mainly use fixed negative voltage amplitude and fixed negative voltage duration to turn off the dual-gate transistors. However, fixed negative voltage amplitude and fixed negative voltage duration will cause the turn-off system to be at peak output current for a long time, which will lead to low turn-off reliability of the dual-gate transistors.

[0003] Therefore, improving the turn-off reliability of dual-gate transistors is a problem that urgently needs to be solved. Summary of the Invention

[0004] This application provides a driving circuit and display panel for a dual-gate transistor, which improves the reliability of the dual-gate transistor's turn-off. In a first aspect, this application provides a driving circuit for a dual-gate transistor. The driving circuit includes: a first negative voltage module configured to generate a first negative voltage during a frame interval in response to a first trigger signal; a second negative voltage module configured to generate a second negative voltage during the frame interval in response to a second trigger signal; wherein the second negative voltage is less than the first negative voltage; and an output module connected to the first negative voltage module, the second negative voltage module, and the top gate of the dual-gate transistor, respectively, configured to output the first negative voltage to the top gate of the dual-gate transistor during a first interval sub-period and output the second negative voltage to the top gate of the dual-gate transistor during a second interval sub-period to turn off the dual-gate transistor; wherein the frame interval includes the first interval sub-period and the second interval sub-period.

[0005] Optionally, the output module further includes: an isolation unit, connected to the first negative voltage module, the second negative voltage module, and the sustaining node respectively, configured to: output the first negative voltage to the sustaining node during the first interval period, and output the second negative voltage to the sustaining node during the second interval period; an output unit, connected to the sustaining node, configured to: output the first negative voltage or the second negative voltage on the sustaining node to the top gate of the dual-gate transistor; a detection unit, connected to the sustaining node, configured to: detect the voltage on the sustaining node; and a control unit, connected to the detection unit and the isolation unit respectively, configured to: generate an isolation control signal when it is determined that the voltage on the sustaining node is less than a first preset sustaining threshold, so as to control the isolation unit to disconnect from the sustaining node.

[0006] Optionally, the control unit is further configured to: generate a first switching signal in the first interval sub-period and generate a second switching signal in the second interval sub-period; the isolation unit includes: a switching subunit connected to the control unit, the first negative pressure module, and the second negative pressure module respectively, configured to: output the first negative pressure under the action of the first switching signal and output the second negative pressure under the action of the second switching signal; and an isolation subunit connected to the switching subunit, the control unit, and the maintenance node respectively, configured to: output the first negative pressure or the second negative pressure to the maintenance node; and disconnect from the maintenance node according to the isolation control signal.

[0007] Optionally, the control unit is further configured to generate a compensation control signal when the voltage of the sustaining node is less than a second preset sustaining threshold and greater than a first preset sustaining threshold; wherein the second preset sustaining threshold is less than the first negative voltage; the output module further includes a compensation unit connected to the control unit and configured to charge the sustaining node under the action of the compensation control signal so that the sustaining node stably outputs the second negative voltage.

[0008] Optionally, the control unit is also connected to the first negative pressure module and the second negative pressure module, and is configured to: determine the first trigger signal, the first interval sub-period, the second trigger signal and the second interval sub-period based on temperature parameters, brightness parameters and refresh rate.

[0009] Optionally, the switching subunit includes: a first switch and a second switch; the control terminal of the first switch is connected to the control unit, the first end of the first switch is connected to the first negative pressure module, and the second end of the first switch is connected to the isolation subunit; the control terminal of the second switch is connected to the control unit, the first end of the second switch is connected to the second negative pressure module, and the second end of the second switch is connected to the isolation subunit; or, the isolation subunit includes an isolation switch; the control terminal of the isolation switch is connected to the control unit, the first end of the isolation subunit is connected to the switching subunit, and the second end of the isolation subunit is connected to the maintaining node.

[0010] Optionally, the detection unit includes: a first resistor, a second resistor, and an amplifier; a first end of the first resistor is connected to the sustaining node, a second end of the first resistor is connected to the first end of the second resistor and the non-inverting input of the amplifier; a second end of the second resistor is connected to a low-potential terminal; the inverting input of the amplifier is connected to the low-potential terminal, and the output of the amplifier is connected to the control unit.

[0011] Optionally, the output unit includes: a first capacitor, an output buffer, and a second capacitor; the first terminal of the first capacitor is connected to the input terminal of the output buffer and the sustain node, and the second terminal of the first capacitor is connected to a low-potential terminal; the output terminal of the output buffer is connected to the first terminal of the second capacitor and the top gate of the dual-gate transistor; the second terminal of the second capacitor is connected to a low-potential terminal.

[0012] Optionally, the compensation unit includes: a bias generator, a microcurrent source, and a compensation transistor; the bias generator is connected to a first terminal of the microcurrent source; the second terminal of the microcurrent source is connected to a first terminal of the compensation transistor; the control terminal of the compensation transistor is connected to the control unit, and the second terminal of the compensation transistor is connected to the sustaining node.

[0013] Secondly, this application provides a display panel, comprising: a plurality of dual-gate transistors arranged in an array and a driving circuit for the dual-gate transistors as described in any one of the first aspects, wherein the driving circuit for the dual-gate transistors is connected to the top gate of the dual-gate transistors.

[0014] The technical solution provided in this application has at least the following beneficial effects: In this application, a first negative voltage module is set to output a first negative voltage, and a second negative voltage module is set to output a second negative voltage. The output module outputs the first negative voltage to the top gate of the dual-gate transistor during the first interval period. After the display period ends, it first enters the pre-depletion stage, where some residual electrons in the channel are driven away from the channel region. By outputting the second negative voltage to the top gate of the dual-gate transistor during the second interval period, it enters the deep depletion stage, and the second negative voltage is less than the first negative voltage, which further expands the channel depletion region and clears the remaining electron carriers, realizing the gradual switching of the two-stage negative voltage. Compared with the fixed negative voltage used to turn off the dual-gate transistor in related technologies, the dual-gate transistor is turned off by two-stage negative voltage in this application, which can reduce the transient electric field impact of the gate dielectric and reduce the peak output current of the first and second negative voltage modules, thereby improving the turn-off reliability of the dual-gate transistor. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0016] Figure 1 A schematic diagram of a driving circuit for a dual-gate transistor provided in an embodiment of this application is shown.

[0017] Figure 2 A schematic diagram of a dual-gate transistor provided in an embodiment of this application is shown.

[0018] Figure 3 The diagram shows a driving timing diagram of a dual-gate transistor according to an embodiment of this application.

[0019] Figure 4 A schematic diagram of another driving circuit for a dual-gate transistor provided in an embodiment of this application is shown.

[0020] Figure 5 A circuit diagram of a driving circuit for a dual-gate transistor provided in an embodiment of this application is shown.

[0021] Figure 6 A circuit diagram of a negative pressure module provided in an embodiment of this application is shown.

[0022] Figure 7 A circuit diagram of another negative pressure module provided in an embodiment of this application is shown.

[0023] Explanation of reference numerals in the attached figures: 100, First negative pressure module; 110, Energy storage unit; 200, Second negative pressure module; 300, Output module; 310, Isolation unit; 311, Switching subunit; 312, Isolation subunit; 320, Output unit; 330, Control unit; 340, Detection unit; 350, Compensation unit; 351, Bias generator.

[0024] S1, First switch; S2, Second switch; S3, Third switch; T1, Isolating switch; T2, Compensation transistor; T3, Enable transistor; T4, Fourth transistor; T5, Fifth transistor; C1, First capacitor; C2, Second capacitor; C3, Third capacitor; C4, Fourth capacitor; C5, Fifth capacitor; R1, First resistor; R2, Second resistor; R3, Third resistor; R4, Fourth resistor; D1, First diode; D2, Second diode; D3, Third diode; VDD, Power supply terminal; GND, Low potential terminal; Icomp, Microcurrent source; EA, Amplifier; H1, Output buffer; H2, Input buffer; EN1, First trigger signal; EN2, Second trigger signal; N1, First enable signal; N2, Second enable signal; EN_Comp, Compensation control signal; EN_hold, Isolation control signal; VCP, Negative voltage receiver; VTG, Top gate of dual-gate transistor. Detailed Implementation

[0025] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0026] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0027] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0028] Figure 1A schematic diagram of a driving circuit for a dual-gate transistor according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 1 As shown, the driving circuit includes: a first negative pressure module 100, a second negative pressure module 200 and an output module 300. The output module 300 is connected to the first negative pressure module 100, the second negative pressure module 200 and the top gate of the dual-gate transistor, respectively.

[0029] In some embodiments, the first negative pressure module 100 is configured to generate a first negative pressure during a frame interval in response to a first trigger signal.

[0030] Figure 2 A schematic diagram of a dual-gate transistor provided in an embodiment of this application is shown below. Please refer to [link / reference]. Figure 2 As shown, the dual-gate transistor includes: a substrate (glass / PI) (1), a bottom gate dielectric layer (2), and a bottom gate dielectric layer (SiN). x (3) IGZO channel dielectric layer (20nm) (4) Source electrode (Mo) (5) Top gate dielectric layer (SiO2) (6) Top gate electrode (Mo / Al / Mo) (7). The source electrode (5) is located on both sides of the IGZO channel layer; when a positive voltage is applied to the top gate electrode (7), the dual-gate transistor is turned on; when a negative voltage is applied to the top gate electrode (7), the dual-gate transistor is turned off.

[0031] For example, the first trigger signal will trigger the first negative voltage module 100 to start. During the frame interval, the first negative voltage module 100 generates a first negative voltage to be output to the top gate of the dual-gate transistor. The first negative voltage can be between -1V and -2V, and specifically it can be -1.5V.

[0032] In some embodiments, the second negative pressure module 200 is configured to generate a second negative pressure during a frame interval in response to a second trigger signal; wherein the second negative pressure is less than the first negative pressure.

[0033] For example, the second trigger signal will trigger the second negative voltage module 200 to start. By setting the second negative voltage module 200 to generate a second negative voltage during the frame interval, the second negative voltage can be output to the top gate of the dual-gate transistor. The second negative voltage can be between -3V and -6V, specifically -4V.

[0034] In some embodiments, the output module 300 is configured to: output a first negative voltage to the top gate of the dual-gate transistor during a first interval period, and output a second negative voltage to the top gate of the dual-gate transistor during a second interval period to turn off the dual-gate transistor; wherein the frame interval period includes: a first interval period and a second interval period.

[0035] For example, the output module 300 outputs a first negative voltage to the top gate of the dual-gate transistor during the first interval period. After the display period ends, it first enters the pre-depletion stage, where some residual electrons in the channel are driven away from the channel region. Then, the output module 300 outputs a second negative voltage to the top gate of the dual-gate transistor during the second interval period, entering the deep depletion stage. The second negative voltage is less than the first negative voltage, which further expands the channel depletion region and clears the remaining electron carriers, realizing the gradual switching of two negative voltages. Compared with the fixed negative voltage used to turn off the dual-gate transistor in related technologies, the present application uses two negative voltages to gradually turn off the dual-gate transistor, which can reduce the transient electric field impact of the gate dielectric and reduce the peak output current of the first negative voltage module 100 and the second negative voltage module 200, thereby improving the turn-off reliability of the dual-gate transistor.

[0036] Figure 3 This paper illustrates a driving timing diagram of a dual-gate transistor according to an embodiment of this application. Please refer to [link / reference]. Figure 3 As shown, the driving timing includes the bottom gate scan signal (BG Sacn) and the top gate voltage V. TG Negative voltage enable N1 / N2, maintain node Vnood and negative voltage state NEG-STATUS. A scan frame signal includes a display period T1 and a frame interval period T2. During the display period T1, the top gate V of the dual-gate transistor... TG Upon receiving a positive voltage (+2V), the transistor is turned on to drive the pixel; the frame interval T2 includes a first interval sub-period and a second interval sub-period; the top gate V of the dual-gate transistor... TG The voltage received in the first interval sub-period is -1.5V, and the voltage received in the second interval sub-period is -4V. The first trigger signal includes a first enable signal and a first clock signal; the second trigger signal includes a second enable signal and a second clock signal. The first enable signal and the second enable signal are 0V in the display period T1 and the second frame interval sub-period, and 1V in the first frame interval sub-period. In the display period T1, the first negative voltage module 100 and the second negative voltage module 200 output voltage of 0V. In the first interval sub-period, the first negative voltage module 100 outputs a first negative voltage of -1.5V, and in the second interval sub-period, the second negative voltage module 200 outputs a second negative voltage of -4V.

[0037] Figure 4 A circuit diagram of a driving circuit for a dual-gate transistor according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 4 As shown, the output module 300 also includes: an isolation unit 310, an output unit 320, a detection unit 340, and a control unit 330. The isolation unit 310 is connected to the first negative pressure module 100, the second negative pressure module 200, the maintenance node Vnood, and the control unit 330, respectively. The detection unit 340 is connected to the maintenance node Vnood, and the control unit 330 is connected to the detection unit 340.

[0038] In some embodiments, the isolation unit 310 is configured to output a first negative voltage to the sustaining node Vnood in a first interval period and output a second negative voltage to the sustaining node Vnood in a second interval period.

[0039] For example, by setting up an isolation unit 310, the isolation unit 310 will form an isolation between the first negative pressure module 100 and the maintenance node Vnood, and between the second negative pressure module 200 and the maintenance node Vnood. It can output the first negative pressure output by the first negative pressure module 100 to the maintenance node Vnood in the first interval period, and output the second recovery output by the second negative pressure module 200 to the maintenance node Vnood in the second interval period to charge the maintenance node Vnood.

[0040] In some embodiments, the output unit 320 is configured to output a first negative voltage or a second negative voltage on the sustaining node Vnood to the top gate of the dual-gate transistor.

[0041] For example, the output unit 320 is connected to the sustain node Vnood and the top gate of the dual-gate transistor, respectively. When the sustain node Vnood is charged to a first negative voltage or a second negative voltage, the output unit 320 outputs the first negative voltage or the second negative voltage to the top gate of the dual-gate transistor to turn off the dual-gate transistor.

[0042] In some embodiments, the detection unit 340 is configured to detect the voltage on the sustaining node Vnood.

[0043] For example, by setting the detection unit 340 to be connected to the sustaining node Vnood, the voltage magnitude on the sustaining node Vnood can be detected, and the isolation unit 310 can be disconnected from the sustaining node Vnood based on the voltage magnitude on the sustaining node Vnood.

[0044] In some embodiments, the control unit 330 is configured to generate an isolation control signal when it is determined that the voltage on the sustaining node Vnood is less than a first preset sustaining threshold, so as to control the isolation unit 310 to disconnect from the sustaining node Vnood.

[0045] For example, when the negative voltage on the sustaining node Vnood is less than the first preset sustaining threshold, the voltage on the sustaining node Vnood has reached the second negative voltage, which can turn off the dual-gate transistor. This generates an isolation control signal to control the connection between the isolation unit 310 and the sustaining node Vnood, forming isolation between the first negative voltage module 100 and the sustaining node Vnood, and between the second negative voltage module 200 and the sustaining node Vnood. This prevents the first negative voltage module 100 or the second negative voltage module 200 from outputting excessively low negative voltages that could damage the downstream load of the sustaining node Vnood. Specifically, the first preset sustaining threshold can be located between -4V and -6V.

[0046] In some embodiments, the control unit 330 is further configured to generate a first switching signal in a first interval sub-period and a second switching signal in a second interval sub-period.

[0047] For example, by setting the control unit 330 to generate a first switching signal in the first interval sub-period, the first negative pressure output by the first negative pressure module 100 is controlled to be output to the maintenance node Vnood in the first interval sub-period; by setting the control unit 330 to generate a second switching signal in the second interval sub-period, the second negative pressure output by the second negative pressure module 200 is controlled to be output to the maintenance node Vnood in the second interval sub-period.

[0048] In some embodiments, the isolation unit 310 includes a switch subunit 311 and an isolation subunit 312; the switch subunit 311 is connected to the control unit 330, the first negative pressure module 100 and the second negative pressure module 200 respectively; the isolation subunit 312 is connected to the switch subunit 311, the control unit 330 and the maintenance node Vnood respectively.

[0049] In some embodiments, the switch subunit 311 is configured to output a first negative voltage under the action of a first switch signal and to output a second negative voltage under the action of a second switch signal.

[0050] For example, when the switch subunit 311 receives the first switch signal, it will control the first negative pressure submodule to connect with the isolation subunit 312, thereby outputting the first negative pressure to the isolation subunit 312; when the switch subunit 311 receives the second switch signal, it will control the second negative pressure module 200 to connect with the isolation subunit 312, thereby outputting the second negative pressure to the isolation subunit 312.

[0051] In some embodiments, the isolation subunit 312 is configured to: output a first negative pressure or a second negative pressure to the sustaining node; and disconnect from the sustaining node Vnood according to the isolation control signal.

[0052] For example, when the isolation subunit 312 receives the first negative voltage or the second negative voltage, it will charge the maintenance node Vnood to transmit the first negative voltage or the second negative voltage to the output unit 320; when the voltage on the maintenance node Vnood is less than the first preset maintenance threshold, the isolation subunit 312 receives the isolation control signal and turns off, thereby disconnecting the connection with the maintenance node Vnood, thus forming isolation between the first negative voltage module 100 and the maintenance node Vnood, and between the second negative voltage module 200 and the maintenance node Vnood.

[0053] In some embodiments, the control unit 330 is further configured to generate a compensation control signal when the voltage of the sustaining node Vnood is less than a second preset sustaining threshold and greater than a first preset sustaining threshold; wherein the second preset sustaining threshold is less than the first negative voltage.

[0054] For example, when the voltage of the sustaining node Vnood is less than the second preset sustaining threshold and greater than the first preset sustaining threshold, it indicates that the current stage is the second interval period. When the voltage of the current sustaining node Vnood is greater than the second negative voltage, it may cause the second negative voltage to fail to turn off the dual-gate transistor. A compensation control signal is generated to compensate for the voltage of the sustaining node Vnood.

[0055] In some embodiments, the output module 300 further includes a compensation unit 350, which is connected to the control unit 330 and configured to charge the maintenance node Vnood under the action of a compensation control signal, so that the maintenance node Vnood can stably output a second negative voltage.

[0056] For example, when the compensation unit 350 receives the compensation control signal from the control unit 330, it will be turned on to charge the maintenance node Vnood, so as to ensure that the maintenance node Vnood outputs a stable second negative voltage and can turn off the dual-gate transistor.

[0057] In some embodiments, the control unit 330 is also connected to the first negative pressure module 100 and the second negative pressure module 200, and is configured to determine a first trigger signal, a second trigger signal, a first interval period, and a second interval period based on temperature parameters, brightness parameters, and refresh rate.

[0058] For example, temperature parameters, brightness parameters, and refresh rate all affect the channel electron depletion capability of the dual-gate transistor. Based on experiments or calibration, a Look-Up Table (LUT) can be obtained for temperature parameters, brightness parameters, refresh rate, first negative voltage, first interval period, and second interval period. When the temperature parameter is detected by the temperature detection unit, the brightness parameter is detected by the brightness detection unit, and the current refresh rate is obtained by the refresh rate detection unit, the LUT table can be consulted to determine the value of the first negative voltage, the value of the second negative voltage, the period of the first interval period, and the period of the second interval period. A first trigger signal is generated based on the value of the first negative voltage to cause the first negative voltage module to output the first negative voltage; a second trigger signal is generated based on the value of the second negative voltage to cause the second negative voltage module to output the second negative voltage. The control unit controls the on-time of the first switch S1 in the control subunit 311 based on the first interval period and the on-time of the second switch S2 in the control subunit 311 based on the second interval period, thereby controlling the output duration of the first and second negative voltages.

[0059] In some embodiments, the control unit determines whether the current period is a display period or a frame interval period based on the vertical synchronization signal, the horizontal synchronization signal, and the data enable signal. When the vertical synchronization signal, the horizontal synchronization signal, and the data enable signal are detected to be in an active state, it indicates that the current period is a display period. At this time, pixel data is being written, the bottom gate drive signal controls the dual-gate oxide thin-film transistor to turn on according to the normal scan timing, and at the same time, the top gate control signal outputs a near-zero voltage or a forward bias voltage to enhance the channel carrier concentration and improve the conduction capability and data writing speed of the thin-film transistor. When the data enable signal is detected to be in an inactive state, it indicates that the current period is a frame interval period, and the control unit 330 outputs a first trigger signal and a second trigger signal to trigger the output of a first negative voltage and a second negative voltage.

[0060] Figure 5 A circuit diagram of a driving circuit for a dual-gate transistor according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 5 As shown, the switch subunit 311 includes: a first switch S1 and a second switch S2; the control terminal of the first switch S1 is connected to the control unit 330, the first end of the first switch S1 is connected to the first negative pressure module 100, and the second end of the first switch S1 is connected to the isolation subunit 312; the control terminal of the second switch S2 is connected to the control unit 330, the first end of the second switch S2 is connected to the second negative pressure module 200, and the second end of the second switch S2 is connected to the isolation subunit 312; the isolation subunit 312 includes an isolation switch T1; the control terminal of the isolation switch T1 is connected to the control unit 330, the first end of the isolation subunit 312 is connected to the switch subunit 311, and the second end of the isolation subunit 312 is connected to the maintenance node Vnood.

[0061] For example, when the first switch S1 receives the first switch signal output by the control unit 330 in the first interval period, the first switch S1 will be turned on, thereby outputting the first negative pressure output by the first negative pressure module 100 to the isolation subunit 312; when the second switch S2 receives the second switch signal output by the control unit 330 in the second interval period, the second switch S2 will be turned on, outputting the second negative pressure output by the second negative pressure module 200 to the isolation subunit 312.

[0062] For example, when the isolating switch T1 receives the isolation control signal output by the control unit 330, the isolating switch T1 will open, thereby disconnecting the connection with the maintenance sub-node. The first negative pressure output by the first negative pressure module 100 or the second negative pressure output by the second negative pressure module 200 will not be output to the maintenance node Vnood.

[0063] In some embodiments, please refer to Figure 4 As shown, the detection unit 340 includes: a first resistor R1, a second resistor R2, and an amplifier EA; the first end of the first resistor R1 is connected to the sustain node Vnood, the second end of the first resistor R1 is connected to the first end of the second resistor R2 and the non-inverting input of the amplifier EA; the second end of the second resistor R2 is connected to the low potential GND; the inverting input of the amplifier EA is connected to the low potential GND, and the output of the amplifier EA is connected to the control unit 330.

[0064] For example, by setting a first resistor R1 and a second resistor R2 to divide the voltage of the sustaining node Vnood, the amplifier EA scales the voltage received on the second resistor R2 proportionally so that the control unit 330 can calculate the voltage value of the sustaining node Vnood based on the received voltage, thus preventing the voltage of the sustaining node Vnood from being directly input to the control unit 330 and damaging the control unit 330.

[0065] In some embodiments, please refer to Figure 4 As shown, the output unit 320 includes: a first capacitor C1, an output buffer H1, and a second capacitor C2; the first terminal of the first capacitor C1 is connected to the input terminal of the output buffer H1 and the sustain node Vnood, and the second terminal of the first capacitor C1 is connected to the low potential terminal GND; the output terminal of the output buffer H1 is connected to the first terminal of the second capacitor C2 and the top gate of the dual-gate transistor; the second terminal of the second capacitor C2 is connected to the low potential terminal GND.

[0066] For example, the first capacitor C1 is connected to the sustaining node Vnood. The first negative voltage or the second negative voltage received by the sustaining node Vnood will be stored in the first capacitor C1. By setting the output buffer H1, the current can be limited when a short circuit current occurs, and it can also form isolation with the top of the dual-gate transistor to prevent the short circuit current of the dual-gate transistor from flowing in reverse. By setting the second capacitor C2, the first negative voltage or the second negative voltage of the output can be filtered to make the first negative voltage or the second negative voltage of the output more stable.

[0067] In some embodiments, the compensation unit 350 includes: a bias generator 351, a microcurrent source I comp, and a compensation transistor T2; the bias generator 351 is connected to a first terminal of the microcurrent source I comp; the second terminal of the microcurrent source I comp is connected to a first terminal of the compensation transistor T2; the control terminal of the compensation transistor T2 is connected to a control unit 330, and the second terminal of the compensation transistor T2 is connected to a sustaining node Vnood.

[0068] For example, the bias generator 351 is used to output the power supply voltage of the micro current source I comp to power the micro current source I comp. When the compensation transistor T2 receives the compensation control signal output by the control unit 330, the compensation transistor T2 will be turned on, and the micro current source I comp will output current to charge the sustaining node Vnood so that the sustaining node Vnood can stably output the second negative voltage. Moreover, the degree of turn-on of the compensation transistor T2 can be controlled according to the compensation control signal, thereby controlling the magnitude of the current input from the micro current source I comp to the sustaining node Vnood.

[0069] Figure 6 A circuit diagram of a negative pressure module according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 6As shown, the negative voltage module includes: an enable transistor T3, an input buffer H2, multiple energy storage units 110, and a third resistor R3; the control terminal of the enable transistor T3 is connected to the control unit 330, the first terminal of the enable transistor T3 is connected to the power supply terminal VDD and the first terminal of the first energy storage unit 110 among the multiple energy storage units 110, and the second terminal of the enable transistor T3 is connected to the second terminal of the input buffer H2 and the second terminal of the first energy storage unit 110 among the multiple energy storage units 110; the first terminal of the input buffer H2 is connected to the control unit 330; the multiple energy storage units 110 are connected in series, and each energy storage unit 110 includes: a first diode D1, a third diode D2, a third diode D3, and a third diode D3. The capacitor C3 and the third switch S3 are connected. The positive terminal of the first diode D1 serves as the first terminal of the energy storage unit 110. The cathode of the first diode D1 is connected to the first terminal of the third capacitor C3 and serves as the third terminal of the energy storage unit 110. The second terminal of the third capacitor C3 is connected to the second terminal of the third switch S3 and serves as the fourth terminal of the energy storage unit 110. The first terminal of the third switch S3 serves as the second terminal of the energy storage unit 110. The third terminal of the last energy storage unit 110 is connected to the first terminal of the third resistor R3 and the switch subunit 311, respectively. The fourth terminal of the last energy storage unit 110 is connected to the second terminal of the third resistor R3.

[0070] For example, the negative pressure module can be a first negative pressure module 100 or a second negative pressure module 200. The first trigger signal EN1 includes a first enable signal N1 and a first clock signal. When the negative pressure module is the first negative pressure module 100, the enable transistor T3 receives the first enable signal output by the control unit 330, and the input terminal of the input buffer H2 receives the first clock signal output by the control unit 330. The first clock signal includes two sub-clock signals (φ1 and φ2), which are output through the clock drive node of the control unit 330. The two sub-clock signals are non-overlapping clock signals. Two sub-clock signals control multiple third switches S3 to alternately conduct, thereby changing the reference potential of the third capacitor C3. During the active period of sub-clock signal φ1, the third switch S3 is on, and one end of the third capacitor C3 is connected to a low potential terminal (usually 0V or the clock reference node) via the third switch S3. The other end is connected to the power supply terminal VDD via the first diode D1. At this time, the power supply terminal VDD charges the third capacitor C3 through the first diode D1, establishing a voltage difference across the third capacitor C3 approximately equal to that of the power supply terminal VDD, and storing the corresponding charge between the two substrates of the third capacitor C3. Subsequently, when φ1 is closed and φ2 is on, the third switch S3 switches the connection node of the reference potential terminal of the third capacitor C3. Since the voltage across the third capacitor C3 cannot change abruptly, the third capacitor C3 maintains the original voltage difference, and its overall potential shifts along with the reference node, further pulling down (or raising) the node voltage at the other end of the third capacitor C3. The established charge is then transferred to the next third capacitor C3 through the subsequent first diode D1. As multiple third capacitors C3 and first diodes D1 continuously repeat the above charging, low-potential switching and charge transfer process, the potential of each output node gradually accumulates in the negative direction, eventually forming a stable negative voltage at the first end of the third resistor R3. After multiple accumulation stages, the required negative voltage levels such as -1.5V, -4V or -6V can be obtained.

[0071] For example, when the negative pressure module is the second negative pressure module 200, the control terminal of the enable transistor T3 receives the second trigger signal EN2. The second trigger signal includes the second enable signal N2 and the second clock signal. The first terminal of the input buffer H2 receives the second clock signal. By setting the second clock signal, the number of the multiple energy storage units 110 that are turned on is different, so as to control the magnitude of the second negative pressure output by the second negative pressure module 200. The working principle of the second negative pressure module 200 is the same as that of the first negative pressure module 100, and will not be described again here.

[0072] Figure 7 A circuit diagram of another negative pressure module provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 7As shown, the negative voltage module includes: a fourth transistor T4, a fifth transistor T5, a fourth capacitor C4, a second diode D2, a third diode D3, a fifth capacitor C5, and a fourth resistor R4; the control terminal of the fourth transistor T4 is connected to the control terminal of the fifth transistor T5 and the control unit 330 respectively; the first terminal of the fourth transistor T4 is connected to the power supply terminal VDD; the second terminal of the fourth transistor T4 is connected to the first terminal of the fifth transistor T5 and the first terminal of the fourth capacitor C4 respectively; the second terminal of the fifth transistor T5 is connected to the cathode of the second diode D2, the second terminal of the fifth capacitor C5, and the second terminal of the fourth resistor R4 to the low potential terminal GND; the second terminal of the fourth capacitor C4 is connected to the anode of the second diode D2 and the cathode of the third diode D3 respectively; the anode of the third diode D3 is connected to the first terminal of the fifth capacitor C5, the first terminal of the fourth resistor R4, and the switch subunit 311 respectively.

[0073] For example, the circuit structures of the first negative pressure module 100 and the second negative pressure module 200 are the same. When the negative pressure module is the first negative pressure module 100, the first end of the fourth resistor R4 is connected to the first end of the first switch S1 in the switch subunit 311. The first trigger signal is a waveform signal with a first duty cycle value. When the first trigger signal is high, the fourth transistor T4 is turned on, the fifth transistor T5 is turned off, and the fourth transistor T4, the fourth capacitor C4, the second diode D2, and the low potential terminal GND form a charging circuit. The power supply terminal VDD output voltage charges the fourth capacitor C4. Charging; when the first trigger signal is low, the fourth transistor T4 is off, the fifth transistor T5 is on, the first terminal of the fourth capacitor C4 is pulled down to the low potential terminal GND through the fifth transistor T5, and the second terminal of the fourth capacitor C4 outputs the first negative voltage. The fourth capacitor C4, the third diode D3, the fifth capacitor C5 and the fourth resistor R4 form a power supply circuit. The fourth capacitor C4 charges the fifth capacitor C5 and outputs the first negative voltage to the first terminal of the first switch S1 through the first terminal of the fourth resistor R4. The magnitude of the first negative voltage can be adjusted by adjusting the first duty cycle.

[0074] For example, when the negative pressure module is the second negative pressure module 200, the second terminal of the fourth resistor R4 is connected to the first terminal of the second switch S2 in the switch subunit 311, and the second trigger signal EN2 is a waveform signal with the second duty cycle value. The working principle of the second negative pressure module 200 is the same as that of the first negative pressure module 100, and will not be described again here. The magnitude of the second negative pressure can be adjusted by adjusting the second duty cycle value. The fourth transistor T4 can be an NPN transistor, and the fifth transistor T5 can be a PNP transistor.

[0075] In some embodiments, this application also provides a display panel, including: a plurality of dual-gate transistors arranged in an array and a driving circuit for the dual-gate transistors, wherein the driving circuit for the dual-gate transistors is connected to the top gate of the dual-gate transistors.

[0076] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0077] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0078] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A driving circuit for a dual-gate transistor, characterized in that, The driving circuit includes: The first negative pressure module is configured to generate a first negative pressure during the frame interval in response to a first trigger signal. The second negative pressure module is configured to generate a second negative pressure in response to a second trigger signal during the frame interval; wherein the second negative pressure is less than the first negative pressure; The output module, which is connected to the first negative voltage module, the second negative voltage module, and the top gate of the dual-gate transistor, is configured to: output the first negative voltage to the top gate of the dual-gate transistor in a first interval period, and output the second negative voltage to the top gate of the dual-gate transistor in a second interval period, so as to turn off the dual-gate transistor; wherein the frame interval period includes: the first interval period and the second interval period.

2. The driving circuit for the dual-gate transistor according to claim 1, characterized in that, The output module also includes: An isolation unit, connected to the first negative pressure module, the second negative pressure module, and the maintenance node respectively, is configured to: output the first negative pressure to the maintenance node in the first interval sub-period, and output the second negative pressure to the maintenance node in the second interval sub-period; The output unit, connected to the sustaining node, is configured to output either a first negative voltage or a second negative voltage from the sustaining node to the top gate of the dual-gate transistor. A detection unit, connected to the sustaining node, is configured to detect the voltage on the sustaining node; The control unit, which is connected to the detection unit and the isolation unit respectively, is configured to generate an isolation control signal when it is determined that the voltage on the maintenance node is less than a first preset maintenance threshold, so as to control the isolation unit to disconnect from the maintenance node.

3. The driving circuit for the dual-gate transistor according to claim 2, characterized in that, The control unit is further configured to: generate a first switching signal in the first interval sub-period and generate a second switching signal in the second interval sub-period; The isolation unit includes: The switching subunit, which is connected to the control unit, the first negative pressure module and the second negative pressure module respectively, is configured to output the first negative pressure under the action of the first switching signal and output the second negative pressure under the action of the second switching signal; An isolation subunit, connected to the switch subunit, the control unit, and the sustaining node respectively, is configured to: output the first negative pressure or the second negative pressure to the sustaining node; and disconnect from the sustaining node according to the isolation control signal.

4. The driving circuit for the dual-gate transistor according to claim 2, characterized in that, The control unit is further configured to generate a compensation control signal when the voltage of the sustaining node is less than a second preset sustaining threshold and greater than a first preset sustaining threshold; wherein the second preset sustaining threshold is less than the first negative voltage; The output module further includes a compensation unit connected to the control unit, configured to charge the sustaining node under the action of the compensation control signal, so that the sustaining node stably outputs the second negative pressure.

5. The driving circuit for the dual-gate transistor according to claim 2, characterized in that, The control unit is also connected to the first negative pressure module and the second negative pressure module, and is configured to: determine the first trigger signal, the first interval sub-period, the second trigger signal and the second interval sub-period based on temperature parameters, brightness parameters and refresh rate.

6. The driving circuit for the dual-gate transistor according to claim 3, characterized in that, The switching subunit includes: a first switch and a second switch; The control terminal of the first switch is connected to the control unit, the first terminal of the first switch is connected to the first negative pressure module, and the second terminal of the first switch is connected to the isolation subunit; The control terminal of the second switch is connected to the control unit, the first terminal of the second switch is connected to the second negative pressure module, and the second terminal of the second switch is connected to the isolation subunit; Alternatively, the isolation subunit may include an isolation switch; The control terminal of the disconnecting switch is connected to the control unit, the first terminal of the isolation subunit is connected to the switch subunit, and the second terminal of the isolation subunit is connected to the sustaining node.

7. The driving circuit for the dual-gate transistor according to claim 2, characterized in that, The detection unit includes: a first resistor, a second resistor, and an amplifier; The first end of the first resistor is connected to the sustaining node, and the second end of the first resistor is connected to the first end of the second resistor and the non-inverting input of the amplifier. The second terminal of the second resistor is connected to the low potential terminal; The inverting input terminal of the amplifier is connected to the low potential terminal, and the output terminal of the amplifier is connected to the control unit.

8. The driving circuit for the dual-gate transistor according to claim 2, characterized in that, The output unit includes: a first capacitor, an output buffer, and a second capacitor; The first terminal of the first capacitor is connected to the input terminal of the output buffer and to the sustain node, and the second terminal of the first capacitor is connected to the low potential terminal. The output terminal of the output buffer is connected to the first terminal of the second capacitor and the top gate of the dual-gate transistor; The second terminal of the second capacitor is connected to the low potential terminal.

9. The driving circuit for the dual-gate transistor according to claim 4, characterized in that, The compensation unit includes: a bias generator, a microcurrent source, and a compensation transistor; The bias generator is connected to the first terminal of the microcurrent source; The second terminal of the microcurrent source is connected to the first terminal of the compensation transistor; The control terminal of the compensation transistor is connected to the control unit, and the second terminal of the compensation transistor is connected to the sustaining node.

10. A display panel, characterized in that, include: A plurality of dual-gate transistors arranged in an array and a driving circuit for the dual-gate transistors according to any one of claims 1-9, wherein the driving circuit for the dual-gate transistors is connected to the top gate of the dual-gate transistors.

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