Display panel and display device

Abstract

The application provides a display panel and a display device, and belongs to the technical field of display driving. The display panel comprises a plurality of gate driving circuits and pixel units connected with the gate driving circuits. The gate driving circuit comprises a first input circuit, an output circuit and a reset circuit. The reset circuit is driven by a reset signal to reset at least one of the first node and the output node through a second voltage signal. The potential of the second voltage signal is higher than that of the first voltage signal. The use of the second voltage signal with a higher potential can reduce the potential difference between the second voltage signal and the output node and / or the first node, thereby inhibiting the leakage current phenomenon of the high mobility oxide device caused by the negative threshold voltage shift, reducing the leakage of the first node and the output node through the reset circuit, and improving the stability of the gate driving circuit in the case of the negative threshold voltage shift.

Description

Technical Field

[0001] This application relates to the field of display driver technology, and in particular to a display panel and display device. Background Technology

[0002] High-mobility oxide (HMO) devices are commonly used in display panels to achieve high resolution and high refresh rates due to their advantages such as low leakage current and low power consumption. However, HMO devices are prone to negative threshold voltage (Vth) bias in practical applications, which affects the reliability of the display panel.

[0003] Currently, the gate drive circuit is responsible for outputting scan signals line by line to control the operation of pixel units. If the high-mobility oxide device in the gate drive circuit has a negative threshold voltage bias, a large leakage current will be generated during the reset phase of the gate drive circuit, causing potential drift and resulting in low operating stability of the gate drive circuit. Summary of the Invention

[0004] This application provides a display panel to at least partially solve the above-mentioned technical problems.

[0005] To achieve the above objectives, according to a first aspect of this application, a display panel is provided, comprising a plurality of gate driving circuits and pixel units connected to the gate driving circuits; the gate driving circuits include: The first input circuit is used to receive the transmission signal and control the potential of the first node according to the transmission signal. The output circuit is connected to the first input circuit at the first node and to the pixel unit at the output node; A reset circuit is used to receive a reset signal and a second voltage signal, and under the drive of the reset signal, reset at least one of the first node and the output node through the second voltage signal; Wherein, the potential of the second voltage signal is greater than the potential of the first voltage signal.

[0006] Optionally, the potential difference between the second voltage signal and the first voltage signal is greater than or equal to 2V.

[0007] Optionally, the reset circuit includes a first transistor and a second transistor; The first transistor includes a first electrode for receiving the second voltage signal, a second electrode connected to the first node, and a control electrode for receiving the reset signal; wherein the potential of the second voltage signal is greater than the potential of the first voltage signal, so that when the first transistor is turned off, the potential difference between the first electrode and the second electrode of the first transistor is reduced; The second transistor includes a first electrode for receiving the second voltage signal, a second electrode connected to the output node, and a control electrode for receiving the reset signal; wherein the potential of the second voltage signal is greater than the potential of the first voltage signal, so that when the second transistor is turned off, the potential difference between the first electrode and the second electrode of the second transistor is reduced.

[0008] Optionally, it also includes an inverting circuit, which is connected to the first node and connected to the output circuit at the second node, for receiving the first voltage signal and controlling the potential of the second node according to the potential of the first node, so that the level states of the first node and the second node are different. The inverting circuit includes a third transistor, which is a dual-gate transistor, used to control the potential of the second node according to the potential of the first node, and to isolate the second node and the first voltage signal when the third transistor is in the off state.

[0009] Optionally, the third transistor includes a first sub-transistor and a second sub-transistor; The first sub-transistor includes a first electrode for receiving the first voltage signal, a second electrode connected to the second sub-transistor, and a control electrode connected to the first node; The second sub-transistor includes a first electrode connected to the first sub-transistor, a second electrode connected to the second node, and a control electrode connected to the first node; The first width-to-length ratio of the channel width to the channel length of the first sub-transistor is greater than the second width-to-length ratio of the channel width to the channel length of the second sub-transistor.

[0010] Optionally, the first aspect ratio is 2, and the second aspect ratio is 1; The first sub-transistor has a channel width of 8 μm and a channel length of 4 μm; the second sub-transistor has a channel width of 4 μm and a channel length of 4 μm.

[0011] Optionally, it may also include a second input circuit, the second input circuit including a fourth transistor; The fourth transistor includes a first electrode for receiving a third voltage signal, a second electrode connected to the second node of the output circuit, and a control electrode for receiving a second clock signal.

[0012] Optionally, the first input circuit includes a fifth transistor, a sixth transistor, and a seventh transistor; The fifth transistor includes a first electrode for receiving a third voltage signal, a second electrode connected to the first node, and a control electrode for receiving the transmission signal. The sixth transistor includes a first electrode for receiving the first voltage signal, a second electrode connected to the first node, and a control electrode connected to the second node; The seventh transistor includes a first electrode for receiving the first voltage signal, a second electrode connected to the first node, and a control electrode for receiving the second clock signal.

[0013] Optionally, the output circuit includes an eighth transistor and a ninth transistor; The eighth transistor includes a first electrode for receiving the first clock signal, a second electrode connected to the ninth transistor at the output node, and a control electrode connected to the first node; The ninth transistor includes a first electrode for receiving the first voltage signal, a second electrode connected to the output node, and a control electrode connected to the second node.

[0014] According to a second aspect of this application, a display device is provided, including the above-described display panel and a power management chip, wherein the power management chip includes functions for outputting a first voltage signal and a second voltage signal to the display panel.

[0015] In summary, in this application, the reset circuit uses a second voltage signal with a higher potential for reset. Compared with the first voltage signal, the potential difference between the second voltage signal and the output node and / or the first node can be reduced. Thus, when the reset circuit uses a high-mobility oxide device, the leakage current phenomenon caused by the high-mobility oxide device being negatively biased by its threshold voltage can be suppressed, and the leakage current of the first node and the output node through the reset circuit can be reduced, thereby improving the stability of the gate drive circuit when operating under negative threshold voltage bias.

[0016] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0019] Figure 1This is a schematic diagram of the gate drive circuit in the related technology; Figure 2 This is an architectural diagram of a display panel provided in an exemplary embodiment of this disclosure; Figure 3 This is a circuit diagram of a pixel unit that cooperates with a gate driving circuit provided in an exemplary embodiment of this disclosure; Figure 4 This is a schematic diagram of a gate driving circuit provided in an exemplary embodiment of this disclosure; Figure 5 This is a timing diagram of the gate drive circuit provided in an exemplary embodiment of this disclosure; Figure 6 This is a schematic diagram of the current flow during the reset process of the gate drive circuit provided in an exemplary embodiment of this disclosure; Figure 7 This is a schematic diagram of the current flow during the scanning signal process of the output high-level state provided in the exemplary embodiment of this disclosure; Figure 8 This is a schematic diagram of the current flow during the scanning signal process of the output low-level state provided in the exemplary embodiment of this disclosure; Figure 9 This is a schematic diagram of the negative bias effect provided in an exemplary embodiment of this disclosure.

[0020] Explanation of reference numerals in the attached diagram: T1, first transistor; T2, second transistor; T3-1, first sub-transistor; T3-2, second sub-transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; 1, first input circuit; 2, output circuit; 3, reset circuit; 4, inverting circuit; 5, second input circuit; VGL1, first voltage signal; VGL2, second voltage signal; Reset, reset signal; VGH, third voltage signal; N, first node; P, second node; O, output node. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0022] First, the background of this application will be further explained. In conjunction with... Figure 1 , Figure 1In a gate driving circuit of related technology, the first reset transistor Q8 and the second reset transistor Q9 in the gate driving circuit reset the output node Gout and the cascade node N0 using a low-level signal VGL under the drive of the reset signal Resrt. However, during the period when the output node and the cascade node N0 do not need to be reset and the output node and the cascade node N0 are kept in a high-level state, the output node Gout and the cascade node N0 will leak current to the low-level signal VGL through the first reset transistor Q8 and the second reset transistor Q9, making the signals output by the output node and the cascade node N0 unstable and unable to stably drive the pixel unit. Based on this, the embodiment of this application is proposed.

[0023] Next, the architecture of this application will be described, referring to... Figure 2 As shown, Figure 2 This is a schematic diagram of a display panel in an embodiment of this application. The display panel includes a display area AA and a non-display area NA adjacent to the display area AA, with the non-display area NA surrounding the display area AA. The display area AA is the region within the display panel used for display functions, and it contains multiple display units that implement these functions. The non-display area NA may be a border area of ​​the display panel, and it may contain functional components that assist the display units within the display area AA in performing their display functions.

[0024] Multiple light-emitting devices D1 and pixel units 30 that drive the light-emitting devices D1 can be arrayed within the display area AA. For example, refer to... Figure 3 , Figure 3This is a schematic diagram of pixel unit 30. Pixel unit 30 may include a driving transistor T1A, a switching transistor T2A, a compensation transistor T3A, a first reset transistor T4A, a second reset transistor T7A, a third reset transistor T8A, a first light-emitting transistor T5A, a second light-emitting transistor T6A, a boost capacitor Cboost, and a control capacitor Cst2. The first electrode of the switching transistor T2A is connected to the data signal line Data, the second electrode of the switching transistor T2A is connected to node A1, and the gate of the switching transistor T2A receives the data write signal Pscan1. The first electrode of the driving transistor T1A is connected to node A1, the second electrode of the driving transistor T1A is connected to node B1, and the gate of the driving transistor T1A is connected to node Q1. The first electrode of the compensation transistor T3A is connected to node Q1, the second electrode of the compensation transistor T3A is connected to node B1, and the gate of the compensation transistor T3A receives the threshold compensation signal Nscan1. The first electrode of the first reset transistor T4A receives the first reset signal Vi1, the second electrode of the first reset transistor T4A is connected to node Q1, and the gate of the first reset transistor T4A receives the first reset signal Nscan2. The first electrode of the second reset transistor T7A is connected to the second reset signal Vi2, the second electrode of the second reset transistor T7A is connected to the anode of the light-emitting device, and the gate of the second reset transistor T7A receives the second reset signal Pscan2. The first electrode of the third reset transistor T8A receives the third reset signal Vi3, the second electrode of the third reset transistor T8A is connected to node A1, and the gate of the third reset transistor T8A receives the third reset signal Vi3. The first electrode of the first light-emitting transistor T5A is connected to the high-level source VDD, the second electrode of the first light-emitting transistor T5A is connected to node A1, and the gate of the first light-emitting transistor T5A receives the light-emitting control signal EM. The first electrode of the second light-emitting transistor T6A is connected to node B1, the second electrode of the second light-emitting transistor T6A is connected to the anode of the light-emitting device, and the gate of the second light-emitting transistor T6A receives the light-emitting control signal EM. The cathode of the light-emitting device D1 is connected to the low-level source VSS. Thus, the pixel unit 30 can control the light emission of the light-emitting device D1 based on the data writing signal Pscan1, the threshold compensation signal Nscan1, the first reset signal Nscan2, the second reset signal Pscan2, and the light emission control signal EM.

[0025] Combination Figure 2A gate driving device is provided in the non-display area NA. The gate driving device may include a cascaded second driving circuit 20 and several cascaded first driving circuits; wherein the several first driving circuits may be a threshold compensation circuit 11, a first reset circuit 12, a second reset circuit 13, and a light emission control circuit 14, respectively. As an example, the threshold compensation circuit 11 is used to output a threshold compensation signal Nscan1. The threshold compensation circuit 11 may be located on one side of the display area AA, and each threshold compensation circuit 11 drives two rows of pixel units 30 in the display area AA, that is, the threshold compensation circuit 11 may be configured as one-to-two on one side. The first reset circuit 12 is used to output a first reset signal Nscan2. The first reset circuit 12 may be located on the other side of the display area AA, opposite to the threshold compensation circuit 11. Each first reset circuit 12 drives two rows of pixel units 30 in the display area AA, that is, the first reset circuit 12 may be configured as one-to-two on one side. The second reset circuit 13 is used to output the second reset signal Pscan2. The second reset circuit 13 can be located on one side of the display area AA. Each second reset circuit 13 drives two rows of pixel units 30 in the display area AA, that is, the second reset circuit 13 can be configured as one-to-two on one side. The light emission control circuit 14 is used to output the light emission control signal EM. The light emission control circuit 14 can be located on the other side of the display area AA, opposite to the second reset circuit 13. As an example, each light emission control circuit 14 can drive two rows of pixel units 30 in the display area AA, and the light emission control circuit 14 can be configured as one-to-two on one side. The second driving circuit 20 is used to output the data write signal Pscan1. The second driving circuit 20 is respectively located on both sides of the display area AA. The two second driving circuits 20 located on both sides of the same row of pixel units 30 share the same area of ​​the row of pixel units 30, that is, the second driving circuit 20 can be configured as one-to-one on both sides.

[0026] It should be noted that the structure of the pixel unit 30 and the gate driving device described above is only an example, and this application does not impose any specific limitations.

[0027] According to the first aspect of this application, referring to Figure 4This disclosure provides a display panel including a plurality of gate driving circuits and pixel units connected to the gate driving circuits. The gate driving circuits include a first input circuit 1, an output circuit 2, and a reset circuit 3. The first input circuit 1 is used to receive a transmission signal and control the potential of a first node N according to the transmission signal. The output circuit 2 is connected to the first input circuit 1 at the first node N and to the pixel unit at an output node O. It is used to receive a first voltage signal VGL1 and a first clock signal, and under the drive of the potential of the first node N, outputs a scan signal to the pixel unit through the output node O according to the first voltage signal VGL1 and the first clock signal. The reset circuit 3 is used to receive a reset signal Reset and a second voltage signal VGL2, and under the drive of the reset signal Reset, resets at least one of the first node N and the output node O through the second voltage signal VGL2. The potential of the second voltage signal VGL2 is greater than the potential of the first voltage signal VGL1.

[0028] Combination Figures 2 to 4 In this embodiment, the gate driving circuit can be the threshold compensation circuit 11 for providing the threshold compensation signal Nscan1 or the first reset circuit 12 for providing the first reset signal Nscan2. The scanning signal can be the threshold compensation signal Nscan1 or the first reset signal Nscan2 output to the pixel unit. The effective level state of the scanning signal is a high level state.

[0029] As an example, the stage transmission signal can be a scan signal output from the gate drive circuit of the preceding stage, or a start signal from the timing controller. For instance, the gate drive circuit of the first stage is used to receive the start signal from the timing controller as the stage transmission signal, and the gate drive circuits of other stages besides the first stage are used to receive the scan signal output from the gate drive circuit of the preceding stage as the stage transmission signal. The preceding stage can be the gate drive circuit of the previous stage or multiple stages, without specific limitations.

[0030] As an example, output circuit 2 is connected to a first voltage signal VGL1 and a first clock signal. When the first node N is high, output circuit 2 transmits the first clock signal as a valid scan signal from output node O to the pixel unit, completing the pixel unit selection. When the first node N is low, output circuit 2 outputs the first voltage signal VGL1 as an invalid scan signal from output node O to the pixel unit, and the pixel unit does not operate. After the valid scan signal is output, reset circuit 3 receives reset signal Reset and uses second voltage signal VGL2 to reset the potential of the first node N and output node O, clearing residual charge and avoiding circuit mis-triggering caused by residual potential, thus ensuring the accuracy of the next scan.

[0031] As an example, both the first voltage signal VGL1 and the second voltage signal VGL2 are low-level signals. The potential of the second voltage signal VGL2 is higher than that of the first voltage signal VGL1. For gate drive circuits using high-mobility oxide devices, the increased mobility easily leads to a negative threshold voltage bias, resulting in increased leakage current. Furthermore, the leakage current of high-mobility oxide devices is positively correlated with the potential difference between their source and drain terminals; the smaller the potential difference, the smaller the leakage current. Therefore, adjusting the potential of the second voltage signal VGL2 to a relatively higher level can reduce the potential difference between the second voltage signal VGL2 and the first node N and output node O when the first node N and output node O are in a high-level state, thereby reducing the leakage current of the first node N and output node O through the reset circuit 3.

[0032] In the above embodiments, the reset circuit 3 uses a second voltage signal VGL2 with a higher potential for reset. Compared with the first voltage signal VGL1, the potential difference between the second voltage signal VGL2 and the output node O and / or the first node N can be reduced. Thus, when the reset circuit 3 uses a high-mobility oxide device, the leakage current phenomenon caused by the high-mobility oxide device being negatively biased by its threshold voltage can be suppressed, and the leakage current of the first node N and the output node O through the reset circuit 3 can be reduced, thereby improving the stability of the gate drive circuit when the threshold voltage is negatively biased.

[0033] In some embodiments, the potential difference between the second voltage signal VGL2 and the first voltage signal VGL1 is greater than or equal to 2V.

[0034] As an example, the potential difference between the second voltage signal VGL2 and the first voltage signal VGL1 can be 2.5V, 3V, 3.5V, 4V, etc. Since both the first voltage signal VGL1 and the second voltage signal VGL2 are low-level signals used to drive the high-mobility oxide device to cut off, an upper limit value for the second voltage signal VGL2 can also be set. This upper limit value is less than the third voltage signal VGH, allowing the second voltage signal VGL2 to completely drive the high-mobility oxide device to cut off. The deeper the negative bias of the threshold voltage of the high-mobility oxide device, the greater the leakage current when it is cut off. When the voltage difference between the second voltage signal VGL2 and the first voltage signal VGL1 is greater than or equal to 2V, the leakage current of the high-mobility oxide device in the reset circuit 3 when it is cut off can be reduced, avoiding potential abnormalities caused by leakage.

[0035] Reference Figure 5 and Figure 6In some embodiments, the reset circuit 3 includes a first transistor T1. The first transistor T1 includes a first electrode for receiving a second voltage signal VGL2, a second electrode connected to the first node N, and a control electrode for receiving a reset signal Reset. The potential of the second voltage signal VGL2 is greater than the potential of the first voltage signal VGL1, such that when the first transistor T1 is turned off, the potential difference between the first electrode and the second electrode of the first transistor T1 is reduced.

[0036] As an example, when the reset signal Reset is high, the first transistor T1 is turned on, and the second voltage signal VGL2 is transmitted to the first node N to reset the first node N. When the reset signal Reset is low, the first transistor T1 is turned off to isolate the second voltage signal VGL2 from the first node N.

[0037] When the first transistor T1 is negatively biased by its threshold voltage, leakage current is easily generated in the off state due to the potential difference between its first and second electrodes. By setting the potential of the second voltage signal VGL2 to be greater than that of the first voltage signal VGL1, the potential difference between the first and second electrodes is reduced when the first transistor T1 is off. Since leakage current is positively correlated with potential difference, reducing the potential difference can reduce leakage current and prevent leakage from causing abnormal potential at the first node N.

[0038] In some embodiments, the reset circuit 3 includes a second transistor T2. The second transistor T2 includes a first electrode for receiving a second voltage signal VGL2, a second electrode connected to the output node O, and a control electrode for receiving a reset signal Reset. The potential of the second voltage signal VGL2 is greater than the potential of the first voltage signal VGL1, so that when the second transistor T2 is turned off, the potential difference between the first and second electrodes of the second transistor T2 is reduced.

[0039] As an example, when the reset signal Reset is high, the second transistor T2 is turned on, pulling down the potential of output node O through the second voltage signal VGL2 to clear any residual scan signal. When the reset signal Reset is low, the second transistor T2 is turned off to isolate the second voltage signal VGL2 from output node O.

[0040] When the second transistor T2 is negatively biased by its threshold voltage, leakage current is easily generated in the off state due to the potential difference between its first and second electrodes. By setting the potential of the second voltage signal VGL2 to be greater than that of the first voltage signal VGL1, the potential difference between the first and second electrodes is reduced when the second transistor T2 is off. Since leakage current is positively correlated with potential difference, reducing the potential difference can reduce leakage current and prevent abnormal potential at the output node O caused by leakage.

[0041] In the above embodiments, during the reset operation, the reset circuit 3 resets the first node N through the first transistor T1 and the output node O through the second transistor T2. When the reset circuit 3 is not performing a reset operation, by setting the potential of the second voltage signal VGL2 to be greater than the potential of the first voltage signal VGL1, the potential difference between the first and second electrodes of the first transistor T1 and the second transistor T2 in the off state can be reduced, thereby reducing leakage current. Even if the threshold voltages of the first transistor T1 and the second transistor T2 are negatively biased, the leakage current will not increase significantly. This can, to a certain extent, prevent abnormal shifts in the potentials of the output node O and the first node N due to leakage current, thereby improving the reliability of the gate drive circuit under negative threshold voltage conditions.

[0042] Reference Figure 5 and Figure 7 In some embodiments, the gate drive circuit further includes an inverter circuit 4, which is connected to the first node N and the output circuit 2 to the second node P. The inverter circuit 4 is used to receive the first voltage signal VGL1 and control the potential of the second node P according to the potential of the first node N, so that the voltage levels of the first node N and the second node P are different. The inverter circuit 4 includes a third transistor, which is a dual-gate transistor, used to control the potential of the second node P according to the potential of the first node N, and to isolate the second node P and the first voltage signal VGL1 when the third transistor is in the off state.

[0043] As an example, when the first node N is in a high-level state, the third transistor is in a conducting state to transmit the first voltage signal VGL1 to the second node P. Since the first voltage signal VGL1 is a low-level signal, the second node P is in a low-level state at this time. When the second node P is in a high-level state, the first node N is in a low-level state, and the third transistor is in a cutoff state. In this case, the third transistor is used to isolate the second node P and the first voltage signal VGL1, preventing the first voltage signal VGL1 from pulling down the potential of the second node P.

[0044] As an example, the third transistor is configured as a dual-gate transistor. Compared to a single-gate transistor, the dual-gate transistor has two gate structures, resulting in stronger leakage current suppression. When the third transistor is in the off state and its threshold voltage is negatively biased, the dual-gate transistor can use its leakage current suppression capability to isolate the second node P from the first voltage signal VGL1, thereby reducing the leakage current path from the second node P to the first voltage signal VGL1 and thus reducing the leakage current, keeping the potential of the second node P stable.

[0045] Reference Figure 5 and Figure 7In some embodiments, the third transistor includes a first sub-transistor T3-1 and a second sub-transistor T3-2. The first sub-transistor T3-1 includes a first electrode for receiving a first voltage signal VGL1, a second electrode connected to the second sub-transistor T3-2, and a control electrode connected to the first node N. The second sub-transistor T3-2 includes a first electrode connected to the first sub-transistor T3-1, a second electrode connected to the second node P, and a control electrode connected to the first node N. The first aspect ratio of the channel width to the channel length of the first sub-transistor T3-1 is greater than the second aspect ratio of the channel width to the channel length of the second sub-transistor T3-2.

[0046] As an example, the first sub-transistor T3-1 and the second sub-transistor T3-2 share a common control electrode and are both connected to the first node N, enabling synchronous turn-on and turn-off of the first sub-transistor T3-1 and the second sub-transistor T3-2. A double-gate blocking structure is formed by the series connection of the first sub-transistor T3-1 and the second sub-transistor T3-2. The first sub-transistor T3-1 and the second sub-transistor T3-2 can suppress leakage current step by step, resulting in better leakage current suppression.

[0047] As an example, the larger the width-to-length ratio (W / L) of a transistor, the greater the conduction current and the greater the leakage current. Since the first sub-transistor T3-1 is closer to the first voltage signal VGL1 terminal and needs to withstand a larger potential difference, the first sub-transistor T3-1 uses a larger first width-to-length ratio than the second sub-transistor T3-2 to ensure signal transmission efficiency during conduction. The second sub-transistor T3-2 is closer to the second node P and can use a smaller second width-to-length ratio than the first sub-transistor T3-1, thereby achieving a balance between conduction efficiency and leakage current suppression.

[0048] In the above embodiments, the first sub-transistor T3-1 and the second sub-transistor T3-2 share a common control electrode, enabling synchronous switching control. This allows the second node P to be quickly pulled down to a low level by the first voltage signal VGL1 when the first node N is in a high-level state, ensuring the synchronization of the level inversion. By connecting the first sub-transistor T3-1 and the second sub-transistor T3-2 in series to obtain a third transistor, a two-stage leakage resistance structure can be formed, enhancing the leakage current suppression capability when the first sub-transistor T3-1 and the second sub-transistor T3-2 are in the off state. Furthermore, the first width-to-length ratio of the first sub-transistor T3-1 is greater than the second width-to-length ratio of the second sub-transistor T3-2, which can balance the signal transmission efficiency of the third transistor when it is on and the leakage current suppression effect when it is off.

[0049] In some embodiments, the first width-to-length ratio is 2, and the second width-to-length ratio is 1. The channel width of the first sub-transistor T3-1 is 8 μm, and the channel length is 4 μm. The channel width of the second sub-transistor T3-2 is 4 μm, and the channel length is 4 μm.

[0050] As an example, the first width-to-length ratio of the first sub-transistor T3-1 is 2, which ensures sufficient drive current when the first sub-transistor T3-1 is turned on, thus avoiding a delay in the potential adjustment of the second node P. The second width-to-length ratio of the second sub-transistor T3-2 is 1, which suppresses the leakage current of both the first and second sub-transistors T3-1. Even if the first and second sub-transistors T3-1 and T3-2 are negatively biased at their threshold voltages, the leakage current suppression requirement can still be met, thereby preventing continuous leakage at the second node P to some extent.

[0051] Reference Figure 5 and Figure 8 In some embodiments, the display panel further includes a second input circuit 5, which includes a fourth transistor T4. The fourth transistor T4 includes a first electrode for receiving a third voltage signal VGH, a second electrode connected to the output circuit 2 at the second node P, and a control electrode for receiving a second clock signal.

[0052] As an example, the third voltage signal VGH is a high-level signal, and the switching on and off of the fourth transistor T4 is controlled by the second clock signal. When the second clock signal is high, the fourth transistor T4 is turned on, and the third voltage signal VGH is transmitted to the second node P, pulling the potential of the second node P high. When the second clock signal is low, the fourth transistor T4 is turned off, isolating the third voltage signal VGH from the second node P.

[0053] As an example, the second clock signal CK and the first clock signal XCK are complementary timing signals with opposite level states. The fourth transistor T4 and the inverter circuit 4 work together to control the potential of the second node P. When the first node N is low, the fourth transistor T4 pulls the potential of the second node P high. When the first node N is high, the inverter circuit 4 pulls the potential of the second node P low.

[0054] Reference Figure 5 and Figure 7In some embodiments, the first input circuit 1 includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The fifth transistor T5 includes a first electrode for receiving a third voltage signal VGH, a second electrode connected to the first node N, and a control electrode for receiving a transmission signal. The sixth transistor T6 includes a first electrode for receiving a first voltage signal VGL1, a second electrode connected to the first node N, and a control electrode connected to the second node P. The seventh transistor T7 includes a first electrode for receiving the first voltage signal VGL1, a second electrode connected to the first node N, and a control electrode for receiving a second clock signal.

[0055] As an example, STV represents the cascade signal. The fifth transistor T5 is used to receive the cascade signal, the sixth transistor T6 is used for the second node P potential feedback control, and the seventh transistor T7 is used for the second clock signal timing control. The fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 work together to achieve the high and low level switching of the first node N potential.

[0056] As an example of the operation of the first input circuit 1, when the transmission signal is high, the fifth transistor T5 is turned on, transmitting the third voltage signal VGH to the first node N, raising the potential of the first node N. When the transmission signal is low, the fifth transistor T5 is turned off, isolating the third voltage signal VGH from the first node N. At this time, the second node P is low, and the sixth transistor T6 is turned off, preventing the low-level first voltage signal VGL1 from interfering with the high-level state of the first node N. Simultaneously, when the second clock signal is high, the seventh transistor T7 is turned on, pulling the potential of the first node N low.

[0057] Subsequently, driven by the second clock signal, the fourth transistor T4 controls the second node P to a high level, causing the sixth transistor T6 to conduct. The sixth transistor T6 transmits the first voltage signal VGL1 to the first node N, pulling down the potential of the first node N. This forms a feedback loop between the first node N and the second node P, further ensuring that the potential levels of the first node N and the second node P are opposite. When the second clock signal is low, the seventh transistor T7 is off, working with the fifth transistor T5 to maintain the high potential state of the first node N, further stabilizing the potential of the first node N.

[0058] In some embodiments, the output circuit 2 includes an eighth transistor T8 and a ninth transistor T9. The eighth transistor T8 includes a first electrode for receiving a second clock signal, a second electrode connected to the ninth transistor T9 at output node O, and a control electrode connected to the first node N. The ninth transistor T9 includes a first electrode for receiving a first voltage signal VGL1, a second electrode connected to output node O, and a control electrode connected to the second node P.

[0059] As an example, the eighth transistor T8 is a pull-up transistor, used to output a high-level scan signal driven by the potential of the first node N; the ninth transistor T9 is a pull-down transistor, used to output a low-level scan signal driven by the potential of the second node P, thereby switching the potential of the output node O. The pixel unit may also include a first capacitor C1 connected between the second electrode and the control electrode of the eighth transistor T8 and a second capacitor C2 connected between the second electrode and the control electrode of the ninth transistor T9, so as to make the control electrode potentials of the eighth transistor T8 and the ninth transistor T9 more stable.

[0060] As an example, when the first node N is high and the second node P is low, the eighth transistor T8 is turned on and the ninth transistor T9 is turned off. The first clock signal is transmitted to the output node O through the eighth transistor T8 to output a high-level scan signal, which selects the corresponding switching transistor in the pixel unit. When the first node N is low and the second node P is high, the eighth transistor T8 is turned off and the ninth transistor T9 is turned on. The first voltage signal VGL1 is transmitted to the output node O through the ninth transistor T9 to output a low-level scan signal.

[0061] This disclosure exemplarily describes the operation of a display panel as follows.

[0062] Reference Figure 7 When the fifth transistor T5 receives the transmission signal, it turns on, transmitting the third voltage signal VGH to the first node N, which is then pulled high. At this time, the sixth transistor T6 is turned off because the second node P is low, and the seventh transistor T7 is turned off under the control of the second clock signal, maintaining the first node N at a stable high level. Next, the third transistor of the inverter circuit 4 turns on, transmitting the first voltage signal VGL1 to the second node P, maintaining the second node P at a low level. At this time, the eighth transistor T8 of the output circuit 2 turns on, and the ninth transistor T9 is turned off. The first clock signal is output to the output node O through the eighth transistor T8, forming a high-level scan signal to select the corresponding switching transistor in the pixel unit.

[0063] Reference Figure 8Subsequently, the transmission signal fails, and the seventh transistor T7 turns on when the second clock signal is high, pulling down the potential of the first node N. Simultaneously, the fourth transistor T4 of the second input circuit 5 turns on under the drive of the second clock signal, transmitting the third voltage signal VGH to the second node P, pulling the second node P high and driving the sixth transistor T6 to turn on, further pulling the first node N low, forming a feedback loop to ensure that the first node N and the second node P have opposite voltage levels. Furthermore, during this process, because the third transistor uses a dual-gate structure, even if the third transistor experiences a threshold voltage negative bias, it can effectively suppress leakage current in the second node P, stabilizing the potential of the second node P at a high level. At this time, the eighth transistor T8 of the output circuit 2 turns off, and the ninth transistor T9 turns on. The first voltage signal VGL1 is output to the output node O through the ninth transistor T9, forming a low-level scanning signal and turning off the pixel unit.

[0064] Finally, after the scan is complete, the reset signal Reset triggers the reset circuit 3, which uses the second voltage signal VGL2 to reset the first node N and the output node O, clearing any residual potential. By using a second voltage signal with a higher potential than the first voltage signal for reset, the source-drain voltage difference between the first transistor T1 and the second transistor T21 in the off state in the reset circuit 3 can be reduced, suppressing leakage caused by the negative bias of the threshold voltage, and to a certain extent avoiding abnormal pull-down of the potential of the output node O and the first node N.

[0065] Reference Figure 9 IGZO Vth Shift represents the degree of offset of the transistor threshold voltage. Gout1 indicates that the scan signal output by output node O when the transistor threshold voltage is negatively biased by 2V cannot output a valid pulse waveform. Gout2 indicates that the scan signal output by output node O when the transistor threshold voltage is negatively biased by 0 to 1.5V can output a valid pulse waveform. Gout3 indicates that the scan signal output by output node O when the transistor threshold voltage is positively biased by 0 to 1.5V can output a valid pulse waveform. Gout4 indicates that the scan signal output by output node O when the transistor threshold voltage is positively biased by 2V to 3V cannot output a valid pulse waveform. Therefore, this embodiment improves the margin of the gate drive circuit by setting the third transistor as a dual-gate transistor and using the second voltage signal VGL2 to reset the first node N and the output node O, so that each transistor can work normally within a threshold voltage negative bias of 2V.

[0066] According to a second aspect of this application, a display device is provided, including the above-described display panel and a power management chip, wherein the power management chip includes functions for outputting a first voltage signal and a second voltage signal to the display panel.

[0067] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0068] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0069] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0070] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A display panel, characterized in that, It includes several gate driving circuits and pixel units connected to the gate driving circuits; The gate driving circuit includes: The first input circuit is used to receive the transmission signal and control the potential of the first node according to the transmission signal. The output circuit is connected to the first input circuit at the first node and to the pixel unit at the output node, and is used to receive the first voltage signal; A reset circuit is used to receive a reset signal and a second voltage signal, and under the drive of the reset signal, reset at least one of the first node and the output node through the second voltage signal; Wherein, the potential of the second voltage signal is greater than the potential of the first voltage signal.

2. The display panel according to claim 1, characterized in that, The potential difference between the second voltage signal and the first voltage signal is greater than or equal to 2V.

3. The display panel according to claim 1, characterized in that, The reset circuit includes a first transistor and a second transistor; The first transistor includes a first electrode for receiving the second voltage signal, a second electrode connected to the first node, and a control electrode for receiving the reset signal; wherein the potential of the second voltage signal is greater than the potential of the first voltage signal, so that when the first transistor is turned off, the potential difference between the first electrode and the second electrode of the first transistor is reduced; The second transistor includes a first electrode for receiving the second voltage signal, a second electrode connected to the output node, and a control electrode for receiving the reset signal; wherein the potential of the second voltage signal is greater than the potential of the first voltage signal, so that when the second transistor is turned off, the potential difference between the first electrode and the second electrode of the second transistor is reduced.

4. The display panel according to claim 1, characterized in that, It also includes an inverter circuit, which is connected to the first node and connected to the output circuit at the second node. The inverter circuit is used to receive the first voltage signal and control the potential of the second node according to the potential of the first node, so that the level states of the first node and the second node are different. The inverting circuit includes a third transistor, which is a dual-gate transistor, used to control the potential of the second node according to the potential of the first node, and to isolate the second node and the first voltage signal when the third transistor is in the off state.

5. The display panel according to claim 4, characterized in that, The third transistor includes a first sub-transistor and a second sub-transistor; The first sub-transistor includes a first electrode for receiving the first voltage signal, a second electrode connected to the second sub-transistor, and a control electrode connected to the first node; The second sub-transistor includes a first electrode connected to the first sub-transistor, a second electrode connected to the second node, and a control electrode connected to the first node; The first width-to-length ratio of the channel width to the channel length of the first sub-transistor is greater than the second width-to-length ratio of the channel width to the channel length of the second sub-transistor.

6. The display panel according to claim 5, characterized in that, The first aspect ratio is 2, and the second aspect ratio is 1; The first sub-transistor has a channel width of 8 μm and a channel length of 4 μm; the second sub-transistor has a channel width of 4 μm and a channel length of 4 μm.

7. The display panel according to any one of claims 4 to 6, characterized in that, It also includes a second input circuit, which includes a fourth transistor; The fourth transistor includes a first electrode for receiving a third voltage signal, a second electrode connected to the second node of the output circuit, and a control electrode for receiving a second clock signal.

8. The display panel according to claim 7, characterized in that, The first input circuit includes a fifth transistor, a sixth transistor, and a seventh transistor; The fifth transistor includes a first electrode for receiving a third voltage signal, a second electrode connected to the first node, and a control electrode for receiving the transmission signal. The sixth transistor includes a first electrode for receiving the first voltage signal, a second electrode connected to the first node, and a control electrode connected to the second node; The seventh transistor includes a first electrode for receiving the first voltage signal, a second electrode connected to the first node, and a control electrode for receiving the second clock signal.

9. The display panel according to claim 8, characterized in that, The output circuit includes an eighth transistor and a ninth transistor; The eighth transistor includes a first electrode for receiving a first clock signal, a second electrode connected to the ninth transistor at the output node, and a control electrode connected to the first node; The ninth transistor includes a first electrode for receiving the first voltage signal, a second electrode connected to the output node, and a control electrode connected to the second node.

10. A display device, characterized in that, The device includes a display panel as described in any one of claims 1 to 9 and a power management chip, wherein the power management chip includes functions for outputting the first voltage signal and the second voltage signal to the display panel.

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