A gate driving circuit, a display panel and a display device

Abstract

The present disclosure provides a kind of gate drive circuit, display panel and display device, it is related to display technical field, gate drive circuit includes cascaded shift register unit;First node control module, second node control module, output module in shift register unit include multiple transistors, at least part of transistor is double-gate oxide transistor, the control signal received by the gate of oxide transistor is non-constant signal, first node control module is connected with first node, second node control module is connected with second node, output module is connected with first node, second node and scanning signal output end.This disclosure can improve the stability and reliability of the scanning signal output by gate drive circuit, thereby improving the display effect of display product.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a gate driving circuit, a display panel, and a display device. Background Technology

[0002] Currently, display panels are typically composed of multiple light-emitting sub-pixels arranged in an array. Each light-emitting sub-pixel consists of pixel circuitry and light-emitting elements. Pixel circuitry typically consists of TFTs (Thin Film Transistors) and capacitors. Light-emitting elements can typically include OLEDs (Organic Light-Emitting Diodes) or other light-emitting devices.

[0003] To improve display quality and reduce costs, related technologies replace the LTPS (Low Temperature Poly-Silicon) transistors that provide scanning signals to the pixel circuits with oxide transistors, such as IGZO (Indium Gallium Zinc Oxide) transistors. However, LTPS transistors possess excellent PBTS (Positive Bias Temperature Stress) characteristics; even when forward biased for extended periods at high temperatures, the threshold voltage Vth of the transistor does not deviate significantly. In contrast, IGZO transistors have inferior PBTS characteristics compared to LTPS transistors. This results in more severe device characteristic drift when the same forward bias voltage is applied at the same temperature, leading to a significant shift in the threshold voltage and ultimately preventing the proper provision of scanning signals to the pixel circuits.

[0004] Therefore, how to improve the insufficient PBTS characteristics of IGZO transistors in the gate drive circuit, which affect the output of the scan signal, has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] To address the aforementioned technical problems, this disclosure provides a gate driving circuit, a display panel, and a display device, which can ensure the stability and reliability of the output signal of the gate driving circuit and improve the display effect of the display product.

[0006] In a first aspect, this disclosure provides a gate driving circuit comprising multiple cascaded shift register units, each shift register unit including a first node control module, a second node control module, an output module, and a first voltage signal terminal; the first node control module, the second node control module, and the output module each include multiple transistors, at least some of which are oxide transistors, and some of which are dual-gate oxide transistors; some of the dual-gate oxide transistors have two gates receiving the same control signal, while the other dual-gate oxide transistors have two gates receiving two different control signals; the control signal received by the gate of the oxide transistor is different from the first voltage signal output from the first voltage signal terminal; the first voltage signal is a constant voltage signal; The first node control module is connected to the first node, the second node control module is connected to the second node, and the output module is connected to the first node, the second node, and the scan signal output terminal.

[0007] Secondly, based on the same inventive concept, this disclosure provides a display panel including the gate driving circuit of the first aspect.

[0008] Thirdly, based on the same inventive concept, this disclosure provides a display device, including the display panel described in the second aspect.

[0009] The technical solution provided in this disclosure has the following advantages compared with the prior art: This disclosure provides a gate driving circuit, a display panel, and a display device. The gate driving circuit consists of multiple cascaded shift register units. Each shift register unit includes a first node control module, a second node control module, and an output module. Among the transistors constituting these modules, some are oxide transistors. For oxide transistors with dual gates, the two gates can receive the same control signal or different control signals, but neither dual-gate oxide transistor's gate will receive a constant high-level first voltage signal as a control signal. Therefore, during normal operation of the gate driving circuit, the control signal received by the gate of the dual-gate oxide transistor will switch between high and low levels, that is, the dual-gate oxide transistor will switch between a conducting state and a cutoff state, preventing the dual-gate oxide transistor from remaining on for a long time, thereby reducing the impact of the forward bias voltage received in the conducting state. After long-term operation, the threshold voltage deviation of the dual-gate oxide transistor can be maintained within the normal range, without affecting the normal output of the scan signal, ensuring the stability and reliability of the gate driving circuit, and improving the display effect of the display product. Attached Figure Description

[0010] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0011] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 This is a schematic diagram of a shift register unit in a scan drive circuit in related technologies. Figure 2 This is a schematic diagram showing the relationship between the threshold offset ΔVth of IGZO TFT and LTPS TFT and time. Figure 3 A schematic diagram of a display panel provided in an embodiment of this disclosure; Figure 4 A schematic diagram of a shift register unit in a gate drive circuit provided in an embodiment of this disclosure; Figure 5 Another schematic diagram of the shift register unit in the gate drive circuit provided in the embodiments of this disclosure; Figure 6 Another schematic diagram of a shift register unit in a gate drive circuit provided in this disclosure embodiment; Figure 7 Another schematic diagram of a shift register unit in a gate drive circuit provided in this disclosure embodiment; Figure 8 Another schematic diagram of a shift register unit in a gate drive circuit provided in this disclosure embodiment; Figure 9 Another schematic diagram of a shift register unit in a gate drive circuit provided in this disclosure embodiment; Figure 10 This is yet another schematic diagram of a shift register unit in a gate drive circuit provided in an embodiment of the present disclosure; Figure 11 This is yet another schematic diagram of a shift register unit in a gate drive circuit provided in an embodiment of the present disclosure; Figure 12 Another schematic diagram of a shift register unit in a gate drive circuit provided in this disclosure embodiment; Figure 13 Another schematic diagram of a shift register unit in a gate drive circuit provided in this disclosure embodiment; Figure 14A schematic diagram of a gate drive circuit provided in an embodiment of this disclosure; Figure 15 A timing diagram of a shift register unit provided in an embodiment of this disclosure; Figure 16 A schematic diagram of another circuit structure for the gate drive circuit provided in an embodiment of this disclosure; Figure 17 Another schematic diagram of a shift register unit in a gate drive circuit provided in this disclosure embodiment; Figure 18 Another schematic diagram of a shift register unit in a gate drive circuit provided in this disclosure embodiment; Figure 19 Another schematic diagram of a shift register unit in a gate drive circuit provided in this disclosure embodiment; Figure 20 Another schematic diagram of a shift register unit in a gate drive circuit provided in this disclosure embodiment; Figure 21 Another schematic diagram of a shift register unit in a gate drive circuit provided in this disclosure embodiment; Figure 22 Another schematic diagram of a shift register unit in a gate drive circuit provided in this disclosure embodiment; Figure 23 Another timing diagram of the shift register unit provided in the embodiments of this disclosure; Figure 24 Another schematic diagram of a shift register unit in a gate drive circuit provided in this disclosure embodiment; Figure 25 This is a schematic diagram of a display device provided in an embodiment of the present disclosure.

[0013] Among them, 100 is the gate drive circuit; 10 is the shift register unit; 11 is the first node control module; 12 is the second node control module; 13 is the output module; 14 is the first voltage regulator module; 15 is the second voltage regulator module; 16 is the reset module; VGH is the first voltage signal terminal; VGL is the second voltage signal terminal; N1 is the first node; N2 is the second node; N3 is the third node; OUT is the scan signal output terminal; 111 is the first node pull-up module; 112 is the first node pull-down module; 121 is the second node pull-up module; 122 is the second node pull-down module; 113 is the third node pull-down module; CK is the first clock signal line; XCK is the first clock signal line. Second clock signal line; CK1, first clock signal line; CK2, second clock signal line; CK3, third clock signal line; CK4, fourth clock signal line; CK_Buffer, fourth clock signal terminal; VGL_Buffer, third voltage signal terminal; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; 200, display panel; 300, display device. Detailed Implementation

[0014] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0015] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0016] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The embodiments will now be described in detail with reference to the accompanying drawings.

[0017] Currently, display panels are typically composed of multiple light-emitting sub-pixels arranged in an array. Each light-emitting sub-pixel consists of pixel circuitry and light-emitting elements. Pixel circuitry typically consists of TFTs (Thin Film Transistors) and capacitors. Light-emitting elements can typically include OLEDs (Organic Light-Emitting Diodes) or other light-emitting devices.

[0018] To improve display quality and reduce costs, related technologies replace the transistors in the gate drive circuit that provide scanning signals to the pixel circuit with LTPS (Low Temperature Poly-Silicon) TFTs. In these technologies, for a single shift register unit constituting the gate drive circuit, after replacing the transistor with an IGZO transistor, and by specifically adjusting the connection relationships between the transistors and the control signals of the transistors, the following can be achieved: Figure 1 The circuit diagram shown is of a shift register unit, which includes transistors M1' to M8', and each transistor is an N-type oxide transistor, such as an IGZO transistor.

[0019] However, LTPS TFTs possess excellent PBTS (Positive Bias Temperature Stress) characteristics. Even when forward biased for extended periods at high temperatures, the TFT's threshold voltage Vth does not exhibit significant shift. In contrast, IGZO TFTs have inferior PBTS characteristics compared to LTPS TFTs. Consequently, when the same forward bias voltage is applied at the same temperature, IGZO TFTs experience more severe device characteristic drift, leading to a significant shift in their threshold voltage. Ultimately, this prevents the transistors from properly switching between on and off states, hindering the gate drive circuit from providing the necessary scanning signals to the pixel circuit. Figure 2 As shown, it can be determined that, under the same ambient temperature and forward bias voltage conditions, after the same time, the shift ΔVth of the threshold voltage of the LTPS TFT is significantly smaller than that of the IGZO TFT. That is, the PBTS characteristic of the IGZO TFT is lower than that of the LTPS TFT. Therefore, referring to... Figure 1 The shift register shown can operate normally in the initial stage. However, because each IGZO transistor receives a high-level signal as the control signal for transistor conduction, the IGZO transistors are in a forward-biased state when in conduction. After prolonged operation, the threshold voltage Vth of some IGZO transistors will become significantly forward-biased, eventually causing the transistors to be unable to maintain a stable conduction state under high-level signals, thus affecting the scan signal output by the shift register.

[0020] Therefore, how to improve the insufficient PBTS characteristics of IGZO TFT in the gate drive circuit, which affects the output of the scanning signal, has become a technical problem that urgently needs to be solved by those skilled in the art.

[0021] To address the aforementioned technical problems, embodiments of this application provide a gate driving circuit, a display panel, and a display device. The gate driving circuit provided in the embodiments of this application will be described first.

[0022] Figure 3 The diagram shows a schematic of the gate driving circuit provided in one embodiment of this application. The display panel 200 includes a gate driving circuit 100 and a display area 20. The gate driving circuit 100 includes a plurality of cascaded shift register units 10. In the following embodiments, a single shift register unit 10 is used as an example for illustration.

[0023] It is understood that the location of the gate drive circuit 100 is not limited in the embodiments of this application. Figure 3 In the illustrated embodiment, the gate driving circuit 100 can be located in a non-display area outside the display area 20. Alternatively, the gate driving circuit can be located within the display area 20; this is not a limitation.

[0024] Figure 4 This is a schematic diagram of a shift register unit in a gate drive circuit provided in an embodiment of this disclosure. Please refer to... Figure 4 A single shift register unit 10 may include a first node control module 11, a second node control module 12, an output module 13, and a first voltage signal terminal VGH.

[0025] The first node control module 11, the second node control module 12, and the output module 13 each include multiple transistors. At least some of the transistors in each module are oxide transistors, such as IGZO transistors. A portion of the multiple oxide transistors are dual-gate oxide transistors with two gates. In a subset of the dual-gate oxide transistors, the two gates of one subset can receive the same control signal, while the two gates of another subset receive two different control signals.

[0026] In the aforementioned dual-gate oxide transistors (DMTs), whether both gates receive the same control signal or both gates receive different control signals, the received control signal is different from the first voltage signal output from the first voltage signal terminal VGH. That is, the gate of any DMT will not receive the first voltage signal as a control signal. The first voltage signal terminal VGH can be connected to a first voltage signal line laid out within the display panel to receive the first voltage signal transmitted by the first voltage signal line. This first voltage signal can be a constant voltage signal. This first voltage signal can be a high-level signal that drives the oxide transistor to conduct, such as the VGH signal.

[0027] It is understood that the constant high-level signal received by the first voltage signal terminal VGH is only one of multiple high-level signals provided by multiple signal traces within the display panel. Apart from the high-level signal received by the first voltage signal terminal VGH, the gate of the aforementioned dual-gate oxide transistor will not receive any other constant high-level signals as control signals.

[0028] The first node control module 11 can be connected to the first node N1, and the first node control module 11 can control the signal of the first node N1. The second node control module 12 can be connected to the second node N2, and the second node control module 12 can control the signal of the second node N2. The output module 13 can be connected to the first node N1, the second node N2, and the scan signal output terminal OUT, and the output module 13 can control the scan signal output by the scan signal output terminal OUT according to the signals of the first node N1 and the second node N2.

[0029] It should be noted that a single shift register unit 10 can output a scan signal through the scan signal output terminal OUT. This scan signal can drive a single row or multiple rows of pixel circuits, and it can also be used as a transmission signal for the next-level shift register unit 10, so that each level of shift register unit 10 can output the scan signal line by line according to the scan signal output by the previous level shift register unit 10.

[0030] Some transistors within the shift register unit 10 are configured as dual-gate oxide transistors (DMTs). Since an oxide transistor receives a high-level signal at its gate, it is equivalent to applying a forward bias voltage to the gate. If the gate receives a high-level signal for an extended period, the oxide transistor will remain in a forward bias state for a prolonged time, which is a typical PBTS (Platelet-Barred Threshold Voltage Shift). Therefore, in the above embodiment, by setting the gate of any dual-gate oxide transistor to not receive a constant high-level first voltage signal as a control signal, the gate of the dual-gate oxide transistor can be prevented from being subjected to a prolonged forward bias voltage, thereby improving the threshold voltage shift of the oxide transistor.

[0031] In this embodiment, the gate driving circuit 100 consists of multiple cascaded shift register units 10. Each shift register unit 10 includes a first node control module 11, a second node control module 12, and an output module 13. Among the transistors constituting these modules, some are oxide transistors. For oxide transistors with dual gates, the two gates can receive the same control signal or different control signals, but neither dual-gate oxide transistor's gate will receive a constant high-level first voltage signal as a control signal. Therefore, during the normal driving operation of the gate driving circuit 100, the control signal received by the gate of the dual-gate oxide transistor will switch between high and low levels, that is, the dual-gate oxide transistor will switch between the on and off states, so that the dual-gate oxide transistor will not remain on for a long time, thereby reducing the influence of the forward bias voltage received in the on state. After a long period of operation, the deviation of the threshold voltage of the dual-gate oxide transistor can be maintained within the normal range, without affecting the normal output of the scan signal, ensuring the stability and reliability of the gate driving circuit 100.

[0032] Figure 5 For another schematic diagram of the shift register unit in the gate drive circuit provided in this embodiment, please refer to... Figure 5 In some embodiments, the first node control module 11 may include a third node N3. The third node N3 can be connected to the first node N1 through at least one transistor of the first node control module 11, and the third node N3 can also be connected to the second node N2 through at least one transistor of the second node control module 12. That is, the node signal of the third node N3 can control at least one transistor of the first node control module 11, thereby realizing signal control of the first node N1; the node signal of the third node N3 can also control at least one transistor of the second node control module 12, thereby realizing signal control of the second node N2.

[0033] It is understandable that the above Figure 5 The transistors shown between the third node N3 and the first node N1 are merely illustrative examples and are not intended to limit the number or connection relationship of the transistors between the third node N3 and the first node N1.

[0034] Figure 6 For another schematic diagram of the shift register unit in the gate drive circuit provided in the embodiments of this disclosure, please refer to... Figure 6Taking the scan signal output terminal of the current shift register unit 10 as OUT[n] as an example, the first node control module 11 can be connected to the cascade signal input terminal STV / IN, the first clock signal terminal CK, the first voltage signal terminal VGH, the second voltage signal terminal VGL, the scan signal output terminal OUT[n+1] of the next-stage shift register unit 10, and the first node N1. That is, the first node control module 11 can control the signals of the first node N1 and the third node N3 according to the signals of the cascade signal input terminal STV / IN, the first clock signal terminal CK, the first voltage signal terminal VGH, the second voltage signal terminal VGL, and the scan signal output terminal OUT[n+1] of the next-stage shift register unit 10.

[0035] The second node control module 12 can be connected to the third node N3, the first clock signal terminal CK, the first voltage signal terminal VGH, and the second node N2. That is, the second node control module 12 can control the signal of the second node N2 according to the signals of the third node N3, the first clock signal terminal CK, and the first voltage signal terminal VGH.

[0036] In this embodiment, the first node control module 11 can control the signals of the first node N1 and the third node N3, and the second node control module 12 can control the signal of the second node N2. Through the first node control module 11 and the second node control module 12, signal control of the first node N1 and the second node N2 can be realized. The output module 13 can generate a valid scan signal based on the signals of the first node N1 and the second node N2. The valid scan signal can drive the corresponding pixel circuit to realize light emission control, and drive the next-level shift register unit 10 to continue outputting the valid scan signal, ultimately realizing the line-by-line output of the scan signal.

[0037] Figure 7 For another schematic diagram of the shift register unit in the gate drive circuit provided in this embodiment, please refer to... Figure 7 In some embodiments, the first node control module 11 may include a first node pull-up module 111 and a first node pull-down module 112.

[0038] The first node pull-up module 111 is connected to the cascade signal input terminal STV / IN, the first clock signal terminal CK, the first voltage signal terminal VGH, and the first node N1. The first node pull-up module 111 can introduce the first voltage signal of the first voltage signal terminal VGH to the first node N1 according to the signals of the cascade signal input terminal STV / IN and the first clock signal terminal CK, thereby pulling the signal of the first node N1 high as a high-level signal.

[0039] The first node pull-down module 112 is connected to the scan signal output terminal OUT[n+1] of the next-stage shift register unit 10, the second voltage signal terminal VGL, and the first node N1. The first node pull-down module 112 can introduce the second voltage signal provided by the second voltage signal terminal VGL to the first node N1 according to the signal of the scan signal output terminal OUT[n+1] of the next-stage shift register unit 10, thereby pulling the signal of the first node N1 low to a low level signal.

[0040] In this embodiment, the first node pull-up module 111 and the first node pull-down module 112 can respectively introduce a first voltage signal and a second voltage signal to the first node N1, thereby realizing the pull-up or pull-down of the first node N1, that is, realizing signal control of the first node N1.

[0041] Figure 8 For another schematic diagram of the shift register unit in the gate drive circuit provided in the embodiments of this disclosure, please refer to... Figure 8 As an optional implementation, the first node pull-up module 111 may include a first transistor T1 and a second transistor T2. The first transistor T1 and the second transistor T2 may be dual-gate oxide transistors.

[0042] The first transistor T1 has its first terminal connected to the stage signal input terminal STV / IN, its second terminal connected to the third node N3, and its first gate connected to the first clock signal terminal CK. The second transistor T2 has its first terminal connected to the first voltage signal terminal VGH, its second terminal connected to the first node N1, and its first gate connected to the third node N3.

[0043] The first gate of the first transistor T1 receives the first clock signal provided by the first clock signal terminal CK. When the first clock signal changes from low level to high level, the first transistor T1 is turned on, connecting the stage transmission signal input terminal STV / IN with the third node N3.

[0044] Understandably, taking a single shift register unit 10 as an example, when the previous stage shift register unit 10 does not output a valid scan signal, the cascade signal input terminal STV / IN of the current shift register unit 10 receives a low-level signal. Even when the first transistor T1 is turned on, the signal of the third node N3 will remain at a low level. Only when the first transistor T1 is turned on and the previous stage shift register unit 10 outputs a valid scan signal, can the valid scan signal, as a high-level signal, pull the signal of the third node N3 high.

[0045] When the signal at the third node N3 is a high-level signal, the first gate of the second transistor T2 receives a high-level signal, the second transistor T2 is turned on, and the first voltage signal terminal VGH is connected to the first node N1. At this time, the signal at the first node N1 is pulled high as the first voltage signal.

[0046] In this embodiment, the first clock signal can control the conduction of the first transistor T1, introduce the effective signal of the scan signal output by the previous stage shift register unit 10 into the third node N3, so that the third node N3 is pulled high as a high level signal, and drives the second transistor T2 to conduct, introducing the first voltage signal into the first node N1, thereby realizing the signal pull-up of the first node N1.

[0047] It should be noted that the control signal received by the first gate of the first transistor T1 is the first clock signal provided by the first clock signal terminal CK. This first clock signal is a clock signal with alternating high and low levels. Therefore, the first gate of the first transistor T1 will not receive a constant high-level signal. Similarly, the third node N3 is only pulled high when the scan signal output by the previous stage shift register unit 10 is valid and the first transistor T1 is in the on state. Therefore, the first gate of the second transistor T2 will not receive a constant high-level signal. Since the first gates of both the first transistor T1 and the second transistor T2 will not receive constant high-level signals, it is possible to avoid the first transistor T1 and the second transistor T2 being in a forward biased state for a long time. This helps to reduce the threshold voltage offset of the oxide transistor, thereby improving the problem that the shift register unit 10 cannot output the scan signal normally due to excessive forward bias of the threshold voltage.

[0048] In some embodiments, the second gate of the first transistor T1 can be connected to the second voltage signal terminal VGL, and the second gate of the first transistor T1 can also be connected to the first terminal of the first transistor T1. That is, the first gate and the second gate of the first transistor T1 are respectively connected to different control signals.

[0049] Understandable, Figure 8 The diagram shows a schematic of the connection between the second gate of the first transistor T1 and the second voltage signal terminal VGL. Alternatively, the second gate of the first transistor T1 can also be directly connected to the first terminal of the first transistor T1. Similarly, in the following embodiments, when a transistor has dual gates and the two gates receive two different control signals, the diagrams only disclose one of the two connection methods: the second gate of the transistor is connected to the second voltage signal terminal VGL, or the second gate of the transistor is connected to the first terminal of the transistor. However, those skilled in the art can flexibly change the connection method of the second gate of the transistor to another method, which is not limited here.

[0050] Taking a first gate as the top gate and a second gate as the bottom gate as an example, when the first gate and the second gate are connected to different control signals, such as when the second gate of the first transistor T1 in the above embodiment is connected to the second voltage signal terminal VGL or to its own source, the second gate will not enter a forward bias state because the control signal received by the second gate is a low-level signal or is consistent with the source signal. At this time, only the first gate is in a forward bias state when receiving a high-level signal. Therefore, the above connection method of the second gate can reduce the forward bias amplitude of the threshold voltage of the transistor after long-term operation.

[0051] like Figure 8 As shown, the second gate of the second transistor T2 can be connected to the first gate of the second transistor T2. That is, the first gate and the second gate of the second transistor T2 are connected to the same control signal.

[0052] In the second transistor T2 of the above embodiment, since the top gate and bottom gate are connected to the same control signal, the driving capability of the transistor can be improved and the conduction threshold voltage Vth of the transistor can be reduced. However, during the process of driving the second transistor T2 to conduct when both the top gate and bottom gate receive high-level signals, both the first gate and the second gate are in a forward bias state. Under the same conditions, after a long period of operation, the forward bias amplitude of the threshold voltage of the second transistor T2 will increase compared to the first transistor T1. Therefore, when setting the control signal received by the second gate of the oxide transistor with dual gates, it can be set according to whether the first gate of the dual-gate oxide transistor is affected by PBTS. For example, in the first transistor T1 and the second transistor T2 described above, the control signal received by the first gate of the first transistor T1 is a first clock signal. Although the first clock signal is not a constant high-level signal, as a clock signal, the duty cycle of the high-level signal is about 50% (because in order to avoid the high-level signal intervals of the two clock signals overlapping, a corresponding dead time is usually set when the high-level signals are alternately output, so that the duty cycle of the high-level signal is slightly less than 50%). Therefore, during normal operation of the display panel, the on-time and off-time of the first transistor T1 can be considered approximately equal. In this case, the cumulative time for the first gate of the first transistor T1 to receive a high-level signal is still relatively long, meaning the first transistor T1 will be affected by PBTS. At this point, the second gate of the first transistor T1 can be connected to the second voltage signal terminal VGL or the first terminal of the first transistor T1. This dual-gate structure ensures the stability of the threshold voltage of the first transistor T1 and reduces the positive bias amplitude of the threshold voltage after prolonged operation.

[0053] Correspondingly, the control signal received by the first gate of the second transistor T2 is the high-level signal of the third node N3. Based on the characteristic of the shift register unit 10 outputting the scan signal line by line, each shift register unit 10 outputs a valid scan signal once per single image frame. Therefore, the conduction time of the second transistor T2 is short. It can be considered that within the time interval of a single image frame, the first gate of the second transistor T2 only receives a high-level signal for a short period, meaning that the second transistor T2 is not affected by PBTS or is only minimally affected by PBTS. In this case, the second gate of the first transistor T1 can be connected to the same control signal as its first gate, thereby improving the driving capability of the transistor and reducing the threshold voltage Vth when the transistor is turned on, as well as the on-state voltage drop.

[0054] Figure 9 For another schematic diagram of the shift register unit in the gate drive circuit provided in the embodiments of this disclosure, please refer to... Figure 9 In some embodiments, the first node pull-down module 112 may include a third transistor T3. The first terminal of the third transistor T3 is connected to the second voltage signal terminal VGL, the second terminal of the third transistor T3 is connected to the first node N1, and both the first gate and the second gate of the third transistor T3 are connected to the scan signal output terminal OUT of the next-stage shift register unit 10.

[0055] The third transistor T3 can be turned on or off under the control of the scan signal output from the scan signal output terminal OUT of the next-stage shift register unit 10. When the third transistor T3 is off, the second voltage signal terminal VGL is disconnected from the first node N1, and the second voltage signal will not affect the signal of the first node N1. When the third transistor T3 is on, the second voltage signal terminal VGL can transmit the second voltage signal to the first node N1, thereby pulling the signal of the first node N1 low to a low level signal.

[0056] The control signal received by the third transistor T3 is the scan signal output from the scan signal output terminal OUT of the next-stage shift register unit 10. Based on the principle that the shift register unit 10 outputs scan signals line by line, each shift register unit 10 outputs a valid scan signal within a single image frame. Therefore, it can be considered that within the time interval of a single image frame, the first gate of the third transistor T3 only receives the valid scan signal as a high-level signal for a short period. That is, the conduction time of the third transistor T3 accounts for a short proportion of the total time, and the third transistor T3 is not affected by PBTS or is only minimally affected by PBTS. Therefore, for the same reason as the second transistor T2 described above, the first gate and the second gate of the third transistor T3 can be connected to the same control signal.

[0057] Figure 10For another schematic diagram of the shift register unit in the gate drive circuit provided in the embodiments of this disclosure, please refer to... Figure 10 In some embodiments, the second node control module 12 may include a second node pull-up module 121 and a second node pull-down module 122.

[0058] The second node pull-up module 121 is connected to the first clock signal terminal CK, the first voltage signal terminal VGH, and the second node N2. The second node pull-up module 121 can introduce a first voltage signal to the second node N2 according to the signal of the first clock signal terminal CK, thereby pulling the signal of the second node N2 high as a high-level signal.

[0059] The second node pull-down module 122 is connected to the third node N3, the first clock signal terminal CK, and the second node N2. The second node pull-down module 122 can draw the signal from the first clock signal terminal CK based on the signal from the third node N3. When the signal from the first clock signal terminal CK changes from high to low, it can pull the signal from the second node N2 down to a low level.

[0060] In this embodiment, the second node pull-up module 121 and the second node pull-down module 122 can respectively introduce the first voltage signal and the first clock signal terminal CK to the second node N2, thereby realizing the pull-up or pull-down of the second node N2, that is, realizing the signal control of the second node N2.

[0061] Figure 11 For another schematic diagram of the shift register unit in the gate drive circuit provided in the embodiments of this disclosure, please refer to... Figure 11 In some embodiments, the second node pull-up module 121 described above may include a fourth transistor T4.

[0062] The first terminal of the fourth transistor T4 is connected to the first voltage signal terminal VGH, the second terminal is connected to the second node N2, and the first gate is connected to the first clock signal terminal CK. The second gate of the fourth transistor T4 can be connected in two ways: one is that the second gate of the fourth transistor T4 is connected to the second voltage signal terminal VGL, and the other is that the second gate of the fourth transistor T4 is connected to the second terminal of the fourth transistor T4.

[0063] The fourth transistor T4 can be turned on or off under the signal control of the first clock signal terminal CK. When the fourth transistor T4 is on, it can introduce the first voltage signal into the second node N2, thereby pulling the signal of the second node N2 high. When the fourth transistor T4 is off, the first voltage signal terminal VGH is disconnected from the second node N2, and the first voltage signal will not affect the signal magnitude of the first node N1.

[0064] The control signal received by the fourth transistor T4 is the signal from the first clock signal terminal CK. Since the duty cycle of the first clock signal provided by the first clock signal terminal CK is approximately 50%, it can be assumed that the on-time and off-time of the fourth transistor T4 are approximately equal. That is, the on-time of the fourth transistor T4 is relatively long, making it susceptible to PBTS. Therefore, for the same reason as the first transistor T1 described above, the second gate of the fourth transistor T4 can be connected to the second voltage signal terminal VGL or the first terminal of the fourth transistor T4.

[0065] Figure 12 For another schematic diagram of the shift register unit in the gate drive circuit provided in the embodiments of this disclosure, please refer to... Figure 12 In some embodiments, the second node pull-down module 122 described above may include a fifth transistor T5. The first terminal of the fifth transistor T5 is connected to the first clock signal terminal CK, the second terminal is connected to the second node N2, the first gate is connected to the third node N3, and the second gate is connected to the third node N3.

[0066] The fifth transistor T5 can be turned on or off under the signal control of the first node N1. When the fifth transistor T5 is off, the first clock signal terminal CK is disconnected from the second node N2, and the signal of the second node N2 is not affected by the first clock signal terminal CK. When the fifth transistor T5 is on, the first clock signal of the first clock signal terminal CK is introduced into the second node N2. When the signal of the first clock signal terminal CK changes from high level to low level, it can pull the signal of the second node N2 low level signal.

[0067] It should be noted that the fifth transistor T5 can pull the signal of the second node N2 low when the first clock signal terminal CK provides a low-level signal.

[0068] In the above embodiment, the first gate of the fifth transistor T5 is connected to the third node N3. The third node N3 is only pulled high when the scan signal output by the previous shift register unit 10 is valid and the first transistor T1 is in the on state. Therefore, the fifth transistor T5 is only turned on during the row scan cycle in which the shift register unit 10 outputs the scan signal. For example, taking a single image frame with n pixel rows as an example, the image frame may include n row scan cycles. For each shift register unit 10, the fifth transistor T5 is turned on only in response to the high-level pulse of the third node N3 during a single row scan cycle. During the other n-1 row scan cycles, the third node N3 is not pulled high, so the fifth transistor T5 will not be turned on. That is, the on-time of the fifth transistor T5 accounts for a short proportion of the total time, and the fifth transistor T5 is not affected by PBTS or is only slightly affected by PBTS. Therefore, for the same reason as the second transistor T2 described above, the first gate and the second gate of the fifth transistor T5 can be connected to the same control signal, that is, connected to the first node N3 as the control signal.

[0069] Figure 13 For another schematic diagram of the shift register unit in the gate drive circuit provided in the embodiments of this disclosure, please refer to... Figure 13 In some embodiments, the output module 13 may include a sixth transistor T6, a seventh transistor T7, a first capacitor C1, and a second capacitor C2. The sixth transistor T6 and the seventh transistor T7 are dual-gate oxide transistors.

[0070] The first terminal of the sixth transistor T6 is connected to the second clock signal terminal XCK, the second terminal is connected to the scan signal output terminal OUT, and the first gate is connected to the first node N1. The first terminal of the seventh transistor T7 is connected to the second voltage signal terminal VGL, the second terminal is connected to the scan signal output terminal OUT, and the first gate is connected to the second node N2. The first capacitor C1 is connected between the second terminal and the first gate of the sixth transistor T6, and the second capacitor C2 is connected between the first terminal and the first gate of the seventh transistor T7.

[0071] The sixth transistor T6 can be turned on or off under the signal control of the first node N1. When the sixth transistor T6 is on, it can output the second clock signal of the second clock signal terminal XCK as a scan signal to the scan signal output terminal OUT. When the sixth transistor T6 is off, the second clock signal terminal XCK is disconnected from the scan signal output terminal OUT.

[0072] When the sixth transistor T6 is turned on, the first clock signal at the first clock signal terminal CK is a high-level signal, and the second clock signal at the second clock signal terminal XCK is a low-level signal. At this time, the signal output by the scan signal output terminal OUT is the low-level signal of the second clock signal. During the conduction of the sixth transistor T6, the clock signals of the first clock signal terminal CK and the second clock signal terminal XCK alternate, and the second clock signal of the second clock signal terminal XCK jumps to a high-level signal. During the time interval when the sixth transistor T6 is turned on and the second clock signal terminal XCK outputs a high-level signal, the scan signal output terminal OUT can output a high-level signal as a valid scan signal.

[0073] When the second clock signal output from the second clock signal terminal XCK transitions from a low level to a high level, the signal at the scan signal output terminal OUT also transitions. At this time, the first capacitor raises the voltage of the first node N1 through coupling, and the voltage amplitude of the coupled boost is the voltage difference between the high-level signal and the low-level signal. After the first capacitor couples and boosts the voltage of the first node N1, the voltage of the first node N1 is further raised from its original high-level signal. At this time, there is still a certain voltage difference between the voltage of the first node N1 and the high-level signal of the second clock signal terminal XCK, which allows the sixth transistor T6 to maintain a stable conducting state and prevents the gate-source voltage difference of the sixth transistor T6 from narrowing and causing the transistor to turn off.

[0074] The seventh transistor T7 can be turned on or off under the signal control of the second node N2. When the seventh transistor T7 is on, the second voltage signal at the second voltage signal terminal VGL can be used as an invalid signal of the scan signal output terminal OUT. When the seventh transistor T7 is off, the second voltage signal terminal VGL is disconnected from the scan signal output terminal OUT.

[0075] In some embodiments, the second gate of the sixth transistor T6 is connected to the first node N1. The second gate of the seventh transistor T7 is connected to the second voltage signal terminal VGL, or the second gate of the seventh transistor T7 is connected to the first terminal of the seventh transistor T7.

[0076] The control signal received by the sixth transistor T6 is the signal from the first node N1. Since the first node N1 is only pulled high when the second transistor T2 is turned on, the conduction frequency and conduction duration of the sixth transistor T6 can be approximately considered to be the same as those of the second transistor T2. That is, the conduction duration of the sixth transistor T6 is much shorter than its turn-off duration, making it less susceptible to PBTS effects. Therefore, for the same reasons as with the second transistor T2, the first gate and the second gate of the sixth transistor T6 can be connected to the first node N1.

[0077] The control signal received by the seventh transistor T7 is the signal from the second node N2. Since the second node N2 is only pulled low when the fifth transistor T5 is on, and both the fifth transistor T5 and the second transistor T2 receive the same control signal, the on-time of the seventh transistor T7 can be approximated as complementary to that of the second transistor T2. That is, the on-time of the seventh transistor T7 is much longer than its off-time, making it highly susceptible to PBTS. Therefore, for the same reasoning as with the first transistor T1, the second gate of the seventh transistor T7 can be connected to the second voltage signal terminal VGL, or the second gate of the seventh transistor T7 can be connected to the first terminal of the seventh transistor T7.

[0078] Figure 14 Please refer to the schematic diagram of a gate drive circuit provided in an embodiment of this disclosure. Figure 14 In the above embodiments, the gate driving circuit 100 may further include a first clock signal line CK1 and a second clock signal line CK2, wherein the clock signal output by the first clock signal line CK1 and the clock signal output by the second clock signal line CK2 are complementary clock signals from the same source.

[0079] In two adjacent shift register units 10, the first clock signal terminal CK of one shift register unit 10 is connected to the first clock signal line CK1, and the second clock signal terminal XCK is connected to the second clock signal line CK2. The first clock signal terminal CK of the other shift register unit 10 is connected to the second clock signal line CK2, and the second clock signal terminal XCK is connected to the first clock signal line CK1.

[0080] In this embodiment, by alternately connecting two adjacent shift register units 10 to two clock signal lines, the valid signal of the scan signal output by the previous shift register unit 10 can be used as the cascading signal of the next shift register unit 10, triggering the next shift register unit 10 to output the valid signal of the scan signal. Through the cascading transmission of multiple shift register units 10, the scan signal is finally output line by line.

[0081] The gate drive circuit 100 in the above embodiments includes a first clock signal line CK1 and a second clock signal line CK2, referred to as the 2CK scheme.

[0082] Figure 15 Please refer to the timing diagram of a shift register unit provided in the embodiments of this disclosure. Figures 13 to 15 .by Figure 15Taking stages T1 to T4 as an example, in stage T1, the STV and CK signals are at a high level, and the XCK signal is at a low level; in stage T2, the STV and CK signals are at a low level, and the XCK signal is at a high level; in stage T3, the STV and XCK signals are at a low level, and the CK signal is at a high level; in stage T4, the STV and CK signals are at a low level, and the XCK signal is at a high level.

[0083] Taking a single shift register unit as an example, in stage T1, when the STV signal outputs a valid pulse, the first transistor T1 is turned on based on the valid pulse of the CK signal, introducing the high-level STV signal to the third node N3 and pulling up the level of the third node N3. The second transistor T2 and the fifth transistor T5 are turned on under the drive of the high-level signal of the third node N3. The second transistor T2 introduces the high-level signal of the first voltage signal terminal VGH to pull up the voltage of the first node N1, and the fifth transistor T5 introduces the CK signal to the second node N2. Since the CK signal is still in the high-level range at this time, it can drive the fourth transistor T4 to turn on, introducing a high-level signal to the second node N2. Therefore, the first node N1 and the second node N2 maintain a high level simultaneously.

[0084] During stage T2, when the CK signal is low, the low-level signal drives the fourth transistor to turn off. At this time, the fifth transistor can pull the second node N2 low through the CK signal.

[0085] During stage T2, when the XCK signal transitions to a high level, since the first node N1 is a high level signal, the conducting sixth transistor T6 can introduce the high level signal into the scan signal output terminal OUT[n]. At this time, the voltage at one end of the first capacitor C1 transitions from the low level signal VGL to the high level signal XCK. The first capacitor C1 will pull up the voltage of the first node N1 through bootstrap boost coupling, further raising the high level signal of the first node N1.

[0086] When the high-level signal of the first node N1 is higher than the high-level signal of XCK, the sixth transistor T6 satisfies the condition that the gate-source voltage difference is greater than the conduction threshold, allowing the sixth transistor T6 to maintain stable conduction. Therefore, during the period when XCK maintains a high-level signal, the scan signal output terminal OUT[n] can output a high-level effective pulse as the scan signal.

[0087] During phase T3, when the XCK signal transitions to a low level, the scan signal output terminal OUT[n] outputs a low level signal, and the first capacitor C1 pulls the voltage of the first node N1 down to its original high level.

[0088] During stage T3, when the CK signal transitions to a high level, the first transistor T1 turns on, and the introduced STV / IN signal becomes a low level, thus pulling the third node N3 low. Simultaneously, the fourth transistor T4 turns on, pulling the second node N2 high.

[0089] During the T3 stage, when the CK signal is a high-level signal, the scan signal output terminal OUT[n+1] of the next-level shift register unit 10 outputs a high-level valid pulse. This valid pulse can drive the third transistor T3 to turn on, pulling the first node N1 low.

[0090] During stage T4, the CK signal is low, and the fourth transistor T4 is cut off under the control of the CK signal; the third node N3 is low, and the fifth transistor T5 is cut off under the control of the third node N3. The first node N1 is low, and the sixth transistor T6 is cut off; the second node N2 is high, and the seventh transistor T7 is turned on under the control of the second node N2, and the scan signal output terminal OUT[n] outputs a low-level signal.

[0091] The following embodiments are based on a gate drive circuit 100 including a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3, and a fourth clock signal line CK4, such as... Figure 16 As shown, this is referred to as the 4CK scheme. The 4CK scheme differs from the 2CK scheme in the connection relationships of some transistors; please refer to the following explanation for details.

[0092] Figure 16 This is a schematic diagram of another circuit structure for the gate drive circuit provided in an embodiment of this disclosure. Figure 17 For another schematic diagram of the shift register unit in the gate drive circuit provided in the embodiments of this disclosure, please refer to... Figures 16 to 17 In some embodiments, the first node pull-down module 112 may include a third transistor T3. The first terminal of the third transistor T3 is connected to the second voltage signal terminal VGL, and the second terminal of the third transistor T3 may be connected to the first node N1. In the 4CK scheme, the first gate of the third transistor T3 may be connected to the third clock signal terminal CKC. The first clock signal terminal CKA, the second clock signal terminal CKB, and the third clock signal terminal CKC are respectively connected to three of the four clock signal lines. For example... Figure 16 As shown in VSR i, the first clock signal terminal CKA can be connected to the fourth clock signal line CK4, the second clock signal terminal CKB can be connected to the first clock signal line CK1, and the third clock signal terminal CKC can be connected to the second clock signal line CK2.

[0093] The first node pull-down module 112 needs to pull the signal of the first node N1 low as soon as the current shift register unit 10 completes the output of the valid scan signal. In the 2CK scheme, since the current shift register unit 10 has already completed the output of the high-level signal when the next-stage shift register unit 10 outputs the high-level signal, the high-level signal output by the next-stage shift register unit 10 can be used as the control signal of the first node pull-down module 112, thereby pulling the signal of the first node N1 low in a timely manner.

[0094] In the 4CK scheme of this embodiment, since the effective pulse of the clock signal received by the third clock signal terminal CKC follows the effective pulse of the clock signal received by the second clock signal terminal CKB, it can also be determined that the current shift register unit 10 has completed the output of a high-level signal when the third clock signal terminal CKC receives the effective pulse of the clock signal. Therefore, the effective pulse of the clock signal received by the third clock signal terminal CKC can also be used as the control signal of the first node pull-down module 112, thereby timely pulling down the signal of the first node N1. Compared with the above 2CK scheme, which introduces the output signal of the next-level shift register unit 10 as the control signal of the first node pull-down module 112, this embodiment introduces the clock signal received by the third clock signal terminal CKC as the control signal of the first node pull-down module 112, which can reduce the signal traces between different shift register units 10, reduce trace interference between different shift register units 10, and improve the output stability of the shift register unit 10.

[0095] Please continue to refer to Figure 17 In some embodiments, the second node pull-up module 121 described above may include a fourth transistor T4. The first terminal of the fourth transistor T4 is connected to the first voltage signal terminal VGH, the second terminal is connected to the second node N2, and the first gate is connected to the third clock signal terminal CKC. The second gate of the fourth transistor T4 is connected to the second voltage signal terminal VGL, or the second gate of the fourth transistor T4 is connected to the second terminal of the fourth transistor T4.

[0096] The second node pull-up module 121 needs to pull the signal of the second node N2 high as soon as possible after the current shift register unit 10 completes the output of the valid signal of the scan signal.

[0097] Please refer to Figures 13 to 14 In the 2CK scheme, since the two clock signal lines alternately output valid pulses of the clock signal, after the second clock signal terminal XCK outputs a valid pulse of the clock signal, it can be considered that the current shift register unit 10 has completed the output of a high-level signal. Therefore, the valid pulse of the clock signal output from the first clock signal terminal CK can be used as the control signal for the second node pull-up module 121.

[0098] However, in the 4CK scheme of this embodiment, after the second clock signal terminal CKB outputs a valid pulse, the first clock signal terminal CKA does not continue to output a valid pulse; instead, the third clock signal terminal CKC outputs a valid pulse. If the same control method as in the 2CK scheme is used, and the valid pulse of the clock signal output by the first clock signal terminal CKA is used as the control signal for the second node pull-up module 121, then the second node pull-up module 121 needs to receive the valid pulse of the clock signal output by the first clock signal terminal CKA after the second clock signal terminal CKB outputs a valid pulse, with an interval of two valid pulses. The second node pull-up module 121 will turn on later, resulting in the second node N2 in the 4CK scheme being pulled high later. Therefore, in this embodiment, in order to pull the signal of the second node N2 high as quickly as possible, the third clock signal terminal CKC can be connected to the first gate of the fourth transistor T4, and the valid pulse of the clock signal output by the third clock signal terminal CKC can be used as the control signal for the second node pull-up module 121.

[0099] Compared to the above 4CK scheme, which uses the effective pulse of the clock signal received by the first clock signal terminal CKA as the control signal of the second node pull-up module 121, the 4CK scheme in this embodiment uses the clock signal received by the third clock signal terminal CKC as the control signal of the second node pull-up module 121. This allows the signal of the second node N2 to be pulled high earlier, so that the seventh transistor T7 can enter the conduction state earlier, thereby stably outputting a low-level signal through the scan signal output terminal OUT.

[0100] Understandably, in both the 2CK and 4CK schemes, the fourth transistor T4 has a longer conduction time and is more susceptible to PBTS. Therefore, in the 4CK scheme, the second gate of the fourth transistor T4 can be connected to either the second voltage signal terminal VGL or the first terminal of the fourth transistor T4.

[0101] Please continue to refer to Figure 17 In some embodiments, the second node pull-down module 122 described above may include a fifth transistor T5. The first terminal of the fifth transistor T5 is connected to the third clock signal terminal CKC, the second terminal is connected to the second node N2, the first gate is connected to the third node N3, and the second gate is connected to the third node N3.

[0102] In the 2CK scheme, the signal introduced by the second node pull-down module 122 to pull the node level low by the second node N2 can be the same signal as the control signal of the second node pull-up module 121. Therefore, in the 4CK scheme, if the first gate of the fourth transistor T4 in the second node pull-up module 121 is changed to be connected to the third clock signal terminal CKC, then the first gate of the fifth transistor T5 in the second node pull-down module 122 can also be changed to be connected to the third clock signal terminal CKC. Furthermore, regardless of whether it is the 2CK or 4CK scheme, the PBTS effect on the fifth transistor T5 will not change. Therefore, the second gate of the fifth transistor T5 can be directly connected to the first gate and receive the same control signal.

[0103] Figure 18 For another schematic diagram of the shift register unit in the gate drive circuit provided in the embodiments of this disclosure, please refer to... Figure 18 In some embodiments, the shift register unit 10 may further include a third node pull-down module 113. The third node pull-down module 113 may include a twelfth transistor T12.

[0104] The first terminal of the twelfth transistor T12 is connected to the second voltage signal terminal VGL, the second terminal of the twelfth transistor T12 is connected to the third node N3, and the first gate of the twelfth transistor T12 is connected to the third clock signal terminal CKC.

[0105] In the 4CK scheme, the control signal received by the first gate of the first transistor T1 is the clock signal introduced by the first clock signal terminal CKA. After the first transistor T1 is turned on based on the valid pulse of the clock signal introduced by the first clock signal terminal CKA, and introduces the high-level signal provided by the stage transfer signal input terminal STV / IN to the third node N3, the signal of the third node N3 needs to be pulled low in time after the valid signal pulse of the scan signal output by the current shift register unit 10. If the twelfth transistor T12 is not added, after the other three clock signal lines in the 4CK scheme provide valid pulses of the clock signal in sequence, the first clock signal terminal CKA will provide the next valid pulse. At this time, the first transistor T1 turns on in response to the valid pulse, and introduces the low-level signal provided by the stage transfer signal input terminal STV / IN to the third node N3 to pull down the signal of the third node N3. That is, after the first transistor T1 introduces the high-level signal provided by the stage transfer signal input terminal STV / IN to pull up the signal of the third node N3, it is necessary to wait for three valid pulses of the clock signal to pull down the signal of the third node N3.

[0106] In this embodiment, with the addition of the twelfth transistor T12, when a valid pulse of the clock signal is provided at the first clock signal terminal, the first transistor T1 turns on, introducing a high-level signal from the cascade signal input terminal STV / IN to pull the signal of the third node N3 high; when a valid pulse of the clock signal is provided at the third clock signal terminal, the twelfth transistor T12 turns on, introducing a second voltage signal to pull the signal of the third node N3 low. Compared with the above implementation, only a single valid pulse of the clock signal provided at the second clock signal terminal CKB is needed to pull the signal of the third node N3 low. That is, this embodiment can pull the signal of the third node N3 low earlier, so that the transistor that uses the third node N3 as a control signal can be turned off as early as possible.

[0107] Please refer to Figure 16 In the above embodiments, the gate driving circuit 100 may include a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3 and a fourth clock signal line CK4. The clock signals output by the first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3 and the fourth clock signal line CK4 are four-phase interleaved clock signals.

[0108] In a plurality of adjacent shift register units 10, i is a positive integer. The first clock signal terminal CKA of the (i+1)th shift register unit 10 and the second clock signal terminal CKB of the ith shift register unit 10 are connected to the first clock signal line CK1; the second clock signal terminal CKB of the (i+1)th shift register unit 10 and the third clock signal terminal CKC of the ith shift register unit 10 are connected to the second clock signal line CK2; the third clock signal terminal CKC of the (i+1)th shift register unit 10 and the second clock signal terminal CKB of the (i+2)th shift register unit 10 are connected to the third clock signal line CK3; and the third clock signal terminal CKC of the (i+2)th shift register unit 10 and the first clock signal terminal CKA of the ith shift register unit 10 are connected to the fourth clock signal line CK4.

[0109] In this embodiment, by connecting the four clock signal lines to each shift register unit 10 through the above-described implementation method, a single shift register unit 10 can receive effective pulses of three adjacent clock signals, thereby realizing the output of the scan signal of the shift register unit 10 through the effective pulses of the three clock signals.

[0110] By comparing the 2CK and 4CK schemes, it can be seen that for the same number of shift register units 10, the 2CK scheme uses two clock signal lines for load driving, while the 4CK scheme uses four clock signal lines. Therefore, in the 4CK scheme, the load on a single clock signal line is significantly reduced compared to the 2CK scheme, and the parasitic capacitance on a single clock signal line is also significantly reduced, effectively reducing the dynamic switching power consumption of a single clock signal line, and ultimately reducing the overall power consumption of all clock signal lines.

[0111] Figure 19 For another schematic diagram of the shift register unit in the gate drive circuit provided in the embodiments of this disclosure, please refer to... Figure 19 In the above embodiments, taking the 2CK scheme as an example, the shift register unit 10 may further include a first voltage regulator module 14, which can be connected to the third node N3. The first voltage regulator module 14 can play a voltage stabilizing role, stabilizing the voltage of the third node N3, so as to prevent the voltage of the third node N3 from exceeding the preset range.

[0112] like Figure 19 As shown, in one optional implementation, the first voltage regulator module 14 may include an eighth transistor T8. The first terminal of the eighth transistor T8 is connected to the third node N3, the second terminal is connected to the first voltage signal terminal VGH, the first gate is connected to the third node N3, and the second gate is connected to the third node N3.

[0113] The first gate of the eighth transistor T8 is connected to the first electrode of the eighth transistor T8. At this time, the eighth transistor T8 is equivalent to a diode whose anode is connected to the third node N3 and whose cathode is connected to the first voltage signal terminal VGH. When the node voltage of the third node N3 is higher than the first voltage signal, the third node N3 can release charge to the first voltage signal terminal VGH, so that the node voltage of the third node N3 is not higher than the first voltage signal of the first voltage signal terminal VGH.

[0114] Understandably, in the above embodiment, when the signal of the first node N1 is high, the sixth transistor T6 is turned on. At this time, the signal received by the first terminal of the sixth transistor T6 changes from low to high, causing the second terminal of the sixth transistor T6, i.e., the scan signal output terminal OUT, to change to a high-level signal. Through the bootstrap boosting effect of the first capacitor, the signal of the first node N1 can be further coupled and pulled high based on the first voltage signal.

[0115] If the voltage at the third node N3 is higher than the first voltage signal, the gate-source voltage difference of the second transistor T2 will increase, causing the second transistor T2 to partially conduct. This will pull down the voltage at the first node N1, which was higher than the first voltage signal, to the first voltage signal, preventing the sixth transistor T6 from conducting stably and affecting the stability of the output scan signal. However, by using the eighth transistor T8, the node voltage at the third node N3 can be prevented from being higher than the first voltage signal, thus preventing the node voltage at the first node N1 from being pulled down and maintaining the stable conduction of the sixth transistor T6.

[0116] Figure 20 For another schematic diagram of the shift register unit in the gate drive circuit provided in this embodiment, please refer to... Figure 20 In some embodiments, taking the 2CK scheme as an example, the output module 13 may include a sixth transistor T6, a seventh transistor T7, a first capacitor, and a second capacitor. The sixth transistor T6 and the seventh transistor T7 are dual-gate oxide transistors.

[0117] The first terminal of the sixth transistor T6 can be connected to the fourth clock signal terminal CK_Buffer, the second terminal is connected to the scan signal output terminal OUT, and the first gate is connected to the first node N1. The first terminal of the seventh transistor T7 is connected to the third voltage signal terminal VGL_Buffer, the second terminal is connected to the scan signal output terminal OUT, and the first gate is connected to the second node N2. A first capacitor is connected between the first terminal and the first gate of the sixth transistor T6, and a second capacitor is connected between the first terminal and the first gate of the seventh transistor T7.

[0118] Please refer to Figure 13 and Figure 20 ,and Figure 13 Compared to the connection relationship of the sixth transistor T6 shown, in this embodiment, the first terminal of the sixth transistor T6 is connected to the fourth clock signal terminal CK_Buffer.

[0119] The fourth clock signal output from the fourth clock signal terminal CK_Buffer and the second clock signal output from the second clock signal terminal XCK are clock signals with the same frequency and phase, but the high and low level potential difference of the second clock signal is different from that of the fourth clock signal.

[0120] In the embodiment where the sixth transistor T6 is connected to the second clock signal terminal XCK, since the high-low level potential difference between the first voltage signal and the second voltage signal is the same as the high-low level potential difference of the first clock signal, when the sixth transistor T6 is turned on, the first gate and the first terminal of the sixth transistor T6 receive the same high-level signal, thereby making the gate-source voltage difference of the sixth transistor T6 less than the turn-on threshold of the oxide transistor. Therefore, by providing a first capacitor, when the scan signal output terminal OUT transitions from a low-level signal to a high-level signal, the bootstrap effect of the first capacitor couples and pulls up the voltage of the first node N1, thereby maintaining the stable conduction of the sixth transistor T6.

[0121] In this embodiment, by setting the high-low level potential difference of the fourth clock signal to be different from that of the first clock signal, the high level of the fourth clock signal can be lower than the high level of the first clock signal, that is, the high level of the fourth clock signal is lower than the first voltage signal at the first voltage signal terminal VGH. At this time, the first gate of the sixth transistor T6 receives the first voltage signal, and the first terminal receives the high level of the fourth clock signal. Since the first voltage signal is greater than the high level of the fourth clock signal, the gate-source voltage difference of the sixth transistor T6 can be greater than the conduction threshold of the oxide transistor. In other words, in this embodiment, since the high-level voltage of the first node N1 under normal conditions is greater than the high-level voltage of the fourth clock signal, even without the first voltage regulator module 14, the gate-source voltage difference of the sixth transistor T6 can still meet the conduction threshold voltage requirement, thereby maintaining the stable conduction of the sixth transistor T6.

[0122] It should be noted that, although the first voltage regulator module 14 can be omitted in the above embodiment, setting the first voltage regulator module 14 can further increase the conduction stability of the sixth transistor T6.

[0123] Please refer to Figure 13 and Figure 20 Compared with the connection relationship of the seventh transistor T7 in the previous embodiment, in this embodiment, the first terminal of the seventh transistor T7 is connected to the third voltage signal terminal VGL_Buffer.

[0124] The third voltage signal terminal VGL_Buffer can output a low-level signal, but the output voltage of the third voltage signal terminal VGL_Buffer is different from the output voltage of the second voltage signal terminal VGL.

[0125] When the output voltages of the second voltage signal terminal VGL and the third voltage signal terminal VGL_Buffer are set to different low levels, when the first node N1 is pulled low, the node voltage of the first node N1 is the second voltage signal, and when the seventh transistor T7 is turned on, the voltage of the scan signal output terminal OUT is the third voltage signal.

[0126] As an optional implementation, the output voltage of the second voltage signal terminal VGL can be set lower than the output voltage of the third voltage signal terminal VGL_Buffer. In this case, the first node N1 receives the lower voltage second voltage signal. Even if the clock signal connected to the first terminal of the sixth transistor T6 jumps upwards, because the seventh transistor T7 is in the on state, and the scan signal output terminal OUT is voltage-coupled to the first node N1 through the first capacitor, the node voltage of the first node N1 will not exceed the third voltage signal. This avoids unnecessary pulse signals being generated by leakage from the first terminal of the sixth transistor T6 to the scan signal output terminal OUT due to the voltage of the first node N1 being coupled up during the scan signal period when the shift register unit 10 does not need to output a scan signal.

[0127] As an optional implementation, the low-level potential of the second clock signal is the same as the output voltage of the second voltage signal terminal VGL, and the output voltage of the third voltage signal terminal VGL_Buffer can be the same as the low-level potential of the fourth clock signal terminal CK_Buffer. In this case, the low-level signal received by the transistors other than the sixth transistor T6 and the seventh transistor T7 is either the low-level potential of the first clock signal or the output voltage of the second voltage signal terminal VGL. Since both voltages are the same, each transistor can receive the same low-level signal.

[0128] The low-level signals received by the sixth transistor T6 and the seventh transistor T7 are the output voltage of the third voltage signal terminal VGL_Buffer and the low-level potential of the fourth clock signal terminal CK_Buffer, respectively. Since the voltages are the same, the output low-level signal can remain consistent regardless of whether the sixth transistor T6 or the seventh transistor T7 is turned on. This avoids the situation where the output voltage of the third voltage signal terminal VGL_Buffer is inconsistent with the low-level potential of the fourth clock signal terminal CK_Buffer, resulting in two different potentials in the low-level signal of the output scan signal.

[0129] In some embodiments, the second gate of the sixth transistor T6 is connected to the first node N1. The second gate of the seventh transistor T7 is connected to the second voltage signal terminal VGL, or the second gate of the seventh transistor T7 is connected to the first terminal of the seventh transistor T7.

[0130] In the above embodiments, the first terminal of the sixth transistor T6 is connected to the fourth clock signal terminal CK_Buffer, and the first terminal of the seventh transistor T7 is connected to the third voltage signal terminal VGL_Buffer. Compared with the aforementioned embodiments, when the sixth transistor T6 is turned on, the magnitude of the signal voltage output at the scan signal output terminal OUT changes; when the seventh transistor T7 is turned on, the magnitude of the signal voltage output at the scan signal output terminal OUT also changes. However, since the sixth transistor T6 still receives the control signal from the first node N1, and the seventh transistor T7 still receives the control signal from the second node N2, the conduction duration of the sixth transistor T6 and the seventh transistor T7 in a single image frame remains unchanged, provided that the control signals received by the sixth transistor T6 and the seventh transistor T7 do not change.

[0131] In a single image frame, the potential of the first node N1 is only pulled high during the row scan cycle corresponding to the shift register unit 10, and remains low during the remaining row scan cycles. This means that the duration of the first node N1 at a low potential in a single image frame is much longer than the duration at a high potential. Since the first node N1 drives the sixth transistor T6 to conduct when it is at a high potential, the conduction time of the sixth transistor T6 in a single image frame is much shorter than its off-time, making it less susceptible to PBTS effects.

[0132] Similarly, since the potential of the second node N2 is only pulled low during the row scan cycle corresponding to the shift register unit 10, and remains high during the remaining row scan cycles, the duration of the second node N2 at a high potential is much longer than the duration at a low potential. The second node N2 can drive the seventh transistor T7 to conduct at a high potential; therefore, the conduction time of the seventh transistor T7 in a single image frame is much longer than its off time, making it susceptible to PBTS (Packet Bit Shift) effects.

[0133] The second gates of the sixth transistor T6 and the seventh transistor T7 can be connected to the same control signal as the first gate, depending on whether they are affected by PBTS. For example, the first and second gates of the sixth transistor can be connected to the first node N1; the second gate of the seventh transistor T7 can be connected to the second voltage signal terminal VGL, or the second gate of the seventh transistor T7 can be connected to the first terminal of the seventh transistor T7.

[0134] In some embodiments, in two adjacent shift register units 10, the scan signal output terminal OUT of the previous shift register unit 10 is connected to the cascade signal input terminal STV / IN of the next shift register unit 10, and the scan signal output terminal OUT of the next shift register unit 10 is connected to the first node pull-down module 112 of the previous shift register unit 10.

[0135] It is understandable that, in the above 4CK scheme, if the above implementation method is adopted, then Figure 18 The driving method shown, in which the third transistor T3 and the twelfth transistor T12 are controlled by the CKC signal, can be changed to drive and control the third transistor T3 and the twelfth transistor T12 by the scan signal output terminal OUT[n+] of the next-stage shift register unit 10. In this case, the third clock signal terminal of a single shift register unit 10 does not need to be set. Therefore, a single shift register unit 10 can be connected to two of the four clock signal lines.

[0136] Figure 21 For another schematic diagram of the shift register unit in the gate drive circuit provided in this embodiment, please refer to... Figure 21 In some embodiments, the shift register unit 10 may further include a second voltage regulator module 15. The second voltage regulator module 15 may be connected to the first node N1, the second node N2, the second clock signal terminal XCK, and the second voltage signal terminal VGL. The second voltage regulator module 15 may be used to stabilize the voltage of the first node N1.

[0137] Figure 22 For another schematic diagram of the shift register unit in the gate drive circuit provided in this embodiment, please refer to... Figure 22 As an example, the second voltage regulator module 15 described above may include a ninth transistor T9 and a tenth transistor T10. The ninth transistor T9 and the tenth transistor T10 may be dual-gate oxide transistors.

[0138] The first terminal of the ninth transistor T9 is connected to the second voltage signal terminal VGL, the second terminal is connected to the fourth node N4, and the first gate is connected to the second node N2. The first terminal of the tenth transistor T10 is connected to the fourth node N4, the second terminal is connected to the first node N1, and the first gate is connected to the second clock signal terminal XCK.

[0139] The ninth transistor T9 can be turned on or off under the signal control of the second node N2. When the ninth transistor T9 is on, the output signal of the second voltage signal terminal VGL can be introduced to the fourth node N4. When the ninth transistor T9 is off, the second voltage signal terminal VGL is disconnected from the fourth node N4.

[0140] The tenth transistor T10 can be turned on or off under the control of the second clock signal XCK. When the tenth transistor T10 is on, the signal of the fourth node N4 can be introduced to the first potential. When the tenth transistor T10 is off, the fourth node N4 is disconnected from the first node N1.

[0141] When the shift register unit 10 does not output a valid scan signal, the first node N1 is low, and the sixth transistor T6 is off; the second node N2 is high, and the seventh transistor T7 is on. The high-level signal of the second node N2 controls the ninth transistor T9 to turn on, pulling the fourth node N4 low. When the second clock signal terminal XCK outputs a high-level pulse signal, the tenth transistor T10 turns on. At this time, the on-state ninth transistor T9 and tenth transistor T10 can stably pull the first node N1 low, thereby preventing the sixth transistor T6 from being mis-turned on and causing the shift register unit 10 to output an erroneous scan signal.

[0142] Please continue to refer to Figure 22 In some embodiments, the second gate of the ninth transistor T9 is connected to the second voltage signal terminal VGL, or the second gate of the ninth transistor T9 is connected to the first terminal of the ninth transistor T9.

[0143] The second gate of the tenth transistor T10 is connected to the second voltage signal terminal VGL, or the second gate of the tenth transistor T10 is connected to the first terminal of the tenth transistor T10.

[0144] The control signal received by the ninth transistor T9 is the signal from the second node N2. Since the second node N2 maintains a high level signal when the shift register unit 10 is not outputting a valid pulse of the scan signal, the conduction time of the ninth transistor T9 is relatively long, making it susceptible to PBTS (Power Shift Switching). Therefore, for the same reason as the first transistor T1 described above, the second gate of the ninth transistor T9 can be connected to the second voltage signal terminal VGL or the first terminal of the ninth transistor T9.

[0145] Accordingly, the control signal received by the tenth transistor T10 is the signal from the second clock signal terminal XCK. Since the duty cycle of the high-level signal output from the second clock signal terminal XCK is approximately 50%, the on-time of the tenth transistor T10 is relatively high, making it susceptible to PBTS (Power Buffer Switching). Therefore, for the same reason as with the first transistor T1, the second gate of the tenth transistor T10 can be connected to either the second voltage signal terminal VGL or the first terminal of the tenth transistor T10.

[0146] Figure 23 This is another timing diagram of the shift register unit provided in the embodiments of this disclosure. In the 4CK scheme, please refer to the diagram as well. Figure 16 , Figure 18 as well as Figure 23 ,Will Figure 15 The timing diagram of the 2CK scheme shown is... Figure 23 The timing diagrams of the 4CK scheme are shown for comparison.

[0147] by Figure 23Taking stages T1 to T4 as an example, in stage T1, the STV signal and the CK4 signal are at a high level; in stage T2, the CK1 signal is at a high level; in stage T3, the CK2 signal is at a high level; and in stage T4, the CK3 signal is at a high level.

[0148] by Figure 16 Taking the shift register unit VSR i as an example, the first clock signal terminal CKA can be connected to the fourth clock signal line CK4, the second clock signal terminal CKB can be connected to the first clock signal line CK1, and the third clock signal terminal CKC can be connected to the second clock signal line CK2.

[0149] In phase T1, both the STV and CK4 signals are high-level signals. This means the first clock signal terminal CKA receives a high-level signal, driving the first transistor T1 to turn on and introduce the high-level STV signal to the third node N3, pulling up the level of N3. The second transistor T2 and the fifth transistor T5 are also turned on under the high-level signal from the third node N3. The second transistor T2 introduces a high-level signal from the first voltage signal terminal VGH, pulling up the voltage of the first node N1. The fifth transistor T5 introduces the CKC signal to the second node N2, pulling it low. Since the CKC signal is low at this time, the fourth transistor T4 is turned off under the control of the low-level signal. Therefore, in phase T1, the first node N1 and the third node N3 are high-level, and the second node N2 is low-level.

[0150] During stage T2, the CK1 signal is high, meaning the second clock signal terminal CKB receives a high-level signal. Since the first node N1 is high, it drives the sixth transistor T6 to conduct, introducing the high-level signal from the second clock signal terminal CKB to the scan signal output terminal OUT[n]. At this time, the voltage at one end of the first capacitor C1 jumps from a low-level signal VGL to a high-level signal from the second clock signal terminal CKB. The first capacitor C1 will then pull up the voltage of the first node N1 through bootstrap coupling, further increasing the high-level signal of the first node N1. When the high-level signal of the first node N1 is higher than the high-level signal of the second clock signal terminal CKB, the sixth transistor T6 satisfies the condition that the gate-source voltage difference is greater than the conduction threshold, allowing the sixth transistor T6 to maintain stable conduction. Therefore, within the range where the second clock signal terminal CKB maintains a high-level signal, the scan signal output terminal OUT[n] can output a high-level effective pulse as the scan signal.

[0151] During phase T3, the CK2 signal is high, meaning the third clock signal terminal CKC receives a high-level signal. The third transistor T3, the fourth transistor T4, and the twelfth transistor T12 are turned on under the high-level signal at the third clock signal terminal CKC. The third transistor T3 pulls the first node N1 low, the fourth transistor T4 pulls the second node N2 high, and the twelfth transistor pulls the third node N3 low. Therefore, during phase T3, the first node N1 and the third node N3 are low, and the second node N2 is low.

[0152] During stage T4, the CK3 signal is a high-level signal. Since the shift register unit VSR i is not connected to the CK3 signal, the level of each node is the same as that in stage T3 during stage T4 and does not change.

[0153] Will Figure 15 and Figure 23 By comparing the potentials of the first node N1, the second node N2, and the third node N3 in each stage, we can see that in stages T2 to T4, Figure 15 and Figure 23 The potential of each node remains consistent. The difference lies in... Figure 15 In the T1 phase shown, the second node N2 is at a high level; while Figure 23 In the T1 phase shown, the second node N2 is at a low level.

[0154] exist Figure 16 , 18 In the 4CK scheme shown in Figure 23, during stage T1, the second clock signal line CK2 connected to the third clock signal terminal CKC provides a low-level signal. At this time, the fifth transistor T5 is turned on, introducing the low-level signal of the third clock signal terminal CKC to the second node N2; while the fourth transistor T4 is turned off under the low-level signal, causing the VGH signal to be disconnected from the second node N2. Therefore, in Figure 23 In the T1 stage of the timing diagram shown, the second node N2 is pulled low to a low level signal. That is, in the 4CK scheme, the second node N2 is pulled low to a low level earlier.

[0155] Figure 24 For another schematic diagram of the shift register unit in the gate drive circuit provided in the embodiments of this disclosure, please refer to... Figure 24 In some embodiments, the shift register unit 10 may further include a reset module 16, which may be connected to the second node N2.

[0156] Because the effective pulse of the scan signal output by shift register unit 10 accounts for a small proportion of the time, shift register unit 10 outputs a low-level signal most of the time. Therefore, for most of the time, in order to drive the seventh transistor T7 to conduct, the signal of the second node N2 is a high-level signal. At this time, during the normal power-down process of the display panel, due to the small leakage current characteristic of oxide transistors, the charge accumulated on the second node N2 cannot be discharged. At this time, the charge on the second node N2 can be discharged by the reset module 16, thereby resetting the voltage of the second node N2 to a low level.

[0157] As an optional implementation, the reset module 16 may include an eleventh transistor T11. The first terminal of the eleventh transistor T11 is connected to the second voltage signal terminal VGL, the second terminal is connected to the second node N2, and the first gate is connected to the reset signal terminal. Alternatively, the second gate of the eleventh transistor T11 may be connected to the second voltage signal terminal VGL, or the second gate of the eleventh transistor T11 may be connected to the first terminal of the eleventh transistor T11.

[0158] The eleventh transistor T11 can be turned on or off under the control of the reset signal. When the eleventh transistor T11 is on, the second voltage signal terminal VGL is connected to the second node N2, which can discharge the charge accumulated in the second node N2. When the eleventh transistor T11 is on, the second voltage signal terminal VGL is disconnected from the second node N2.

[0159] Understandably, when the display panel is operating normally, the reset signal terminal remains at a low level, and the eleventh transistor T11 is turned off. When the display panel is powered off, the reset signal terminal provides a brief high-level signal, causing the eleventh transistor T11 to conduct, thereby discharging the charge at the second node N2.

[0160] In some embodiments, the oxide transistor described above may be an indium gallium zinc oxide transistor.

[0161] As an optional implementation method, such as Figure 14 or Figure 16 As shown, in the multiple shift register units 10, the stage transfer signal input terminal STV / IN of the first stage shift register unit 10 is connected to the start signal line STV, and the stage transfer signal input terminal STV / IN of the nth shift register unit 10 is connected to the scan signal output terminal OUT of the (n-1)th shift register unit 10; where n is a positive integer and n≥2.

[0162] Understandably, the stage pass signal input terminal STV / IN of the first-stage shift register unit 10 is connected to the start signal line STV, directly receiving the start signal as the trigger signal. Subsequent shift register units 10 receive the valid signal of the scan signal output from the previous stage as the trigger signal.

[0163] Based on the same inventive concept, this disclosure provides a display panel, please refer to... Figure 3 The display panel 200 includes the gate driving circuit 100 provided in any embodiment of this disclosure. It should be noted that the specific implementation of the display panel 200 can be referred to the implementation of the gate driving circuit 100 provided in this disclosure, and the repeated parts will not be described again in this disclosure.

[0164] Based on the same inventive concept, this disclosure provides a display device. Figure 25 The diagram shown is a schematic representation of a display device provided in an embodiment of this disclosure. Please refer to it. Figure 25 The display device 300 includes a display panel 200. The display device 300 provided in this embodiment can be any electronic device with display function, such as a touch screen, mobile phone, tablet computer, laptop computer, e-reader, or television. The display device 300 provided in this embodiment has the beneficial effects of the display panel 200 provided in this embodiment; for details, please refer to the specific descriptions of the display panel 200 in the above embodiments, which will not be repeated here.

[0165] Understandable Figure 25 The rounded rectangle structure is used as an example to illustrate one shape of the display device 300. In some other embodiments of this disclosure, the display device 300 may also be circular, elliptical or any other feasible shape, and this disclosure does not specifically limit it.

[0166] As can be seen from the above embodiments, the gate driving circuit, display panel, and display device provided in this disclosure achieve at least the following beneficial effects: This disclosure provides a gate driving circuit, a display panel, and a display device. The gate driving circuit includes cascaded shift register units. Each shift register unit controls the signal of a first node through a first node pull-up module and a first node pull-down module. A second node pull-up module and a second node pull-down module control the signal of a second node. An output module outputs a gate driving signal based on the signals of the first and second nodes through a drive signal output terminal. In this disclosure, the transistors used in the shift register units are turned on or off under the control of a non-constant voltage signal. This helps avoid the transistors being in a constantly conducting state, shortening the time the transistors are subjected to positive bias temperature stress. Therefore, it helps reduce the offset of the transistor's threshold voltage, thereby improving the problem of insufficient driving capability caused by excessive forward bias of the threshold voltage. Simultaneously, this disclosure also includes a voltage regulator module in the shift register unit. When the voltage of the third node is coupled up, the voltage regulator module releases part of the voltage, thereby preventing the voltage of the first node, which was originally higher than the first voltage signal, from being reduced to the first voltage signal. This stabilizes the output module's stable state. Therefore, this disclosure helps improve the reliability of the gate driving circuit, thereby improving the display effect of the display product.

[0167] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0168] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A gate driving circuit, characterized in that, include: A plurality of cascaded shift register units are provided. Each shift register unit includes a first node control module, a second node control module, an output module, and a first voltage signal terminal. The first node control module, the second node control module, and the output module each include a plurality of transistors. At least some of the transistors are oxide transistors, and some of the oxide transistors are dual-gate oxide transistors. A subset of the dual-gate oxide transistors receive the same control signal at both gates, while another subset receives two different control signals at each gate. The control signal received by the gate of the oxide transistor is different from the first voltage signal output from the first voltage signal terminal. The first voltage signal is a constant voltage signal. The first node control module is connected to the first node, the second node control module is connected to the second node, and the output module is connected to the first node, the second node, and the scan signal output terminal.

2. The gate driving circuit according to claim 1, characterized in that, The first node control module further includes a third node (N1), which is connected to the first node through at least one transistor of the first node control module, and is connected to the second node through at least one transistor of the second node control module. The first node control module is connected to the cascade signal input terminal (STV / IN), the first clock signal terminal (CK), the first voltage signal terminal (VGH), the second voltage signal terminal (VGL), the scan signal output terminal (OUTn+1) of the next-stage shift register unit, and the first node. The second node control module is connected to the third node, the first clock signal terminal, the first voltage signal terminal, and the second node.

3. The gate driving circuit according to claim 2, characterized in that, The shift register unit further includes a first voltage regulator module, which is connected to the third node.

4. The gate driving circuit according to claim 3, characterized in that, The first node control module includes a first node pull-up module and a first node pull-down module; The first node pull-up module is connected to the cascade signal input terminal, the first clock signal terminal, the first voltage signal terminal, and the first node; The first node pull-down module is connected to the scan signal output terminal of the next-level shift register unit, the second voltage signal terminal, and the first node.

5. The gate driving circuit according to claim 3, characterized in that, The first node pull-up module includes a first transistor (T8) and a second transistor (T1), wherein the first transistor and the second transistor are dual-gate oxide transistors; The first terminal of the first transistor is connected to the stage signal input terminal, the second terminal is connected to the third node, and the first gate is connected to the first clock signal terminal. The first terminal of the second transistor is connected to the first voltage signal terminal, the second terminal is connected to the first node, and the first gate is connected to the third node.

6. The gate driving circuit according to claim 5, characterized in that, The second gate of the first transistor is connected to the second voltage signal terminal, or the second gate of the first transistor is connected to the first terminal of the first transistor; The second gate of the second transistor is connected to the first gate of the second transistor.

7. The gate driving circuit according to claim 4, characterized in that, The first node pull-down module includes a third transistor (T2); The first terminal of the third transistor is connected to the second voltage signal terminal, the second terminal of the third transistor is connected to the first node, and the first gate and the second gate of the third transistor are both connected to the scan signal output terminal of the next-stage shift register unit.

8. The gate driving circuit according to claim 3, characterized in that, The second node control module includes a second node pull-up module and a second node pull-down module; The second node pull-up module is connected to the first clock signal terminal, the first voltage signal terminal, and the second node; The second node pull-down module is connected to the third node, the first clock signal terminal, and the second node.

9. The gate driving circuit according to claim 8, characterized in that, The second node pull-up module includes a fourth transistor (T5); The first terminal of the fourth transistor is connected to the first voltage signal terminal, the second terminal is connected to the second node, and the first gate is connected to the first clock signal terminal. The second gate of the fourth transistor is connected to the second voltage signal terminal, or the second gate of the fourth transistor is connected to the second terminal of the fourth transistor.

10. The gate driving circuit according to claim 8, characterized in that, The second node pull-down module includes a fifth transistor (T10). The first terminal of the fifth transistor is connected to the first clock signal terminal, the second terminal is connected to the second node, the first gate is connected to the third node, and the second gate is connected to the third node.

11. The gate driving circuit according to claim 3, characterized in that, The output module includes a sixth transistor (T6), a seventh transistor (T7), a first capacitor (C1), and a second capacitor (C2). The sixth transistor and the seventh transistor are dual-gate oxide transistors. The first terminal of the sixth transistor is connected to the second clock signal terminal, the second terminal is connected to the scan signal output terminal, and the first gate is connected to the first node. The first terminal of the seventh transistor is connected to the second voltage signal terminal, the second terminal is connected to the scan signal output terminal, and the first gate is connected to the second node. The first capacitor is connected between the second terminal and the first gate of the sixth transistor, and the second capacitor is connected between the first terminal and the first gate of the seventh transistor.

12. The gate driving circuit according to claim 11, characterized in that, The second gate of the sixth transistor is connected to the first node; The second gate of the seventh transistor is connected to the second voltage signal terminal, or the second gate of the seventh transistor is connected to the first terminal of the seventh transistor.

13. The gate driving circuit according to claim 11 or 12, characterized in that, The gate driving circuit further includes a first clock signal line and a second clock signal line, wherein the clock signal output by the first clock signal line and the clock signal output by the second clock signal line are complementary clock signals from the same source. In two adjacent shift register units, the first clock signal terminal of one shift register unit is connected to the first clock signal line, and the second clock signal terminal is connected to the second clock signal line; the first clock signal terminal of the other shift register unit is connected to the second clock signal line, and the second clock signal terminal is connected to the first clock signal line.

14. The gate driving circuit according to claim 4, characterized in that, The first node pull-down module includes a third transistor (T2); The first terminal of the third transistor is connected to the second voltage signal terminal, the second terminal of the third transistor is connected to the first node, and the first gate of the third transistor is connected to the third clock signal terminal. The second gate of the third transistor is connected to the second voltage signal terminal, or the second gate of the third transistor is connected to the first terminal of the third transistor.

15. The gate driving circuit according to claim 8, characterized in that, The second node pull-up module includes a fourth transistor (T5); The first terminal of the fourth transistor is connected to the first voltage signal terminal, the second terminal is connected to the second node, and the first gate is connected to the third clock signal terminal. The second gate of the fourth transistor is connected to the second voltage signal terminal, or the second gate of the fourth transistor is connected to the second terminal of the fourth transistor.

16. The gate driving circuit according to claim 8, characterized in that, The second node pull-down module includes a fifth transistor (T10). The first terminal of the fifth transistor is connected to the third clock signal terminal, the second terminal is connected to the second node, the first gate is connected to the third node, and the second gate is connected to the third node.

17. The gate driving circuit according to claim 14, characterized in that, The shift register unit also includes a third node pull-down module, which includes a twelfth transistor (T12). The first terminal of the twelfth transistor is connected to the second voltage signal terminal, the second terminal of the twelfth transistor is connected to the third node, and the first gate of the twelfth transistor is connected to the third clock signal terminal.

18. The gate driving circuit according to any one of claims 14-17, characterized in that, The gate driving circuit further includes a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line. The clock signals output by the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line are four-phase interleaved clock signals. In a plurality of adjacent shift register units, the first clock signal terminal (CKA) of the (i+1)th shift register unit and the second clock signal terminal (CKB) of the ith shift register unit are connected to the first clock signal line (CK1); the second clock signal terminal of the (i+1)th shift register unit and the third clock signal terminal (CKC) of the ith shift register unit are connected to the second clock signal line (CK2); the third clock signal terminal of the (i+1)th shift register unit and the second clock signal terminal of the (i+2)th shift register unit are connected to the third clock signal line (CK3); the third clock signal terminal of the (i+2)th shift register unit and the first clock signal terminal of the ith shift register unit are connected to the fourth clock signal line (CK4); where i is a positive integer.

19. The gate driving circuit according to claim 2, characterized in that, The output module includes a sixth transistor (T6), a seventh transistor (T7), a first capacitor (C1), and a second capacitor (C2). The sixth transistor and the seventh transistor are dual-gate oxide transistors. The first terminal of the sixth transistor is connected to the fourth clock signal terminal (CK_Buffer), the second terminal is connected to the scan signal output terminal, and the first gate is connected to the first node; The first terminal of the seventh transistor is connected to the third voltage signal terminal (VGL_Buffer), the second terminal is connected to the scan signal output terminal, and the first gate is connected to the second node; The first capacitor is connected between the second terminal and the first gate of the sixth transistor, and the second capacitor is connected between the first terminal and the first gate of the seventh transistor; wherein... The second clock signal terminal outputs a second clock signal, and the fourth clock signal terminal outputs a fourth clock signal. The second clock signal and the fourth clock signal are clock signals with the same frequency and phase. The high and low level potential difference of the second clock signal is different from that of the fourth clock signal. The output voltage of the second voltage signal terminal is different from the output voltage of the third voltage signal terminal.

20. The gate driving circuit according to claim 19, characterized in that, The second gate of the sixth transistor is connected to the first node; The second gate of the seventh transistor is connected to the second voltage signal terminal, or the second gate of the seventh transistor is connected to the first terminal of the seventh transistor.

21. The gate driving circuit according to claim 20, characterized in that, The output voltage of the second voltage signal terminal is less than the output voltage of the third voltage signal terminal; The low-level potential of the second clock signal is the same as the output voltage of the second voltage signal terminal, and the low-level potential of the fourth clock signal is the same as the output voltage of the third voltage signal terminal.

22. The gate driving circuit according to claim 4, characterized in that, In two adjacent shift register units, the scan signal output terminal of the previous shift register unit is connected to the cascade signal input terminal of the next shift register unit, and the scan signal output terminal of the next shift register unit is connected to the first node pull-down module of the previous shift register unit.

23. The gate driving circuit according to claim 3, characterized in that, The first voltage regulator module includes an eighth transistor (T9); The first terminal of the eighth transistor is connected to the third node, the second terminal is connected to the first voltage signal terminal, the first gate is connected to the third node, and the second gate is connected to the third node.

24. The gate driving circuit according to claim 1, characterized in that, The shift register unit also includes a second voltage regulator module; The second voltage regulator module is connected to the first node, the second node, the second clock signal terminal, and the second voltage signal terminal.

25. The gate driving circuit according to claim 24, characterized in that, The second voltage regulator module includes a ninth transistor (T3) and a tenth transistor (T4), wherein the ninth transistor and the tenth transistor are dual-gate oxide transistors; The first terminal of the ninth transistor is connected to the second voltage signal terminal, the second terminal is connected to the fourth node (N2), and the first gate is connected to the second node; The first terminal of the tenth transistor is connected to the fourth node, the second terminal is connected to the first node, and the first gate is connected to the second clock signal terminal.

26. The gate driving circuit according to claim 25, characterized in that, The second gate of the ninth transistor is connected to the second voltage signal terminal, or the second gate of the ninth transistor is connected to the first terminal of the ninth transistor; The second gate of the tenth transistor is connected to the second voltage signal terminal, or the second gate of the tenth transistor is connected to the first terminal of the tenth transistor.

27. The gate driving circuit according to claim 1, characterized in that, The shift register unit also includes a reset module; The reset module is connected to the second node.

28. The gate driving circuit according to claim 27, characterized in that, The reset module includes an eleventh transistor (T11). The first terminal of the eleventh transistor is connected to the second voltage signal terminal, the second terminal is connected to the second node, and the first gate is connected to the reset signal terminal. The second gate of the eleventh transistor is connected to the second voltage signal terminal, or the second gate of the eleventh transistor is connected to the first terminal of the eleventh transistor.

29. The gate driving circuit according to claim 1, characterized in that, The oxide transistor is an indium gallium zinc oxide transistor.

30. The gate driving circuit according to claim 1, characterized in that, In a plurality of shift register units, the stage transfer signal input terminal of the first stage shift register unit is connected to the start signal line, and the stage transfer signal input terminal of the nth shift register unit is connected to the scan signal output terminal of the (n-1)th shift register unit; where n is a positive integer and n≥2.

31. A display panel, characterized in that, Includes the gate drive circuit according to any one of claims 1 to 30.

32. A display device, characterized in that, Includes the display panel as described in claim 31.

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