A driving chip set of a micro LED micro display array

Abstract

The application discloses a kind of driving chip groups of MicroLED micro display array, belong to semiconductor micro display technical field.The driving chip group includes support circuit board, timing control chip;Each chip is vertically bonded with support circuit board by bonding electrode, and realizes signal interconnection between chips by metal trace in support circuit board.Timing control chip receives external video and synchronization signal and generates global timing control signal, the application adopts distributed driving architecture, combines partition path selection logic and digital-analog process separation design, effectively improves the layout flexibility of MicroLED driving chip, reduces chip area, reduces chip design complexity and power loss.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor microdisplay technology, specifically relating to a driving chipset for a MicroLED microdisplay array. Background Technology

[0002] MicroLED (micro-light-emitting diode) display technology is widely considered an ideal choice for next-generation display fields such as AR / VR near-eye displays, automotive micro-projections, and ultra-portable micro-displays due to its superior characteristics, including high brightness, high contrast, fast response speed, ultra-high pixel density (PPI), and long lifespan. As micro-display technology develops towards ultra-high resolution (e.g., 1024×768 and above) and ultra-small pixel pitch (e.g., pixel size and pitch reaching the micrometer level), designing an efficient, low-power, highly uniform, and easily manufactured driving architecture corresponding to high-pixel-density MicroLED micro-display arrays has become a key bottleneck restricting the commercial application of MicroLED micro-display chips.

[0003] Currently, the mainstream display driver solutions fall into two categories: traditional discrete drivers and monolithic integrated drivers. Discrete driver solutions were first applied to traditional LCD flat panel displays by several semiconductor manufacturers in the 1990s. Hitachi pioneered the traditional row and column scanning discrete driver technology for monochrome LCDs in the 1980s. This solution, centered on independent timing control chips, scan driver chips, and column driver chips, allows for the selection of optimized manufacturing processes based on the performance requirements of different functional circuits, enabling independent performance improvements for each module. It has long dominated the low-to-mid-range display market. Monolithic integrated driver solutions were first commercially applied in DLP display technology by Texas Instruments around 2000. Sony applied its fully integrated mixed-signal driver technology to OLED microdisplays around 2010. This solution uses the CMOS chip on the support circuit board as the driving substrate, integrating all functional circuits such as timing control, row and column driving, and grayscale modulation onto a single chip. It eliminates the need for external control chips, resulting in a simple system structure with advantages such as high integration, low signal latency, and high reliability, offering more stable system performance at the same resolution.

[0004] Currently, conventional MicroLED microdisplay array driving solutions mainly employ a monolithic integration approach, fully integrating control logic and driving circuitry onto a single mixed-signal chip. However, when faced with the demands of ultra-high pixel density and high resolution, existing driving solutions reveal the following significant technical shortcomings: 1. Using a single driver chip for scanning drive results in a large driver chip area, which is difficult to adapt to the miniaturization design requirements of micro-display devices. Second, the physical layout and routing of the driver chip are extremely difficult. Dense winding and electrode avoidance can easily lead to signal cross-interference, affecting the purity of the display signal. Third, the integration of digital logic and analog driving circuits into the same chip results in a serious conflict between the requirements of digital and analog processes, leading to high chip manufacturing costs and low yield. Fourth, traditional discrete drivers are mounted on the PCB using SMT technology. Multiple chips are independently packaged, occupying surrounding space and making it difficult to miniaturize the module. At the same time, long electrode traces cause severe line loss (IRDrop), and the pixel driving voltage varies greatly in different areas, ultimately resulting in uneven display brightness.

[0005] In view of this, the present invention proposes a driving chipset for a MicroLED microdisplay array. Summary of the Invention

[0006] The purpose of this invention is to provide a driving chipset for MicroLED microdisplay arrays, so as to solve the technical problems mentioned in the background art, such as the difficulty in laying out MicroLED row and column driving chips, the high cost of chip manufacturing, the lack of flexibility in architecture design, and the serious problem of line loss.

[0007] The technical solution of this invention to solve the aforementioned technical problem is to provide a driving chipset for a MicroLED microdisplay array, including a support circuit board, a timing control chip, two scan driver chips, and two data driver chips. The timing control chip, scan driver chips, and data driver chips are all vertically connected to bonding pads on the support circuit board via bonding electrodes, and signal interconnection between the chips is achieved through metal traces inside the support circuit board. The timing control chip is used to receive external video data, column synchronization signals, and frame synchronization signals, and generate global timing logic and row / column drive control signals. The column synchronization signal is a column reference synchronization pulse signal used to instruct the column-by-column scanning switching timing of pixel units in each column of the MicroLED microdisplay array, and the frame synchronization signal is a full-frame synchronization pulse signal used to indicate the start and end of a complete image display cycle. The two scan driver chips are symmetrically arranged on opposite sides of the MicroLED microdisplay array, used to receive the scan drive control signals from the timing control chip, and respectively drive the pixel units of the corresponding columns in the MicroLED microdisplay array. Two data driver chips are symmetrically arranged on the other opposite sides of the MicroLED microdisplay array. They are used to receive the data drive control signal and grayscale data signal from the timing control chip and drive the pixel units of the corresponding row in the MicroLED microdisplay array respectively.

[0008] As a further improvement to this technical solution, the timing control chip has a built-in row and column address partitioning mapping and path selection logic unit, which is used to control the corresponding scan driver chip and data driver chip to output MicroLED driving signals according to the coordinates of the pixel to be lit.

[0009] As a further improvement to this technical solution, the two scanning driver chips integrate a reference current source, a column scanning control module, and a constant current output module. The reference current source provides a reference current. The column scanning control module consists of a shift register and a level converter, used to generate a column-by-column gating control signal. The constant current output module is connected to the reference current source and the column scanning control module respectively, used to generate a MicroLED constant current driving signal with the reference current as a reference, and outputs driving current to the corresponding column pixel unit of the MicroLED microdisplay array under the control of the column-by-column gating control signal.

[0010] As a further improvement to this technical solution, the two data driver chips incorporate a data cache module, a PWM modulation module, and a level converter. The data cache module includes a shift register, an input register, and a data latch, used to receive and cache grayscale data. The PWM modulation module is connected to the data cache module and includes a reference PWM counter and a comparator, used to generate a PWM control signal with a corresponding duty cycle based on the grayscale data. The level converter is connected to the PWM modulation module and is used to perform level conversion on the PWM control signal and output it to the corresponding row pixel unit of the MicroLED microdisplay array to regulate the luminous grayscale of the pixel unit.

[0011] As a further improvement to this technical solution, the MicroLED microdisplay array is provided with MicroLED bonding electrodes, which are vertically connected to the bonding pads of the supporting circuit board to form MicroLED bonding points; the driver chip is provided with driver chip bonding electrodes on its periphery, which are vertically connected to the bonding pads of the supporting circuit board to form driver chip bonding points.

[0012] As a further improvement to this technical solution, the timing control chip divides the MicroLED microdisplay array into four sub-regions based on the row and column lines at the center of the array: the upper left sub-region is driven by the first data driver chip and the first scan driver chip; the upper right sub-region is driven by the second data driver chip and the first scan driver chip; the lower left sub-region is driven by the first data driver chip and the second scan driver chip; and the lower right sub-region is driven by the second data driver chip and the second scan driver chip.

[0013] As a further improvement to this technical solution, the timing control chip and the data driver chip are manufactured using a first CMOS process, and the scan driver chip is manufactured using a second CMOS process; the digital logic integration density of the first CMOS process is higher than that of the second CMOS process, and the operating voltage of the second CMOS process is higher than that of the first CMOS process.

[0014] As a further improvement to this technical solution, the two scan driver chips have the same geometric dimensions and adopt a bilateral symmetrical scan driver design. The two data driver chips have the same geometric dimensions and adopt a bilateral symmetrical data driver design.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. Effectively reduces the overall area of ​​the driver chip, adapting to the miniaturized design of micro-displays. This invention adopts a bilaterally symmetrical distributed driver architecture, which distributes the full-screen scanning and data driving tasks originally undertaken by a single chip to multiple independent driver sub-modules for collaborative completion. Each driver chip only needs to bear the driving load of its corresponding area, without integrating all driving channels and circuit units. This eliminates the space encroachment of large-size driver chips on the display area, perfectly matching the miniaturization and high integration design requirements of MicroLED micro-display devices.

[0016] 2. Optimize trace layout to reduce signal crosstalk interference. This invention symmetrically positions the data driving submodule and the scan driving submodule on the left, right, top, and bottom opposite sides of the pixel array, and ensures that the row and column electrode traces extend in straight lines. In terms of layout design, it achieves traces without bends and with the shortest length, effectively eliminating signal crosstalk interference caused by dense winding and electrode avoidance, and ensuring signal purity under ultra-high density display.

[0017] 3. Achieving decoupling between digital and analog processes reduces manufacturing costs and improves yield. This invention separates the timing control chip from the driver chipset. The timing control chip uses a highly integrated first CMOS process, while the driver chipset uses a high-voltage second CMOS process. This architecture effectively decouples digital and analog processes, reducing power consumption in high-speed digital processing and avoiding the low yield and soaring costs associated with mixed-signal processes.

[0018] 4. Achieving high-density on-chip integrated packaging, significantly improving brightness uniformity. This invention adopts on-chip flip-chip integrated packaging technology, which greatly reduces the overall size of the module through micron-level vertical bonding; at the same time, combined with a four-zone symmetrical discrete driving architecture and path selection logic, it effectively shortens the pixel driving loop, balances line voltage drop, and significantly improves the brightness uniformity of the entire screen, perfectly adapting to the design requirements of micron-level compact micro-display devices.

[0019] 5. Modular architecture enhances scalability and shortens the R&D cycle. This invention adopts a scalable modular driving architecture. When the pixel array resolution increases, matching can be achieved by increasing the number of driving sub-modules or proportionally increasing the number of channels, without changing the wiring pattern. This design greatly enhances the versatility and reusability of the solution, enabling display products to be rapidly and proportionally expanded according to needs, significantly shortening the R&D cycle and reducing development costs. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the overall structure of the MicroLED microdisplay array driver chipset in a preferred embodiment of the present invention; Figure 2 This is a partial schematic diagram of the MicroLED microdisplay array in a preferred embodiment of the present invention; Figure 3 This is a schematic cross-sectional view of the bonding electrodes of the MicroLED microdisplay array in a preferred embodiment of the present invention; Figure 4 This is a schematic diagram of the passive connection of the MicroLED microdisplay array in a preferred embodiment of the present invention; Figure 5 This is a schematic diagram of the bonding electrode structure of the driver chip in a preferred embodiment of the present invention; Figure 6 This is a block diagram of the internal structure of the timing control chip in a preferred embodiment of the present invention; Figure 7 This is a block diagram of the internal structure of the data driver chip in a preferred embodiment of the present invention; Figure 8 This is a block diagram of the internal structure of the scanning driver chip in a preferred embodiment of the present invention; Figure 9 This is a schematic diagram of the partitioning structure of the MicroLED microdisplay array in a preferred embodiment of the present invention; Figure 10 This is a schematic diagram of the MicroLED pixel constant current PWM driving circuit in a preferred embodiment of the present invention; Figure 11 This is a schematic diagram of the cascaded expansion of the row and column driver chips for the MicroLED microdisplay array in a preferred embodiment of the present invention; Figure 12 This is a flowchart of the method of the present invention.

[0021] The labels in the diagram represent the following: 1-1, Supporting circuit board; 1-2, Timing control chip; 1-3, First data driver chip; 1-4, Second data driver chip; 1-5, First scan driver chip; 1-6, Second scan driver chip; 1-7, MicroLED microdisplay array; 1-8, MicroLED bonding electrode; 1-9, Driver chip bonding electrode. Detailed Implementation

[0022] Specific embodiments of the present invention are given below. These specific embodiments are only used to further illustrate the present invention in detail and do not limit the scope of protection of the present invention.

[0023] Example 1 Please see Figures 1-10 As shown, this embodiment provides a driving chipset for a MicroLED microdisplay array, including a support circuit board 1-1, a timing control chip 1-2, a first data driving chip 1-3, a second data driving chip 1-4, a first scan driving chip 1-5 and a second scan driving chip 1-6, and a MicroLED microdisplay array 1-7 disposed on the support circuit board 1-1.

[0024] The first data driver chip 1-3 is located on the left side of the MicroLED microdisplay array 1-7, and the second data driver chip 1-4 is located on the right side of the MicroLED microdisplay array 1-7, symmetrically arranged. The first scan driver chip 1-5 is located on the upper side of the MicroLED microdisplay array 1-7, and the second scan driver chip 1-6 is located on the lower side of the MicroLED microdisplay array 1-7, symmetrically arranged. The timing control chip 1-2 is located in the corner area of ​​the support circuit board 1-1, and is interconnected with the two data driver chips and the two scan driver chips through metal traces inside the support circuit board 1-1.

[0025] In this embodiment, the size of a single pixel in the monolithic MicroLED microdisplay array 1-7 is 5μm × 5μm, the spacing between each pixel and its adjacent pixels is 2.5μm, and the center-to-center distance between two adjacent pixels (i.e. Figure 2 The pixel pitch is 7.5μm. MicroLED adopts a passive driving design with row common N and column common P. MicroLED bonding electrodes 1-8 are fabricated on the back side of the substrate of the MicroLED microdisplay array 1-7. The row and column scanning electrodes correspond one-to-one with the bonding pads of the support circuit board 1-1 through the MicroLED bonding electrodes 1-8. Electrical connection is achieved through vertical bonding process, and signal interconnection is achieved through the internal metal traces of the support circuit board 1-1.

[0026] All driver chips employ an inverted bonding design with the electrode face down. Driver chip bonding electrodes 1-9 are positioned around the periphery of each driver chip, and these electrodes are perpendicularly connected to bonding pads on the support circuit board 1-1, forming driver chip bonding points. In this embodiment, the dimensions of the MicroLED bonding electrodes 1-8, driver chip bonding electrodes 1-9, and bonding pads on the support circuit board 1-1 are all less than 5μm × 5μm, enabling precise one-to-one correspondence between electrodes and pads, ensuring short and bend-free traces, and effectively reducing line losses. The support circuit board 1-1 uses photolithography to pattern and wire the metal leads externally to the bonding pads. Chips are interconnected through internal metal traces on the support circuit board 1-1. This independent chip interconnection method significantly improves the flexibility of chip layout.

[0027] Timing control chip 1-2, first data driver chip 1-3, and second data driver chip 1-4 are fabricated using a first CMOS process. Their functions are to receive external video source signals and generate timing control signals, and to convert the timing control signals into PWM control signals, respectively. First scan driver chip 1-5 and second scan driver chip 1-6 are fabricated using a second CMOS process and are used to convert the timing control signals into analog drive currents. The digital logic integration density of the first CMOS process is higher than that of the second CMOS process, and the operating voltage of the second CMOS process is higher than that of the first CMOS process. By using a separate fabrication scheme for digital and analog processes, the overall chip manufacturing cost is effectively reduced.

[0028] The timing control chip 1-2 internally comprises, sequentially along the signal flow direction, a video and synchronization signal receiving module, a global synchronization timing generation module, a row and column address partitioning mapping and path selection logic unit, a distributed drive signal generation module, and a digital interface output module. It also integrates three basic modules: a clock and PLL (phase-locked loop) module, a power supply module, and a data buffer module. The video and synchronization signal receiving module receives interface signals sent by the external master controller, including video data, column synchronization signals (C-Sync), and frame synchronization signals (V-Sync). Video data is a digital data stream containing the grayscale levels of each pixel in the image to be displayed. The column synchronization signal (C-Sync) is a column reference synchronization pulse signal used to indicate the column-by-column scanning and switching timing of pixel units in the MicroLED microdisplay array. The frame synchronization signal (V-Sync) is a full-frame synchronization pulse signal used to indicate the start and end of a complete image display cycle. The row and column address partitioning and path selection logic unit maps the cached one-dimensional pixel data into the row and column addresses of the two-dimensional array and allocates them to the corresponding driving channels; the distributed driving signal generation module converts the digital grayscale data into digital driving signals that can directly drive MicroLED pixels; the digital interface output module outputs the generated driving signals to the pixel array and supports multi-chip cascading.

[0029] The first data driver chip 1-3 and the second data driver chip 1-4 are identical in size and function; the first data driver chip 1-3 will be used as an example for explanation. Internally, the first data driver chip contains a data buffer module, a PWM modulation module, and a level converter arranged sequentially along the signal flow direction. The data buffer module includes a shift register, an input register, and a data latch: the shift register converts serially input display data into parallel output; the input register receives the converted data and performs temporary buffering; the data latch latches and fixes the data after a frame or group of data has been received, preventing screen flickering or control errors during display. The PWM modulation module includes a reference PWM counter and a comparator: the reference PWM counter generates a reference counting timing signal, and the comparator compares the grayscale data output from the data latch with the reference counting timing signal to generate a pulse width modulation signal with a corresponding duty cycle, thereby achieving pixel grayscale adjustment control. The level converter amplifies and converts the low-voltage control signal output from the front end into a high-voltage control signal to match the operating level requirements of the subsequent pixel driver circuit, outputting a drive signal to drive the corresponding MicroLED pixel unit.

[0030] The first scan driver chip 1-5 and the second scan driver chip 1-6 have the same size and function. The first scan driver chip 1-5 will be used as an example here. The chip has an external reference current source and internally includes a column scan control module and a constant current output module. The column scan control module consists of a shift register and a level converter. The shift register generates and transmits the scan signal, and simultaneously outputs cascaded signals. The level converter converts the low-voltage scan signal into a high-voltage signal to ensure reliable conduction of the pixel switch. The reference current source provides a stable current reference, and the constant current output module outputs a constant drive current based on this reference to drive the corresponding pixel load.

[0031] The pixel driving circuit in this embodiment adopts Figure 10 The architecture shown integrates a current mirror constant current circuit within the scan driver chip, and uses a PWM grayscale control scheme to achieve grayscale adjustment. The specific working principle is as follows: the reference current source I within the scan driver chip... REF The reference MOSFET, shorted to its gate and drain, forms the reference branch, generating a stable gate bias voltage. The mirror MOSFET is connected to the reference MOSFET via a common gate, forming a current mirror structure that mirrors and replicates the current of the reference branch, outputting a constant bias current I. bias This ensures the consistency of the driving current for each pixel; the gate of the output MOS transistor of the data driver chip is connected to a PWM modulation signal, and the switching duration is controlled by adjusting the duty cycle of the signal, thereby controlling the light emission time of the MicroLED and realizing pixel grayscale adjustment.

[0032] In terms of driving addressing logic, the MicroLED microdisplay array 1-7 is divided into four sub-regions: the upper left sub-region selects the first data driver chip 1-3 and the first scan driver chip 1-5 to output driving signals; the upper right sub-region selects the second data driver chip 1-4 and the first scan driver chip 1-5 to output driving signals; the lower left sub-region selects the first data driver chip 1-3 and the second scan driver chip 1-6 to output driving signals; and the lower right sub-region selects the second data driver chip 1-4 and the second scan driver chip 1-6 to output driving signals. The timing control chip 1-2 automatically selects the corresponding driver chip combination based on the pixel coordinates to minimize the driving current path and reduce line voltage drop.

[0033] Example 2 Please see Figure 11This embodiment provides a scalable MicroLED microdisplay driving architecture, which is a resolution expansion scheme based on Embodiment 1. In this embodiment, the pixel array size is 2048×1536. The data driving module group includes four independent data driving sub-modules, which are symmetrically arranged on the left and right opposite sides of the pixel array. Each data driving sub-module connects to and drives one-quarter of the MicroLED pixel units in the corresponding row of the pixel array. The scanning driving module group includes four independent scanning driving sub-modules, which are symmetrically arranged on the top and bottom opposite sides of the pixel array. Each scanning driving sub-module connects to and drives only one-quarter of the MicroLED pixel units in the corresponding column of the pixel array.

[0034] Specifically, the scan driver module group adopts a dual-sided symmetrical distributed architecture. First scan driver submodule A and first scan driver submodule B are cascaded, as are second scan driver submodule A and second scan driver submodule B, each possessing complete column scan logic and current driving capabilities. First scan driver submodule A is responsible for driving all column pixel units in the upper left corner region of the pixel array; first scan driver submodule B is responsible for driving all column pixel units in the upper right corner region of the pixel array; second scan driver submodule A is responsible for driving all column pixel units in the lower left corner region of the pixel array; and second scan driver submodule B is responsible for driving all column pixel units in the lower right corner region of the pixel array. The four scan driver submodules achieve precise timing alignment through a global synchronization clock signal, ensuring complete synchronization of column scan actions in the four regions and avoiding left-right misalignment or time differences in the displayed image.

[0035] The data-driven module group also adopts a dual-sided symmetrical distributed architecture; the first data-driven submodule A and the first data-driven submodule B are cascaded, and the second data-driven submodule A and the second data-driven submodule B are cascaded, each possessing complete grayscale data buffering, PWM modulation, and driving capabilities. The first data-driven submodule A is responsible for driving all rows of pixel units in the upper left corner region of the pixel array, the first data-driven submodule B is responsible for driving all rows of pixel units in the lower left corner region of the pixel array, the second data-driven submodule A is responsible for driving all rows of pixel units in the upper right corner region of the pixel array, and the second data-driven submodule B is responsible for driving all rows of pixel units in the lower right corner region of the pixel array. The four data-driven submodules receive different sets of grayscale data bus signals, realizing independent driving and synchronous display of the four regions.

[0036] When the resolution of the pixel array is further improved, the driving capability can be matched with the number of pixels by increasing the number of scan driving sub-modules or data driving sub-modules, or by proportionally increasing the number of driving channels of a single scan driving sub-module and data driving sub-module. All row electrode traces and column electrode traces remain straight and without bends, without the need to redesign the overall layout architecture.

[0037] Furthermore, this scalable architecture supports independent refresh for different display areas. The pixel array is divided into multiple independent display sub-regions, each driven independently by a corresponding set of scan driver sub-modules and data driver sub-modules. Each sub-region can be refreshed at a different refresh rate. For static content areas in the display, a lower refresh rate can be used to reduce power consumption; for dynamic content areas, a higher refresh rate is used to ensure smoothness. This asynchronous refresh mechanism further optimizes the overall system power consumption while ensuring display quality.

[0038] Example 3 like Figure 12 As shown, this embodiment provides a driving method based on the MicroLED microdisplay array driving chipset described in Embodiment 1, specifically including the following steps: S1, System Power-On Initialization Power is supplied to the support circuit board 1-1 and each functional chip. The internal clock of the timing control chip 1-2 and the PLL module are started and phase-locked loop calibration is completed. The global reference clock is output to the two scan driver chips and the two data driver chips. The output parameters of the built-in reference current source of the scan driver chip are configured synchronously, the reference current value of the constant current output module is calibrated, and the initial state reset and working parameter configuration of the entire system are completed.

[0039] S2, Video signal reception and buffering Timing control chip 1-2 receives video data stream, column synchronization signal and frame synchronization signal output from host computer through external interface. After the video and synchronization signal receiving module completes protocol parsing and format conversion, the grayscale pixel data is written into the internal data buffer module for temporary storage. At the same time, the global synchronization timing generation module generates a three-level global timing reference of frame, row and column based on the synchronization signal.

[0040] S3, Pixel Address Partitioning and Path Allocation The row and column address partitioning and path selection logic unit reads the cached pixel data and performs four-part matching on the MicroLED micro-display array 1-7 according to the two-dimensional coordinates of each pixel: For pixels whose coordinates fall into the upper left sub-region, the driving path is assigned as the first data driving chip 1-3 + the first scan driving chip 1-5; For pixels whose coordinates fall into the upper right sub-region, the driving path is assigned as the second data driving chip 1-4 + the first scan driving chip 1-5; For pixels whose coordinates fall into the lower left sub-region, the driving path is assigned as the first data driving chip 1-3 + the second scan driving chip 1-6; For pixels whose coordinates fall into the lower right sub-region, the driving path is assigned as the second data driving chip 1-4 + the second scan driving chip 1-6.

[0041] After the allocation is completed, the distributed drive signal generation module sends the corresponding grayscale data and timing control signals to the corresponding drive chips.

[0042] S4, row-column cooperative scan driver After receiving the scan control signal, the two scan driver chips generate column-by-column pass-through selection signals through their internal shift registers. These signals are then boosted by a level converter and output to the corresponding column pixels, achieving column-by-column pass-through in the column direction. Simultaneously, the two data driver chips receive grayscale data from the corresponding partition. After being converted from serial to parallel by a shift register, buffered by an input register, and latched by a data latch for the entire row, the grayscale data is converted into a PWM control signal with the corresponding duty cycle by the PWM modulation module. This signal is then boosted by a level converter and output to the corresponding row pixels.

[0043] When a column is selected, the PWM signal of the corresponding row controls the conduction time of the pixel unit. Combined with the constant drive current output by the scan driver chip, the grayscale emission control of the corresponding pixel is realized.

[0044] S5, Full Frame Refresh and Loop After the scanning drive of all columns of a frame is completed, the timing control chip 1-2 triggers the frame synchronization signal, and each driver chip resets the scanning pointer and enters the driving cycle of the next frame. During the continuous frame driving process, the dual-sided symmetrical driving architecture ensures that the driving current loop path length of each pixel is consistent, maintaining the brightness uniformity of the entire screen.

[0045] Example 4 This embodiment provides a high-reliability driving chipset for MicroLED microdisplay arrays, which is a reliability optimization scheme based on Embodiment 1. It is suitable for application scenarios with high stability requirements, such as automotive and industrial microdisplays.

[0046] In this embodiment, each scanning driver chip and data driver chip has a built-in channel self-test and redundancy backup unit in its driving channel, and timing control chips 1-2 are equipped with a driving status monitoring and fault bypass module.

[0047] Specifically, each scanning driver chip's constant current output module is equipped with a current sampling subunit corresponding to each column of driving channels, which can acquire the amplitude of the output driving current in real time; each data driver chip's PWM modulation module is equipped with a level detection subunit corresponding to each row of driving channels, which can acquire the level status of the output driving signal in real time. The detection results of the current sampling subunit and the level detection subunit are fed back to the driving status monitoring module of the timing control chip 1-2 through the metal traces of the supporting circuit board 1-1.

[0048] When an open circuit or current offset fault occurs in a certain column of the scanning drive channel, the drive status monitoring module identifies the address of the faulty channel, triggers the fault bypass logic, and switches the drive task of the column to the redundant backup circuit of the adjacent channel on the same side. The drive compensation of the faulty column is completed through time-division multiplexing. Similarly, when a signal abnormality occurs in a certain row of the data drive channel, the output of the PWM control signal is switched to the redundant backup channel of the corresponding row to avoid the failure of the entire row or column of pixels due to a single channel fault.

[0049] Furthermore, this embodiment incorporates a multi-level current calibration module within each data driver chip. Based on calibration parameters issued by timing control chips 1-2, it can fine-tune the PWM output duty cycle of each drive channel channel by channel, compensating for current differences between channels caused by process variations. After calibration, the pixel brightness uniformity of the entire MicroLED microdisplay array 1-7 can be improved to over 97%, further enhancing display quality.

[0050] The remaining structures, connections, and driving principles in this embodiment are consistent with those in Embodiment 1.

[0051] Comparative Example 1 This comparative example uses a traditional monolithic integrated MicroLED microdisplay driving solution as the comparison object. This solution integrates all functional circuits, such as timing control logic, row and column scanning drive, PWM grayscale modulation, and constant current output, into a single mixed-signal driver chip. Its performance is compared with the driver chipset described in Embodiment 1 of this application under the same resolution (1024×768) and the same pixel size (5μm×5μm pixels). The comparison results are as follows: Traditional monolithic integration solutions require integrating all 1024 scan channels and 768 data drive channels on a single chip, while simultaneously supporting high-speed digital logic and high-voltage analog drive circuits. The total chip area is approximately 12.8 mm². 2 Embodiment 1 of this application adopts a dual-sided symmetrical distributed architecture. A single scan driver chip only needs to support 512 columns of channels, and a single data driver chip only needs to support 384 rows of channels. The total area of ​​four driver chips plus one timing control chip is approximately 7.2 mm². 2The total chip area is reduced by approximately 43.75%, making it more suitable for the miniaturized packaging requirements of micro-display devices.

[0052] Traditional monolithic solutions employ single-sided, single-chip driving, where the electrode trace length of edge pixels can be more than twice that of the center pixels. This long trace length results in a voltage drop of up to 120mV, leading to an overall screen brightness uniformity of approximately 89%. In contrast, Embodiment 1 of this application employs a four-sided symmetrical partitioned driving approach, where each driving chip is responsible for only an adjacent sub-region. This reduces the maximum length of the pixel driving loop path by 62%, minimizes the voltage drop to approximately 42mV, and achieves an overall screen brightness uniformity of 96.5%, effectively improving the problem of darker edge pixels.

[0053] Traditional fully integrated active display solutions require the simultaneous integration of an active display array, timing control chip, and peripheral driver integrated circuits on the same substrate. The physical dimensions of the active display array are calculated based on a resolution of 1024×768, a pixel size of 5μm×5μm, and a pixel pitch of 2.5μm, resulting in a length of 7.68mm, a width of 5.76mm, and an area of ​​approximately 44.24mm². 2 The timing control chip measures 2.5mm × 2.5mm and occupies an area of ​​approximately 6.25mm². 2 The peripheral driver integrated circuit (calculated based on the industry standard of reserving 15% of the active area) occupies an area of ​​approximately 7.8 mm². 2 The total area occupied by this traditional solution is as high as approximately 58.29 mm². 2 This application's embodiment employs a passive, discrete, high-density architecture. While ensuring the pin pad spacing meets high-density wiring requirements, the area of ​​the independently configured peripheral driver chip can be controlled to approximately 7.8 mm², similar to the reserved size of the active area. 2 In conjunction with the aforementioned timing control chip (approximately 6.25 mm²), 2 This reduces the total footprint of the driver and control chips to approximately 14.05 mm². 2 This architecture optimization significantly reduces the physical space occupied by peripheral circuits, making it more suitable for the miniaturization and highly compact packaging requirements of micro-display devices.

[0054] Traditional monolithic solutions employ single-sided, single-chip driving, resulting in long electrode traces for edge pixels, with a maximum trace length of approximately 7.68 mm. Taking a 5 μm × 5 μm pixel as an example, the operating current of a single pixel is approximately 2 μA, and the total current on a single trace is approximately 2.048 mA. At the 130nm process node, according to the line voltage drop formula V = I × R (where the line resistance R = RS × L / W, calculated with a maximum trace length L of 7.68 mm, a trace width W of 3 μm, and a sheet resistance RS of 0.02 Ω / sq), the line voltage drop caused by long traces can reach up to approximately 104 mV. Embodiment 1 of this application employs a four-sided symmetrical partitioned driving approach, where each driving chip is responsible for only an adjacent sub-region. This halves the maximum path length of the pixel driving loop (reducing it to approximately 3.84 mm), and correspondingly reduces the maximum line voltage drop by half to approximately 52 mV, effectively improving the problem of darker edge pixels.

[0055] Traditional monolithic solutions employ mixed-signal CMOS technology, which requires simultaneous compliance with the process requirements of high-density digital logic and high-voltage analog devices, resulting in high process complexity and high wafer manufacturing costs. According to the Poisson yield model Y=eD×A, under a mature 130nm process, the typical defect density D of such mixed-signal chips is generally 0.3. If the chip area A is 15mm², the calculated yield of this monolithic solution is approximately 95.6%. Embodiment 1 of this application adopts a separate design for digital and analog processes. The timing control chip and data driver chip use a high-density low-voltage CMOS process, while the scan driver chip uses a high-voltage analog CMOS process. Both types of chips can be matched with their respective optimal mature processes, significantly reducing the overall manufacturing cost compared to the monolithic solution. At the same time, as a pure digital chip, the timing control chip typically has a defect density D of 0.1, increasing the calculated yield to 98.51% under the same area conditions.

[0056] Traditional monolithic solutions require a complete redesign of the chip layout for resolution upgrades, including readjusting the routing architecture and driver module layout. The development cycle for a single resolution upgrade is approximately 6 to 8 months. In contrast, Embodiment 1 of this application adopts a modular distributed architecture. Resolution upgrades only require a corresponding increase in the number of driver sub-chips or an expansion of the number of channels per chip. The routing remains straight and without bends, making the solution highly reusable. The development cycle for the same resolution upgrade can be shortened to 2 to 3 months.

[0057] In summary, the driver chipset of this application is significantly superior to traditional monolithic integrated driver solutions in terms of chip size, display uniformity, manufacturing cost, and architecture scalability, and is more suitable for the development needs of ultra-high resolution MicroLED micro-display technology.

[0058] Any aspects not covered in this invention are applicable to existing technologies.

Claims

1. A driving chipset for a MicroLED microdisplay array, characterized in that, It includes a support circuit board (1-1), a timing control chip (1-2), two scan driver chips, and two data driver chips; The timing control chip (1-2), the scan driver chip, and the data driver chip are all vertically connected to the bonding pads on the support circuit board (1-1) through bonding electrodes, and the signal interconnection between the chips is achieved through the metal traces inside the support circuit board (1-1). The timing control chip (1-2) is used to receive external video data, column synchronization signal and frame synchronization signal, and generate global timing logic and row and column drive control signals; The column synchronization signal is a column reference synchronization pulse signal used to indicate the column-by-column scanning and switching timing of each column of pixel units in a MicroLED microdisplay array; The frame synchronization signal is a frame synchronization pulse signal used to indicate the start and end of a complete frame image display cycle; Two scanning driver chips are symmetrically arranged on opposite sides of the MicroLED microdisplay array (1-7) to receive the scanning drive control signal from the timing control chip (1-2) and drive the pixel units of the corresponding column in the MicroLED microdisplay array (1-7) respectively. Two data driving chips are symmetrically arranged on the other opposite sides of the MicroLED microdisplay array (1-7) to receive the data driving control signal and grayscale data signal from the timing control chip (1-2) and drive the pixel units of the corresponding row in the MicroLED microdisplay array (1-7) respectively.

2. The driving chipset for the MicroLED microdisplay array according to claim 1, characterized in that, The timing control chip (1-2) has a built-in row and column address partitioning and path selection logic unit, which is used to control the corresponding scan driver chip and data driver chip to output MicroLED driving signals according to the coordinates of the pixel to be lit.

3. The driving chipset for the MicroLED microdisplay array according to claim 2, characterized in that, The two scan driver chips have built-in reference current sources, column scan control modules, and constant current output modules. The reference current source is used to provide a reference current; the column scan control module consists of a shift register and a level converter, and is used to generate a column-by-column gating control signal; the constant current output module is connected to the reference current source and the column scan control module respectively, and is used to generate a MicroLED constant current driving signal with the reference current as a reference, and output driving current to the corresponding column pixel unit of the MicroLED microdisplay array (1-7) under the control of the column-by-column gating control signal.

4. The driving chipset for the MicroLED microdisplay array according to claim 3, characterized in that, The two data driver chips have built-in data cache modules, PWM modulation modules, and level converters; the data cache module includes a shift register, an input register, and a data latch, which are used to receive and cache grayscale data. The PWM modulation module is connected to the data buffer module and includes a reference PWM counter and a comparator, used to generate a PWM control signal with a corresponding duty cycle based on the grayscale data; the level converter is connected to the PWM modulation module and is used to perform level conversion on the PWM control signal and output it to the corresponding row pixel unit of the MicroLED microdisplay array (1-7) to regulate the light emission grayscale of the pixel unit.

5. The driving chipset for the MicroLED microdisplay array according to claim 4, characterized in that, The MicroLED microdisplay array (1-7) is provided with MicroLED bonding electrodes (1-8), which are vertically connected to the bonding pads of the support circuit board (1-1) to form MicroLED bonding points; the driver chip is provided with driver chip bonding electrodes (1-9) around its periphery, which are vertically connected to the bonding pads of the support circuit board (1-1) to form driver chip bonding points.

6. The driving chipset for the MicroLED microdisplay array according to claim 5, characterized in that, The timing control chip (1-2) divides the MicroLED microdisplay array (1-7) into four sub-regions based on the row and column lines at the center of the array: In the upper left sub-region, select the first data driver chip (1-3) and the first scan driver chip (1-5) to output drive signals; In the upper right sub-region, select the second data driver chip (1-4) and the first scan driver chip (1-5) to output drive signals; In the lower left sub-region, select the first data driver chip (1-3) and the second scan driver chip (1-6) to output drive signals; In the lower right sub-region, select the second data driver chip (1-4) and the second scan driver chip (1-6) to output drive signals.

7. The driving chipset for the MicroLED microdisplay array according to claim 6, characterized in that, The timing control chip (1-2) and the data driver chip are manufactured using a first CMOS process, and the scan driver chip is manufactured using a second CMOS process. The digital logic integration density of the first CMOS process is higher than that of the second CMOS process, and the operating voltage of the second CMOS process is higher than that of the first CMOS process.

8. The driving chipset for the MicroLED microdisplay array according to claim 7, characterized in that, The two scan driver chips have the same geometric dimensions and adopt a dual-sided symmetrical scan driver design; the two data driver chips have the same geometric dimensions and adopt a dual-sided symmetrical data driver design.

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