Display device and driving method thereof

Abstract

Embodiments of the present application provide a display device and a driving method thereof. The display device includes a display panel including a display area and a non-display area, and the display panel further includes a plurality of pixel rows and a plurality of control circuits. A pixel row includes a plurality of pixels, and the pixels are arranged in the display area. The pixels include driving transistors. The control circuits are arranged in the non-display area, and one control circuit is electrically connected to the driving transistors of the plurality of pixels in one pixel row. The driving method provides an off level to a gate of a first control transistor in an initialization stage and a data writing stage in a driving period of the display panel displaying one frame of picture, provides an on level to the gate of the first control transistor in a compensation stage and an emitting stage in the driving period, and provides a first power voltage to the driving transistors via the first control transistor through a first power voltage line. The technical solution of the present application can improve the brightness uniformity of the picture displayed by the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and its driving method. Background Technology

[0002] In applications such as Virtual Reality (VR) and Augmented Reality (AR), the pixel density (Pixels Per Inch, PPI) of Organic Light-Emitting Diode (OLED) display devices is one of the factors affecting immersive visual experiences.

[0003] As pixel size shrinks, the threshold voltage drift and mobility non-uniformity of pixel driving transistors in organic light-emitting diode (OLED) displays become increasingly prominent. Due to inherent variations in the manufacturing process, the threshold voltage and mobility of driving transistors in different pixels within the same display device differ. This difference leads to inconsistent brightness across pixels under the same data voltage, resulting in uneven brightness in the displayed image.

[0004] To address the aforementioned issues, traditional solutions compensate for deviations in driving transistor parameters within the pixel using a combination of transistors and capacitors, combined with driving timing. However, to achieve a more comprehensive compensation function, these traditional solutions typically require a larger number of transistors and capacitors, such as six transistors with two capacitors or seven transistors with one capacitor. This encroaches on pixel space, leading to a decrease in the aperture ratio of the display device. Furthermore, some simplified internal compensation circuits can only compensate for the threshold voltage, resulting in poor mobility compensation and an inability to simultaneously and effectively suppress both sources of non-uniformity.

[0005] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0006] The purpose of this application is to provide a display device and its driving method, which aims to solve the problem of poor brightness uniformity of the screen displayed by existing display devices.

[0007] This application provides a display device, the display device including a display panel, the display panel including a display area and a non-display area, the display panel further including: a plurality of pixel rows, the pixel rows including a plurality of pixels, the pixels being disposed in the display area, the pixels including a driving transistor; and a plurality of control circuits, the control circuits being disposed in the non-display area, one of the control circuits being electrically connected to the driving transistors of the plurality of pixels in one of the pixel rows.

[0008] In the aforementioned display device, the gate of the driving transistor is electrically connected to a first node, one of its source and drain is electrically connected to a second node, and the other of its source and drain is electrically connected to a third node; the control circuit includes: a first control transistor, the gate of which is electrically connected to a first light-emitting control signal line, one of its source and drain is electrically connected to a first power supply voltage line, and the other of its source and drain is electrically connected to the third node; and a second control transistor, the gate of which is electrically connected to a second light-emitting control signal line, one of its source and drain is electrically connected to a first initialization voltage line, and the other of its source and drain is electrically connected to the third node.

[0009] In the above-described display device, the first light-emitting control signal line is used to control the first control transistor to turn off during the initialization phase and data writing phase of the driving cycle in which a frame of image is displayed on the display panel, and to control the first control transistor to turn on during the compensation phase and light-emitting phase of the driving cycle.

[0010] In the above-described display device, the second light emission control signal line is used to control the second control transistor to turn on during at least one of the initialization phase and the data writing phase in the driving cycle of displaying a frame of image on the display panel.

[0011] In the aforementioned display device, the pixel further includes: a first switching transistor, the gate of which is electrically connected to a first scan signal line, one of its source and drain being electrically connected to a data signal line, and the other of its source and drain being electrically connected to the first node; a second switching transistor, the gate of which is electrically connected to a second scan signal line, one of its source and drain being electrically connected to a second initialization voltage line, and the other of its source and drain being electrically connected to the second node; a storage capacitor, the first plate of which is electrically connected to the first node, and the second plate of which is electrically connected to the second node; and a light-emitting device, the anode of which is electrically connected to the second node, and the cathode of which is electrically connected to a second power supply voltage line.

[0012] In the above-described display device, the channel width of at least one of the first control transistor and the second control transistor is greater than the channel width of any one of the driving transistor, the first switching transistor, and the second switching transistor.

[0013] In the above-described display device, the second power supply voltage line is used to provide different voltage values ​​according to the target grayscale value of the pixel.

[0014] In the above-mentioned display device, the second power supply voltage line is used to provide a first voltage when the target grayscale value is in a first grayscale value range, and to provide a second voltage when the target grayscale value is in a second grayscale value range, wherein the maximum grayscale value in the first grayscale value range is less than the minimum grayscale value in the second grayscale value range, the first voltage is -2V to 0V, and the second voltage is 0.1V to 5V.

[0015] In the aforementioned display device, the first scan signal line is used to output a first-type level signal during the initialization phase, the second scan signal line is used to output a first-type level signal during the initialization phase, the second initialization voltage line is used to provide a second initialization voltage to the second node via the second switching transistor during the initialization phase, the first scan signal line is used to output a first-type level signal during the data writing phase, the second scan signal line is used to output a first-type level signal during the data writing phase, the data signal line is used to provide a data voltage to the first node via the first switching transistor during the data writing phase, the first scan signal line is used to maintain the output of a first-type level signal during the compensation phase, the second scan signal line is used to switch to a second-type level signal during the compensation phase, the second switching transistor is turned off during the compensation phase, the first power supply voltage line is used to charge the second node via the first control transistor and the driving transistor during the compensation phase, the first scan signal line is used to switch to a second-type level signal during the light emission phase, the first switching transistor is turned off during the light emission phase, the storage capacitor is used to maintain the potential difference between the first node and the second node during the light emission phase, and the light-emitting device is used to emit light during the light emission phase.

[0016] This application also provides a driving method for a display device, the display device including a display panel, the display panel including a display area and a non-display area, the display panel further including a plurality of pixel rows and a plurality of control circuits, the pixel row including a plurality of pixels, the pixels being disposed in the display area, the pixels including a driving transistor, the control circuits being disposed in the non-display area, one of the control circuits being electrically connected to the driving transistors of the plurality of pixels in one pixel row, the control circuit including a first control transistor and a second control transistor; the driving method including: in an initialization phase and a data writing phase during a driving cycle in which the display panel displays a frame, providing a turn-off level to the gate of the first control transistor, the first control transistor being turned off; and in a compensation phase and a light emission phase during the driving cycle, providing a turn-on level to the gate of the first control transistor, the first control transistor being turned on, a first power supply voltage line providing a first power supply voltage to the driving transistor via the first control transistor, and charging one of the source and drain of the driving transistor via the driving transistor.

[0017] In the above driving method, the pixel further includes a first switching transistor, a second switching transistor, and a storage capacitor; the driving method further includes: in the initialization phase, a first scan signal line outputs a first-type level signal, a second scan signal line outputs a first-type level signal, and a second initialization voltage line provides a second initialization voltage to one of the source and drain of the driving transistor via the second switching transistor; in the data writing phase, the first scan signal line outputs a first-type level signal, the second scan signal line outputs a first-type level signal, and a data signal line provides a data voltage to the gate of the driving transistor via the first switching transistor; in the compensation phase, the first scan signal line maintains the output of the first-type level signal, the second scan signal line switches to a second-type level signal, the second switching transistor is turned off, and the first power supply voltage line charges one of the source and drain of the driving transistor via the first control transistor and the driving transistor; and in the light emission phase, the first scan signal line switches to a second-type level signal, the first switching transistor is turned off, the storage capacitor maintains the potential difference between the gate of the driving transistor and one of the source and drain of the driving transistor, and the light-emitting device emits light.

[0018] In the above driving method, the driving method further includes: adjusting the voltage value of the second power supply voltage line according to the target gray value of the pixel.

[0019] In the above driving method, adjusting the voltage value of the second power supply voltage line according to the target gray value of the pixel includes: providing a first voltage to the second power supply voltage line when the target gray value is within a first gray value range, the first voltage being -2V to 0V; and / or providing a second voltage to the second power supply voltage line when the target gray value is within a second gray value range, the second voltage being 0.1V to 5V.

[0020] In the above driving method, the driving method further includes: providing a conduction level to the gate of the second control transistor during at least one of the initialization phase and the data writing phase, so that the second control transistor is turned on, and the first initialization voltage line provides a first initialization voltage to the driving transistor via the second control transistor.

[0021] This application provides a display device and its driving method. The display panel of the display device includes a display area and a non-display area. The display panel also includes multiple pixel rows and multiple control circuits. Each pixel row includes multiple pixels, which are disposed in the display area and include driving transistors. The control circuits are disposed in the non-display area, and one control circuit is electrically connected to the driving transistors of multiple pixels in a pixel row. Because the control circuits are disposed in the non-display area rather than in each pixel within the display area, the number of transistors inside the pixel is reduced, saving space within the pixel. Under the same pixel size, reducing the number of transistors inside the pixel is beneficial for increasing the aperture ratio of the display panel; under the same aperture ratio, reducing the number of transistors inside the pixel is beneficial for reducing the pixel size to increase pixel density. Furthermore, since the control circuits are disposed in the non-display area and shared by multiple pixels in the same pixel row, the transistors in the control circuits no longer occupy space inside the pixel. The parasitic capacitive load on the nodes inside the pixel is reduced, and the potential change during the compensation stage is closer to the theoretically derived model. This improves the compensation effect on the threshold voltage and mobility of the driving transistors, thereby improving the brightness uniformity of the image displayed on the display panel. Furthermore, since the non-display area has relatively ample space, the transistors in the control circuit can be manufactured to a sufficiently large size to meet the current carrying capacity required to drive an entire row of pixels, thus reducing the voltage drop on the power supply lines. Additionally, because the control circuit is located in the non-display area, the signal lines electrically connected to the control circuit only need to be connected to the transistors in the control circuit within the non-display area. This reduces the overlap of traces within the display area, lowering the probability of pixel defects caused by short circuits or open circuits during manufacturing, and ultimately improving the overall yield of the display panel.

[0022] The technical solution of this application also provides a driving method for a display device. In the initialization phase and data writing phase of the driving cycle in which the display panel displays a frame, the driving method provides a turn-off level to the gate of the first control transistor. The first control transistor is turned off, and the electrical connection between the first power supply voltage line and the driving transistor inside the pixel is isolated, thus avoiding crosstalk between the first power supply voltage and the initialization voltage. In the compensation phase and light emission phase of the driving cycle, the driving method provides a conduction level to the gate of the first control transistor. The first control transistor is turned on, and the first power supply voltage line provides a first power supply voltage to the driving transistor through the first control transistor. The first power supply voltage charges the node connected to the source or drain of the driving transistor through the first control transistor and the driving transistor. Since the potential rise rate of this node is directly related to the threshold voltage and mobility of the driving transistor, the driving transistor with higher mobility or lower threshold voltage charges faster, resulting in a larger potential rise of the node connected to its source or drain, and the gate-source voltage of the driving transistor is adaptively reduced. Conversely, the driving transistor with lower mobility or higher threshold voltage charges slower, resulting in a smaller potential rise of the node connected to its source or drain, and a smaller reduction in the gate-source voltage. The technical solution of this application, through the aforementioned driving timing, enables automatic compensation of the threshold voltage and mobility differences between different driving transistors, making the driving current of each pixel more consistent and improving the brightness uniformity of the image displayed on the display panel. Attached Figure Description

[0023] Figure 1 A schematic diagram of a display device provided for an embodiment of this application.

[0024] Figure 2 A circuit diagram of a display device provided for an embodiment of this application.

[0025] Figure 3 Timing diagram of a display device provided for an embodiment of this application.

[0026] Figure 4 and Figure 5 The graphs showing the relationship between threshold voltage drift and current deviation before and after internal compensation under different grayscale conditions are provided for embodiments of this application. Detailed Implementation

[0027] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0028] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0029] The technical solutions of different embodiments of this application can be combined with each other.

[0030] The display devices provided in the embodiments of this application may be, for example, organic light-emitting diode (OLED) display devices, mini light-emitting diode (Mini-LED) display devices, or micro light-emitting diode (Micro-LED) display devices. The embodiments of this application are described using organic light-emitting diode display devices as an example.

[0031] The embodiments of this application aim to provide a display device and its driving method to solve the problem of poor brightness uniformity of the screen displayed by existing display devices.

[0032] like Figure 1 As shown, the display device provided in the embodiments of this application includes a timing controller TCON, a source driver chip SDIC, a power management chip PMIC, and a display panel DP. The display panel DP is an organic light-emitting diode (OLED) display panel. The timing controller TCON receives externally input image data, parses the image data into driving timing signals and image grayscale data, and transmits the driving timing signals and image grayscale data to the source driver chip SDIC, the gate driver circuit GOA, and the light-emitting driver circuit, respectively. The source driver chip SDIC outputs a corresponding data voltage to the data signal line DL of the display panel DP according to the image grayscale data transmitted by the timing controller TCON. The gate driver circuit GOA outputs scan signals to the first scan signal line GL1 and the second scan signal line GL2 of the display panel DP according to the scan timing transmitted by the timing controller TCON. The light-emitting driver circuit outputs light-emitting control signals to the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 of the display panel DP according to the light-emitting control timing transmitted by the timing controller TCON. The power management chip PMIC provides corresponding voltages to the first power supply voltage line VDD and the second power supply voltage line VSS, respectively. The display panel DP includes a display area AA and a non-display area PA. The display area AA contains multiple pixels PX, which are arranged into a pixel array.

[0033] like Figure 2As shown, the display panel DP provided in the embodiments of this application further includes multiple pixel rows and multiple control circuits. Each pixel row includes multiple pixels PX, which are disposed in the display area AA and include a driving transistor T1. Control circuits are disposed in the non-display area PA, and one control circuit is electrically connected to the driving transistor T1 of each pixel PX in a pixel row. Specifically, the control circuit is disposed on at least one side of a corresponding pixel row.

[0034] In embodiments of this application, the pixel PX further includes a first switching transistor T2, a second switching transistor T3, a storage capacitor Cst, and a light-emitting device EL. The gate of the driving transistor T1 is electrically connected to a first node G, one of its source and drain is electrically connected to a second node S, and the other of its source and drain is electrically connected to a third node D. The gate of the first switching transistor T2 is electrically connected to a first scan signal line GL1, one of its source and drain is electrically connected to a data signal line DL, and the other of its source and drain is electrically connected to the first node G. The gate of the second switching transistor T3 is electrically connected to a second scan signal line GL2, one of its source and drain is electrically connected to a second initialization voltage line Vini_2, and the other of its source and drain is electrically connected to the second node S. The first plate of the storage capacitor Cst is electrically connected to the first node G, and the second plate is electrically connected to the second node S. The anode of the light-emitting device EL is electrically connected to the second node S, and the cathode is electrically connected to a second power supply voltage line VSS. The parasitic capacitance of the second node S includes the capacitance of the storage capacitor Cst and the equivalent capacitance of the light-emitting device EL.

[0035] In embodiments of this application, the control circuit includes a first control transistor T4 and a second control transistor T5. The gate of the first control transistor T4 is electrically connected to a first light-emitting control signal line EM1, one of its source and drain is electrically connected to a first power supply voltage line VDD, and the other of its source and drain is electrically connected to a third node D. The gate of the second control transistor T5 is electrically connected to a second light-emitting control signal line EM2, one of its source and drain is electrically connected to a first initialization voltage line Vini_1, and the other of its source and drain is electrically connected to the third node D. The first light-emitting control signal line EM1 outputs a first light-emitting control signal, which controls the on / off state of the first control transistor T4, thereby controlling the conduction state between the first power supply voltage line VDD and the driving transistor T1. In embodiments of this application, the driving transistor T1, the first switching transistor T2, the second switching transistor T3, the first control transistor T4, and the second control transistor T5 are all N-type transistors. In other embodiments, the driving transistor T1, the first switching transistor T2, the second switching transistor T3, the first control transistor T4, and the second control transistor T5 are all P-type transistors. In another embodiment, at least one of the driving transistor T1, the first switching transistor T2, the second switching transistor T3, the first control transistor T4, and the second control transistor T5 is a P-type transistor.

[0036] In the embodiments of this application, the control circuit is disposed in the non-display area PA, and the first control transistor T4 and the second control transistor T5 in the control circuit are shared by multiple pixels PX in the same pixel row. The first control transistor T4 is used to control the electrical connection state between the first power supply voltage line VDD and the third node D, and the second control transistor T5 is used to control the electrical connection state between the first initialization voltage line Vini_1 and the third node D. Since the control circuit is disposed in the non-display area PA instead of in each pixel PX within the display area AA, the number of components inside the pixel PX is reduced from five transistors and one capacitor to three transistors and one capacitor, thus saving the arrangement space inside the pixel PX. Under the same pixel size conditions, the reduction in the number of transistors inside the pixel PX is beneficial to improving the aperture ratio of the display panel DP; under the same aperture ratio conditions, the reduction in the number of transistors inside the pixel PX is beneficial to reducing the pixel size to increase the pixel density.

[0037] In the embodiments of this application, since the control circuit is located in the non-display area PA and shared by multiple pixels PX in the same pixel row, the first control transistor T4 and the second control transistor T5 in the control circuit no longer occupy the space inside the pixel PX. The parasitic capacitance load on the nodes inside the pixel PX is reduced, and the potential change in the compensation stage is closer to the theoretical derivation model, thereby improving the compensation effect on the threshold voltage and mobility of the driving transistor T1, and thus improving the brightness uniformity of the image displayed on the display panel DP.

[0038] In the embodiments of this application, the channel width of at least one of the first control transistor T4 and the second control transistor T5 is greater than the channel width of any one of the driving transistor T1, the first switching transistor T2, and the second switching transistor T3. Since the space in the non-display area PA is relatively ample, the dimensions of the first control transistor T4 and the second control transistor T5 during fabrication are sufficient to meet the current carrying capacity required to drive the entire row of pixels PX, thus reducing the voltage drop on the first power supply line VDD. Furthermore, since the control circuit is located in the non-display area PA, the first light-emitting control signal line EM1 and the second light-emitting control signal line EM2 only need to be electrically connected to the first control transistor T4 and the second control transistor T5 in the non-display area PA. This reduces the overlap of traces within the display area AA, lowering the probability of pixel PX defects caused by short circuits or open circuits during manufacturing, which is beneficial for improving the overall yield of the display panel DP.

[0039] In the embodiments of this application, the first light emission control signal line EM1 and the second light emission control signal line EM2 are output by independent light emission driving circuits, rather than by the shift register in the gate driving circuit GOA. By adjusting the pulse width of the first light emission control signal line EM1, the light emission time ratio of the light-emitting device EL can be changed, thereby meeting the low duty cycle black insertion modulation requirement of the display device in virtual reality application scenarios to reduce motion blur.

[0040] like Figure 3As shown, embodiments of this application provide a driving method for a display device. This driving method sequentially executes an initialization phase P1, a data writing phase P2, a compensation phase P3, and a light emission phase P4 during the driving cycle of a display panel (DP) displaying one frame. A first scan signal line GL1 outputs a first scan signal, and a second scan signal line GL2 outputs a second scan signal. The first scan signal and the second scan signal have a phase difference. The duration of the first type of level signal (e.g., a high-level signal) of the second scan signal is shorter than the duration of the first type of level signal of the first scan signal. Specifically, the duration of the first type of level signal output by the first scan signal line GL1 covers the initialization phase P1, the data writing phase P2, and the compensation phase P3, with a total duration of 3 microseconds; the duration of the first type of level signal output by the second scan signal line GL2 only covers the initialization phase P1 and the data writing phase P2, with a total duration of 2.9 microseconds. The time period during which the first scan signal line GL1 outputs a first-class level signal partially overlaps with the time period during which the second scan signal line GL2 outputs a first-class level signal. Both output first-class level signals during the initialization phase P1 and the data writing phase P2. During the compensation phase P3, the first scan signal line GL1 continues to output a first-class level signal, while the second scan signal line GL2 switches to a second-class level signal (e.g., a low-level signal).

[0041] During initialization phase P1, the first scan signal line GL1 outputs a first-class level signal, and the first switching transistor T2 is turned on; the second scan signal line GL2 outputs a first-class level signal, and the second switching transistor T3 is turned on. The second initialization voltage line Vini_2 provides a second initialization voltage to the second node S via the second switching transistor T3, and the potential of the second node S is reset to the potential corresponding to the second initialization voltage. During initialization phase P1, the data signal line DL is in a second-class level state (e.g., low level state), and the potential of the first node G is reset to the potential corresponding to the second-class level (e.g., low level). During initialization phase P1, the first light emission control signal line EM1 controls the first control transistor T4 to turn off, and the electrical connection between the first power supply voltage line VDD and the third node D is isolated, thus avoiding short circuits or crosstalk between the first power supply voltage and the first initialization voltage. Simultaneously, during initialization phase P1, the second light emission control signal line EM2 controls the second control transistor T5 to turn on, and the first initialization voltage line Vini_1 provides a first initialization voltage to the third node D via the second control transistor T5 to assist in resetting the potential of the third node D. During the initialization phase P1, the potentials of the gate (first node G) of the driving transistor T1, the source or drain of the driving transistor T1 that is electrically connected to the second node S, and the one that is electrically connected to the third node D are reset to their initial states, thereby clearing the node charge.

[0042] During the data writing phase P2, the first scan signal line GL1 outputs a first-class level signal, and the first switching transistor T2 remains on; the second scan signal line GL2 outputs a first-class level signal, and the second switching transistor T3 remains on. The data signal line DL switches from a second-class level to a first-class level, and the data voltage output by the data signal line DL is written to the gate (first node G) of the driving transistor T1 via the first switching transistor T2. The potential of the first node G rises to the potential Vg_initial corresponding to the data voltage, and the driving transistor T1 turns on. The potential of the second node S remains at the initial low potential Vs_0 corresponding to the second initialization voltage. During the data writing phase P2, the first light emission control signal line EM1 controls the first control transistor T4 to turn off, and the electrical connection between the first power supply voltage line VDD and the third node D remains isolated to prevent the first power supply voltage from interfering with the potential of the third node D during the data writing phase P2. During the data writing phase P2, the second light-emitting control signal line EM2 controls the second control transistor T5 to remain on, and the first initialization voltage line Vini_1 continues to provide the first initialization voltage to the third node D via the second control transistor T5, ensuring that the third node D is at a stable initial potential before the compensation phase P3 begins.

[0043] During the compensation phase P3, the first scan signal line GL1 maintains a first-class level signal output, and the first switching transistor T2 remains on. The second scan signal line GL2 transitions from a first-class level signal to a second-class level signal, and the second switching transistor T3 turns off. After the second switching transistor T3 turns off, the second node S is disconnected from the second initialization voltage line Vini_2, and the potential of the second node S is determined by the amount of charge flowing in. Since the first node G has been written with data voltage, the driving transistor T1 turns on. The first light emission control signal line EM1 transitions to an active level during the compensation phase P3, the first control transistor T4 turns on, and simultaneously the second light emission control signal line EM2 controls the second control transistor T5 to turn off. The first power supply voltage line VDD charges the parasitic capacitance of the second node S through the first control transistor T4 and the driving transistor T1, and the potential of the second node S rises from the initial low potential Vs_0 to the potential Vs_initial. The parasitic capacitance of the second node S includes the capacitance of the storage capacitor Cst and the equivalent capacitance of the light-emitting device EL. The driving method provided in the embodiments of this application controls the potential rise of the second node S by adjusting the duration of the compensation phase P3, thereby adjusting the adaptive reduction of the gate-source voltage of the driving transistor T1 of each pixel PX, so that the current deviation caused by the threshold voltage and mobility is offset by the adaptively adjusted gate-source voltage.

[0044] like Figure 3As shown, the rate of potential rise of the second node S is directly related to the threshold voltage and mobility of the driving transistor T1. For driving transistor T1 with higher mobility or lower threshold voltage, its conductivity is stronger, and the charging speed of the parasitic capacitance of the second node S is faster, causing the second node S to reach a higher potential. For driving transistor T1 with lower mobility or higher threshold voltage, its conductivity is weaker, and the charging speed of the parasitic capacitance of the second node S is slower, causing the second node S to reach a lower potential.

[0045] During the light-emitting phase P4, the first scan signal line GL1 transitions from a first-class level signal to a second-class level signal, and the first switching transistor T2 turns off. At the start of the light-emitting phase P4, the data signal line DL transitions from a first-class level (e.g., high level) to a second-class level. After the first switching transistor T2 turns off, the gate (first node G) of the driving transistor T1 is disconnected from the data signal line DL, and the first node G enters a floating state. Due to the coupling effect of the storage capacitor Cst, the potential difference between the first node G and the second node S (i.e., the gate-source voltage Vgs of the driving transistor T1) is adaptively locked. Since the potential of the first node G is fixed at the data voltage during the compensation phase P3, the higher the potential of the second node S, the smaller the ultimately locked gate-source voltage Vgs. A driving transistor T1 that originally tended to output a larger current due to a lower threshold voltage or higher mobility has its actual gate-source voltage Vgs automatically reduced; a driving transistor T1 that originally tended to output a smaller current due to a higher threshold voltage or lower mobility has its actual gate-source voltage Vgs reduced by a smaller margin.

[0046] As the potential of the second node S continues to rise and eventually exceeds the turn-on voltage of the light-emitting device EL, the light-emitting device EL begins to emit light. Since the first node G is in a floating state, the potential change of the second node S is proportionally coupled to the first node G through the storage capacitor Cst, thereby maintaining the adaptively regulated gate-source voltage Vgs constant. The storage capacitor Cst maintains the potential difference between the first node G and the second node S during the light-emitting phase P4. This compensation process effectively offsets the inherent threshold voltage and mobility differences between the different driving transistors T1, making the final luminous current flowing through each light-emitting device EL tend to be consistent, achieving dual compensation for threshold voltage and mobility. Figure 3 As shown, taking two driving transistors T1 and T1' with different electrical characteristics as examples, during the compensation stage P3 and the light emission stage P4, the potential of the second node S in the pixel PX where the driving transistor T1 is located and the potential of the second node S in the pixel PX where the driving transistor T1' is located continue to rise along different curves, and finally stabilize at different potential levels.

[0047] In the embodiments of this application, the output current formula of the driving transistor T1 is: Ioled = (1 / 2) × μ × Cox × (W / L) × (Vgs - Vth)². Where Cox is the gate oxide capacitance per unit area, Cox = εox / tox, εox is the dielectric constant of the gate insulating dielectric layer (usually an oxide), and tox is the thickness of the insulating dielectric layer. At the moment the compensation phase P3 ends and the first scan signal line GL1 jumps to the second-type level signal, the potential Vs of the second node S reaches a specific value, at which point the locked gate-source voltage is Vgs = Vdata - Vs. The charging speed of the second node S is proportional to the current driving capability of the driving transistor T1. If the mobility μ of the driving transistor T1 of a certain pixel PX is too large or the threshold voltage Vth is too small, the driving transistor T1 charges the second node S more during the compensation phase P3, and the potential Vs of the second node S rises higher. Substituting into the current formula, we know that when the mobility μ increases, the potential Vs of the second node S increases, and the locked gate-source voltage Vgs decreases, thus suppressing the increase in current. When the threshold voltage Vth decreases, the potential Vs of the second node S also increases, and the gate-source voltage Vgs decreases, offsetting the current increment caused by the decrease in threshold voltage. By controlling the duration of the compensation phase P3, the current deviation caused by the threshold voltage deviation ΔVth and the mobility deviation Δμ is offset by the adaptively adjusted (Vgs-Vth)² term, so the luminous current Ioled of the light-emitting device EL is ultimately only related to the data voltage Vdata.

[0048] In the embodiments of this application, the first light-emitting control signal line EM1 controls the first control transistor T4 to turn off during the initialization phase P1 and data writing phase P2 of the driving cycle in which the display panel DP displays a frame, and controls the first control transistor T4 to turn on during the compensation phase P3 and light-emitting phase P4 of the driving cycle. When the first control transistor T4 is turned off during the initialization phase P1 and data writing phase P2, the electrical connection between the first power supply voltage line VDD and the third node D is isolated, preventing short circuits or crosstalk between the first power supply voltage and the first initialization voltage. When the first control transistor T4 is turned on during the compensation phase P3, the first power supply voltage line VDD provides the first power supply voltage to the third node D through the first control transistor T4. The first power supply voltage charges the parasitic capacitance of the second node S via the driving transistor T1, realizing the potential rise of the second node S and the adaptive locking of the subsequent gate-source voltage. When the first control transistor T4 remains on during the light-emitting phase P4, the driving current can flow stably to the light-emitting device EL.

[0049] like Figure 4 and Figure 5As shown in the figure, in the embodiment of the present application, the second power supply voltage line VSS provides different voltage values according to the target gray scale value of the pixel PX. The second power supply voltage line VSS provides a first voltage when the target gray scale value is in a first gray scale range, and provides a second voltage when the target gray scale value is in a second gray scale range, wherein the maximum gray scale value in the first gray scale range is smaller than the minimum gray scale value in the second gray scale range. The first voltage is -2V to 0V, for example, -1V; the second voltage is 0.1V to 5V, for example, 3V. The first gray scale range is a low gray scale range (e.g., gray scale value G0 to gray scale value G127), and the second gray scale range is a high gray scale range (e.g., gray scale value G128 to gray scale value G255).

[0050] In the compensation phase P3 under the low gray scale condition, the charging current provided by the driving transistor T1 is small, and the potential Vs of the second node S gradually rises. If the voltage of the second power supply voltage line VSS is relatively high (e.g., 3V), as the potential Vs of the second node S rises, the voltage difference (Vs-Vss) between the anode and the cathode of the light-emitting device EL reaches the turn-on voltage of the light-emitting device EL in advance, causing part of the current originally used for charging the parasitic capacitance to leak into the light-emitting device EL. This leakage current destroys the mapping relationship between the potential rise curve of the second node S and the electrical parameters of the driving transistor T1, resulting in a decreased compensation effect. In the embodiment of the present application, when the gray scale is low, the voltage of the second power supply voltage line VSS is dynamically adjusted down to a negative voltage (e.g., -1V), which ensures that Vs-Vss < Vth_oled (where Vth_oled is the turn-on voltage of the light-emitting device EL) during the entire compensation phase P3, so that the light-emitting device EL is in a reverse biased or zero biased state. This ensures that the current output by the driving transistor T1 is all used for charging the parasitic capacitance of the second node S, and improves the sensitivity of weak current compensation under low gray scale values.

[0051] Under the high gray scale condition, the light-emitting device EL is already in an activated state during the compensation phase P3, which changes the current path. At this time, setting the voltage of the second power supply voltage line VSS to a relatively high value (e.g., 3V) has better performance than setting it to a negative voltage value (e.g., -1V).

[0052] As Figure 4 and Figure 5 shown, Figure 4 and Figure 5 respectively correspond to the conditions of gray scale value G64 and gray scale value G255. The abscissa is the threshold voltage shift Vth_shift of the driving transistor T1, with a value range from -0.1V to 0.1V; the ordinate is the current deviation ΔI of the light-emitting current of the light-emitting device EL. Figure 4 and Figure 5Each curve contains four relationship curves, corresponding to four test conditions: the second power supply voltage line VSS provides a 3V second power supply voltage with internal compensation; the second power supply voltage line VSS provides a 3V second power supply voltage without internal compensation; the second power supply voltage line VSS provides a -1V second power supply voltage with internal compensation; and the second power supply voltage line VSS provides a -1V second power supply voltage without internal compensation. Figure 4 In the data, when the threshold voltage drift Vth_shift deviates from 0V, the current deviation ΔI corresponding to the curve without internal compensation is generally higher than that of the curve with internal compensation. Furthermore, the current deviation ΔI corresponding to the curve with the second power supply voltage line VSS providing a -1V second power supply voltage and internal compensation is at its lowest level. On the vertical axis, the current deviation ΔI corresponding to the curve with the second power supply voltage line VSS providing a 3V second power supply voltage and without internal compensation (W / O_Comp_VSS=3V) > the current deviation ΔI corresponding to the curve with the second power supply voltage line VSS providing a 3V second power supply voltage and internal compensation (Inter_Comp_VSS=3V) > the current deviation ΔI corresponding to the curve with the second power supply voltage line VSS providing a -1V second power supply voltage and without internal compensation (W / O_Comp_VSS=-1V) > the current deviation ΔI corresponding to the curve with the second power supply voltage line VSS providing a -1V second power supply voltage and internal compensation (Inter_Comp_VSS=-1V). Figure 5 In the above, when the threshold voltage drift Vth_shift deviates from 0V, the current deviation ΔI corresponding to the curve where the second power supply voltage line VSS provides a second power supply voltage of 3V and internal compensation is performed is at its lowest level; on the vertical axis, the current deviation ΔI corresponding to the curve where the second power supply voltage line VSS provides a second power supply voltage of 3V and no internal compensation is (W / O_Comp_VSS=3V) > the current deviation ΔI corresponding to the curve where the second power supply voltage line VSS provides a second power supply voltage of -1V and no internal compensation is (W / O_Comp_VSS=-1V) > the current deviation ΔI corresponding to the curve where the second power supply voltage line VSS provides a second power supply voltage of -1V and internal compensation is (Inter_Comp_VSS=-1V) > the current deviation ΔI corresponding to the curve where the second power supply voltage line VSS provides a second power supply voltage of 3V and internal compensation is (Inter_Comp_VSS=3V).

[0053] The aforementioned method for dynamically adjusting the voltage of the second power supply line VSS is achieved through the coordinated control of the display driver chip and the power management chip PMIC. Specifically, the display driver chip analyzes the average image level or regional grayscale value data of the current image frame in real time. When it is determined that the display panel DP is in a low grayscale display state, the display driver chip sends a control command to the power management chip PMIC. In response to the control command, the power management chip PMIC synchronously outputs a -1V second power supply voltage during the compensation phase; in a high grayscale display state, the power management chip PMIC switches to outputting a 3V second power supply voltage. The technical solution of this application improves the compensation effect across the entire grayscale range without increasing the complexity of the internal circuitry of the pixel PX.

[0054] The technical solution of this application provides a display device. The display panel DP of the display device includes a display area AA and a non-display area PA. The display panel DP also includes multiple pixel rows and multiple control circuits. Each pixel row includes multiple pixels PX. Each pixel PX is disposed in the display area AA and includes a driving transistor T1. The control circuits are disposed in the non-display area PA, and each control circuit is electrically connected to the driving transistors T1 of the multiple pixels PX in a pixel row. Because the control circuits are disposed in the non-display area PA rather than in each pixel PX within the display area AA, the number of transistors inside each pixel PX is reduced, and the arrangement space inside each pixel PX is saved. Under the same pixel size conditions, the reduction in the number of transistors inside each pixel PX is beneficial to improving the aperture ratio of the display panel DP; under the same aperture ratio conditions, the reduction in the number of transistors inside each pixel PX is beneficial to reducing the pixel size to increase the pixel density. Furthermore, since the control circuit is located in the non-display area PA and shared by multiple pixels PX in the same pixel row, the first control transistor T4 and the second control transistor T5 in the control circuit no longer occupy space inside the pixel PX. This reduces the parasitic capacitance load on the nodes inside the pixel PX, and the potential change during the compensation stage is closer to the theoretically derived model. This improves the compensation effect on the threshold voltage and mobility of the driving transistor T1, thereby enhancing the brightness uniformity of the image displayed on the display panel DP. Further, because the space in the non-display area PA is relatively ample, the transistors in the control circuit are sized sufficiently during fabrication to meet the current carrying capacity required to drive the entire row of pixels PX, reducing the voltage drop on the first power supply line VDD. Moreover, since the control circuit is located in the non-display area PA, the signal lines electrically connected to the control circuit only need to be electrically connected to the transistors in the control circuit within the non-display area PA. This reduces the overlap of traces within the display area AA, lowering the probability of pixel PX defects caused by short circuits or open circuits during manufacturing, which is beneficial for improving the overall yield of the display panel DP.

[0055] The technical solution of this application also provides a driving method for a display device. In the initialization phase P1 and data writing phase P2 of the driving cycle in which the display panel DP displays a frame, the driving method provides a turn-off level to the gate of the first control transistor T4, turning off the first control transistor T4 and isolating the electrical connection between the first power supply voltage line VDD and the driving transistor T1 inside the pixel PX, thus avoiding short circuits or crosstalk between the first power supply voltage and the first initialization voltage. In the compensation phase P3 of the driving cycle, the driving method provides a conduction level to the gate of the first control transistor T4, turning on the first control transistor T4. The first power supply voltage line VDD provides the first power supply voltage to the driving transistor T1 through the first control transistor T4, and the first power supply voltage charges the second node S connected to the source or drain of the driving transistor T1 through the first control transistor T4 and the driving transistor T1. Since the potential rise rate of the second node S is directly related to the threshold voltage and mobility of the driving transistor T1, the driving transistor T1 with a higher mobility or a lower threshold voltage charges faster, resulting in a larger potential rise of the second node S connected to the source or drain of the driving transistor T1, and the gate-source voltage of the driving transistor T1 is adaptively reduced. Conversely, the driving transistor T1 with a lower mobility or a higher threshold voltage charges slower, resulting in a smaller potential rise of the second node S connected to the source or drain of the driving transistor T1, and a smaller reduction in the gate-source voltage of the driving transistor T1. During the light-emitting stage P4, the first control transistor T4 remains on, and the driving current flows stably to the light-emitting device EL. The technical solution of this application automatically compensates for the differences in threshold voltage and mobility between different driving transistors T1 through the above driving timing, making the driving current of each pixel PX more consistent, and improving the brightness uniformity of the image displayed on the display panel DP.

[0056] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, characterized in that, The display device includes a display panel, the display panel includes a display area and a non-display area, and the display panel further includes: Multiple pixel rows, each pixel row comprising multiple pixels, the pixels being disposed in the display area, each pixel including a driving transistor; and Multiple control circuits are disposed in the non-display area, and one of the control circuits is electrically connected to the driving transistors of multiple pixels in a pixel row.

2. The display device according to claim 1, characterized in that, The gate of the driving transistor is electrically connected to the first node, one of the source and drain is electrically connected to the second node, and the other of the source and drain is electrically connected to the third node. The control circuit includes: A first control transistor, wherein the gate of the first control transistor is electrically connected to a first light-emitting control signal line, one of its source and drain is electrically connected to a first power supply voltage line, and the other of its source and drain is electrically connected to the third node; and The second control transistor has its gate electrically connected to the second light-emitting control signal line, one of its source and drain electrically connected to the first initialization voltage line, and the other of its source and drain electrically connected to the third node.

3. The display device according to claim 2, characterized in that, The first light emission control signal line is used to control the first control transistor to turn off during the initialization phase and data writing phase of the driving cycle in which a frame of image is displayed on the display panel, and to control the first control transistor to turn on during the compensation phase and light emission phase of the driving cycle.

4. The display device according to claim 2, characterized in that, The second light emission control signal line is used to control the second control transistor to turn on during at least one of the initialization phase and the data writing phase in the driving cycle of displaying a frame of the image on the display panel.

5. The display device according to claim 2, characterized in that, The pixels also include: The first switching transistor has its gate electrically connected to the first scan signal line, one of its source and drain electrically connected to the data signal line, and the other of its source and drain electrically connected to the first node. The second switching transistor has its gate electrically connected to the second scan signal line, one of its source and drain electrically connected to the second initialization voltage line, and the other of its source and drain electrically connected to the second node. A storage capacitor, wherein a first plate of the storage capacitor is electrically connected to the first node, and a second plate is electrically connected to the second node; and The light-emitting device has its anode electrically connected to the second node and its cathode electrically connected to the second power supply voltage line.

6. The display device according to claim 5, characterized in that, The channel width of at least one of the first control transistor and the second control transistor is greater than the channel width of any one of the driving transistor, the first switching transistor, and the second switching transistor.

7. The display device according to claim 5, characterized in that, The second power supply voltage line is used to provide different voltage values ​​according to the target grayscale value of the pixel.

8. The display device according to claim 7, characterized in that, The second power supply voltage line is used to provide a first voltage when the target grayscale value is within a first grayscale value range, and to provide a second voltage when the target grayscale value is within a second grayscale value range, wherein the maximum grayscale value in the first grayscale value range is less than the minimum grayscale value in the second grayscale value range, the first voltage is -2V to 0V, and the second voltage is 0.1V to 5V.

9. The display device according to claim 5, characterized in that, The first scan signal line is used to output a first-type level signal during the initialization phase. The second scan signal line is used to output a first-type level signal during the initialization phase. The second initialization voltage line is used to provide a second initialization voltage to the second node via the second switching transistor during the initialization phase. The first scan signal line is used to output a first-type level signal during the data writing phase. The second scan signal line is used to output a first-type level signal during the data writing phase. The data signal line is used to provide a data voltage to the first node via the first switching transistor during the data writing phase. The first scan signal line is used to maintain the output of the first-type level signal during the compensation phase. The second scan signal line is used to switch to a second-type level signal during the compensation phase. The second switching transistor is turned off during the compensation phase. The first power supply voltage line is used to charge the second node via the first control transistor and the driving transistor during the compensation phase. The first scan signal line is used to switch to a second-type level signal during the light emission phase. The first switching transistor is turned off during the light emission phase. The storage capacitor is used to maintain the potential difference between the first node and the second node during the light emission phase. The light-emitting device is used to emit light during the light emission phase.

10. A driving method for a display device, characterized in that, The display device includes a display panel, which includes a display area and a non-display area. The display panel also includes multiple pixel rows and multiple control circuits. Each pixel row includes multiple pixels, each pixel is disposed in the display area, and each pixel includes a driving transistor. Each control circuit is disposed in the non-display area. One control circuit is electrically connected to the driving transistors of the multiple pixels in one pixel row. Each control circuit includes a first control transistor and a second control transistor. The driving method includes: During the initialization and data writing phases of the drive cycle for displaying a frame on the display panel, a turn-off level is provided to the gate of the first control transistor, thus turning off the first control transistor; and During the compensation and light-emitting phases of the driving cycle, a conduction level is provided to the gate of the first control transistor, the first control transistor is turned on, a first power supply voltage line provides a first power supply voltage to the driving transistor via the first control transistor, and charges one of the source and drain of the driving transistor via the driving transistor.

11. The driving method according to claim 10, characterized in that, The pixel also includes a first switching transistor, a second switching transistor, and a storage capacitor; The driving method further includes: During the initialization phase, the first scan signal line outputs a first-type level signal, the second scan signal line outputs a first-type level signal, and the second initialization voltage line provides a second initialization voltage to one of the source and drain of the driving transistor via the second switching transistor. During the data writing phase, the first scan signal line outputs a first-level signal, the second scan signal line outputs a first-level signal, and the data signal line provides a data voltage to the gate of the driving transistor via the first switching transistor. During the compensation phase, the first scan signal line maintains a first-type level signal output, the second scan signal line switches to a second-type level signal, the second switching transistor is turned off, and the first power supply voltage line charges one of the source and drain of the driving transistor via the first control transistor and the driving transistor; and During the light-emitting phase, the first scan signal line switches to a second-level signal, the first switching transistor is turned off, and the storage capacitor maintains the potential difference between the gate of the driving transistor and one of the source or drain of the driving transistor, causing the light-emitting device to emit light.

12. The driving method according to claim 10, characterized in that, The driving method further includes: Adjust the voltage value of the second power supply voltage line according to the target grayscale value of the pixel.

13. The driving method according to claim 12, characterized in that, The step of adjusting the voltage value of the second power supply voltage line according to the target gray value of the pixel includes: When the target grayscale value is within a first grayscale value range, a first voltage is provided to the second power supply voltage line, wherein the first voltage is -2V to 0V; and / or When the target grayscale value is within the second grayscale value range, a second voltage is provided to the second power supply voltage line, the second voltage being 0.1V to 5V.

14. The driving method according to claim 10, characterized in that, The driving method further includes: In at least one of the initialization phase and the data writing phase, a conduction level is provided to the gate of the second control transistor, the second control transistor is turned on, and a first initialization voltage line provides a first initialization voltage to the driving transistor via the second control transistor.

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