Display panel and display device

Abstract

The application relates to the technical field of display, and particularly discloses a display panel and a display device, the display panel comprises a pixel circuit array, is located in a displayable area, and comprises a plurality of pixel circuits arranged in an array; the row direction of the pixel circuit array intersects with the column direction; a display driving module is electrically connected with the pixel circuit array, is used for determining a target display area, and provides a data signal to the pixel circuit located in the target display area; wherein the area of the target display area is less than or equal to the display area of the displayable area; the display driving module adjusts the position of the target display area in the row direction of the pixel circuit array every first preset time, and / or the display driving module adjusts the position of the target display area in the column direction of the pixel circuit array every second preset time. The display panel utilizes the display driving module to realize driving control on the pixel circuit array, and the position of the actual display image in the display panel can be moved in the row direction and / or the column direction.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a display panel and display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and flat panel displays based on light-emitting diodes (LEDs) are widely used in various consumer electronics products such as mobile phones, televisions, laptops, and desktop computers due to their advantages such as high image quality, energy saving, thin body and wide range of applications, becoming the mainstream of display devices.

[0003] However, the performance of current OLED display products needs to be improved. Summary of the Invention

[0004] Therefore, it is necessary to provide a display panel and display device to address the issue of the performance of current OLED display products needing improvement.

[0005] A display panel includes a displayable area and a non-display area disposed around at least a portion of the displayable area, the display panel comprising:

[0006] A pixel circuit array is located in the displayable area, the pixel circuit array comprising a plurality of pixel circuits arranged in an array; the row direction and column direction of the pixel circuit array intersect; the pixel circuits are used to drive light-emitting devices to emit light; A display driving module is electrically connected to the pixel circuit array and is used to determine a target display area in the pixel circuit array and provide data signals to the pixel circuit located in the target display area; wherein the area of ​​the target display area is less than or equal to the display area of ​​the displayable area; The display driving module adjusts the position of the target display area in the row direction of the pixel circuit array every first preset time interval, and / or the display driving module adjusts the position of the target display area in the column direction of the pixel circuit array every second preset time interval.

[0007] In one possible implementation, the display driving module includes thin-film transistors.

[0008] In one possible implementation, the pixel circuit includes thin-film transistors, and at least a portion of the active layer of the thin-film transistors in the display driving module is disposed on the same layer as at least a portion of the active layer of the thin-film transistors in the pixel circuit.

[0009] In one possible implementation, the display driving module includes a control module, a data driving module, and a gate driving module. The control module is electrically connected to the data driving module and the gate driving module. The data driving module is electrically connected to the pixel circuit via a data line, and the gate driving module is electrically connected to the pixel circuit via a gate line. The control module is used to output a first position parameter and / or a second position parameter. The control module adjusts the first position parameter every first preset time interval and adjusts the second position parameter every second preset time interval. The data driving module is used to determine the target pixel circuit column according to the first position parameter, and transmit the data signal to the data line corresponding to the target pixel circuit column; The gate driving module is used to determine the target pixel circuit row according to the second position parameter and control the data signal to be written into the target pixel circuit row. Wherein, the number of target pixel circuit columns is less than or equal to the total number of columns of pixel circuits in the pixel circuit array, and the number of target pixel circuit rows is less than or equal to the total number of rows of pixel circuits in the pixel circuit array.

[0010] In one possible implementation, the control module includes a counter, a first parameter register, a second parameter register, and a trigger signal generator. The counter is electrically connected to both the first parameter register and the second parameter register. The first parameter register is electrically connected to the data driving module, the second parameter register is electrically connected to the trigger signal generator, and the trigger signal generator is electrically connected to the gate driving module. When the first count of the counter reaches the first preset value, the counter resets the first count to zero and outputs a first adjustment signal to the first parameter register; When the second count of the counter reaches the second preset value, the counter resets the second count to zero and outputs a second adjustment signal to the second parameter register; The first parameter register is used to store the first position parameter, which includes the coordinates of the enabled area of ​​the data driving module. The first parameter register is also used to offset the coordinates of the enabled area of ​​the data driving module along the row direction of the pixel circuit array according to the first adjustment signal, and to update the first position parameter. The second parameter register is used to store the second position parameter, which includes the coordinates of the enabled area of ​​the gate driving module. The second parameter register is also used to offset the coordinates of the enabled area of ​​the gate driving module along the column direction of the pixel circuit array according to the second adjustment signal, and to update the second position parameter. The trigger signal generator is used to output a trigger signal to the gate drive module according to the second position parameter.

[0011] In one possible implementation, the data driving module includes a shift register, a row buffer, and a discharge logic unit. The row buffer is electrically connected to the control module and is used to determine the enabled channel in the row buffer according to the first position parameter. The shift register is electrically connected to the row buffer and is used to receive image data and write the image data into the enabled channel in the row buffer. The row buffer is electrically connected to the discharge logic unit, which is used to convert the image data temporarily stored in the row buffer into a data signal and transmit the data signal to the data line corresponding to the target pixel circuit column.

[0012] In one possible implementation, the data driving module further includes a level converter electrically connected between the row buffer and the discharge logic unit, the level converter being used to convert the incoming signal from a first voltage domain to a second voltage domain.

[0013] In one possible implementation, the voltage value of the output signal of the level converter is greater than the voltage value of the input signal of the level converter.

[0014] In one possible implementation, the pixel circuit array includes n+k columns of pixel circuits, and each column of pixel circuits is electrically connected to the data driving module via a data line. The number of target pixel circuit columns is n, where n and k are both positive integers.

[0015] In one possible implementation, the data driving module includes a shift register, a row buffer, a level shifter, and a discharge logic unit. The shift register includes n first channels, the row buffer includes n+k second channels, the level shifter includes n+k third channels, and the discharge logic unit includes n+k fourth channels. One second channel is electrically connected to one corresponding third channel, one third channel is electrically connected to one corresponding fourth channel, and one fourth channel is electrically connected to a column of pixel circuits via a data line. The row buffer is electrically connected to the control module and is used to determine n enabled channels in the row buffer according to the first position parameter; The shift register is used to receive image data, and the n first channels transmit the image data to the n enabled channels in the row buffer; The row buffer transmits the image data to the n third channels connected to the n enabled channels to perform level conversion on the image data; The level converter transmits the image data after level conversion to the n fourth channels corresponding to the n third channels, so as to convert the image data into the data signal; The discharge logic unit transmits the data signal to the n columns of target pixel circuits connected to the n fourth channels.

[0016] In one possible implementation, after the row buffer determines the n enabled channels in the row buffer according to the first position parameter, it sets the data stored in the other second channels besides the n enabled channels to zero.

[0017] A display device, such as the display panel described in any of the above embodiments. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the display panel structure in one embodiment of this application; Figure 2 This is a schematic diagram of the display panel structure in another embodiment of this application; Figure 3 This is a schematic diagram of the pixel circuit structure in one embodiment of this application; Figure 4 This is a schematic diagram of the control module in one embodiment of this application; Figure 5 This is a schematic diagram of the data-driven module in one embodiment of this application; Figure 6 This is a schematic diagram of the display panel structure in another embodiment of this application; Figure 7 This is a schematic diagram of the display panel in a first display state in one embodiment of this application; Figure 8 This is a schematic diagram of the display panel in a second display state in one embodiment of this application; Figure 9 This is a schematic diagram illustrating the relative relationship between the trigger signal and the data signal in one embodiment of this application; Figure 10 This is a schematic diagram of the display panel in a third display state in one embodiment of this application; Figure 11 This is a schematic diagram illustrating the relative relationship between the trigger signal and the data signal in another embodiment of this application; Figure 12 This is a schematic diagram of the display panel in a fourth display state in one embodiment of this application; Figure 13 This is a schematic diagram of the structure of a display device in one embodiment of this application. Detailed Implementation

[0020] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of the invention.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0022] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0023] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0024] In this application, unless otherwise expressly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium, or they can refer to the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0025] AMOLED (Active Matrix Organic Light Emitting Diode) displays use organic materials to create light-emitting devices and TFTs (Thin Film Transistors) to construct pixel circuits. Pixels are arranged in an array, and the display uses a progressive scan refresh method. With technological advancements, AMOLED display technology has been further upgraded, developing the use of TFT devices and arrayed film capacitors to construct display driver ICs (Integrated Circuits). However, in existing solutions, the driver IC can only output image signals at fixed positions, thus the display screen can only display images at fixed positions.

[0026] To address the aforementioned technical problems, this application provides a display panel and a display device. The following description, in conjunction with the accompanying drawings, will illustrate various embodiments of the display panel and the display device.

[0027] This application provides a display panel, which may be an organic light-emitting diode (OLED) display panel. Figure 1 This is a schematic diagram of the structure of a display panel in one embodiment of this application. The display panel 10 provided in this embodiment may include a displayable area AA and a non-display area NA surrounding at least a portion of the displayable area AA. The display panel 10 may include a pixel circuit array 100 and a display driving module 200. The displayable area AA refers to the area where light-emitting devices are provided, enabling image display using these devices.

[0028] The display panel 10 can be applied to any product or component with display function, including but not limited to the following categories: mobile phones, televisions, digital cameras, tablet computers, laptops, desktop monitors, smart bracelets, smart glasses, in-vehicle displays, medical devices, industrial control equipment, touch interactive terminals, etc. The embodiments of the present invention do not impose any special limitations on this.

[0029] The displayable area AA of the display panel 10 can be rectangular, square, circular, elliptical, or other shapes. Preferably, the non-display area NA surrounds the entire displayable area AA and is an annular shape corresponding to the shape of the displayable area AA. For example, when the displayable area AA is rectangular, the shape of the non-display area NA is a rectangular ring; when the displayable area AA is circular, the shape of the non-display area NA is an annular ring.

[0030] Pixel circuit array 100 is located in the displayable area AA. Pixel circuit array 100 may include multiple pixel circuits 110 arranged in an array. Pixel circuits 110 can be used to control the light emission of light-emitting elements. The combination of pixel circuits 110 and light-emitting elements can be the smallest controllable light-emitting unit in the display panel 10. The row direction and column direction of pixel circuit array 100 intersect. For example, the first direction X is the row direction, and the second direction Y is the column direction. Figure 1 As shown, multiple pixel circuits 110 are arranged in rows and columns along the intersecting first direction X and second direction Y. Each pixel circuit 110 may include circuits for driving different light-emitting elements, such as red, green, and blue light-emitting elements, but is not limited to these. The pixel arrangement of the different colored light-emitting elements is not limited and can be set according to actual needs.

[0031] The display driving module 200 can be electrically connected to the pixel circuit array 100. The display driving module 200 can be used to determine a target display area in the pixel circuit array 110 and provide data signals to the pixel circuits 110 located in the target display area. The area of ​​the target display area is less than or equal to the display area of ​​the pixel circuit array 100. In this embodiment, the display area of ​​the displayable area AA can refer to the area of ​​the display area when all pixel circuits 110 in the pixel circuit array 100 simultaneously drive their corresponding connected light-emitting elements to emit light, that is, the area of ​​the usable display area of ​​the pixel circuit array 100. The target display area can refer to the actual light-emitting area of ​​the pixel circuit array 100. The target display area can be less than or equal to the display area of ​​the displayable area AA. That is, when the display panel 10 is actually used for display, all pixel circuits 110 can drive their corresponding light-emitting elements to emit light, or some pixel circuits 110 can drive their light-emitting elements to emit light while others do not.

[0032] The display driving module 200 adjusts the position of the target display area in the row direction of the pixel circuit array 100 every first preset time interval, and / or, the display driving module 200 adjusts the position of the target display area in the column direction of the pixel circuit array 100 every second preset time interval. The first preset time interval and the second preset time interval can be the same or different. Simultaneously, the displacement of the new target display area determined by the display driving module 200 each time relative to the previous target display area can be the same or different. For example, a new target display area determined by the display driving module 200 in the pixel circuit array 110 after a 16.6ms interval is shifted by one pixel circuit column distance in the row direction of the pixel circuit array 100 compared to the previously determined target display area; a new target display area determined by the display driving module 200 in the pixel circuit array 110 after a 20ms interval is shifted by three pixel circuit rows distance in the column direction of the pixel circuit array 100 compared to the previously determined target display area.

[0033] The display panel provided in this application utilizes a display driving module 200 to select a target display area within the pixel circuit array 100 and provides data signals to the pixel circuits 110 located in the target display area. Simultaneously, the display driving module 200 adjusts the position of the target display area in the row direction of the pixel circuit array 100 at first preset time intervals, and / or adjusts the position of the target display area in the column direction of the pixel circuit array 100 at second preset time intervals. That is, the image displayed on the display panel moves periodically in the row and / or column directions.

[0034] In existing technologies, when a display panel needs to display a static image, the IC outputs an image signal at a fixed position, and the display panel displays the image at that fixed position. However, the applicant has discovered that when the pixel brightness at a fixed position on the display panel remains high for an extended period, image retention occurs. The display panel provided in this application utilizes a display driver module 200 to drive and control the pixel circuit array 100, allowing the actual display position of the image to move in the row and / or column directions. When displaying static or dynamic images, the display driver module 200 can cause a slight movement in the image's display position. This slight change in image position will not attract the user's attention and will not affect functionality. Simultaneously, this slight change in image position can reduce image retention or blur the boundaries of long-term image retention, making it less noticeable.

[0035] In one possible implementation, the display driving module 200 includes a thin-film transistor (TFT). That is, the circuit architecture of the display driving module 200 can be constructed based on TFTs. This application does not limit the specific circuit architecture of the display driving module 200, as long as the circuit architecture of the display driving module 200 can drive the pixel circuit 110. Compared to using rigid silicon-based ICs to drive the display panel, the display panel provided in this application uses a display driving module 200 constructed based on TFTs. TFTs are flexible devices, enabling the display panel to be applied to flexible display products. Furthermore, because the driving system constructed with TFTs can be integrated into the display panel, it can be packaged uniformly with other structures of the display panel. Compared to the packaging structure of silicon-based ICs, this reduces space requirements and thus reduces volume.

[0036] Thin-film transistors (TFTs) come in N-type and P-type types. N-type and P-type TFTs can be fabricated using low-temperature polysilicon (LTPS), or N-type TFTs can be fabricated using amorphous silicon (a-Si) or indium gallium zinc oxide (IGZO). N-type and P-type TFTs can be used to construct digital logic gates such as NAND gates, NOR gates, and NOT gates. Furthermore, digital logic gates can be used to construct the display driving module 200, achieving a micro-shifting effect on the actual displayed image of the pixel circuit array 100. This micro-shifting reduces image retention, making the edges of image retention on the display panel blurry and less noticeable.

[0037] In one possible implementation, the pixel circuit 110 can be used to drive a light-emitting element to emit light. The pixel circuit 110 is electrically connected to a corresponding gate line GL and a corresponding data line DL. The pixel circuit 110 may include at least one thin-film transistor (TFT), the gate of which may be disposed on the same layer as multiple gate lines GL, and the source and drain of which may be disposed on the same layer as multiple data lines DL. For an OLED display panel, the pixel circuit 110 may also include an organic light-emitting device driven by the pixel circuit 110.

[0038] In one possible implementation, the active layers of at least some of the thin-film transistors in the display driving module 200 are disposed on the same layer as the active layers of at least some of the thin-film transistors in the pixel circuit 110. This allows the display driving module 200 and the pixel circuit array 100 to be integrated together within the array substrate, replacing the rigid silicon-based IC with a display driving module 200 composed entirely of thin-film transistors, thus ensuring that the display panel can be better applied to flexible display products. This embodiment can simultaneously display at least some of the thin-film transistors in the display driving module 200 and at least some of the thin-film transistors in the pixel circuit 110 through the same process steps, thereby simplifying the process.

[0039] For example, the pixel circuit 110 includes a P-type thin film transistor, and the active layer of the P-type thin film transistor in the display driving module 200 and the active layer of the P-type thin film transistor in the pixel circuit 110 are both disposed on the same layer.

[0040] In the case where the pixel circuit 110 includes only P-type thin-film transistors and not N-type thin-film transistors, and the display driving module 200 includes N-type thin-film transistors, the active layer of the N-type thin-film transistor in the display driving module 200 and the active layer of the P-type thin-film transistor in the pixel circuit 110 can be located in different film layers.

[0041] The display panel may include a substrate and a driving device layer located on one side of the substrate. The driving device layer may include thin-film transistors in the pixel circuit 110 or thin-film transistors in the display driving module 200. That is, the pixel driving circuit of the pixel circuit 110 and the thin-film transistors used to build the display driving module 200 may both be formed in the driving device layer, and the display driving module 200 is not an external structure of the display panel.

[0042] In one possible implementation, Figure 2 This is a schematic diagram of the display panel structure in another embodiment of this application. The display driving module 200 may include a control module 210, a data driving module 220, and a gate driving module 230. The control module 210 is electrically connected to both the data driving module 220 and the gate driving module 230. The data driving module 220 can be electrically connected to the pixel circuit 110 via a data line DL, and the gate driving module 230 can be electrically connected to the pixel circuit 110 via a gate line GL.

[0043] The data line DL extends along the second direction Y, and one data line DL can be electrically connected to multiple pixel circuits 110 in the same column. In some embodiments, one data line DL can connect multiple columns of pixel circuits 110. The gate line GL extends along the first direction X, and one gate line GL is electrically connected to multiple pixel circuits 110 in the same row. In some embodiments, one gate line GL can connect multiple rows of pixel circuits 110.

[0044] In some embodiments, the control module 210, data driving module 220, and gate driving module 230 all include thin-film transistors. The active layers of at least a portion of the thin-film transistors in the control module 210, data driving module 220, and gate driving module 230 are disposed on the same layer as the active layers of at least a portion of the thin-film transistors in the pixel circuit 110. The control module 210, data driving module 220, and gate driving module 230 are constructed using pure thin-film transistors to replace rigid silicon-based ICs.

[0045] The control module 210 can be used to output a first position parameter and / or a second position parameter. The first position parameter can be used to indicate the target pixel circuit column corresponding to the target display area, and the second position parameter can be used to indicate the target pixel circuit row corresponding to the target display area. The control module adjusts the first position parameter every first preset time interval and adjusts the second position parameter every second preset time interval. That is, by periodically updating the first position parameter and / or the second position parameter, the control module drives the selection of new target pixel circuit columns and / or target pixel circuit rows for image display.

[0046] The data driving module 220 can be used to determine the target pixel circuit column according to the first position parameter and transmit the data signal to the data line DL corresponding to the target pixel circuit column. The gate driving module 230 can be used to determine the target pixel circuit row according to the second position parameter and control the data signal to be written to the target pixel circuit row.

[0047] Specifically, the number of target pixel circuit columns is less than or equal to the total number of pixel circuit columns in pixel circuit array 100, and the number of target pixel circuit rows is less than or equal to the total number of pixel circuit rows in pixel circuit array 100. That is, the number of pixel circuits 110 corresponding to the target display area is less than or equal to the total number of pixel circuits 110 in pixel circuit array 100.

[0048] The control module 210 controls the operation of the data driving module 220 and the gate driving module 230. The data driving module 220 receives image data and converts it into a data signal, transmitting the data signal to the data line DL corresponding to the target pixel circuit column. The data line DL can write the data voltage Data of each row of pixel circuit 110 to the pixel circuit 10 corresponding to the target pixel circuit column row by row. The gate driver 23 inputs a gate driving signal to the gate line GL of the target pixel circuit row. The gate driving signal input to the gate line GL can scan and turn on the transistors of the pixel circuit 110 in the corresponding target pixel circuit row row by row to write the data signal to the corresponding pixel circuit 110.

[0049] In some specific implementations, the data driving module 220 can receive image data from the host system. The image data may include at least grayscale data of the image to be displayed. The data driving module 220 converts the image data into a data signal that can directly drive the pixel circuit 110.

[0050] Figure 3 This is a schematic diagram of the pixel circuit in one embodiment of this application. The pixel circuit 110 may include a driving transistor M1 and a switching transistor M2. The gate of the switching transistor M2 is connected to the gate line GL, the first electrode of the switching transistor M2 is connected to the data line DL, the second electrode of the switching transistor M2 is connected to the gate of the driving transistor M1, the first electrode of the driving transistor M1 is connected to the first power line ELVDD, the second electrode of the driving transistor M1 is connected to the anode of the light-emitting element 112, and the cathode of the light-emitting element 112 is connected to the second power line ELVSS. A capacitor may also be connected between the gate of the driving transistor M1 and the first power line ELVDD.

[0051] When the gate drive signal output by the gate drive module 230 scans to the corresponding pixel circuit 110 in the target pixel circuit row, the switching transistor M2 turns on according to the on-level, so that the data signal transmitted on the data line DL can be written into the gate of the driving transistor M1. The driving transistor M1 generates a driving current based on the data signal, thereby driving the light-emitting element 112 to emit light. The magnitude of the data signal will affect the magnitude of the driving current generated by the driving transistor M1. Furthermore, the light-emitting element 112 emits light of different brightness based on different driving currents.

[0052] It should be noted that, Figure 3 The pixel circuit structure shown is merely an example and is not intended to limit this application; other pixel circuit structures are also possible.

[0053] In one possible implementation, Figure 4 This is a schematic diagram of the control module in one embodiment of the present application. The control module 210 may include a counter 211, a first parameter register 212, a second parameter register 213, and a trigger signal generator 214. The counter 211 is electrically connected to the first parameter register 212 and the second parameter register 213. The first parameter register 212 is electrically connected to the data driving module 220. The second parameter register 213 is electrically connected to the trigger signal generator 214. The trigger signal generator 214 is electrically connected to the gate driving module 230.

[0054] When the first count of counter 211 reaches a first preset value, counter 211 resets the first count to zero and outputs a first adjustment signal to the first parameter register 212. For example, when counter 211 accumulates from 0 to the first preset value (e.g., 1125) and overflows, counter 211 resets the first count to zero and outputs a first adjustment signal. The first adjustment signal can be a signal used to instruct the first parameter register 212 to update the first position parameter. For example, the first adjustment signal can be a high-level pulse, and the first parameter register 212 adjusts the first position parameter according to the received high-level pulse.

[0055] When the second count of counter 211 reaches the second preset value, counter 211 resets the second count to zero and outputs a second adjustment signal to the second parameter register 213. For example, when counter 211 accumulates from 0 to the second preset value (e.g., 1200) and overflows, counter 211 resets the second count to zero and outputs a second adjustment signal. The second adjustment signal can be a signal used to instruct the second parameter register 213 to update the second position parameter. For example, the second adjustment signal can be a low-level pulse, and the second parameter register 213 adjusts the second position parameter according to the received low-level pulse.

[0056] In some embodiments, the first count and the second count can be the same, the first preset value and the second preset value are the same, and the first adjustment signal and the second adjustment signal are the same. For example, when counter 211 accumulates from 0 to a set value (e.g., 1025) and overflows, counter 211 will reset the count to zero and output a high-level pulse to the first parameter register 212 and the second parameter register 213. That is, at this time, the first parameter register 212 and the second parameter register 213 simultaneously update the first position parameter and the second position parameter.

[0057] In a preferred embodiment, counter 211 is a slow counter. The slow counter operates periodically (typically tens to hundreds of kHz) based on a low-frequency clock, and can be used to handle less time-critical tasks during the refresh cycle of the display panel. In this embodiment, the slow counter operates at a lower frequency, periodically instructing the first parameter register 212 and / or the second parameter register 213 to be updated, preventing excessively frequent displacement of the target display area from affecting the display effect of the content.

[0058] The first parameter register 212 can be used to store a first position parameter. The first position parameter may include the coordinates of the enabled area of ​​the data driving module 220. The first parameter register 212 can also be used to offset the coordinates of the enabled area of ​​the data driving module 220 along the row direction of the pixel circuit array 100 according to the first adjustment signal, and update the first position parameter. The offset distance of the enabled area coordinates in the data driving module 220 each time can be arbitrarily selected according to actual application requirements, for example, moving the distance of one pixel column in the same direction each time. For example, the data driving module 220 may include different output ports, different output ports are connected to different data lines DL, and different output ports are connected to different position coordinates. The first position parameter may store the position coordinates corresponding to the output ports connected to the target pixel circuit column, so that the data driving module 220 enables the corresponding output port according to the first position parameter, so that the data driving module 220 outputs a data signal to the enabled output port, and then transmits it to the target pixel circuit column through the data line DL connected to the enabled output port.

[0059] The second parameter register 213 can be used to store a second position parameter. The second position parameter may include the coordinates of the enabled area of ​​the gate driving module 230. The second parameter register 213 can also be used to offset the coordinates of the enabled area of ​​the gate driving module 230 along the column direction of the pixel circuit array 100 according to a second adjustment signal, and update the second position parameter. The offset distance of the enabled area coordinates of the gate driving module 230 can be arbitrarily selected according to actual application requirements; for example, moving the distance of one pixel row in the same direction each time. The trigger signal generator 214 can be used to output a trigger signal STV to the gate driving module 230 according to the second position parameter. The gate driving module 230 can determine the relative positional relationship between the trigger signal STV and the pixel circuit row where data is written in the first row based on the second position parameter. For example, the information stored in the second position parameter indicates that there is a gap of 3 pixel circuit rows between the trigger signal STV and the pixel circuit row where data is written in the first row. Based on the second position parameter, the switching transistor in the pixel circuit 110 corresponding to the target pixel circuit row can be controlled to be turned on.

[0060] In one possible implementation, the control module can also be used to generate other signals that drive the display panel, such as clock signals CLK1 and CLK2, or other signals that indicate the operation of the data driving module 220, the gate driving module 230, etc.

[0061] In one possible implementation, Figure 5 This is a schematic diagram of the structure of the data driving module in one embodiment of the present application. The data driving module 220 may include a shift register 221, a row buffer 222, and a discharge logic unit 223.

[0062] The row buffer 222 can be electrically connected to the control module 210. The row buffer 222 can be used to determine the enabled channel in the row buffer 222 according to the first position parameter. The shift register 221 can be electrically connected to the row buffer 222. The shift register 221 can be used to receive image data and write the image data into the enabled channel in the row buffer 222. The row buffer 222 can be electrically connected to the discharge logic unit 223. The discharge logic unit 223 can be used to convert the image data temporarily stored in the row buffer into a data signal and transmit the data signal to the data line DL corresponding to the target pixel circuit column.

[0063] Shift register 221, also known as the shift register, can receive serial image data from the host system (such as a graphics card). Shift register 221 can store an entire line of display data. When shift register 221 is full of data for an entire line, it will transfer that line of data to the line buffer 222 in parallel, all at once. The enabled channel in line buffer 222 writes the image data for each line of pixel circuits. After writing the data voltage (Data) for one line of pixel circuits, shift register 221 receives the image data for the next line of pixel circuits, and the above process is repeated.

[0064] Once all the image data corresponding to a row of pixel circuits 110 is written into the row buffer 222, the row buffer 222 can latch the entire row of image data in parallel. Before writing the image data corresponding to the next row of pixel circuits 110, the data in the row buffer 222 will remain unchanged as the data of the current row. The row buffer synchronously outputs to the discharge logic unit 223, which can convert the image data of the current row stored in the row buffer 222 into a data signal and apply it to the pixel circuits 110 in the target pixel circuit column through the data line DL corresponding to the target pixel circuit column. It can be understood that at this time, the gate driving module 230 scans the target pixel circuit rows sequentially according to the second position parameter, that is, the gate driving module 230 controls the thin-film transistors used for data writing in the target pixel circuit rows to be in the on state.

[0065] Once all pixel circuits 110 located in the target display area have been written with data signals, the display of one frame of image in the target display area is completed. The display driving module 200 adjusts the first position parameter and / or the second position parameter at regular intervals to shift the target display area in the row direction and / or column direction, thereby realizing the micro-movement of the displayed image in different directions.

[0066] The shift register 221, row buffer 222, and discharge logic unit 223 may all include thin-film transistors. In this embodiment, the shift register 221, row buffer 222, and discharge logic unit 223 work together to form a simple function similar to a silicon-based IC, realizing the provision of data signals required for display driving to the pixel circuit 110 located in the target display area. The signal output by the data driving module 220, which is composed of TFTs, is an analog voltage signal of image data, and the voltage value represents the size of the display grayscale. The data driving module 220 is integrated with the pixel circuit array 100 of the display area AA in the same display panel and is produced by the array process of the display panel.

[0067] In one possible implementation, the data driving module 220 may further include a level shifter. The level shifter may be electrically connected between the line buffer 222 and the discharge logic unit 223, and may be used to convert the incoming signal from a first voltage domain to a second voltage domain.

[0068] For example, the high voltage of the second voltage domain is greater than the high voltage of the first voltage domain, and the low voltage of the second voltage domain is lower than the low voltage of the first voltage domain. For instance, the high voltage of the second voltage domain is VGH, the low voltage of the second voltage domain is VGL, the high voltage of the first voltage domain is VDD, the low voltage of the first voltage domain is VSS, and VGH > VDD, VGL < VSS.

[0069] For example, the signal level received from the host system is in a first voltage domain, which has a lower voltage, such as 1.8V or 3.3V. In this embodiment, by setting a level shifter, at least some circuits in the display driver module 200 can operate in a high voltage domain to improve signal integrity and thus improve the reliability of the display panel.

[0070] In some embodiments, the level shifting circuit includes a thin-film transistor; for example, an N-type thin-film transistor and a P-type thin-film transistor can be used to construct the level shifter.

[0071] In one possible implementation, the voltage value of the output signal of the level converter is greater than the voltage value of the input signal of the level converter. That is, the level converter is used to convert an input signal with a smaller voltage value into an output signal with a larger voltage value. The function of the level converter is to change the high and low voltage values ​​of the input signal, but not to change the phase of the signal.

[0072] In one possible implementation, the pixel circuit array 100 may include n+k columns of pixel circuits, and each column of pixel circuits is electrically connected to the data driving module 220 via a data line DL. The number of target pixel circuit columns is n, where n and k are both positive integers.

[0073] In one possible implementation, Figure 6 The diagram below illustrates the structure of the display panel in another embodiment of this application. The data driving module 220 may include a shift register 221, a row buffer 222, a level converter 224, and a discharge logic unit 223. The shift register may include n first channels, the row buffer may include n+k second channels, the level converter may include n+k third channels, and the discharge logic unit may include n+k fourth channels. One second channel is electrically connected to one third channel, one third channel is electrically connected to one fourth channel, and one fourth channel is electrically connected to one column of pixel circuits via a data line.

[0074] like Figure 6 As shown, the number of first channels in the shift register 221 of the data driving module 220 is the same as the number of target pixel circuit columns, both being n. The number of second channels in the row buffer 222, the number of third channels in the level converter 224, and the number of fourth channels in the discharge logic unit 223 are all n+k, and the positions and connections of the n+k second channels, n+k third channels, and n+k fourth channels correspond one-to-one. That is, the number of channels in the row buffer 222, level converter 224, and discharge logic unit 223 is redundant relative to the number of target pixel circuit columns, and the redundant k channels in the row buffer 222, level converter 224, and discharge logic unit 223 can be used for horizontal image movement.

[0075] The line buffer 222 is electrically connected to the control module 210. The line buffer 222 can be used to determine the n enabled channels in the line buffer based on the first position parameter. More specifically, the line buffer 222 can be electrically connected to the first parameter register 212. The data of the first position parameter stored in the first parameter register 212 controls the enabled area of ​​the line buffer 222. When the data of the first position parameter stored in the first parameter register 212 is different, the second channel of the enabled line buffer 222 is different, thus the position of the output image is different.

[0076] Shift register 221 can be used to receive image data. The n first channels transmit image data to the n enabled channels in row buffer 222. Row buffer 222 transmits image data to the n third channels corresponding to the n enabled channels, where level converter 224 performs level conversion on the image data. Level converter 224 can also transmit the level-converted image data to the n fourth channels corresponding to the n third channels, where discharge logic unit 223 converts the image data into a data signal. Discharge logic unit 223 can also transmit the data signal to the n target pixel circuit columns corresponding to the n fourth channels, thus achieving the effect of transmitting the data signal to the n target pixel circuit columns.

[0077] like Figure 6 As shown, assuming the horizontal resolution of the display panel is n columns, the actual target display area is as indicated in the figure, and the number of target pixel circuit columns is n. The display panel 10 requires n+k data lines DL, and the total number of output channels of the data driver module 220 is also n+k. Figure 6 In the diagram, the solid black line extending from the non-display area NA to the display area AA is the data line DL. The number of data lines DL in the row direction in the pixel circuit array 100 is the same as the total capacity of the second channel of the row buffer 222, which is n+k.

[0078] The first parameter register 212 can be a counter. When the value of the first position parameter stored in the first parameter register 212 is 0, the enabled channels of the row buffer 222 are the 1st to nth second channels; when the value of the first position parameter stored in the first parameter register 212 is 1, the enabled channels of the row buffer 222 are the 2nd to n+1th second channels. And so on, when the value of the first position parameter stored in the first parameter register 212 is k, the enabled channels of the row buffer 222 are the k+1th to n+kth second channels. If the value of the first position parameter stored in the first parameter register 212 exceeds k and is set to 0, the enabled channels of the row buffer 222 are readjusted to the 1st to nth second channels.

[0079] In one possible implementation, Figure 7 This is a schematic diagram of the display panel in a first display state in one embodiment of this application. When the value of the first position parameter in the first parameter register 212 is 0, the actual n channel data used are stored in the first to nth second channels of the row buffer 222. The position of the target display area is as follows: Figure 7 As shown, the image is located in the left-hand area of ​​the pixel circuit array 100 and is displayed as follows. Figure 7The target display area is shown. Each row of the display screen has n data points, which are stored in the enabled channel of the row buffer 222. In some preferred embodiments, the area data stored in the other second channels of the row buffer 222 besides the enabled channel is 0. That is, when the display panel is working in this state, the pixel circuits corresponding to the inactive channels in the row buffer 222 do not emit light or are black; the enabled channels in the row buffer 222 are used to store cached data, and the pixel circuits 110 corresponding to the enabled channels in the row buffer 222 are used to provide the actual image. Figure 6 As shown, the actual data of the n channels used are stored in the first to the nth second channels of the row buffer 222. The enabled channels of the row buffer 222 are the first to the nth second channels.

[0080] Figure 8 This is a schematic diagram of the display panel in a second display state in one embodiment of this application. When the value of the first position parameter in the first parameter register 212 is k, as shown... Figure 8 The actual data used for the n channels is stored in the (k+1)th to (n+k)th second channels of the row buffer 222, and the image display positions are as follows. Figure 8 The image is located in the right-hand region of the pixel circuit array 100. It can be seen that the aforementioned display panel utilizes the first display parameter register 212 to achieve micro-movement of the displayed image horizontally within the display panel. As the first position parameter stored in the first parameter register 212 gradually increases, the target display area gradually moves horizontally from left to right.

[0081] In some other embodiments, the display panel described above may also be designed such that as the first position parameter stored in the first parameter register 212 gradually increases, the target display area gradually moves from right to left in the horizontal direction.

[0082] The control module 210 may include a trigger signal generator 214, which outputs a trigger signal STV. The trigger signal generator 214 determines the relative relationship between the pulse signal of the trigger signal STV and the first row of data writing based on a second position parameter. Under the control of the second position parameter, the relative position of the trigger signal STV pulse with respect to the first row of data writing pixel circuits changes, thereby achieving vertical movement of the image.

[0083] Figure 9 This is a schematic diagram illustrating the relative relationship between the trigger signal and the data signal in one embodiment of this application. Figure 10This is a schematic diagram of the display panel in a third display state in one embodiment of this application. When the value of the second position parameter in the second parameter register 213 is 0, the first row of data signals can be written to the top of the pixel circuit array 100. At this time, the waveforms of the trigger signal and the data signal are as follows: Figure 9 As shown (the numbers in the waveform represent the row numbers of the pixel circuits where valid data signals are written). When the value of the second position parameter in the second parameter register 213 is 0, the target pixel circuits where actual data is written are the pixel circuits from row 1 to row m (m is a positive integer), and the position of the target display area is as follows. Figure 10 As shown, the image is located in the upper region of the pixel circuit array 100 and is displayed as follows. Figure 10 The target display area is shown. In some preferred embodiments, after the valid data signal transmitted on the data line DL is written to the m target pixel circuit rows, the remaining pixel circuit rows may not be displayed, or a black screen may be displayed.

[0084] Figure 11 This is a schematic diagram illustrating the relative relationship between the trigger signal and the data signal in another embodiment of this application. Figure 12 This is a schematic diagram of the display panel in a fourth display state in one embodiment of this application. When the value of the second position parameter in the second parameter register 213 is p, the first row of image data is written to the first row of data signal at a position p rows down from the top in the column direction of the pixel circuit array 100. At this time, the waveforms of the trigger signal and the data signal are as follows: Figure 11 As shown (the numbers in the waveform represent the row numbers of the pixel circuit rows where valid data signals are written). When the value of the second position parameter in the second parameter register 213 is p, the target pixel circuit row where the actual data is written is the lowermost m-row pixel circuit row in the 100-column direction of the pixel circuit array. The position of the target display area is as follows: Figure 10 As shown, the image is located in the lower region of the pixel circuit array 100 and is displayed as follows. Figure 10 The target display area is shown. After the pulse of the trigger signal STV appears, the gate drive module 230 begins to scan and refresh the pixels line by line. No valid data signal waveform appears in the first 1-p rows, so a black screen is displayed. Valid data signal waveforms are input to the last m rows of pixel circuits in the column direction; therefore, the last m rows of pixel circuits are used to display the image.

[0085] As can be seen, the above-mentioned display panel can achieve micro-movement of the displayed image in the vertical direction in the display panel by using the second parameter register 213. As the second position parameter stored in the second parameter register 213 gradually increases, the target display area gradually moves from top to bottom in the horizontal direction.

[0086] In some other embodiments, the display panel described above may also be designed such that as the second position parameter stored in the second parameter register 213 gradually increases, the target display area gradually moves from bottom to top in the horizontal direction.

[0087] In one specific implementation, the first parameter register 212 can also be implemented using a counter. Specifically, each time the slow counter overflows and resets to 0, it causes the value of the first position parameter stored in the first parameter register 212 to increment by 1. The maximum value of the first parameter register 212 can be set to k. When the value of the first position parameter reaches k, the first parameter register 212 is reset to zero and the count restarts. The first position parameter and the second position parameter are independent of each other and have no correlation. In this case, the value of the first position parameter can be used to indicate the starting position of the second channel enabled in the line buffer 222.

[0088] In some other embodiments, the first parameter register 212 can also be designed such that: when the value in the first parameter register 212 is 0, the slow counter increments the value of the first position parameter stored in the first parameter register 212 by 1 each time it overflows and is reset to 0; when the value of the first position parameter increases to k, the slow counter decrements the value of the first position parameter stored in the first parameter register 212 by 1 each time it overflows and is reset to 0; when the value of the first position parameter decreases to 0, the slow counter increments the value of the first position parameter stored in the first parameter register 212 by 1 each time it overflows and is reset to 0, and the above process is repeated. That is, as the first position parameter stored in the first parameter register 212 gradually increases, the target display area gradually moves from left to right in the horizontal direction; at the same time, as the first position parameter stored in the first parameter register 212 gradually decreases, the target display area gradually moves from right to left in the horizontal direction.

[0089] In one specific implementation, the second parameter register 213 can also be implemented using a counter. Specifically, each time the slow counter overflows and resets to 0, it causes the value of the second position parameter stored in the second parameter register 213 to increment by 1. The maximum value of the second parameter register 212 can be set to p (p is a positive integer). When the value of the second position parameter is increased to p, the second parameter register 212 is reset to zero and starts counting again. In this case, the value of the second position parameter can be used to indicate the number of rows between the STV signal and the pixel circuit row written by the first row of data.

[0090] In some other embodiments, the second parameter register 213 can also be designed such that: when the value in the second parameter register 213 is 0, the slow counter increments the value of the second position parameter stored in the second parameter register 213 by 1 each time it overflows and is reset to 0; when the value of the second position parameter is increased to p, the slow counter decrements the value of the second position parameter stored in the second parameter register 213 by 1 each time it overflows and is reset to 0; when the value of the second position parameter is decreased to 0, the slow counter increments the value of the second position parameter stored in the second parameter register 213 by 1 each time it overflows and is reset to 0, and the above process is repeated. That is, as the second position parameter stored in the second parameter register 213 gradually increases, the target display area gradually moves from top to bottom in the vertical direction; at the same time, as the second position parameter stored in the second parameter register 213 gradually decreases, the target display area gradually moves from bottom to top in the vertical direction.

[0091] In the display panel provided in this application, the display driving module 200 constructed using TFT circuitry enables the display panel to achieve micro-movement of the image when displaying an image. The number of available channels in the line buffer 222 is greater than the number of channels required for display, i.e., the line buffer 222 has redundant channels. The enabled area of ​​the line buffer 222 is controlled by a first position parameter stored in the first parameter register 212. The enabled channels in the line buffer 222 are controlled using the first parameter register 212 to achieve horizontal movement of the target display area. The valid pulse in the trigger signal STV output by the trigger signal generator 214 is the scan start control pulse of the gate driving module 230. The timing of the occurrence of the valid pulse in the trigger signal STV is controlled by a second position parameter. The touch signal STV is controlled using the second parameter register 213, thereby controlling the driving timing output by the gate driving module 230 to achieve vertical movement of the target display area. A slow counter is set to periodically update the parameters stored in the first parameter register 212 and the second parameter register 213. As can be seen, the above-mentioned display panel adopts a system linkage control method, which enables the driving IC constructed with TFT circuit to have the function of image micro-shifting, which can reduce the afterimage of the display panel, or make the edges of the fixed afterimage / image of the display panel blurry and less noticeable, so as to improve the display effect.

[0092] In one possible implementation, after determining the n enabled channels in the line buffer 222 according to the first position parameter, the data stored in the other second channels besides the n enabled channels is set to zero. That is, the enabled second channels of the line buffer 222 are used to store valid image data, and the data in the disabled second channels of the line buffer 222 is set to 0.

[0093] A display device, such as the display panel described in any of the above embodiments. Figure 13This is a schematic diagram of the structure of a display device in one embodiment of this application. Figure 13 The provided display device 1 includes the display panel 10 provided in any of the above embodiments of this application. Figure 13 This embodiment uses AR glasses as an example to illustrate the display device 1. It is understood that the display device provided in this application embodiment can be other types of wearable products, mobile phones, computers, televisions, vehicle display devices, or other display devices with display functions. This application does not impose specific limitations on these. The display device provided in this application embodiment has the beneficial effects of the display panel provided in this application embodiment. For details, please refer to the specific descriptions of the display panel in the above embodiments. These descriptions will not be repeated here.

[0094] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0095] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes a displayable area and a non-display area disposed around at least a portion of the displayable area, the display panel comprising: A pixel circuit array is located in the displayable area, the pixel circuit array comprising a plurality of pixel circuits arranged in an array; the row direction and column direction of the pixel circuit array intersect; the pixel circuits are used to drive light-emitting devices to emit light; A display driving module is electrically connected to the pixel circuit array and is used to determine a target display area in the pixel circuit array and provide data signals to the pixel circuit located in the target display area; wherein the area of ​​the target display area is less than or equal to the display area of ​​the displayable area; The display driving module adjusts the position of the target display area in the row direction of the pixel circuit array every first preset time interval, and / or the display driving module adjusts the position of the target display area in the column direction of the pixel circuit array every second preset time interval.

2. The display panel according to claim 1, characterized in that, The display driving module includes thin-film transistors; Preferably, the pixel circuit includes thin-film transistors, and the active layer of at least a portion of the thin-film transistors in the display driving module is disposed on the same layer as the active layer of at least a portion of the thin-film transistors in the pixel circuit.

3. The display panel according to claim 1 or 2, characterized in that, The display driving module includes a control module, a data driving module, and a gate driving module. The control module is electrically connected to the data driving module and the gate driving module. The data driving module is electrically connected to the pixel circuit through a data line, and the gate driving module is electrically connected to the pixel circuit through a gate line. The control module is used to output a first position parameter and / or a second position parameter. The control module adjusts the first position parameter every first preset time interval and adjusts the second position parameter every second preset time interval. The data driving module is used to determine the target pixel circuit column according to the first position parameter, and transmit the data signal to the data line corresponding to the target pixel circuit column; The gate driving module is used to determine the target pixel circuit row according to the second position parameter and control the data signal to be written into the target pixel circuit row. Wherein, the number of target pixel circuit columns is less than or equal to the total number of columns of pixel circuits in the pixel circuit array, and the number of target pixel circuit rows is less than or equal to the total number of rows of pixel circuits in the pixel circuit array.

4. The display panel according to claim 3, characterized in that, The control module includes a counter, a first parameter register, a second parameter register, and a trigger signal generator. The counter is electrically connected to both the first parameter register and the second parameter register. The first parameter register is electrically connected to the data driving module. The second parameter register is electrically connected to the trigger signal generator. The trigger signal generator is electrically connected to the gate driving module. When the first count of the counter reaches the first preset value, the counter resets the first count to zero and outputs a first adjustment signal to the first parameter register; When the second count of the counter reaches the second preset value, the counter resets the second count to zero and outputs a second adjustment signal to the second parameter register; The first parameter register is used to store the first position parameter, which includes the coordinates of the enabled area of ​​the data driving module. The first parameter register is also used to offset the coordinates of the enabled area of ​​the data driving module along the row direction of the pixel circuit array according to the first adjustment signal, and to update the first position parameter. The second parameter register is used to store the second position parameter, which includes the coordinates of the enabled area of ​​the gate driving module. The second parameter register is also used to offset the coordinates of the enabled area of ​​the gate driving module along the column direction of the pixel circuit array according to the second adjustment signal, and to update the second position parameter. The trigger signal generator is used to output a trigger signal to the gate drive module according to the second position parameter.

5. The display panel according to claim 3, characterized in that, The data driving module includes a shift register, a row buffer, and a discharge logic unit. The row buffer is electrically connected to the control module and is used to determine the enabled channel in the row buffer according to the first position parameter. The shift register is electrically connected to the row buffer and is used to receive image data and write the image data into the enabled channel in the row buffer. The row buffer is electrically connected to the discharge logic unit, which is used to convert the image data temporarily stored in the row buffer into a data signal and transmit the data signal to the data line corresponding to the target pixel circuit column.

6. The display panel according to claim 5, characterized in that, The data driving module further includes a level converter, which is electrically connected between the row buffer and the discharge logic unit. The level converter is used to convert the incoming signal from a first voltage domain to a second voltage domain. Preferably, the voltage value of the output signal of the level converter is greater than the voltage value of the input signal of the level converter.

7. The display panel according to claim 3, characterized in that, The pixel circuit array includes n+k columns of pixel circuits. Each column of pixel circuits is electrically connected to the data driving module via a data line. The number of target pixel circuit columns is n, where n and k are both positive integers.

8. The display panel according to claim 7, characterized in that, The data driving module includes a shift register, a row buffer, a level shifter, and a discharge logic unit. The shift register includes n first channels, the row buffer includes n+k second channels, the level shifter includes n+k third channels, and the discharge logic unit includes n+k fourth channels. One second channel is electrically connected to one corresponding third channel, one third channel is electrically connected to one corresponding fourth channel, and one fourth channel is electrically connected to one corresponding column of pixel circuits via one data line. The row buffer is electrically connected to the control module and is used to determine n enabled channels in the row buffer according to the first position parameter; The shift register is used to receive image data, and the n first channels transmit the image data to the n enabled channels in the row buffer; The row buffer transmits the image data to the n third channels connected to the n enabled channels to perform level conversion on the image data; The level converter transmits the image data after level conversion to the n fourth channels connected to the n third channels, so as to convert the image data into the data signal; The discharge logic unit transmits the data signal to the n columns of target pixel circuits connected to the n fourth channels.

9. The display panel according to claim 8, characterized in that, After determining the n enabled channels in the row buffer according to the first position parameter, the data stored in the other second channels besides the n enabled channels is set to zero.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1-9.

Images