Double-electric layer transistor optoelectronic cascade type deep reservoir pool computing system and implementation method

Abstract

The application discloses a double-electric-layer transistor photoelectric cascade type deep reservoir pool computing system and an implementation method. The system comprises a dynamic space-time signal input module, an optical perception reservoir pool module, an interlayer state mapping module, an electrical computing reservoir pool module and a readout identification module. The optical perception reservoir pool module forms a first layer reservoir pool state by using the optical relaxation response of the device. The interlayer state mapping module converts the current state output by the previous layer into a voltage input signal required by the next layer. The electrical computing reservoir pool module forms subsequent multi-layer reservoir pool states by using the electrical relaxation response of the device. The application constructs a cascade deep reservoir pool by using the optical and electrical relaxation dynamics of the same type of double-electric-layer transistor, uses the slower optical relaxation for front-end visual perception and accumulation, and uses the faster electrical relaxation for back-end deep calculation. In this way, the dependence on traditional mask processing and time division multiplexing is reduced, and the expression ability and identification accuracy of the system to dynamic space-time signals are improved.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing architecture design technology, specifically to a deep storage pool computing system and implementation method based on a double-layer transistor opto-cascaded system. Background Technology

[0002] Reservoir computing is a neuromorphic computing method suitable for time-series signal processing. It maps input signals to a high-dimensional state space through a fixed high-dimensional dynamic system, and then performs classification and recognition through a lightweight readout layer, showing potential application in low-power edge computing. In hardware reservoir computing systems based on physical devices, the state richness directly affects the signal representation capability. Existing hardware reservoir computing systems, when the number of physical nodes is limited, often expand the equivalent state space through masking, time-division multiplexing, or virtual nodes. While these methods can increase the number of readable dynamic responses, they usually require pre-encoding and time-division expansion of the input signal, and the state richness largely depends on external modulation processes, leading to relatively complex input organization, state sampling, and readout processing. For signals with spatial distribution and temporal evolution characteristics, such as dynamic images and depth map sequences, complex external encoding may also increase the front-end processing burden, hindering the device's direct perception of the original spatiotemporal information. Therefore, it is necessary to construct a hardware reservoir computing system that primarily utilizes the intrinsic relaxation dynamics of the device to form reservoir states and reduces the dependence on complex masks and time-division multiplexing.

[0003] Electric-double-layer transistors (EDLTs), due to the migration and relaxation behavior of mobile ions in their gate dielectric, can simulate the short-term plasticity of synapses, making them suitable for constructing physical reservoirs. However, existing physical reservoir computing systems mostly rely on a single electrical or optical response to form the reservoir state. A single electrical response typically requires additional photoelectric conversion or front-end sensing modules when processing visual input; while a single optical response facilitates direct reception of visual input, the optical relaxation process is usually slow, which may lead to low cascading speed and complex inter-layer transitions if directly used for multi-layer cascaded computing. For dynamic visual tasks involving spatial distribution and temporal evolution, existing solutions still lack a photoelectric collaborative reservoir architecture that can reasonably divide the work between front-end visual perception and back-end depth computing.

[0004] In existing technologies, such as Chinese patent CN118713761A (published on September 27, 2024), a time-delayed reservoir computing system for high-speed channel equalization is disclosed. This system performs masking processing on the input signal through a signal preprocessing unit and constructs a time-delayed deep reservoir using a time-delayed loop containing nonlinear nodes and multiple virtual nodes to expand the reservoir's state space. Although this type of scheme can increase the number of equivalent states under limited physical node conditions, its state expansion mainly relies on input masking, timing unrolling, and virtual node organization. It requires the original input signal to be externally encoded before being serially injected into the reservoir, making the input mapping, state sampling, and readout processing relatively complex. At the same time, this scheme is mainly aimed at high-speed channel equalization tasks and is not designed for visual inputs with spatial distribution and temporal evolution characteristics, such as dynamic images and depth map sequences. It is difficult to fully utilize the intrinsic relaxation process of the device to achieve direct perception and optoelectronic cascade processing of dynamic visual information.

[0005] For example, Chinese invention patent application CN120833811A (published on October 24, 2025) discloses a reservoir calculation implementation method based on a dual-transistor structure. This method consists of a write transistor and a read transistor as basic units. The write transistor charges the storage node SN, and the nonlinear relaxation process is generated by charge leakage on the storage node SN. The transconductance amplification effect of the read transistor maps the node charge decay to the read bit line current, thus forming various dynamic response states. This scheme has a relatively simple structure and can utilize electrical dynamic nodes to achieve time-series signal processing. However, its input excitation, state maintenance, and output readout all revolve around the charge charging, discharging, and leakage processes, and the reservoir state mainly originates from a single electrical relaxation mechanism. For visual spatiotemporal signals such as dynamic images and depth map sequences, although this type of scheme can be processed through front-end conversion or encoding, its state construction is still mainly based on a single electrical relaxation process. It does not adequately utilize the role of optical response in visual perception and time accumulation, nor does it further develop a depth-cascaded reservoir architecture with collaborative division of labor between optical slow relaxation and electrical fast relaxation.

[0006] Therefore, how to build a reservoir computing system that combines front-end visual perception capabilities and back-end depth computing efficiency by utilizing the optical and electrical relaxation characteristics of the same type of devices while reducing the reliance on complex mask processing and time-division multiplexing is an urgent problem to be solved. Summary of the Invention

[0007] To address the above technical problems, this invention provides a double-layer transistor opto-cascaded deep reservoir computing system, comprising: The dynamic spatiotemporal signal input module is used to receive time-series signals and convert them into optical input signals; The optical sensing reservoir module, composed of an array of electrically double-layer transistors with photoresponse characteristics, receives the optical input signal and generates an optical relaxation current using the optical relaxation response of the transistors, forming a first-layer reservoir state. When the optical input signal acts on the transistor channel, photogenerated carriers are generated in the channel, causing a change in the channel current. After the optical stimulus is removed, the channel current relaxes slowly over time. Because this optical relaxation process lasts for a relatively long time, it is suitable for the initial perception, time accumulation, and preservation of low-frequency temporal characteristics of dynamic visual information; therefore, it is used as the first-layer reservoir state.

[0008] The inter-layer state mapping module is set between adjacent storage pool layers to convert the current state output by the previous storage pool into the voltage input signal required by the next storage pool. The electrical computation reservoir module, composed of an array of double-layer transistors with electrical synaptic responses, receives the voltage input signal output from the interlayer state mapping module and generates an electrical relaxation current using the electrical relaxation response of the double-layer transistors, forming the reservoir state for subsequent layers. When a voltage pulse output from the interlayer state mapping module is applied to the transistor gate, mobile ions in the gate dielectric migrate under the influence of the electric field, forming a double-layer structure at the interface between the gate dielectric and the channel, thereby modulating the channel current and generating an electrical synaptic response and an electrical relaxation current. Compared to optical relaxation, electrical relaxation response is faster, and a stable mapping relationship is more easily established between the voltage input and the current response, making it suitable as the main cascade unit for subsequent multi-layer deep reservoir calculations.

[0009] The readout identification module, whose input is connected to the output of the electrical computation reservoir module, is used to receive the state of the last reservoir layer and output the identification result. This system utilizes the longer-retention optical relaxation in this device for front-end sensing and the faster-responding electrical relaxation for back-end multi-layer computation, reducing the dependence of multi-layer optical cascades on complex light intensity modulation or electro-optical conversion structures, and improving the feasibility of implementing deep reservoir computation in optoelectronic cascades.

[0010] Furthermore, the time-series signal includes a depth map sequence and a dynamic image sequence. The dynamic spatiotemporal signal input module preprocesses the depth map sequence, distinguishes between the background region and the effective action region based on the depth value at each spatial location, and converts the effective action region into a light input signal.

[0011] Furthermore, the inter-layer state mapping module includes: A current-to-voltage conversion unit is used to convert the current signal output from the storage tank into a voltage signal; A level adjustment unit is used to adjust the voltage signal to the operating voltage range of the next layer double-layer transistor; The pulse shaping unit is used to organize the adjusted voltage signal into a voltage pulse sequence.

[0012] Furthermore, the current-to-voltage conversion unit employs a transimpedance amplifier or a load resistor, and the level adjustment unit employs a level shifting circuit.

[0013] Furthermore, the double-layer transistor includes a conductive gate, a double-layer gate dielectric layer, a semiconductor channel layer, a source, and a drain; the surface of the conductive gate is a double-layer gate dielectric layer, the surface of the double-layer gate dielectric layer is a semiconductor channel layer, and the semiconductor channel layer has a source and a drain.

[0014] Furthermore, the double-layer transistor is connected to an external driving and acquisition circuit, enabling it to receive optical pulses, voltage pulses, and output the channel current state.

[0015] Furthermore, the conductive gate is made of indium tin oxide conductive layer on a glass substrate, the double-layer gate dielectric layer is made of chitosan, the semiconductor channel layer is made of indium gallium zinc oxide, and both the source and drain are made of aluminum.

[0016] Furthermore, the readout recognition module employs a linear regression, ridge regression, or fully connected classifier.

[0017] This invention also provides a computational implementation method for a double-layer transistor opto-cascaded deep reservoir, comprising the following steps: Step S1: Convert the dynamic spatiotemporal signal to be processed into an optical input signal and input it into the optical sensing reservoir module; Step S2: The double-layer transistor in the optical sensing reservoir module generates a photoinduced current response under light stimulation, and forms an optical relaxation current after the light stimulation is removed. This optical relaxation current is used as the first layer reservoir state. Step S3: Collect the current signal of the first layer of the storage pool state through the inter-layer state mapping module, and convert it into the voltage input signal required by the next layer of the storage pool; Step S4: Apply the voltage input signal to the electrical calculation reservoir module to cause the double-layer transistors therein to generate electrical synaptic response and electrical relaxation current, and use the electrical relaxation current as the state of the next reservoir layer; Step S5: Repeat steps S3 to S4 to cascade multiple electrical calculation reservoir modules in sequence to form a deep reservoir calculation structure; Step S6: Extract the state of the last-layer reservoir and input it into the readout recognition module to obtain the recognition result of the dynamic spatiotemporal signal. The optical sensing reservoir module serves as the first-level reservoir; due to its relatively slow optical relaxation process, it is more suitable for initial perception and time accumulation of dynamic visual input. The electrical computation reservoir module serves as the subsequent cascaded reservoir. Because of its fast electrical relaxation response and the ease with which voltage input can be obtained through inter-layer state mapping, it is more suitable for multi-layer deep cascaded computation.

[0018] Furthermore, the conversion steps of the inter-layer state mapping module in step S3 specifically include: converting the current signal into a voltage signal through a current-to-voltage conversion unit, adjusting the voltage signal to the linear operating voltage range of the next layer double-layer transistor through a level adjustment unit, and organizing it into a voltage pulse sequence through a pulse shaping unit.

[0019] Furthermore, the relaxation time of the optical relaxation process is longer than that of the electrical relaxation process; the pulse width of the optical input signal is greater than the pulse width of the voltage pulse applied to the electrical computing reservoir module.

[0020] Compared with existing technologies, the advantages and effects of this application are as follows: 1. This application, for the first time, functionally divides and collaboratively utilizes the optical and electrical relaxation responses of double-layer transistors within the same reservoir computing hardware architecture. The optical sensing reservoir module utilizes the device's slower optical relaxation process (e.g., pulse width 70ms), suitable for initial perception and time accumulation of dynamic visual input; the electrical computing reservoir module utilizes the device's faster electrical relaxation process (e.g., pulse width 20ms), suitable for rapid state mapping and multi-layer depth computing. The two are seamlessly connected through an inter-layer state mapping module, overcoming the shortcomings of inefficient cascading of single optical responses and the need for pre-photoelectric conversion of single electrical responses, significantly enriching the spatial dimension of the reservoir states.

[0021] 2. This application employs a cascaded structure of "optical first-layer sensing + electrical multi-layer computing," and utilizes inter-layer state mapping modules (such as transimpedance amplifiers and level shifting circuits) to directly convert the current state of the previous layer into the voltage pulse of the next layer. This avoids the complex masking, time-division multiplexing, or electro-optical conversion structures required in traditional technologies to achieve state extension. This not only reduces the system's dependence on peripheral driving and preprocessing circuits but also reduces hardware implementation complexity and power consumption.

[0022] 3. Both the optical sensing reservoir module and the electrical computing reservoir module of this application use double-layer transistors as the basic computing units, and the device types are uniform. Compared with the existing technology, which requires the combination of multiple heterogeneous devices (such as memristors and transistors, or optical devices and electrical devices), this system is more compatible in terms of process fabrication, which is conducive to large-scale array integration and reduces system mismatch problems caused by device differences.

[0023] 4. The computational method provided in this application processes dynamic spatiotemporal signals (such as depth map sequences) sequentially through an optical sensing reservoir, inter-layer state mapping, and multiple electrical computation reservoirs. The optical relaxation current serves as the first-layer state, preserving the long-term cumulative characteristics of the input signal; subsequent electrical relaxation currents serve as deeper-layer states, extracting high-dimensional nonlinear features layer by layer. This hierarchical processing mechanism enables the method to effectively analyze complex signals that simultaneously contain spatial distribution and temporal evolution, improving the accuracy in human motion recognition tasks from 90.67% for a single optical module and 87.78% for a single electrical module to 92.89% after cascading.

[0024] 5. The calculation method provided in this application sets differentiated signal parameters based on the physical characteristics of electric double-layer transistors: the pulse width of the optical input signal (e.g., 70ms) is greater than the pulse width of the voltage applied to the electrical calculation reservoir (e.g., 20ms). This timescale matching allows the front-end optical sensing to fully accumulate visual information, and the back-end electrical calculation to respond quickly and complete multi-layer mapping, avoiding computational waiting or information loss caused by uniform relaxation time, and improving overall processing efficiency.

[0025] 6. The inter-layer state mapping step (S3) in the calculation method provided in this application specifically includes three sub-steps: current-to-voltage conversion, level adjustment, and pulse shaping, forming a standardized state transfer process. This process uniformly converts the current signal output from the previous layer of the reservoir into a voltage pulse sequence within the linear operating region of the next layer's double-layer transistor, ensuring the compatibility of signal amplitude and timing during cascading. Based on this standardized process, the number of cascaded layers of the electrical computation reservoir can be flexibly increased according to task requirements (as in step S5), realizing the scalability of the deep reservoir computation structure.

[0026] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the preferred embodiments of this application are described in detail below with reference to the accompanying drawings.

[0027] The above and other objects, advantages and features of this application will become more apparent to those skilled in the art from the following detailed description of specific embodiments in conjunction with the accompanying drawings. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. In all drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.

[0029] in: Figure 1 This is a schematic diagram of the overall structure of the double-layer transistor opto-cascaded deep reservoir computing system of this application; Figure 2 This is a schematic diagram of the structure of the double-layer transistor device provided in this application; Figure 3 The optical relaxation response and fitting results of the electric double-layer transistor provided in this application under optical pulse stimulation are shown in the figure. Figure 3 (a) Graph showing the optical relaxation response of an electric double-layer transistor under light pulse stimulation; Figure 3 (b) Fitting results of electric double-layer transistors under light pulse stimulation; Figure 4 The diagram shows the electrical synaptic response, voltage linear mapping relationship, and electrical relaxation fitting results of the double-layer transistor provided in this application under voltage pulse stimulation. Figure 4 (a) Schematic diagram of the electrical synaptic response of a double-layer transistor under voltage pulse stimulation; Figure 4 (b) Voltage linear mapping relationship of double-layer transistor under voltage pulse stimulation; Figure 4 (c) Figure showing the electrical relaxation fitting results of a double-layer transistor under voltage pulse stimulation; Figure 5 The image shows the recognition rate test results of the photoelectric cascaded deep reservoir computing system provided in this application in the human motion recognition task. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. In the following description, specific details such as specific configurations and components are provided merely to help fully understand the embodiments of this application. Therefore, those skilled in the art should understand that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. In addition, for clarity and brevity, descriptions of known functions and structures are omitted in the embodiments.

[0031] It should be understood that the phrase "an embodiment" or "this embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "an embodiment" or "this embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0032] Furthermore, reference numerals and / or letters may be repeated in different examples within this application. Such repetition is for the purpose of simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or settings discussed.

[0033] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, B exists alone, and A and B exist simultaneously. The term " / and" describes another type of relationship between related objects, indicating that two relationships can exist. For example, A / and B can mean: A exists alone, and A and B exist alone. In addition, the character " / " in this article generally indicates that the related objects before and after it have an "or" relationship.

[0034] In this article, the term "at least one" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, "at least one of A and B" can mean: A exists alone, A and B exist simultaneously, or B exists alone.

[0035] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion.

[0036] Example 1 This embodiment introduces a deep reservoir computing system based on a double-layer transistor opto-cascaded system.

[0037] Please refer to Figure 1 As shown, Figure 1 This is a schematic diagram of the overall structure of the double-layer transistor opto-cascaded deep reservoir computing system of this application; The dynamic spatiotemporal signal input module is used to receive time-series signals and convert them into optical input signals; The optical sensing reservoir module is composed of an array of double-layer transistors with photoresponse characteristics. It is used to receive the optical input signal and generate an optical relaxation current by utilizing the optical relaxation response of the double-layer transistors to form the first layer reservoir state. The inter-layer state mapping module is set between adjacent storage pool layers to convert the current state output by the previous storage pool into the voltage input signal required by the next storage pool. The electrical computing reservoir module is composed of an array of double-layer transistors with electrical synaptic response. It is used to receive the voltage input signal output by the interlayer state mapping module and generate electrical relaxation current by utilizing the electrical relaxation response of the double-layer transistors to form the reservoir state of the subsequent layer. The readout identification module has its input end connected to the output end of the electrical calculation reservoir module, and is used to receive the status of the last layer reservoir and output the identification result.

[0038] The time-series signal includes a depth map sequence and a dynamic image sequence. The dynamic spatiotemporal signal input module preprocesses the depth map sequence, distinguishes the background region and the effective action region based on the depth value of each spatial location, and converts the effective action region into a light input signal.

[0039] The inter-layer state mapping module includes: A current-to-voltage conversion unit is used to convert the current signal output from the storage tank into a voltage signal; A level adjustment unit is used to adjust the voltage signal to the operating voltage range of the next layer double-layer transistor; The pulse shaping unit is used to organize the adjusted voltage signal into a voltage pulse sequence.

[0040] The current-to-voltage conversion unit uses a transimpedance amplifier or a load resistor, and the level adjustment unit uses a level shifting circuit.

[0041] The double-layer transistor includes a conductive gate, a double-layer gate dielectric layer, a semiconductor channel layer, a source, and a drain; the surface of the conductive gate is a double-layer gate dielectric layer, the surface of the double-layer gate dielectric layer is a semiconductor channel layer, and the semiconductor channel layer has a source and a drain.

[0042] The double-layer transistor is connected to an external driving and acquisition circuit, enabling it to receive optical pulses, voltage pulses, and output the channel current state.

[0043] The conductive gate is made of indium tin oxide conductive layer on glass substrate, the double-layer gate dielectric layer is made of chitosan, the semiconductor channel layer is made of indium gallium zinc oxide, and the source and drain are both made of aluminum.

[0044] The readout recognition module uses a linear regression, ridge regression, or fully connected classifier.

[0045] The technical advantages of this embodiment are: It utilizes both the optical and electrical relaxation responses of the same type of double-layer transistors to construct the reservoir state, rather than relying solely on a single optical or electrical response. The slower optical relaxation response is placed in the first layer for dynamic visual input perception and temporal accumulation; the faster electrical relaxation response is placed in subsequent layers for multi-layer state mapping and depth feature extraction. An inter-layer state mapping module is incorporated to convert the current state output from the previous reservoir layer into the voltage signal input to the next reservoir layer, enabling continuous connection between the optical sensing reservoir and the electrical computation reservoir. The reservoir state is expanded through the device's own relaxation dynamics and inter-layer cascading process, reducing reliance on traditional masking, time-division multiplexing, and external virtual node expansion methods.

[0046] Example 2 Based on Example 1, this example discloses the electric double-layer transistor and its fabrication method.

[0047] Please refer to Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of the double-layer transistor device provided in this application; The double-layer transistor includes a conductive gate, a double-layer gate dielectric layer, a semiconductor channel layer, a source, and a drain.

[0048] The fabrication method of the electric double-layer transistor device is as follows: Step 101: Prepare a conductive gate.

[0049] Step 102: Prepare a double-layer gate dielectric layer on the conductive gate surface.

[0050] Step 103: Fabricate a semiconductor channel layer on the surface of the double-layer gate dielectric layer.

[0051] Step 104: Fabricate source and drain electrodes on the semiconductor channel layer to form a double-layer transistor.

[0052] Step 105: Connect the double-layer transistor to the external driving and acquisition circuit so that it can receive light pulses, voltage pulses and output the channel current status.

[0053] Preferably, in step 101, the conductive gate is an indium tin oxide conductive layer on a glass substrate, indium tin oxide is abbreviated as ITO.

[0054] Preferably, in step 102, the double-layer gate dielectric layer uses chitosan electrolyte. First, acetic acid is added to deionized water to prepare an acetic acid aqueous solution with a mass fraction of 2.0 wt%. Then, chitosan powder is added to the acetic acid aqueous solution, and after stirring and standing to remove bubbles, a chitosan solution with a mass fraction of 2.0 wt% is obtained. Subsequently, the chitosan solution is spin-coated onto the surface of indium tin oxide conductive glass and dried in air to form a film, thus forming a chitosan double-layer gate dielectric layer.

[0055] Preferably, in step 103, the semiconductor channel layer is indium gallium zinc oxide (IGZO) and is prepared by magnetron sputtering.

[0056] Preferably, in step 104, the source and drain are made of aluminum (Al).

[0057] Example 3 Based on Example 1, this example discloses a method for testing the optical and electrical relaxation characteristics of the electric double-layer transistor.

[0058] Please refer to Figure 3-4 As shown, Figure 3 The optical relaxation response and fitting results of the electric double-layer transistor provided in this application under optical pulse stimulation are shown in the figure. Figure 4 The diagram shows the electrical synaptic response, voltage linear mapping relationship, and electrical relaxation fitting results of the double-layer transistor provided in this application under voltage pulse stimulation. The method for testing the optical relaxation characteristics of the electric double-layer transistor includes the following steps: Step 201: Apply a light pulse to the channel region of the double-layer transistor.

[0059] Step 202: Collect the channel current changes under light stimulation to obtain the light-induced current response.

[0060] Step 203: After the light stimulation is removed, continue to collect the process of channel current decaying over time to obtain the optical relaxation current.

[0061] Step 204: Fit the optical relaxation current to obtain the optical relaxation time constant and optical relaxation index.

[0062] Preferably, the optical pulse width can be 70 ms. This optical relaxation process decays slowly, making it suitable for the first-layer reservoir to accumulate visual input over time.

[0063] The method for testing the electrical relaxation characteristics of the electric double-layer transistor includes the following steps: Step 301: Apply a voltage pulse to the gate of the double-layer transistor.

[0064] Step 302: Collect the channel current response under different gate voltages to obtain the electrical synaptic response.

[0065] Step 303: Establish the mapping relationship between the amplitude of the electrical synaptic response and the gate voltage.

[0066] Step 304: After the voltage pulse is removed, the channel current decays over time to obtain the electrical relaxation current.

[0067] Step 305: Fit the electrical relaxation current to obtain the electrical relaxation time constant and the electrical relaxation index.

[0068] Preferably, the voltage pulse width can be 20ms. The electrical relaxation process has a fast response, and there is a good mapping relationship between the electrical synaptic response amplitude and the gate voltage, making it suitable for multi-stage cascading of subsequent electrical reservoir layers.

[0069] The technical advantages of this embodiment are as follows: In a double-layer transistor, optical relaxation has a longer retention period compared to electrical pulse response, making it suitable for the first layer of sensing and memory; electrical relaxation response is faster and easier to drive with voltage pulses, making it suitable for subsequent deep cascading. The division of labor between the two allows the system to balance visual perception capabilities and depth computing efficiency.

[0070] Example 4 This embodiment discloses a computational implementation method for a double-layer transistor opto-cascaded deep reservoir, including the following steps: Step S1: The dynamic spatiotemporal signal input module receives the dynamic spatiotemporal signal to be identified and converts it into a signal form suitable for the input of the storage pool.

[0071] Specifically, the dynamic spatiotemporal signal can be a human motion depth map sequence, a dynamic image sequence, or other time-series signals. When the input signal is a human motion depth map sequence, the original depth frame is subjected to size compression and normalization processing, and the background area and the effective motion area are distinguished according to the depth value of each spatial location.

[0072] Background regions or regions with invalid depth values ​​are denoted as invalid stimuli; regions with valid depth values ​​corresponding to human movements are denoted as valid stimuli. Therefore, each spatial location can be represented as follows: i The light input state in a frame is represented as follows: P(i)∈{0,1}, Where P(i)=1 represents the first... iThe frame corresponds to a spatial location with valid motion depth information and generates light input; P(i)=0 indicates that the location is a background area or an invalid depth value area, and no valid light input is generated.

[0073] Preferably, the optical input adopts a binary optical pulse method. The optical input wavelength is 405nm, the optical pulse width is 70ms, and the rest interval between adjacent optical pulses is 70ms.

[0074] Step S2: The optical sensing reservoir module receives the optical input signal and uses the optical relaxation response of the double-layer transistor to generate the first layer reservoir state.

[0075] Specifically, the optical input signal obtained in step S1 is applied to the channel region of the electric double-layer transistor. Under optical stimulation, the electric double-layer transistor generates photogenerated carriers, increasing the channel current; after the optical stimulation is removed, the channel current decays over time, forming an optical relaxation current. This optical relaxation current serves as the state of the first optical reservoir.

[0076] For a single optical pulse, the optical relaxation current after its removal can be expressed as: , in, Indicates after the light stimulus is removed t The change in channel current at any given time; This represents the amplitude of the initial optical synaptic current change caused by light stimulation. Represents the optical relaxation time constant; It represents the optical relaxation stretching index.

[0077] For a continuous motion depth frame sequence, since the relaxation current generated by the preceding optical pulse will be superimposed on the subsequent optical input state, the th... n The state of the optical reservoir at each time step can be represented as: , in, Indicates the first n The state of the optical reservoir at each time step; This indicates the time interval between adjacent optical input states; This represents the initial baseline current of the device. Preferably, the optical pulse width is 70ms and the rest interval is 70ms. It can be determined based on the optical pulse input period or relaxation sampling interval.

[0078] Step S3: The interlayer state mapping module acquires the current state output by the optical sensing reservoir layer and converts it into the voltage input signal required by the next reservoir layer.

[0079] Specifically, the interlayer state mapping module converts the current state output from the optical reservoir into a voltage pulse input. The interlayer state mapping module includes a current-to-voltage conversion unit, a level adjustment unit, and a pulse shaping unit.

[0080] For the current state output of the optically sensed reservoir layer It can be mapped to the input voltage of the electrical calculation reservoir through linear normalization: , in, Indicates the double-layer transistor in the first stage n Gate input voltage at each time step; and These represent the minimum and maximum values ​​of the output current of the optical reservoir, respectively. and These represent the lower and upper limits of the electrical linear response region of the next double-layer transistor, respectively.

[0081] Preferably, the electrical linear response region of the second double-layer transistor is 1.0V to 2.0V.

[0082] Through the above mapping, the photocurrent state output by the first-layer optical reservoir is converted into the voltage pulse sequence required by the next-layer electrical computation reservoir.

[0083] Step S4: The electrical calculation reservoir module receives the voltage input signal and uses the electrical relaxation response of the double-layer transistor to generate the state of the subsequent layer reservoir.

[0084] Specifically, the voltage pulse obtained in step S3 is applied to the gate of the electric double-layer transistor. Under the action of the gate voltage, the electric double-layer transistor undergoes ion migration and forms a double-layer structure at the interface between the gate dielectric and the channel, thereby modulating the channel current and generating an electrical synaptic response and an electrical relaxation current. This electrical relaxation current serves as a reservoir state for subsequent layers.

[0085] Within the electrical linear response region of a double-layer transistor, the relationship between the electrical synaptic response amplitude and the gate voltage can be expressed as: , in, Indicates the first n The amplitude of the change in electrical synaptic current caused by the voltage pulse at each time step; Indicates the first n Gate input voltage at each time step; and These are the parameters obtained through fitting the device's linear response test.

[0086] The electrical relaxation current after the voltage pulse is removed can be expressed as: , in, Indicates after the voltage pulse is removed t The change in channel current at any given time; Represents the electrical relaxation time constant; It represents the electrical relaxation stretch index.

[0087] Furthermore, the historical state is superimposed onto the current state of the electrical reserve pool, the first... n The state of the electrical reservoir at each time step can be represented as: , in, Indicates the first l The electrical calculation of the reservoir state at time step n; This indicates the historical state at the previous time step; This represents the electrical relaxation sampling time or the time interval between adjacent electrical states. This indicates the initial baseline current of the device.

[0088] Preferably, the voltage pulse width is 20 ms, and the rest interval between adjacent voltage pulses is 20 ms. Since the electrical relaxation response time is shorter than the optical relaxation response time, the electrical computational reservoir is suitable for subsequent multi-layer state mapping and deep feature extraction.

[0089] Step S5: Repeat steps S3 to S4 as needed for the computation task to form a multi-layered cascaded deep reservoir computation structure.

[0090] Specifically, for a multi-layer electrical cascade structure, the electrical reservoir state obtained from the current layer is... As the input to the interlayer state mapping module, it is again mapped to the gate input voltage of the next layer double-layer transistor through step S3. Then, step S4 is used to generate the state of the next layer of electrical reserve pool.

[0091] Therefore, the input voltage of the (l+1)th layer of the reservoir can be expressed as: , in, l =1,2,…, L 1, L This indicates the total number of layers in the electrical calculation reservoir. Indicates the first l +1 layer double-layer transistor in the... n Gate input voltage at each time step; Indicates the first l Layered electrical storage tank output current; and They represent the first l Minimum and maximum values ​​of the output current of the layer electrical storage tank; and These represent the lower and upper limits of the electrical linear response region of the next double-layer transistor, respectively.

[0092] By repeatedly mapping current states to voltage inputs layer by layer, a deep reservoir computing structure can be constructed by cascading an optical sensing reservoir and a multi-layer electrical computing reservoir.

[0093] Preferably, in the optoelectronic cascade structure, the first layer is an optical sensing reservoir, and subsequent layers are electrical computing reservoirs. The optical sensing reservoir is used to sense and accumulate motion depth information over time, while the electrical computing reservoir is used to perform rapid dynamic mapping and depth feature extraction of the previous layer's state.

[0094] Step S6: The readout recognition module receives the state of the last-layer reservoir and outputs the classification, prediction, or recognition results.

[0095] Specifically, the state of the last layer of the reservoir is extracted as the input feature of the readout identification module. Let the state matrix of the last layer of the reservoir be... X The corresponding target label matrix is Y target The readout recognition module is trained using linear regression, and its output can be expressed as: , in, Represents the output layer weights, denoted by "T" and "". "" represents the matrix transpose and Moore-Penrose pseudoinverse, respectively.

[0096] After training is completed, the test samples are input into the photoelectric cascaded deep reservoir computing system, and the final recognition category is determined based on the maximum response value output by the readout recognition module.

[0097] Preferably, the calculation method further includes the following parameter settings: In the optical sensing reservoir module, the light input wavelength is 405nm, the light pulse width is 70ms, and the resting interval between adjacent light pulses is 70ms; the optical relaxation current after the light stimulus is removed is collected as the state of the first layer reservoir.

[0098] In the electrical calculation reservoir module, the gate voltage input range is 1.0V to 2.0V, the voltage pulse width is 20ms, and the rest interval between adjacent voltage pulses is 20ms; the electrical relaxation current after the voltage pulse is removed is collected as the reservoir state of the subsequent layer.

[0099] In the interlayer state mapping module, the output current of the previous layer is linearly mapped to the electrical linear response region of the double-layer transistor of the next layer, so that the electrical calculation reservoir of the next layer can perform state updates under stable linear input conditions.

[0100] The technical advantages of this embodiment are as follows: It expresses the mapping process of optical reservoir state, electrical reservoir state, and interlayer state using explicit formulas, enabling the optoelectronic cascaded deep reservoir calculation method to have a repeatable parameter calculation flow. Longer-duration optical relaxation is used for front-end dynamic visual perception and time accumulation, while faster-responding electrical relaxation is used for back-end multilayer state mapping and depth feature extraction. Interlayer connection is achieved through current-voltage linear mapping, reducing the dependence of multilayer optical cascades on complex light intensity modulation or electro-optical conversion structures, thus improving the feasibility and scalability of optoelectronic cascaded deep reservoir calculations.

[0101] Example 5 Please refer to Figure 5 This embodiment mainly introduces the verification method of the system described in Embodiment 1 in the standard human motion recognition task.

[0102] The verification method includes the following steps: Step 401: Use depth map sequences from the standard UTD-MHAD human motion dataset as input data.

[0103] Step 402: Select 15 types of human movements as recognition objects, including lunge, walking, picking up and throwing, tapping, pushing, tennis serve, tennis swing, baseball swing, bowling throw, counterclockwise circle drawing, basketball shooting, crossed arms, clapping, waving, and sliding to the left.

[0104] Step 403: Preprocess the original depth frame. Preferably, the original depth frame is compressed from 240×320 to 24×32, and the background area and effective action area are distinguished according to the depth value.

[0105] Step 404: Convert the effective action area into a light input signal and input it into the optical sensing reservoir module to obtain the state of the first layer of optical reservoir.

[0106] Step 405: Convert the state of the first-layer optical reservoir into a voltage pulse through the interlayer state mapping module, and input it into the subsequent electrical calculation reservoir cascade module to obtain the state of the last-layer reservoir.

[0107] Step 406: Train and test the final layer reservoir state input readout recognition module, and output the action category.

[0108] In one verification method, the action recognition rate was 90.67% when using the optical sensing reservoir module alone; 87.78% when using the 3-layer electrical computing reservoir module alone; and 92.89% when the optical sensing reservoir module and the 3-layer electrical computing reservoir module were cascaded together. This result indicates that the optical sensing reservoir module and the electrical computing reservoir module have complementary effects, and their cascading enhances the system's ability to express the spatiotemporal features of action depth sequences.

[0109] The technical effect of this embodiment is as follows: verified by a standard human motion dataset, the photoelectric cascaded deep reservoir computing system described in this application can improve the motion recognition rate. The optical perception reservoir module is used for front-end visual perception and time accumulation, while the electrical computing reservoir module is used for subsequent state mapping and feature extraction. The cascaded combination of the two is superior to either a single optical reservoir or a single electrical reservoir.

[0110] The above description is merely a preferred embodiment of the present invention and does not limit the scope of protection of the present invention. Various modifications and variations are possible with respect to the present invention. Any changes, modifications, substitutions, integrations, and parameter alterations to these embodiments within the spirit and principles of the present invention fall within the scope of protection of the claims of the present invention.

Claims

1. A deep reservoir computing system with double-layer transistor opto-cascaded structure, characterized in that, include: The dynamic spatiotemporal signal input module is used to receive time-series signals and convert them into optical input signals; The optical sensing reservoir module is composed of an array of double-layer transistors with photoresponse characteristics. It is used to receive the optical input signal and generate an optical relaxation current by utilizing the optical relaxation response of the double-layer transistors to form the first layer reservoir state. The inter-layer state mapping module is set between adjacent storage pool layers to convert the current state output by the previous storage pool into the voltage input signal required by the next storage pool. The electrical computing reservoir module is composed of an array of double-layer transistors with electrical synaptic response. It is used to receive the voltage input signal output by the interlayer state mapping module and generate electrical relaxation current by utilizing the electrical relaxation response of the double-layer transistors to form the reservoir state of the subsequent layer. The readout identification module has its input end connected to the output end of the electrical calculation reservoir module, and is used to receive the status of the last layer reservoir and output the identification result.

2. The double-layer transistor opto-cascaded deep reservoir computing system according to claim 1, characterized in that, The time-series signal includes a depth map sequence and a dynamic image sequence. The dynamic spatiotemporal signal input module preprocesses the depth map sequence, distinguishes the background region and the effective action region based on the depth value of each spatial location, and converts the effective action region into a light input signal.

3. A double-layer transistor opto-cascaded deep reservoir computing system according to claim 1 or 2, characterized in that, The inter-layer state mapping module includes: A current-to-voltage conversion unit is used to convert the current signal output from the storage tank into a voltage signal; A level adjustment unit is used to adjust the voltage signal to the operating voltage range of the next layer double-layer transistor; The pulse shaping unit is used to organize the adjusted voltage signal into a voltage pulse sequence.

4. The double-layer transistor opto-cascaded deep reservoir computing system according to claim 3, characterized in that, The current-to-voltage conversion unit uses a transimpedance amplifier or a load resistor, and the level adjustment unit uses a level shifting circuit.

5. The double-layer transistor opto-cascaded deep reservoir computing system according to claim 1, characterized in that, The double-layer transistor includes a conductive gate, a double-layer gate dielectric layer, a semiconductor channel layer, a source, and a drain; the surface of the conductive gate is a double-layer gate dielectric layer, the surface of the double-layer gate dielectric layer is a semiconductor channel layer, and the semiconductor channel layer has a source and a drain.

6. The double-layer transistor opto-cascaded deep reservoir computing system according to claim 5, characterized in that, The double-layer transistor is connected to an external driving and acquisition circuit, enabling it to receive optical pulses, voltage pulses, and output the channel current state.

7. The double-layer transistor opto-cascaded deep reservoir computing system according to claim 5, characterized in that, The conductive gate is made of indium tin oxide conductive layer on glass substrate, the double-layer gate dielectric layer is made of chitosan, the semiconductor channel layer is made of indium gallium zinc oxide, and the source and drain are both made of aluminum.

8. The double-layer transistor opto-cascaded deep reservoir computing system according to claim 1, characterized in that, The readout recognition module uses a linear regression, ridge regression, or fully connected classifier.

9. A computational implementation method for a double-layer transistor opto-cascaded deep reservoir, characterized in that, Includes the following steps: Step S1: Convert the dynamic spatiotemporal signal to be processed into an optical input signal and input it into the optical sensing reservoir module; Step S2: The double-layer transistor in the optical sensing reservoir module generates a photoinduced current response under light stimulation, and forms an optical relaxation current after the light stimulation is removed. This optical relaxation current is used as the first layer reservoir state. Step S3: Collect the current signal of the first layer of the storage pool state through the inter-layer state mapping module, and convert it into the voltage input signal required by the next layer of the storage pool; Step S4: Apply the voltage input signal to the electrical calculation reservoir module to cause the double-layer transistors therein to generate electrical synaptic response and electrical relaxation current, and use the electrical relaxation current as the state of the next reservoir layer; Step S5: Repeat steps S3 to S4 to cascade multiple electrical calculation reservoir modules in sequence to form a deep reservoir calculation structure; Step S6: Extract the state of the last layer of the reservoir and input it into the readout recognition module to obtain the recognition result of the dynamic spatiotemporal signal.

10. The method for calculating and implementing a deep reservoir of double-layer transistor opto-cascade type according to claim 9, characterized in that, The specific steps of the interlayer state mapping module in step S3 include: converting the current signal into a voltage signal through a current-to-voltage conversion unit, adjusting the voltage signal to the linear operating voltage range of the next layer double-layer transistor through a level adjustment unit, and organizing it into a voltage pulse sequence through a pulse shaping unit.

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