Status check using signaling

Abstract

This application relates to status checking using signaling. A memory system can receive a ready signal from a memory die. The ready signal can indicate whether the memory die is available to receive a command. The memory system can generate an indicator of whether the memory die is available based on a value of the ready signal. The memory system can output the indicator to a controller through one or more pins based on generating the indicator.

Description

[0001] Information related to divisional application This application is a divisional application of Chinese invention patent application filed on November 24, 2021, with application number "202111406539.3" and invention title "Status Check Using Signaling". Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 105,053, filed November 25, 2020, entitled “Status Check Using Signaling,” which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The following text generally refers to one or more systems of memory, and more specifically to status checks using signaling.

[0004] The technical field involves using signaling for status checks. Background Technology

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into different states. For example, a binary memory cell can be programmed to one of two supported states, often corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, and the memory cell can store any one of the two possible states. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0006] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D XPoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) may lose their programmed state over time unless periodically refreshed by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for extended periods even in the absence of an external power supply. Summary of the Invention

[0007] An apparatus is described. The apparatus may include: a memory device comprising a plurality of memory dies, each of the plurality of memory dies configured to output a ready signal indicating whether the memory die is available to receive a command; an output circuit coupled to each of the plurality of memory dies and configured to receive a plurality of ready signals associated with the plurality of memory dies and to generate an indicator based at least in part on the values ​​of the plurality of ready signals; and a first pin coupled to the output circuit and configured to output the indicator to a controller via a first input / output (I / O) channel.

[0008] An apparatus is described. The apparatus may include: a memory device; and control circuitry coupled to the memory device and configured such that the apparatus: receives a plurality of ready signals from a plurality of memory dies, wherein one of the plurality of ready signals is configured to indicate whether a memory die among the plurality of memory dies is available to receive a command; generates an indicator indicating whether the memory die is available, at least in part based on the values ​​of the plurality of ready signals; and outputs the indicator to a controller via a first pin, at least in part based on the generation of the indicator.

[0009] A method is described. The method may include: receiving a plurality of ready signals from a plurality of memory dies, wherein one of the plurality of ready signals is configured to indicate whether a memory die among the plurality of memory dies is available to receive a command; generating an indicator indicating whether the memory die is available, at least in part based on the values ​​of the plurality of ready signals; and outputting the indicator to a controller via a first pin, at least in part based on the generation of the indicator. Attached Figure Description

[0010] Figure 1Examples of systems that support status checks using signaling, based on the examples disclosed herein, are shown.

[0011] Figure 2 Examples of systems that support status checks using signaling, based on the examples disclosed herein, are shown.

[0012] Figure 3 Examples of encoder-integrated systems that support status checks using signaling, based on the examples disclosed herein, are shown.

[0013] Figure 4 Examples of shift register-based systems that support status checks using signaling, based on the examples disclosed herein, are shown.

[0014] Figure 5 A block diagram is shown of a memory system that supports status checks using signaling, based on the examples disclosed herein.

[0015] Figure 6 The flowchart illustrates one or more methods for supporting status checks using signaling, based on the examples disclosed herein. Detailed Implementation

[0016] Some memory systems perform status checks by polling a status register. During status register polling, the controller may poll the memory system (e.g., send a request) to determine which memory die is ready to receive a command. In some cases, polling requests and responses may communicate over one or more Open NAND Flash Interface (ONFI) channels. Such procedures can increase command overhead and reduce channel bandwidth availability. As the number of memory dies within a memory system increases, status checks may become an increasingly significant obstacle to ONFI channel efficiency.

[0017] Such techniques can lead to reduced channel utilization and performance loss in memory systems when performing memory device operations, which may increase latency in other memory system-related operations. By performing independent state checks on the memory die, the memory system may use an increased amount of power, thereby degrading the overall performance of the memory system. Techniques for managing state checks without compromising channel bandwidth and memory device performance are described.

[0018] This disclosure addresses the above and other shortcomings by having a memory system that uses signaling to report the readiness status of memory dies. Instead of the controller sending a request at both ends of an ONFI channel, the memory device can send an indication that it is ready to receive commands to the controller. For example, the memory system may include output circuitry configured to receive a readiness signal from each memory die. The readiness signal indicates whether the memory die is available to receive commands. In such cases, the output circuitry may generate an indicator based on the value of the received readiness signal and output the indicator to the controller via a pin. In some instances, the memory system may use general purpose input / output (GPIO) pins to notify the controller of the status.

[0019] The overall performance of a memory system executing host commands can be improved by using dedicated pins and encoding these pins to transmit readiness status instead of using DQ pins (e.g., the ONFI channel). For example, using dedicated pins to report readiness status can improve the overall efficiency of the memory system, potentially reducing latency between command transfers to different memory dies, increasing read, write, and erase speeds, improving processing time, and so on.

[0020] First, as referenced Figure 1 The features of this disclosure are described in the context of the system and the bare die. (See references...) Figure 2-4 The features of this disclosure are described in the context of the system and encoder described herein. References refer to, as in, references to, [references to, and other sources]. Figure 5-6 The device diagrams and flowcharts describing the use of signaling for status checks further illustrate and describe these and other features of this disclosure.

[0021] Figure 1 An example of a system 100 supporting status checks using signaling, based on the examples disclosed herein, is shown. System 100 includes a host system 105 coupled to a memory system 110.

[0022] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash memory (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital card (SD card), a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small form factor DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), and other possibilities.

[0023] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing devices.

[0024] System 100 may include a host system 105 that can be coupled to memory system 110. Host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, host system 105 may include an application configured to communicate with memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory native to host system 105 or included in said host system), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 105 can use memory system 110, for example, to write data to and read data from memory system 110. Although in Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0025] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise convey control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, UFS interfaces, eMMC interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, USB interfaces, Fibre Channel, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR), Dual In-line Memory Module (DIMM) interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR). In some instances, one or more of these interfaces may be contained in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 or memory device 140 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 or memory device 140 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0026] Memory system 110 may include memory system controller 115, memory device 130, and memory device 140. Memory device 130 may include one or more memory arrays of a first type of memory cells (e.g., a type of non-volatile memory cells), and memory device 140 may include one or more memory arrays of a second type of memory cells (e.g., a type of volatile memory cells). Although in Figure 1 The example shows a memory device 130 and a memory device 140, but the memory system 110 may contain any number of memory devices 130 and memory devices 140, and in some cases, the memory system 110 may lack either memory device 130 or memory device 140.

[0027] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface). The memory system controller 115 may also be coupled to and communicate with memory device 130 or memory device 140 to perform operations generally referred to as access operations at memory device 130 or memory device 140, such as reading data, writing data, erasing data, or refreshing data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 or memory device 140 to execute such commands (e.g., at a memory array within one or more memory devices 130 or memory device 140). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to achieve the desired access to memory device 130 or memory device 140. In some cases, the memory system controller 115 may exchange data with the host system 105 and with one or more memory devices 130 or 140 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with memory devices 130 or 140 into corresponding signals for the host system 105.

[0028] The memory system controller 115 may be configured for other operations associated with memory device 130 or memory device 140. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error control operations such as error detection or error correction, encryption, caching, media management, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within memory device 130 or memory device 140.

[0029] The memory system controller 115 may include hardware, such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0030] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or operations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, data may be stored in local memory 120 when read from or written to memory device 130 or memory device 140, and may be available within local memory 120 for subsequent retrieval or manipulation (updating) by the host system 105 according to a caching strategy (e.g., in the case of reduced latency relative to memory device 130 or memory device 140).

[0031] although Figure 1 An example of memory system 110 has been shown to include memory system controller 115, but in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135 or 145, respectively, within memory device 130 or memory device 140, to perform the functions attributed herein to memory system controller 115. Generally, one or more functions attributed herein to memory system controller 115 may, in some cases, be performed by host system 105, local controller 135, or local controller 145, or any combination thereof.

[0032] Memory device 140 may include one or more arrays of volatile memory cells. For example, memory device 140 may include random access memory (RAM) cells, such as dynamic RAM (DRAM) cells and synchronous DRAM (SDRAM) cells. In some instances, memory device 140 may support random access operations (e.g., performed by host system 105) with reduced latency relative to memory device 130, or may provide one or more other performance differences relative to memory device 130.

[0033] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM).

[0034] In some instances, memory device 130 or memory device 140 may each include (e.g., on the same die or within the same package) a local controller 135 or local controller 145, which can perform operations on one or more memory cells of memory device 130 or memory device 140. Local controller 135 or local controller 145 may operate in conjunction with memory system controller 115, or may perform one or more functions categorized herein as belonging to memory system controller 115. In some cases, memory device 130 or memory device 140 including local controller 135 or local controller 145 may be referred to as a managed memory device and may include a memory array and associated circuitry combined with a local (e.g., on-die or within-package) controller (e.g., local controller 135 or local controller 145). An example of a managed memory device is a managed NAND (MNAND) device.

[0035] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be a package containing one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0036] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information; if configured to each store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to each store three bits of information, it may be referred to as a three-level cell (TLC); if configured to each store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write tolerances or greater complexity for supporting circuitry.

[0037] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, memory cells within different blocks 170 may be operated on in parallel, provided that the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175, which have the same page address within their respective planes 165 (e.g., regarding command decoding, page address decoding circuitry, and other circuitry shared across planes 165).

[0038] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled thereto).

[0039] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first-level granularity (e.g., at the page level), but can be erased at a second-level granularity (e.g., at the block level). That is, page 175 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single programming or reading operation), and block 170 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0040] System 100 may include any number of non-transitory computer-readable media that support status checks using signaling. For example, host system 105, memory system controller 115, memory device 130, or memory device 140 may include or otherwise access one or more non-transitory computer-readable media for performing the functions attributed herein to host system 105, memory system controller 115, memory device 130, or memory device 140. For example, such instructions, when executed by host system 105 (e.g., by host system controller 106), memory system controller 115, memory device 130 (e.g., by local controller 135), or memory device 140 (e.g., by local controller 145), may cause host system 105, memory system controller 115, memory device 130, or memory device 140 to perform the associated functions as described herein.

[0041] Memory device 130 may include a plurality of memory dies (e.g., die 160), and each memory die is configured to output a ready signal. The ready signal indicates whether the memory die is available to receive and / or execute commands from a host system. Memory device 130 may also include output circuitry. Output circuitry may be coupled to each memory die and configured to receive the ready signal. In some cases, the output circuitry may generate an indicator based on the value of the ready signal. In some instances, memory device 130 may include pins coupled between the output circuitry and a controller (e.g., memory system controller 115). These pins may be configured to output an indicator to the controller via an I / O channel.

[0042] Figure 2 An example of a system 200 supporting status checks using signaling, according to the examples disclosed herein, is shown. System 200 may include a controller 205 and a memory device 210. Memory device 210 may include output circuitry 215. In some cases, controller 205 and memory device 210 may be coupled via a first set of channels 220 and a second set of channels 225. Controller 205 and memory device 210 may each be as described in reference... Figure 1 Examples of the host system controller 106, memory system controller 115, or aspects thereof as described.

[0043] Memory device 210 may include memory dies. Each memory die may be configured to receive commands from a host system and execute those commands. At some point after executing a command or during the execution of a command, the memory die may be ready to receive and execute another command. Each die may be configured to output a ready signal indicating whether the memory die is available to receive commands. In some cases, memory device 210 may include output circuitry 215. Output circuitry 215 may be configured to receive the ready signal from the memory die and generate an indicator indicating whether the memory die is available. The indicator may be based on the value of the ready signal. In some instances, output circuitry 215 may be an example of an encoder or a shift register.

[0044] The first set of channels 220 may be coupled to the memory device 210 and the controller 205. In some cases, the first set of channels 220 may be an instance of a non-ONFI channel or a general purpose input / output (GPIO) channel. The first set of channels may be coupled to a first pin configured to output an indicator to the controller 205 via the first set of channels 220 (e.g., a first input / output (I / O) channel). The first pin may be coupled to the output circuitry 215 of the memory device 210. For example, the first pin may be an instance of a GPIO pin.

[0045] In some cases, the first set of channels 220 can be used to communicate with the controller 205. For example, the memory device 210 can transmit information to the controller 205 by transmitting signals via the first set of channels 220. In some cases, signals transmitted via the first set of channels 220 can interrupt the operation of the controller 205. In such cases, the first set of channels 220 can be an example of a interruptor for the controller 205. The first set of channels 220 can transmit a single bit per memory die in the memory device 210, the single bit indicating whether the memory device is ready to receive a command.

[0046] In memory systems where polling is used to determine the readiness status of memory dies, there can be a delay between when a memory die is ready and when controller 205 finally identifies that the memory die is ready to receive another command. Using a first set of pins (instead of status polling) to transmit the readiness status of the memory die reduces this delay between when the memory die is ready and when controller 205 identifies it as ready. In such cases, memory device 210 can perform an increased amount of parallel operation (e.g., increased parallelism) because it allows the host system to direct commands to memory dies that are ready earlier than if status polling were used.

[0047] The second channel 225 may be coupled to the memory device 210 and the controller 205. In some cases, the second channel 225 may be an example of an ONFI channel. The second channel 225 may transmit information at a faster speed than information transmitted via the first channel 220. For example, the second channel 225 may increase the compatibility of communication between memory devices 210 by transmitting information at a higher frequency compared to the first channel 220. In some instances, the second channel 225 may use an increased amount of power compared to the first channel 220. When transmitting information using the second channel 225, the resources of the memory device 210 may have a higher demand for other information. In such cases, the second channel 225 may experience inefficiency in the operation of the memory device 210. In some cases, the second channel 225 may not transmit information about ready signals. The increased speed of the second channel 225 (e.g., an ONFI channel) can be used to transfer data between the memory system and the host system, thereby improving the performance of the memory system. Therefore, using such ONFI resources for status polling can reduce the amount of data that can be transferred between the host system and the memory system.

[0048] Instead of the controller 205 transmitting multiple requests to each memory die in the memory device 210 via the second set of channels 225, the memory device 210 may send an indication that it is ready to receive commands to the controller 205. The memory device 210 may send the indication to the controller 205 via the first set of channels 220. The memory device 210 may send the indication via a dedicated pin (e.g., a first pin) coupled to the first set of channels 220, allowing the data to be compressed, thereby reducing signaling overhead and improving the overall operation of the memory device 210. In such cases, a direct connection between the memory device 210 and the controller 205 can increase processing time and reduce latency. In some cases, the first set of pins used to transmit the ready signal may be pins that may not be used in other contexts, or may have a purpose that is inactive during the normal operating mode of the memory system.

[0049] Figure 3 An example of an encoder-included system 300 supporting status checks using signaling, according to the examples disclosed herein, is shown. System 300 may include a controller 305, a memory die 310, and output circuitry 315. The controller 305 and output circuitry 315 may each be as described in the references... Figure 2 Examples of aspects of the described controller 205 and output circuit 215.

[0050] System 300 may include one or more memory dies 310 (e.g., memory dies 310-a, 310-b, 310-c, and 310-d). Memory dies 310 may be included in a memory device. Each memory die 310 may be coupled to an output circuit 315 via a channel 320. For example, memory die 310-a may be coupled to the output circuit 315 via channel 320-a, memory die 310-b may be coupled to the output circuit 315 via channel 320-b, memory die 310-c may be coupled to the output circuit 315 via channel 320-c, and memory die 310-d may be coupled to the output circuit 315 via channel 320-d.

[0051] Output circuit 315 may be an example of an encoder that receives input from one or more memory dies 310 and encodes the output for transmission to controller 305. The output may contain the address of a prepared memory die and / or a signal indicating that the address output by output circuit 315 is valid and should be read by controller 305. In some cases, if more than one memory die is prepared before the address can be output to controller 305, output circuit 315 may include a buffer.

[0052] In some cases, each memory die 310 may be configured to output a ready signal indicating whether it is available to receive a command. For example, memory die 310-a may output a ready signal indicating that it is available to receive a command. In some instances, memory dies 310-b, 310-c, and 310-d may each output a ready signal indicating that each of them is unavailable. In some cases, each memory die 310 may output a ready signal indicating that each of them is ready to receive a command. In such cases, each ready signal may be associated with a timestamp. The timestamp may indicate the order in which the memory dies 310 can receive commands in response to the transmitted ready signals. For example, if memory die 310-a outputs a ready signal before memory die 310-b, then memory die 310-a can receive commands before memory die 310-b.

[0053] Output circuitry 315 can be configured to receive a ready signal associated with each of memory dies 310-a, 310-b, 310-c, and 310-d. Based on the value of the ready signal, output circuitry 315 can generate an indicator. The indicator can contain two parts. A first part and a second part of the indicator can be configured to identify available memory dies 310. For example, the first part of the indicator can identify a memory die 310 ready to receive a command. In some cases, the first part of the indicator can indicate an index or address of an available memory die 310. In some instances, the first part of the indicator can contain more than one bit. For example, the number of bits contained in the first part of the indicator can be based on the number of memory dies 310 providing input to output circuitry 315. For example, if four memory dies provide input to output circuitry 315, the first part can be two bits to uniquely identify each memory die that may be ready.

[0054] The second part of the indicator may instruct the output circuit 315 to output information related to the ready signal transmitted by the memory die 310. For example, the second part of the indicator may indicate that the first part of the indicator is ready and / or output the indicator to the controller 305. In some instances, the second part of the indicator may be an instance of an activation signal.

[0055] Output circuitry 315 may be coupled to controller 305 via pin 325. For example, system 300 may include pins 325-a, 325-b, and 325-c. The number of pins 325 may be based on the number of memory dies coupled to output circuitry 315. For example, if system 300 may include four memory dies (e.g., memory dies 310-a, 310-b, 310-c, and 310-d), then system 300 may include three pins 325 (e.g., pins 325-a, 325-b, and 325-c).

[0056] Pins 325-a (e.g., the first pin) and 325-b (e.g., the second pin) may be coupled to output circuitry 315 and configured to output a portion (e.g., a first portion) of an indicator to controller 305 via a first I / O channel and a second I / O channel, respectively. Pins 325-a and 325-b may be configured to output the first portion of an indicator as identified in Table 1.

[0057]

[0058] Table 1

[0059] The memory device can output a first portion of an indicator via pins 325-a and 325-b, wherein the first portion of the indicator identifies an available memory die 310. For example, memory die 310-a can output a ready signal indicating that memory die 310-a is ready to receive a command. In such a case, the value of the ready signal received at the input of output circuit 315 can be a first value (e.g., "1"). Output circuit 315 can generate an address of the ready memory die (e.g., 00) and output said address via pins 325-a and 325-b. When a valid address is output via pins 325-a and 325-b, output circuit 315 can also output a signal via pin 325-c indicating that controller 305 should read the outputs of pins 325-a and 325-b. In such a case, the first portion of the indicator (e.g., a combination of "00") can be configured to identify that memory die 310-a is available.

[0060] In other instances, memory die 310-b may output a ready signal indicating that it is ready to receive commands. In such cases, output circuitry 315 may generate an address of the ready memory die (e.g., 01 as shown in Table 1) and output this address as a first part via pins 325-a and 325-b. When a valid address is output via pins 325-a and 325-b, output circuitry 315 may also output a signal via pin 325-c indicating that controller 305 should read the outputs of pins 325-a and 325-b. In such cases, the first part of the indicator (e.g., a combination of "01") may be configured to identify that memory die 310-b is available.

[0061] Memory die 310-c can output a ready signal indicating that it is ready to receive commands. In this case, output circuitry 315 can generate an address of the ready memory die (e.g., 10 as shown in Table 1) and output this address as a first part via pins 325-a and 325-b. When a valid address is output via pins 325-a and 325-b, output circuitry 315 can also output a signal via pin 325-c indicating that controller 305 should read the outputs of pins 325-a and 325-b. In this case, the first part of the indicator (e.g., the "10" combination) can be configured to identify that memory die 310-c is available.

[0062] In some cases, memory die 310-d may output a ready signal indicating that memory die 310-c is ready to receive commands. In such cases, output circuitry 315 may generate an address of the ready memory die (e.g., 11 as shown in Table 1) and output this address as a first part via pins 325-a and 325-b. When a valid address is output via pins 325-a and 325-b, output circuitry 315 may also output a signal via pin 325-c indicating that controller 305 should read the outputs of pins 325-a and 325-b. In such cases, the first part of the indicator (e.g., the "11" combination) may be configured to identify that memory die 310-d is available.

[0063] In some instances, the memory device may include a pin 325-c (e.g., a third pin) that can be coupled to output circuitry 315 and configured to output a second portion of an indicator. In some cases, the second portion of the indicator may be referred to as a second indicator to controller 305. The second portion may be configured to indicate whether controller 305 will read the indicator. For example, the value of the first portion may be output continuously on the corresponding pin. However, in some cases, the information may not be valid. The second portion can be used to indicate to controller 305 when controller 305 intends to treat the output of the first portion as valid information (e.g., a valid address). For example, if the value of pin 325-c is a first value, the second portion may indicate to controller 305 that the first portion should be read (e.g., output via pins 325-a and 325-b). If the value of pin 325-c is a second value, the second portion may indicate to controller 305 that the first portion should be ignored (e.g., not read) (e.g., output via pins 325-a and 325-b). In some instances, pins 325-a, 325-b, and 325-c may each be instances of GPIO pins.

[0064] Output circuitry 315 may be an example of an encoder. For example, output circuitry 315 includes an encoder configured to receive a ready signal and generate an indicator based on the ready signal. The use of an encoder reduces the number of pins used to transmit the ready signal rather than reducing the number of pins having dedicated ready signal pins for each memory die. For example, instead of the controller 305 continuously reading the ready signal from each memory die 310, output circuitry 315 may generate an indicator to notify the controller 305 when and which memory dies 310 are available. Using GPIO pins reduces the load on the ONFI channel. The use of an encoder reduces the total number of GPIO pins used to transmit the ready signal. By using dedicated pins and encoding the pins to transmit the ready status to the controller 305, system 300 can efficiently manage status checks without compromising channel bandwidth (e.g., ONFI channel bandwidth) and memory device performance. In such cases, the output circuit 315 can manage the command queue instead of the controller 305, and pins 325-a, 325-b, and 325-c can be dedicated to (e.g.) status checks.

[0065] In other systems, the memory device may be unable to interrupt the operation of the controller 305 and may communicate with the controller 305 after the operation is complete. In such cases, the memory device may experience increased latency, slower read, write, and erase speeds, and reduced processing time. In some cases, the controller 305 may check the state of each memory die, thereby increasing the overhead, latency, and inefficiency of the memory system. By encoding the state of each memory die 310, the memory device can operate with increased flexibility and efficiency by increasing the amount of encoded data. In some cases, the voltage level of each pin 325 can be adjusted to increase the efficiency of memory device operation.

[0066] Figure 4 An example of a shift register-included system 400 supporting status checks using signaling, according to the examples disclosed herein, is shown. System 400 may include a controller 405, a memory die 410, and output circuitry 415. The controller 405, memory die 410, and output circuitry 415 may each be as described in the references... Figure 2 Examples of the described aspects of the controller, memory die, and output circuitry.

[0067] System 400 may include memory dies 410 (e.g., memory dies 410-a, 410-b, 410-c, 410-d, 410-e, 410-f, 410-g, and 410-h). Memory dies 410 may be included in a memory device. Each memory die 410 may be coupled to output circuitry 415 via channel 420. For example, memory die 410-a may be coupled to output circuitry 415 via channel 420-a. In some cases, each memory die 410 may be configured to output a ready signal indicating whether the memory die 410 is available to receive a command. For example, memory die 410-a may output a ready signal indicating that memory die 410-a is ready to receive a command. In other instances, memory die 410-a may output a ready signal indicating that memory die 410-a is not available.

[0068] Output circuitry 415 may be an instance of a shift register that receives input from one or more memory dies 410 and outputs information for each memory die in a rotational manner. The output may include bits indicating whether a particular memory die is ready. The shift register may output signals for the memory dies in each clock cycle. The shift register indicates what the memory dies are indicating, causing the shift register to continuously cycle through signals for different memory dies. Controller 405 may identify which memory die is being output as ready based on the shift register's initialization operation.

[0069] Output circuitry 415 can be configured to receive a ready signal associated with each of the memory dies 410. Based on the value of the ready signal, output circuitry 415 can generate an indicator. The indicator can be configured to indicate whether the memory die 410 is available. In some instances, output circuitry 415 can be an instance of a shift register. Output circuitry 415 (e.g., a shift register) can store the ready signal and output the indicator via pin 425 through a first I / O channel. Output circuitry 415 can output data serially. For example, output circuitry 415 can latch inputs (e.g., ready signals) from each memory die 410 and output data (e.g., an indicator) for each memory die 410. Output circuitry 415 can cycle through each latch 430 associated with each corresponding memory die 410. For example, the output of pin 425-a can be an indicator for a single memory die 410. In such cases, controller 405 and output circuitry 415 can be combined to determine which memory die 410 data to output.

[0070] Output circuitry 415 can be configured to output an indicator to controller 405 based on a clock signal. For example, system 400 may include pin 425-b (e.g., a second pin) configured to receive a clock signal via a second I / O channel. Pin 425-b can be configured to synchronize the indicator output to controller 405 at a clock rate associated with controller 405. In some cases, output circuitry 415 may output information, but controller 405 may not be able to identify which memory die 410 transmitted the information. In such cases, clock signals can coordinate controller 405 and output circuitry 415 such that a clock cycle can correspond to each memory die 410. For example, a first clock cycle can correspond to memory die 410-a, and a second clock cycle can correspond to memory die 410-b. Memory devices can receive clock signals from controller 405 configured to synchronize output circuitry 415, where output circuitry 415 outputs the indicator at a clock rate. In such cases, output circuitry 415 can output an indicator at the same frequency (e.g., clock rate) that controller 405 can read from the indicator. In some instances, output circuitry 415 may output an indicator based on a received clock signal. Pins 425-a and 425-b may each be instances of GPIO pins. In some instances, pin 425-a may contain additional information based on the frequency or voltage of a ready signal. In some cases, when a clock signal is received, the data in the shift register is shifted to different latches.

[0071] In some cases, the output circuitry 415 may include a plurality of latches 430. Each of the latches 430 may be configured to store the value of a ready signal associated with a memory die 410. In such cases, each memory die 410 may be associated with a corresponding latch 430. For example, a first latch 430 may store the value of a ready signal associated with memory die 410-a, and a second latch 430 may store the value of a ready signal associated with memory die 410-b. The memory device may store the ready signal associated with each memory die 410 based on receiving the ready signal. In some instances, the output circuitry 415 may output an indicator based on storing the ready signal.

[0072] Output circuitry 415 may be configured to receive an enable signal via channel 440 and, based on the receipt of the enable signal, output an indicator to controller 405. The enable signal may be an instance of a status read command. In some cases, device 435 may transmit the enable signal to output circuitry 415 via channel 440. Device 435 may be an instance of a device external to the memory device or a device internal to the memory device. In some instances, the enable signal may be configured to activate output circuitry 415 to output an indicator to controller 405 based on the receipt of the enable signal.

[0073] Output circuitry 415 can output indicators, and controller 405 can read the indicators simultaneously and sequentially for each memory die 410. In such cases, output circuitry 415 (e.g., including a shift register) can increase speed and efficiency operation. In some instances, due to... Figure 3 The number of pins described is reduced compared to that of pin 425, thus allowing output circuitry 415 to operate at increased speed. In some cases, an enable signal can allow the memory device to reduce power consumption by preventing the transmission of an enable signal before a pending state (e.g., a ready signal) becomes available. In such cases, device 435 may not issue a command (e.g., an enable signal) until a state (e.g., incomplete) of one of the memory dies 410 becomes available.

[0074] In some cases, system 400 may allow discrete addressing of memory die 410 via planes, blocks, and / or pages identified by an identifier. In some cases, output circuitry 415 may receive a status associated with the completion of an operation (e.g., in the case of operation completion, interruption, or incompleteness), thereby improving the overall performance of the memory device.

[0075] Figure 5 A block diagram 500 illustrates a memory system 505 supporting status checks using signaling, according to an example disclosed herein. The memory system 505 may be as described in the reference... Figures 1 to 4 Examples of aspects of the described memory system. Memory system 505 may include signal receiver 510, indicator generator 515, and output component 520. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0076] Signal receiver 510 may receive a set of ready signals from a set of memory dies, wherein the ready signals in the set are configured to indicate whether a memory die in the set of memory dies is available to receive a command. In some instances, signal receiver 510 may receive a clock signal from a controller, the clock signal being configured to synchronize output circuitry that outputs an indicator at a clock rate, wherein the output indicator is based on the received clock signal.

[0077] In some instances, signal receiver 510 may receive an enable signal configured to activate output circuitry to output an indicator, wherein the output indicator is based on receiving the enable signal. In some instances, signal receiver 510 may store a set of ready signals associated with a set of memory dies based on receiving a set of ready signals, wherein the generation of an indicator is based on storing a set of ready signals.

[0078] The indicator generator 515 can generate an indicator of whether a memory die is available based on the values ​​of a set of ready signals.

[0079] Output component 520 can output an indicator to the controller via a first pin based on the generated indicator. In some instances, output component 520 can output a first portion of the indicator via the first pin. In some instances, output component 520 can output a second portion of the indicator to the controller via a second pin, wherein the first and second portions of the indicator identify available memory dies from a set of memory dies.

[0080] In some instances, output component 520 may output at least a first portion of an indicator via a first pin, the first portion of which identifies an available memory die from a set of memory dies. In some instances, output component 520 may output a second portion of the indicator to a controller via a second pin, wherein the second portion of the indicator indicates that the output circuitry outputs the first portion of the indicator in relation to a set of ready signals.

[0081] Figure 6 A flowchart illustrating one or more methods 600 for supporting status checks using signaling, according to examples disclosed herein, is shown. Operation of method 600 may be implemented by a memory system or its components as described herein. For example, operation of method 600 may be performed by, as referenced... Figure 5 The described memory system performs the function. In some instances, the memory system may execute a set of instructions to control the functional elements of the memory system to perform the described function. Alternatively, the memory system may use dedicated hardware to perform aspects of the described function.

[0082] Aspects of method 600 may be implemented by a controller and other components. Alternatively, aspects of method 600 may be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to a memory device). For example, when executed by a controller (e.g., memory system controller 115), the instructions may cause the controller to perform the operation of method 600.

[0083] At 605, a set of ready signals is received. For example, a memory system may receive a set of ready signals from a set of memory dies, wherein the ready signals in the set are configured to indicate whether a memory die in the set is available to receive a command. Operation of 605 may be performed according to the methods described herein. In some instances, aspects of the operation of 605 may be described by reference to... Figure 5 The described signal receiver is used to perform this action.

[0084] At 610, an indicator is generated. For example, the memory system may generate an indicator of whether a memory die is available based on the values ​​of a set of ready signals. The operation of 610 may be performed according to the method described herein. In some instances, aspects of the operation of 610 may be referenced. Figure 5The described indicator generator is used to execute.

[0085] At pin 615, an indicator is output. For example, a memory system may output an indicator to a controller via a first pin based on the generation of the indicator. The operation of pin 615 can be performed according to the method described herein. In some instances, aspects of the operation of pin 615 may be referenced. Figure 5 The output component described is used for execution.

[0086] In some instances, the device described herein may perform one or more methods, such as method 600. The device may include features, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: receiving a set of ready signals from a set of memory dies, wherein the ready signals are configured to indicate whether a memory die in the set of memory dies is available to receive a command; generating an indicator of memory die availability based on the values ​​of the set of ready signals; and outputting the indicator to a controller via a first pin based on the generated indicator.

[0087] In some instances of method 600 and the device described herein, the output indicator may further include an operation, feature, means, or instruction for outputting a first portion of the indicator via a first pin and a second portion of the indicator to a controller via a second pin, wherein the first and second portions of the indicator identify available memory dies from a set of memory dies.

[0088] In some instances of method 600 and the device described herein, the output indicator may further include an operation, feature, means, or instruction for: outputting a first portion of the indicator via at least a first pin, the first portion of the indicator identifying a usable memory die from a set of memory dies, and outputting a second portion of the indicator to a controller via a second pin, wherein the second portion of the indicator indicates that the output circuitry may output the first portion of the indicator associated with a set of ready signals.

[0089] Method 600 and some examples of the devices described herein may further include operations, features, means, or instructions for receiving a clock signal from a controller, the clock signal being configured to synchronize an output circuit that outputs an indicator at a clock rate, wherein the output indicator may be based on the received clock signal.

[0090] Method 600 and some examples of the apparatus described herein may further include operations, features, means, or instructions for receiving an enable signal configured to activate an output circuit to output an indicator, wherein the output indicator may be based on receiving the enable signal.

[0091] Method 600 and some examples of the apparatus described herein may further include operations, features, means, or instructions for storing a set of ready signals associated with a set of memory dies based on receiving a set of ready signals, wherein generating an indicator may be based on storing a set of ready signals.

[0092] It should be noted that the methods described herein are possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described can be combined.

[0093] An apparatus is described. The apparatus may include: a memory device comprising a set of memory dies, each of the set of memory dies configured to output a ready signal indicating whether the memory die is available to receive a command; an output circuit coupled to each of the set of memory dies and configured to receive a set of ready signals associated with the set of memory dies and generate an indicator based on the values ​​of the set of ready signals; and a first pin coupled to the output circuit and configured to output the indicator to a controller via an I / O channel.

[0094] Some instances of the device may include a second pin coupled to the output circuitry and configured to output a portion of the indicator to the controller via a second I / O channel, wherein the indicator may be configured to indicate whether the memory die is available, at least in part, based on the values ​​of the set of ready signals.

[0095] In some instances, the first and second portions of the indicator may be configured to identify usable memory dies among the set of memory dies. Some instances of the device may include a third pin coupled to the output circuitry and configured to output a second indicator to the controller, the second indicator being configurable to indicate whether the indicator has been read. In some instances, the second and third pins may include GPIO pins.

[0096] In some instances, the output circuitry includes an encoder configured to receive the set of ready signals and generate the indicator based on the set of ready signals. In some instances, the indicator may include a first portion indicating that the memory die in the set of memory dies is ready to receive the command, and a second portion indicating that the output circuitry is ready to output information related to the set of ready signals.

[0097] In some instances, the output circuitry includes a shift register configured to output the indicator to a controller for the memory dies in the set of memory dies based on a clock signal. Some instances of the device may include a second pin configured to receive a clock signal via a second I / O channel and synchronize the output of the indicator to the controller at a clock rate associated with the controller.

[0098] In some instances, the output circuitry may be further configured to receive an enable signal and output the indicator to the controller based on the receipt of the enable signal.

[0099] In some instances, the indicator may be configured to indicate whether a memory die in the set of memory dies is available based on the value of the set of ready signals. In some instances, the output circuitry further includes a set of latches, each configured to store the value of the set of ready signals associated with the set of memory dies. In some instances, the first pin includes a GPIO pin.

[0100] An apparatus is described. The apparatus may include: a memory device; and control circuitry coupled to the memory device and configured such that the apparatus: receives a plurality of ready signals from a plurality of memory dies, one of the ready signals being configured to indicate whether a memory die among the plurality of memory dies is available to receive a command; generates an indicator indicating whether the memory die is available based on the values ​​of the set of ready signals; and outputs the indicator to a controller via a first pin based on the generation of the indicator.

[0101] Some instances may further include control circuitry configured such that the device outputs a first portion of the indicator via a first pin and outputs a second portion of the indicator to the controller via a second pin, wherein the first and second portions of the indicator identify available memory dies among the set of memory dies.

[0102] Some instances may further include control circuitry configured such that the device outputs at least a first portion of the indicator via a first pin, wherein the first portion of the indicator identifies a usable memory die among the set of memory dies, and outputs a second portion of the indicator to the controller via a second pin, wherein the second portion of the indicator indicates that output circuitry can output the first portion of the indicator in relation to the set of ready signals.

[0103] Some examples may further include control circuitry configured such that the device receives a clock signal from the controller, the clock signal being configured to synchronize with an output circuitry that outputs the indicator at a clock rate, wherein the output of the indicator may be based on the receipt of the clock signal.

[0104] Some examples may further include control circuitry configured to cause the device to receive an enable signal, the enable signal being configured to activate the output circuitry to output the indicator, wherein the output of the indicator may be based on receiving the enable signal.

[0105] Some instances may further include control circuitry configured such that the device stores the set of ready signals associated with the set of memory dies based on receiving the set of ready signals, wherein the generation of the indicator may be based on storing the set of ready signals.

[0106] The information and signals disclosed herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, wherein the bus may have various bit widths.

[0107] The terms "electronic connectivity," "conductive contact," "connection," and "coupling" refer to the relationship between components that enable the flow of signals between them. Components are considered electronically connected (or electrically contacting, connected, or coupled) to each other if any conductive path exists between them that can enable the flow of signals between them at any given time. At any given time, the conductive path between electronically connected (or electrically contacting, connected, or coupled) components can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path between connected components that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the signal flow between connected components for a period of time.

[0108] The devices containing memory arrays discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOS), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0109] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. These terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority of charge carriers are electrons), the FET may be called an n-type FET. If the channel is p-type (i.e., the majority of charge carriers are holes), the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can make the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0110] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0111] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0112] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted over a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distribution such that different parts of the functions are implemented in different physical locations.

[0113] For example, the various illustrative blocks and modules described in connection with this disclosure may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor; however, alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0114] As used herein, the word "or" in a list of items contained in the claims (e.g., a list of items beginning with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be construed as the phrase "at least partially based on".

[0115] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then such coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these are also included within the scope of computer-readable media.

[0116] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A memory device comprising a plurality of memory dies, each of the plurality of memory dies being configured to output a ready signal indicating whether the memory die is ready to receive a command; An output circuit is coupled to each of the plurality of memory dies and configured to receive a plurality of ready signals associated with the plurality of memory dies via corresponding latches and to generate an indicator corresponding to a selected memory die among the plurality of memory dies based at least in part on the receipt of the plurality of ready signals. as well as A first pin, which is coupled to the output circuit and configured to output the indicator to the controller via a first input / output I / O channel.

2. The device according to claim 1, further comprising: Multiple channels are provided for coupling each of the multiple memory dies to the output circuit, respectively.

3. The device of claim 1, wherein the indicator includes bits indicating whether a particular memory die can be used to receive the command.

4. The device of claim 1, wherein the output circuit transmits the indicator for one of the plurality of memory dies in each clock cycle.

5. The device of claim 1, wherein the controller identifies the ready signal associated with each of the plurality of memory dies, based at least in part on an initialization operation for the output circuit.

6. The device of claim 1, wherein the output circuitry synchronizes the indicator corresponding to the selected memory die, at least in part based on a clock rate associated with the controller.

7. The device of claim 1, wherein the output circuitry includes a shift register that receives the ready signal from each of the plurality of memory dies.

8. The device of claim 7, wherein the shift register outputs the indicator for each of the plurality of memory dies in a rotational manner.

9. The device of claim 1, wherein the indicator includes information capable of indicating one or more of the planes, blocks, or pages associated with each of the plurality of memory dies.

10. An apparatus comprising: A memory device comprising a plurality of memory dies, each of the plurality of memory dies being configured to output a ready signal indicating whether the memory die is capable of receiving a command; An output circuit coupled to each of the plurality of memory dies and configured to receive a plurality of ready signals associated with the plurality of memory dies, and to generate an indicator configured to indicate whether the memory die is available, based at least in part on the values ​​of the plurality of ready signals; A plurality of first pins coupled to the output circuit and configured to output a first portion of the indicator to the controller via a first input / output I / O channel, wherein the plurality of memory dies comprises 2ⁿ memory dies, where n is the number of the plurality of first pins; as well as A second pin, coupled to the output circuit and configured to output a second portion of the indicator to the controller via a second I / O channel, wherein the second portion of the indicator is configured to indicate whether the controller can access the first portion of the indicator via the first I / O channel.

11. The device of claim 10, wherein the output circuitry includes an encoder for receiving the plurality of ready signals and encoding the first portion of the indicator and the second portion of the indicator.

12. The device of claim 10, wherein the indicator contains an address of the available memory die.

13. The device of claim 10, wherein the first portion of the indicator includes an indication of an index or address of the available memory die.

14. The apparatus of claim 10, wherein each of the plurality of ready signals includes a timestamp that provides an indication of the order in which the plurality of memory dies can receive the command.

15. An apparatus comprising: Memory devices; as well as Control circuitry, coupled to and configured to enable the device to: Multiple ready signals are received from multiple memory dies, wherein one of the multiple ready signals is configured to indicate whether the memory die among the multiple memory dies is capable of receiving a command; An indicator of whether the memory die is available is generated, at least in part, based on the values ​​of the plurality of ready signals; and The indicator is output to the controller, wherein the indicator contains an indication of the available memory dies among the plurality of memory dies.

16. The device of claim 15, wherein the control circuitry includes an encoder for receiving the plurality of ready signals and encoding the indicator.

17. The device of claim 15, wherein the indicator contains an address of the available memory die.

18. The device of claim 15, wherein the indicator includes a second indication of an index of the available memory die.

19. The apparatus of claim 15, wherein each of the plurality of ready signals includes a timestamp that provides the order in which the plurality of memory dies are capable of receiving the command.

20. The device of claim 15, wherein the control circuitry is further configured such that the device: Receive an enable signal configured to activate the output circuitry to output the indicator, wherein the output of the indicator is based at least in part on receiving the enable signal.

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