Magnetic storage array test structure and test method

Abstract

The application provides a magnetic storage array test structure, comprising: a magnetic storage array composed of a plurality of magnetic tunnel junction storage units distributed in an array; a plurality of test excitation lines corresponding to at least part of columns in the magnetic storage array, wherein each test excitation line is electrically connected to the first end of at least part of the magnetic tunnel junction storage units in a corresponding column; a plurality of test excitation electrodes electrically connected to the plurality of test excitation lines one by one; a plurality of test read lines corresponding to at least part of rows in the magnetic storage array, wherein each test excitation line is electrically connected to the second end of at least part of the magnetic tunnel junction storage units in a corresponding row; and a plurality of test read electrodes electrically connected to the plurality of test read lines one by one. The application can improve the number ratio of the magnetic tunnel junction storage units and the test electrodes, reduce the process development cost and improve the array test efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device testing technology, and in particular to a magnetic storage array testing structure and testing method. Background Technology

[0002] Magnetic random access memory (MRM) possesses advantages such as non-volatility, fast erase / write speeds, and low power consumption, making it a promising memory device. During MRM performance testing, it is necessary to test the device's low-resistivity (Rp) and tunneling magnetoresistance (TMR) to assess its performance. Traditional single-bit test structures require at least one test electrode (pad) per device, which suffers from high mask costs, a limited number of measurable devices, and difficulty in obtaining array information.

[0003] In traditional single-bit magnetic memory test structures, the top of the magnetic tunnel junction (MTJ) is electrically connected to the top metal layer (TM) via a top via (TV), and then connected to the test excitation electrode via a TM trace. The bottom is electrically connected to the bottom metal layer (BM) via a bottom via (BV), and then connected to the test read electrode via a trace. The test module contacts both the test excitation and read electrodes with probes to measure the voltage and current between them, thus determining the resistance value of the MTJ. Summary of the Invention

[0004] The magnetic storage array test structure and test method provided by this invention can significantly increase the ratio of magnetic tunnel junction storage cells to test electrodes, which is beneficial to reducing process development costs and improving array test efficiency.

[0005] In a first aspect, the present invention provides a magnetic storage array test structure, comprising:

[0006] A magnetic storage array, which consists of multiple magnetic tunnel junction storage cells distributed in an array;

[0007] Multiple test excitation lines, each test excitation line corresponding to at least a portion of columns in a magnetic storage array, wherein each test excitation line is electrically connected to a first end of at least a portion of the magnetic tunnel junction storage cells in the corresponding column;

[0008] Multiple test excitation electrodes are electrically connected to the multiple test excitation lines in a one-to-one correspondence.

[0009] Multiple test read lines, each corresponding to at least a portion of rows in the magnetic storage array, wherein each test excitation line is electrically connected to the second end of at least a portion of the magnetic tunnel junction memory cells in the corresponding row;

[0010] Multiple test readout electrodes are electrically connected to the multiple test readout lines in a one-to-one correspondence.

[0011] Optionally, the magnetic storage array includes two symmetrically arranged subarrays, with the plurality of test read electrodes disposed between the two subarrays; and / or, the plurality of test excitation electrodes disposed between the two subarrays.

[0012] Optionally, the plurality of test excitation lines correspond to columns 1 to i and columns j to n in the magnetic storage array, where n is the total number of columns in the magnetic storage array, and 1 ≤ i ≤ j ≤ n;

[0013] The plurality of test read lines correspond to rows 1 to k and rows l to m in the magnetic storage array, where m is the total number of rows in the magnetic storage array, and 1 ≤ k ≤ l ≤ m.

[0014] Optionally, each test excitation line is electrically connected to 1 to a magnetic tunnel junction memory cells and b to m magnetic tunnel junction memory cells in a corresponding column, where m is the total number of rows of the magnetic memory array, and 1 ≤ a ≤ b ≤ m;

[0015] Each test read line is electrically connected to 1 to c magnetic tunnel junction memory cells and d to n magnetic tunnel junction memory cells in the corresponding row, where n is the total number of rows in the magnetic memory array, and 1 ≤ c ≤ d ≤ n.

[0016] Optionally, the plurality of test readout electrodes have a first readout electrode group and a second readout electrode group;

[0017] The first read electrode group and the second read electrode group are respectively disposed on opposite sides of the magnetic storage array arranged in a horizontal direction. The first read electrode group corresponds to at least a portion of the rows in the upper 1 / 2 region of the magnetic storage array, and the second read electrode group corresponds to at least a portion of the rows in the lower 1 / 2 region of the magnetic storage array.

[0018] The plurality of test excitation electrodes have a first excitation electrode group and a second excitation electrode group;

[0019] The first excitation electrode group and the second excitation electrode group are respectively disposed on opposite sides of the magnetic storage array arranged in a vertical direction. The first excitation electrode group corresponds to at least a portion of the magnetic storage array in the half-region away from the first read electrode, and the second excitation electrode group corresponds to at least a portion of the magnetic storage array in the half-region close to the first read electrode.

[0020] Optionally, the magnetic tunnel junction storage unit includes a two-terminal device that utilizes one or more of the following to perform resistive state switching: spin-torque effect, voltage-controlled magnetic anisotropy effect, spin-orbit torque effect, and spin-torque effect.

[0021] Optionally, the magnetic tunnel junction storage unit includes a three-terminal device that uses the spin-orbit moment effect for resistive state switching, wherein the top electrode of the three-terminal device is electrically connected to the corresponding test excitation line, one of the bottom electrodes of the three-terminal device is electrically connected to the test read line, and the other bottom electrode of the three-terminal device is suspended.

[0022] Optionally, in the magnetic storage array, the row containing the magnetic tunnel junction storage cell electrically connected to the test excitation line has a corresponding test read line, and the magnetic tunnel junction storage cell electrically connected to the test excitation line is electrically connected to the corresponding test read line.

[0023] Secondly, the present invention also provides a method for testing magnetic storage arrays, the method comprising:

[0024] A write stimulus is provided to the magnetic tunnel junction memory cells in the magnetic storage array test structure described in any of the preceding claims, so that the plurality of magnetic tunnel junction memory cells are in a first resistive state or a second resistive state;

[0025] Test excitations are sequentially applied to multiple test excitation electrodes. When a test excitation is applied to each test excitation electrode, the output parameters of multiple test read electrodes are sequentially read to determine the first resistance value of the multiple magnetic tunnel junction memory cells in the first resistance state, or to determine the second resistance value of the multiple magnetic tunnel junction memory cells in the second resistance state.

[0026] Optionally, after providing write stimuli to the magnetic tunnel junction memory cells in the magnetic storage array test structure described in any of the preceding claims to put the plurality of magnetic tunnel junction memory cells into a first resistive state or a second resistive state, the method further includes: providing auxiliary stimuli to the magnetic tunnel junction memory cells in the magnetic storage array test structure.

[0027] In the technical solution provided by this invention, the magnetic storage array is composed only of magnetic tunnel junction memory cell arrays and does not contain MOS devices. Furthermore, by setting test excitation lines and test read lines corresponding to rows and columns in the magnetic storage array, the resistance of any magnetic tunnel junction memory cell in the magnetic storage array can be read through selective contact between the test excitation lines and test read lines and probes. Using this cross-point array as the test structure effectively increases the ratio of magnetic tunnel junction memory cells to test excitation electrodes and test read electrodes. Simultaneously, this test structure allows for the formation of multiple magnetic tunnel junction memory cells to be tested in a single fabrication process, effectively reducing the cost of the photomask and improving the testing efficiency of the fabrication process. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of a magnetic storage array test structure according to an embodiment of the present invention;

[0029] Figure 2 This is a schematic diagram of a magnetic storage array test structure according to another embodiment of the present invention;

[0030] Figure 3 This is a schematic diagram of a magnetic storage array test structure according to another embodiment of the present invention;

[0031] Figure 4 This is a schematic diagram of a magnetic storage array test structure according to another embodiment of the present invention;

[0032] Figure 5 This is a schematic diagram of a magnetic storage array test structure according to another embodiment of the present invention;

[0033] Figure 6 This is a schematic diagram of a magnetic storage array test structure according to another embodiment of the present invention;

[0034] Figure 7 This is a schematic diagram of a magnetic storage array test structure according to another embodiment of the present invention;

[0035] Figure 8 This is a schematic diagram of a magnetic storage array test structure according to another embodiment of the present invention;

[0036] Figure 9 This is a TMR-Rp diagram formed by the theoretical values ​​of a magnetic storage array without short circuits, according to another embodiment of the magnetic storage array testing method of the present invention.

[0037] Figure 10 The TMR-Rp diagram is formed by the theoretical values ​​of the magnetic storage array test structure with short circuits in another embodiment of the present invention.

[0038] Figure 11 This is a TMR-Rp diagram generated by a non-short-circuit array test in another embodiment of the magnetic storage array test method of the present invention;

[0039] Figure 12 The TMR-Rp diagram is generated for array testing with short circuits in another embodiment of the magnetic storage array test structure of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] This invention provides a magnetic storage array test structure, such as... Figure 1-2 As shown, it includes:

[0042] A magnetic storage array, which consists of multiple magnetic tunnel junction storage cells distributed in an array;

[0043] Multiple test excitation lines, each test excitation line corresponding to at least a portion of columns in a magnetic storage array, wherein each test excitation line is electrically connected to a first end of at least a portion of the magnetic tunnel junction storage cells in the corresponding column;

[0044] Multiple test excitation electrodes are electrically connected to the multiple test excitation lines in a one-to-one correspondence.

[0045] In some embodiments, the test excitation line is a metal lead used to input the test excitation. During the test, a voltage can be applied to the test excitation electrode by contacting it with a probe.

[0046] Multiple test read lines, each corresponding to at least a portion of rows in the magnetic storage array, wherein each test excitation line is electrically connected to the second end of at least a portion of the magnetic tunnel junction memory cells in the corresponding row;

[0047] Multiple test readout electrodes are electrically connected to the multiple test readout lines in a one-to-one correspondence.

[0048] In some embodiments, the test readout line is a metal lead used to read test results. During the test, the output parameters of the test readout electrode can be read by contacting the probe with the test readout electrode.

[0049] In some embodiments, the test excitation lines can be configured to correspond one-to-one with each column in the magnetic storage array, and the test read lines can be configured to correspond one-to-one with each row in the magnetic storage array. The test excitation lines are electrically connected to all magnetic tunnel junction memory cells in the corresponding column, and the test read lines are electrically connected to all magnetic tunnel junction memory cells in the corresponding row. This allows testing of each magnetic tunnel junction memory cell in the magnetic storage array. In this test structure, for an n×n array, the ratio of magnetic tunnel junction memory cells to motors is n:2.

[0050] In the technical solution provided by this invention, the magnetic storage array is composed only of a magnetic tunnel junction memory cell array and does not contain MOS devices. Furthermore, by setting test excitation lines and test read lines corresponding to rows and columns in the magnetic storage array, the resistance of any magnetic tunnel junction memory cell in the magnetic storage array can be read through selective contact between the test excitation lines and test read lines and probes. Using this cross-point array as the test structure effectively increases the ratio of magnetic tunnel junction memory cells to test excitation electrodes and test read electrodes. Simultaneously, this test structure allows for the formation of multiple magnetic tunnel junction memory cells to be tested in a single fabrication process, effectively reducing the cost of the photomask and improving the testing efficiency of the fabrication process.

[0051] As an optional implementation method, such as Figure 3 As shown, the magnetic storage array includes two symmetrically arranged sub-arrays, and the plurality of test read electrodes are disposed between the two sub-arrays; and / or, the plurality of test excitation electrodes are disposed between the two sub-arrays.

[0052] In some embodiments, Figure 3 The diagram illustrates a symmetrical arrangement of two subarrays, array 1 and array 2, with the test read electrodes positioned between them. This arrangement increases the ratio of magnetic tunnel junction memory cells to electrodes. Array 1 can be tested using test electrode groups A and B, while array 2 can be tested using test electrode groups B and C. For the case of two n×n arrays to be tested, this ratio increases to 2n:3.

[0053] As an optional implementation method, such as Figure 4 As shown, the plurality of test excitation lines correspond to columns 1 to i and columns j to n in the magnetic storage array, where n is the total number of columns in the magnetic storage array, and 1 ≤ i ≤ j ≤ n;

[0054] The plurality of test read lines correspond to rows 1 to k and rows l to m in the magnetic storage array, where m is the total number of rows in the magnetic storage array, and 1 ≤ k ≤ l ≤ m.

[0055] As an optional implementation, continue as follows Figure 4As shown, each test excitation line is electrically connected to 1 to a magnetic tunnel junction memory cells and b to m magnetic tunnel junction memory cells in a corresponding column, where m is the total number of rows in the magnetic memory array, and 1 ≤ a ≤ b ≤ m;

[0056] Each test read line is electrically connected to 1 to c magnetic tunnel junction memory cells and d to n magnetic tunnel junction memory cells in the corresponding row, where n is the total number of rows in the magnetic memory array, and 1 ≤ c ≤ d ≤ n.

[0057] In some embodiments, and in certain scenarios, it is not necessary to know the information of all magnetic tunnel junction memory cells in the array; rather, it is more important to know the information of a portion of the magnetic tunnel junction memory cells. For example... Figure 4 As shown, only the magnetic tunnel junction memory cells that need to be focused on have test excitation lines and corresponding electrodes, as well as test read lines and corresponding electrodes. Other bits do not need to be connected to both test excitation lines and corresponding electrodes at the same time. They can be left unconnected or connected to one of them. Therefore, only the magnetic tunnel junction memory cells that need to be focused on can be tested.

[0058] The aforementioned Figure 4 The illustration shows a scenario where only the magnetic tunnel junction memory cells at the four corner positions of the magnetic memory array are considered; however, those skilled in the art should understand that the aforementioned... Figure 4 The scenario described is merely one exemplary approach and does not constitute a limitation. For example, when focusing only on the magnetic tunnel junction memory cells at the center of the magnetic storage array, it can also be handled as follows: Figure 5 The configuration is as shown, where the plurality of test excitation lines correspond to columns i to j in the magnetic storage array, where n is the total number of columns in the magnetic storage array, 1 ≤ i ≤ j ≤ n; and the plurality of test read lines correspond to rows k to l in the magnetic storage array, where m is the total number of rows in the magnetic storage array, 1 ≤ k ≤ l ≤ m. As an optional implementation, the configuration continues as follows... Figure 5 As shown, each test excitation line is electrically connected to a to b magnetic tunnel junction memory cells in a corresponding column, where m is the total number of rows in the magnetic memory array, 1 ≤ a ≤ b ≤ m; each test read line is electrically connected to c to d magnetic tunnel junction memory cells in a corresponding row, where n is the total number of rows in the magnetic memory array, 1 ≤ c ≤ d ≤ n. It should be understood that the test excitation and read lines can be set in any row and column combination, mainly depending on which part of the magnetic tunnel junction memory cells is of greater interest during the test. In practice, the performance of the bits in the "middle" or "edge" of the array is mainly considered. The selected bit should be "centrally symmetrical" in its position within the array.

[0059] As an optional implementation method, such as Figure 6As shown, the plurality of test readout electrodes have a first readout electrode group and a second readout electrode group;

[0060] The first read electrode group and the second read electrode group are respectively disposed on opposite sides of the magnetic storage array arranged in a horizontal direction. The first read electrode group corresponds to at least a portion of the rows in the upper 1 / 2 region of the magnetic storage array, and the second read electrode group corresponds to at least a portion of the rows in the lower 1 / 2 region of the magnetic storage array.

[0061] The plurality of test excitation electrodes have a first excitation electrode group and a second excitation electrode group;

[0062] The first excitation electrode group and the second excitation electrode group are respectively disposed on opposite sides of the magnetic storage array arranged in a vertical direction. The first excitation electrode group corresponds to at least a portion of the magnetic storage array in the half-region away from the first read electrode, and the second excitation electrode group corresponds to at least a portion of the magnetic storage array in the half-region close to the first read electrode.

[0063] In some embodiments, since the resistance of the test excitation lines and test readout lines has a significant impact on the test results, the wiring can be optimized to ensure that each bit is in a similar conductive environment. In this embodiment, the "first half" of the test excitation electrode group is denoted as AH (high-order), and the second half is denoted as AL (low-order); similarly, the readout electrode group is also divided into BH and BL. Figure 6 As shown, the electrodes are arranged clockwise as AL-BL-AH-BH. This arrangement ensures that the total length of the test excitation line and test read line used in each magnetic tunnel junction storage unit is approximately the same during testing, effectively avoiding the influence of the resistance of the metal wires on the test results.

[0064] As an optional implementation, the magnetic tunnel junction storage unit includes a two-terminal device that utilizes any one or more of the following to perform resistive state switching: spin-torque effect, voltage-controlled magnetic anisotropy effect, spin-orbit torque effect, and spin-torque effect.

[0065] As an optional implementation method, such as Figure 7-8 As shown, the magnetic tunnel junction storage unit includes a three-terminal device that uses the spin-orbit moment effect for resistive state switching. The top electrode of the three-terminal device is electrically connected to the corresponding test excitation line, one of the bottom electrodes of the three-terminal device is electrically connected to the test read line, and the other bottom electrode of the three-terminal device is suspended.

[0066] In some embodiments, the novel spin-orbit torque (SOT) magnetic memory typically employs a three-terminal device structure. This SOT device includes at least a magnetic tunnel junction and a spin-orbit torque layer. During writing, current flows through the SOT layer, utilizing the spin-orbit torque effect to switch the magnetic tunnel junction, which is adjacent to the SOT layer, between high and low resistance states. During reading, current flows from the TV through the magnetic tunnel junction to one of the two BVs electrically contacting the SOT layer. This embodiment is applicable to the testing of the SOT device array. A complete three-terminal SOT device should have two vias on the bottom to provide the write current flowing through the SOT layer during writing. Since this embodiment primarily focuses on the device testing process, it can employ methods such as... Figure 8 The structure shown omits one of the through-holes (shown by the dashed line in the figure). For the magnetic storage array test structure formed by this device, the following is formed: Figure 7 The array structure shown.

[0067] As an optional implementation, in the magnetic storage array, the row containing the magnetic tunnel junction storage cell electrically connected to the test excitation line has a corresponding test read line, and the magnetic tunnel junction storage cell electrically connected to the test excitation line is electrically connected to the corresponding test read line.

[0068] This invention also provides a method for testing magnetic storage arrays, the method comprising:

[0069] A write stimulus is provided to the magnetic tunnel junction memory cells in the magnetic storage array test structure described in any of the preceding claims, so that the plurality of magnetic tunnel junction memory cells are in a first resistive state or a second resistive state;

[0070] Test excitations are sequentially applied to multiple test excitation electrodes. When a test excitation is applied to each test excitation electrode, the output parameters of multiple test read electrodes are sequentially read to determine the first resistance value of the multiple magnetic tunnel junction memory cells in the first resistance state, or to determine the second resistance value of the multiple magnetic tunnel junction memory cells in the second resistance state.

[0071] In some embodiments, during the testing process, a test module with a specified function is employed. The test module includes an excitation probe group electrically connected to test excitation electrode group A, and an excitation module that applies an excitation voltage to selected test excitation electrodes via the excitation probe group. This excitation voltage can be used for device state changes or readings. A read probe group electrically connected to test read electrode group B, and a read module that uses the read probe group to bring all test read electrodes to the same potential and can read the current flowing through each read electrode in turn or simultaneously. Using excitation methods such as magnetic fields, all bits in the array are set to a low-resistance state (Rp) or a high-resistance state (Rap). Then, read voltages are sequentially applied to the test excitation electrodes connected to each test excitation line where the corresponding magnetic tunnel junction memory cell is located, while bringing all test read electrodes to the same potential. The read module, which reads the current flowing through each test read electrode in turn or simultaneously, can obtain the resistance information of all magnetic tunnel junction memory cells. The core purpose of this embodiment is to test the TMR and Rp information of the array. Using, for example, an external magnetic field as excitation, all magnetic tunnel junction memory cells in the magnetic memory array are magnetized, bringing them all to the p-state or ap-state. For an array where all bits are in the p state, a read voltage V is applied to the excitation electrode of the selected i-th column. ri For example, approximately 10–100 mV; then, all read electrodes are placed at the same low potential, such as grounded. Utilizing the read module's functionality, the current value I flowing through each read electrode is read sequentially or simultaneously. p1 I p2 , ...I pm Then the p-state resistances of the magnetic tunnel junction in the i-th column are as follows: Similarly, for an array where all bits are in the ap state, the ap-state resistance of the magnetic tunnel junction in the i-th column can also be obtained. This method can be used to test the high and low resistance values ​​of all magnetic tunnel junctions in the array, and then calculate the tunneling magnetoresistance (TMR) of each magnetic tunnel junction. The TMR is calculated as follows: After completing the TMR calculation, plot the TMR-Rp graph.

[0072] like Figure 9-12 As shown, simulation results for this embodiment are presented. Considering the influence of the wire resistance of the test excitation line and test read line on the test results, the resistance of the test excitation line and test read line between the magnetic tunnel junction memory cells is set to 1Ω. For arrays without short circuits, the distributions of TMR and Rp are very concentrated, and their theoretical distribution diagrams are shown below. Figure 9 As shown, if short-circuit bits exist, they are represented by outlier bits in the graph, also known as tails. Their theoretical distribution is shown in the figure below. Figure 10 As shown. For arrays of magnetic tunnel junction memory cells without short circuits, the simulation results obtained using the aforementioned implementation methods are as follows. Figure 11 As shown. For arrays of magnetic tunnel junction memory cells with short circuits, simulation tests were performed using the aforementioned implementation methods, and the results are as follows. Figure 12 As shown in the diagram, based on the aforementioned simulation results, this embodiment can acquire array TMR-Rp information quite accurately; in particular, it can accurately identify tailing at different locations caused by different factors (such as partial short, CD variation, open, etc.). Therefore, this embodiment can serve as an effective method for acquiring array TMR-Rp information. It is worth noting that the resistance of the test excitation lines and test readout lines has a significant impact on the test results. In the metal interconnect process of the test structure, the resistance of the wires should be minimized as much as possible through material selection, structural design, and process optimization.

[0073] When the array size exceeds the expected number of test bits, only the magnetic tunnel junction memory cells of interest can be selected. This is achieved by connecting only the test excitation electrode to the test excitation line containing the memory cell of interest, leaving other test excitation lines floating; and only connecting the test read electrode to the test read line containing the memory cell of interest, connecting other test read lines to shunt electrodes. During bit reading, all test read electrode groups and shunt electrodes need to be connected to the same potential. This mitigates the creeping current caused by the unselected test read lines, allowing for accurate testing of the resistance information of the memory cell of interest. Preferably, the number of shunt electrodes should be minimized, for example, to one.

[0074] As an optional implementation, after providing write stimuli to the magnetic tunnel junction memory cells in the magnetic storage array test structure described in any of the foregoing claims to put the plurality of magnetic tunnel junction memory cells into a first resistive state or a second resistive state, the method further includes: providing auxiliary stimuli to the magnetic tunnel junction memory cells in the magnetic storage array test structure.

[0075] In some embodiments, all magnetic tunnel junction memory cells in the array are set to a low-resistance state (Rp) or a high-resistance state (Rap), and then auxiliary excitations such as magnetic fields and temperatures are applied. Then, read voltages are sequentially applied to the test excitation electrodes connected to each test excitation line where the expected test bit is located, while all test read electrodes are at the same potential. The read modules that read the current flowing through each test read electrode are read in turn or simultaneously to obtain the resistance information of all magnetic tunnel junction memory cells, and then the dependence of array flipping probability on auxiliary excitation is calculated.

[0076] Those skilled in the art will understand that all or part of the processes in the above method embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0077] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A magnetic storage array test structure, characterized in that, include: A magnetic storage array, which consists of multiple magnetic tunnel junction storage cells distributed in an array; Multiple test excitation lines, each corresponding to at least a portion of columns in a magnetic storage array, wherein each test excitation line is electrically connected to a first end of at least a portion of the magnetic tunnel junction memory cells in the corresponding column; Multiple test excitation electrodes are electrically connected to the multiple test excitation lines in a one-to-one correspondence. Multiple test read lines, each corresponding to at least a portion of rows in the magnetic storage array, wherein each test excitation line is electrically connected to the second end of at least a portion of the magnetic tunnel junction memory cells in the corresponding row; Multiple test readout electrodes are electrically connected to the multiple test readout lines in a one-to-one correspondence.

2. The magnetic storage array test structure according to claim 1, characterized in that, The magnetic storage array includes two symmetrically arranged sub-arrays, with the plurality of test read electrodes disposed between the two sub-arrays; and / or, the plurality of test excitation electrodes disposed between the two sub-arrays.

3. The magnetic storage array test structure according to claim 1, characterized in that, The plurality of test excitation lines correspond to columns 1 to i and columns j to n in the magnetic storage array, where n is the total number of columns in the magnetic storage array, and 1 ≤ i ≤ j ≤ n; The plurality of test read lines correspond to rows 1 to k and rows l to m in the magnetic storage array, where m is the total number of rows in the magnetic storage array, and 1 ≤ k ≤ l ≤ m.

4. The magnetic storage array test structure according to claim 1, characterized in that, Each test excitation line is electrically connected to 1 to a magnetic tunnel junction memory cells and b to m magnetic tunnel junction memory cells in a corresponding column, where m is the total number of rows of the magnetic memory array, and 1≤a≤b≤m; Each test read line is electrically connected to 1 to c magnetic tunnel junction memory cells and d to n magnetic tunnel junction memory cells in the corresponding row, where n is the total number of rows in the magnetic memory array, and 1 ≤ c ≤ d ≤ n.

5. The magnetic storage array test structure according to claim 1, characterized in that, The plurality of test read electrodes have a first read electrode group and a second read electrode group; The first read electrode group and the second read electrode group are respectively disposed on opposite sides of the magnetic storage array arranged in a horizontal direction. The first read electrode group corresponds to at least a portion of the rows in the upper 1 / 2 region of the magnetic storage array, and the second read electrode group corresponds to at least a portion of the rows in the lower 1 / 2 region of the magnetic storage array. The plurality of test excitation electrodes have a first excitation electrode group and a second excitation electrode group; The first excitation electrode group and the second excitation electrode group are respectively disposed on opposite sides of the magnetic storage array arranged in a vertical direction. The first excitation electrode group corresponds to at least a portion of the magnetic storage array in the half-region away from the first read electrode, and the second excitation electrode group corresponds to at least a portion of the magnetic storage array in the half-region close to the first read electrode.

6. The magnetic storage array test structure according to claim 1, characterized in that, The magnetic tunnel junction storage unit includes a two-terminal device that utilizes one or more of the following to perform resistive state switching: spin-torque effect, voltage-controlled magnetic anisotropy effect, spin-orbit torque effect, and spin-torque effect.

7. The magnetic storage array test structure according to claim 1, characterized in that, The magnetic tunnel junction storage unit includes a three-terminal device that uses the spin-orbit moment effect for resistive state switching. The top electrode of the three-terminal device is electrically connected to the corresponding test excitation line, one bottom electrode of the three-terminal device is electrically connected to the test read line, and the other bottom electrode of the three-terminal device is left floating.

8. The magnetic storage array test structure according to claim 1, characterized in that, In the magnetic storage array, the row containing the magnetic tunnel junction storage cell electrically connected to the test excitation line has a corresponding test read line, and the magnetic tunnel junction storage cell electrically connected to the test excitation line is electrically connected to the corresponding test read line.

9. A method for testing magnetic storage arrays, characterized in that, The method includes: A write stimulus is provided to the magnetic tunnel junction memory cells in the magnetic storage array test structure according to any one of claims 1-8, so that the plurality of magnetic tunnel junction memory cells are in a first resistive state or a second resistive state; Test excitations are sequentially applied to multiple test excitation electrodes. When a test excitation is applied to each test excitation electrode, the output parameters of multiple test read electrodes are sequentially read to determine the first resistance value of the multiple magnetic tunnel junction memory cells in the first resistance state, or to determine the second resistance value of the multiple magnetic tunnel junction memory cells in the second resistance state.

10. The method according to claim 9, characterized in that, After providing a write stimulus to the magnetic tunnel junction memory cells in the magnetic storage array test structure according to any one of claims 1-8, so that the plurality of magnetic tunnel junction memory cells are in a first resistive state or a second resistive state, the method further includes: providing an auxiliary stimulus to the magnetic tunnel junction memory cells in the magnetic storage array test structure.

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