Method, apparatus, device, medium for testing minimum operating voltage

Abstract

The application relates to a minimum working voltage test method, device, equipment and medium. The minimum working voltage test method can quickly locate relatively weak failed storage blocks in all storage blocks by adopting a reference working voltage to test other storage blocks except reference storage blocks and screening out the failed storage blocks; only the failed storage blocks screened out are subjected to voltage iteration tests until the failed storage blocks all meet preset passing conditions, and a test voltage when the conditions are met is taken as a minimum working voltage of a static random storage, so that multiple scanning voltage points do not need to be set for point-by-point tests, thereby greatly shortening the overall test duration and improving the test efficiency.

Description

Technical Field

[0001] This application relates to the field of semiconductor device testing technology, and in particular to a test method, apparatus, device, and medium for a minimum operating voltage. Background Technology

[0002] Static Random-Access Memory (SRAM) is widely used in large-scale integrated circuits (VLSI) due to its high speed, low power consumption, and good compatibility. However, during the manufacturing process of SRAM, physical factors such as process fluctuations and transistor threshold voltage drift can cause deviations in the electrical characteristics of the internal memory cells, resulting in changes in their minimum operating voltage (Vmin).

[0003] Currently, the Vmin of SRAM is typically obtained during the wafer testing stage using multi-point voltage testing and voltage scanning testing. Multi-point voltage testing involves setting a set of fixed voltage points for testing, but it can only obtain yield statistics at each fixed voltage point and cannot directly determine the exact minimum operating voltage of each chip. Voltage scanning testing, on the other hand, sets a starting voltage and a fixed step size during testing, and obtains the failure number of bits (FBC) distribution at different voltage points through step-by-step voltage scanning. Vmin can then be inferred from the changes in the failure number of bits.

[0004] However, existing testing technologies, which require manual setting of scan parameters, are prone to test errors and waste of resources; full-range point-by-point scanning is extremely time-consuming; at the same time, a large number of failure bit data logs occupy the memory of the Automatic Test Equipment (ATE), which seriously restricts mass production efficiency. Summary of the Invention

[0005] Therefore, it is necessary to provide a test method, apparatus, device, and medium for the minimum operating voltage to address the aforementioned technical problems.

[0006] In a first aspect, this application provides a method for testing the minimum operating voltage, the method comprising:

[0007] An initial test voltage is set, and a voltage convergence test is performed on the reference memory block of the static random access memory starting from the set initial test voltage. Based on the test results of the reference memory block, the test voltage that meets the preset convergence condition is taken as the reference operating voltage of the reference memory block.

[0008] Using the reference operating voltage, other memory blocks in the static random access memory, excluding the reference memory block, are tested to screen out failed memory blocks;

[0009] Based on the reference operating voltage, voltage iteration tests are performed on the failed memory blocks until all the selected failed memory blocks meet the preset pass conditions, and the test voltage when the preset pass conditions are met is taken as the minimum operating voltage of the static random access memory.

[0010] In one embodiment, the step of performing a voltage convergence test on a reference memory block of the static random access memory, starting from a predetermined initial test voltage, and using the test results of the reference memory block to determine the test voltage that satisfies a preset convergence condition as the reference operating voltage of the reference memory block, includes:

[0011] Using the initial test voltage as the test voltage, the reference memory block is tested to obtain the initial test result of the reference memory block under the initial test voltage;

[0012] The direction of the test voltage adjustment is determined based on the initial test results, and the next test voltage is determined based on the preset voltage adjustment strategy.

[0013] Repeatedly test and adjust the voltage of the reference memory block until the test result of the reference memory block changes, and take the test voltage when the test result of the reference memory block changes as the reference working voltage.

[0014] In one embodiment, the step of testing and adjusting the voltage of the reference memory block until the test result of the reference memory block changes, and using the test voltage at which the test result of the reference memory block changes as the reference operating voltage, includes:

[0015] Based on the initial test results, determine the first-stage voltage adjustment direction for the reference memory block and set the first-stage test voltage;

[0016] The reference memory block is tested using a first-level test voltage. If the test result of the reference memory block under the first-level test voltage changes state relative to the initial test result, a second-level test voltage is set between the initial test voltage and the first-level test voltage according to a step strategy, and a fine-tuning strategy is used to continue to approach the reference operating voltage.

[0017] If the test result of the reference memory block under the first-level test voltage does not change relative to the initial test result, the test voltage is adjusted along the first-level voltage adjustment direction and according to the fine-tuning strategy until the test result of the reference memory block changes.

[0018] In one embodiment, the step of continuing to approximate the reference operating voltage using a fine-tuning strategy includes:

[0019] If the test result of the reference memory block changes state relative to the initial test result, then starting from the second-level test voltage, the fine-tuning direction is determined according to the test result of the reference memory block under the second-level test voltage, and the test voltage is gradually adjusted in steps.

[0020] If the test result of the reference storage block does not change relative to the initial test result, then the first-stage voltage adjustment direction is maintained, and the test voltage is gradually adjusted with the first step length.

[0021] The test results of the reference memory block change again, and the boundary test voltage at the point of change is taken as the reference operating voltage.

[0022] In one embodiment, setting the second-level test voltage between the initial test voltage and the first-level test voltage according to a step strategy includes: using the intermediate voltage value between the initial test voltage and the first-level test voltage as the second-level test voltage.

[0023] In one embodiment, the step of using the reference operating voltage to test other memory blocks in the static random access memory besides the reference memory block, and screening out failed memory blocks, includes:

[0024] The reference operating voltage was used as the test voltage to perform read and write tests on the other memory blocks.

[0025] Based on the read / write test results of the other storage blocks, the storage blocks with a failure bit value greater than zero are identified as the failed storage blocks.

[0026] In one embodiment, the step of performing voltage iteration testing on the failed memory blocks based on the reference operating voltage until all the selected failed memory blocks meet the preset pass conditions includes:

[0027] Starting from the reference operating voltage, the test voltage is increased according to the second step size;

[0028] The failed memory block was subjected to read / write tests using the increased test voltage.

[0029] If there are still failed memory blocks that do not meet the preset pass conditions, then continue to execute the step of raising the test voltage according to the second step size and using the raised test voltage to perform read and write tests on the failed memory blocks; until all failed memory blocks meet the preset pass conditions.

[0030] In one embodiment, using the test voltage that satisfies the preset pass condition as the minimum operating voltage of the static random access memory includes:

[0031] If no failed memory block exists at the reference operating voltage, then the reference operating voltage shall be used as the minimum operating voltage of the static random access memory.

[0032] If a failed memory block exists at the reference operating voltage, the test voltage at which all failed memory blocks meet the preset pass condition shall be taken as the minimum operating voltage of the static random access memory.

[0033] Secondly, this application provides a test device for minimum operating voltage, the device comprising:

[0034] The benchmark testing module is used to set an initial test voltage, and to perform voltage convergence testing on the benchmark memory block of the static random access memory starting from the set initial test voltage. Based on the test results of the benchmark memory block, the test voltage that meets the preset convergence condition is used as the benchmark operating voltage of the benchmark memory block.

[0035] The screening module is used to test other memory blocks in the static random access memory, excluding the reference memory block, using the reference operating voltage, and to screen out the failed memory blocks.

[0036] The determination module is used to perform voltage iteration tests on the failed memory blocks based on the reference operating voltage until all the selected failed memory blocks meet the preset pass conditions, and the test voltage when the preset pass conditions are met is taken as the minimum operating voltage of the static random access memory.

[0037] Thirdly, this application provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the minimum operating voltage testing method described in the first aspect.

[0038] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the test method for the minimum operating voltage described in the first aspect.

[0039] The aforementioned minimum operating voltage test method, apparatus, equipment, and medium, by using a reference operating voltage to test other memory blocks besides the reference memory block and screening out the failed memory blocks, can quickly locate the weakest failed memory blocks among all memory blocks; voltage iteration testing is performed only on the screened failed memory blocks until all failed memory blocks meet the preset pass conditions, and the test voltage when the conditions are met is taken as the minimum operating voltage of the static random access memory. There is no need to set multiple scan voltage points for point-by-point testing, thereby significantly shortening the overall test time, improving test efficiency, reducing the amount of data logs generated, and freeing up the memory space of the test equipment. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the accompanying drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is a flowchart illustrating a method for testing the minimum operating voltage in one embodiment.

[0042] Figure 2 is a schematic diagram of the voltage convergence test of a reference memory block in one embodiment;

[0043] Figure 3 is a flowchart illustrating the testing and voltage adjustment of a reference memory block in one embodiment;

[0044] Figure 4 is another flowchart illustrating the test method for the minimum operating voltage in one embodiment;

[0045] Figure 5 is a structural block diagram of the test device for minimum operating voltage in one embodiment;

[0046] Figure 6 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0048] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0049] The minimum operating voltage testing method provided in this application embodiment can be applied to terminals, including but not limited to testing equipment, such as testing devices used in the wafer testing stage.

[0050] In one exemplary embodiment, refer to Figure 1As shown in Figure 4, a test method for minimum operating voltage is provided. Taking the application of this method to a terminal as an example, the terminal may include the following steps S110 to S130.

[0051] Step S110: Set the initial test voltage. Starting from the set initial test voltage, perform a voltage convergence test on the reference memory block of the static random access memory. Based on the test results of the reference memory block, use the test voltage that meets the preset convergence condition as the reference operating voltage of the reference memory block.

[0052] In this application, "reference memory block" refers to a memory block (e.g., Block1) selected from the chip array on the wafer, used as a reference object to determine the starting point for global testing of the entire chip. The reference memory block can be a randomly selected memory block.

[0053] In this application, "test result" refers to the feedback result of whether the number of failure bits (Δfbc) output by the test machine after performing a test on the memory block under the set test voltage is 0. When Δfbc=0, it is a pass; when Δfbc>0, it is a fail.

[0054] In this application, "preset convergence condition" refers to the state change of the test result of the reference memory block between adjacent test voltages (i.e., from pass to fail).

[0055] In this application, the “reference working voltage” is the critical voltage value at which the reference memory block can meet the preset pass condition (i.e., Δfbc=0).

[0056] In this embodiment, an initial test voltage is first applied to the reference memory block to obtain the test result of the reference memory block at the current voltage. If the current test result is a pass, it indicates that the reference memory block can still work normally at this voltage, and the test voltage has room for adjustment towards a lower voltage. If the current test result is a failure, it indicates that the current voltage is close to or below the critical value, and the test voltage needs to be adjusted towards a higher voltage. By repeatedly adjusting the test voltage and testing the reference memory block, the current test voltage continuously approaches the critical boundary voltage at which the test result of the reference memory block changes, thus obtaining the reference operating voltage.

[0057] In this embodiment, the initial test voltage can be set based on historical test data.

[0058] Step S120: Using a reference operating voltage, test other memory blocks in the static random access memory except for the reference memory block, and screen out the failed memory blocks.

[0059] The testing equipment uses a reference operating voltage as the test voltage to test all other memory blocks (e.g., Blocks 2-32) in the static random access memory (SRAM) sequentially, excluding the reference block. If any other memory block meets the preset pass condition (i.e., no failure bit is generated) under the reference minimum operating voltage, it indicates that the minimum operating voltage of this memory block is not higher than the reference minimum operating voltage. Conversely, if any other memory block generates a failure bit under the reference minimum operating voltage, it indicates that the minimum operating voltage of this memory block is higher than the reference operating voltage. In this case, this memory block is marked and recorded as a failed memory block.

[0060] Step S130: Based on the reference operating voltage, perform voltage iteration test on the failed memory blocks until all the selected failed memory blocks meet the preset pass conditions, and take the test voltage when the preset pass conditions are met as the minimum operating voltage of the static random access memory.

[0061] It should be understood that the minimum operating voltage (Vcc min) of a circuit refers to the minimum power supply voltage threshold that ensures the circuit can perform its internal functions. When the power supply voltage applied to the circuit is lower than the minimum operating voltage threshold, it will lead to insufficient transistor driving capability, signal setup timeout, or loss of charge in the storage nodes, thereby causing the circuit to malfunction. Taking the static random access memory (SRAM) of this application as an example, the minimum operating voltage of the SRAM refers to the lowest voltage value that ensures all storage cells within the SRAM can perform data read and write operations; once the power supply voltage is lower than this threshold, the logic state of the storage cells will undergo erroneous flipping or cannot be properly sensed.

[0062] In this embodiment, for failed memory blocks that cannot function properly at the reference operating voltage, the test voltage needs to be further increased. Starting from the reference operating voltage, the current test voltage is adjusted according to a preset increase direction (i.e., towards a higher voltage). Simultaneously, to reduce unnecessary operations on the testing equipment, after each voltage increase, the testing equipment only tests the selected failed memory blocks. If any failed memory blocks still fail the test at the increased test voltage, the voltage is further increased according to the aforementioned increase direction, and the testing process for the failed memory blocks is repeated. This cycle continues until all previously marked failed memory blocks can meet the preset pass conditions at the current test voltage. At this point, the current test voltage is the minimum operating voltage that can guarantee the global normal operation of the static random access memory.

[0063] The aforementioned minimum operating voltage testing method, by using a reference operating voltage to test other memory blocks besides the reference memory block and screening out the failed memory blocks, can quickly locate the weakest failed memory blocks among all memory blocks. Voltage iteration testing is performed only on the screened failed memory blocks until all failed memory blocks meet the preset pass conditions, and the test voltage when the conditions are met is taken as the minimum operating voltage of the static random access memory. There is no need to set multiple scan voltage points for point-by-point testing, which greatly shortens the overall test time, improves test efficiency, reduces the amount of data logs generated, and frees up the memory space of the test equipment.

[0064] In some embodiments, step S110 starts with a set initial test voltage and performs a voltage convergence test on the reference memory block of the static random access memory. Based on the test results of the reference memory block, the test voltage that meets the preset convergence condition is used as the reference operating voltage of the reference memory block. Referring to Figures 2 and 4, this includes steps S111-S113.

[0065] Step S111: Using the initial test voltage as the test voltage, test the reference memory block to obtain the initial test result of the reference memory block under the initial test voltage.

[0066] A preset initial test voltage is applied to a reference memory block, and the reference memory block is tested using a testing machine (e.g., read / write test). Based on the test results, it is determined whether the reference memory block has generated any failure bits, thus determining the initial test result of the reference memory block under the initial test voltage. For example, if the number of failure bits in the initial test result of the reference memory block is zero, the initial test result is determined to be a pass; if the number of failure bits in the functional test result is greater than zero, the initial test result is determined to be a failure.

[0067] Step S112: Determine the adjustment direction of the test voltage based on the initial test results, and determine the next test voltage according to the preset voltage adjustment strategy.

[0068] If the initial test result is a pass, it indicates that the reference memory block can function normally under the current test voltage. The minimum operating voltage of the reference memory block must be lower than the current test voltage; therefore, the adjustment direction of the test voltage is set to downward. Conversely, if the initial test result is a failure, it indicates that the current test voltage can no longer guarantee the normal operation of the reference memory block, and the test voltage must be adjusted towards a higher voltage. Therefore, the adjustment direction of the test voltage is set to upward. After determining the adjustment direction, the next test voltage for the reference memory block is set based on the preset voltage adjustment strategy, so that the reference memory block can be tested based on the next test voltage.

[0069] Step S113: Repeat the test and voltage adjustment of the reference memory block until the test result of the reference memory block changes, and take the test voltage when the test result of the reference memory block changes as the reference working voltage.

[0070] In this embodiment, the reference memory block is tested using the next test voltage determined in step S112 as the current test voltage. The test result of the reference memory block under the current test voltage is obtained. If the test result of the reference memory block under the current test voltage is a failure, the test is stopped, and the current test voltage is used as the reference operating voltage of the reference memory block. If the test result of the reference memory block under the current test voltage is a pass, the step of determining the next test voltage according to the preset voltage adjustment strategy and using the determined next test voltage as the current test voltage to test the reference memory block is repeated until the test result of the reference memory block is a failure, indicating that the preset convergence condition has been met. The test voltage at which the test result changes is determined as the reference operating voltage of the reference memory block.

[0071] Thus, by performing an initial test on the reference memory block and determining the voltage adjustment direction of the next test voltage based on the initial test results of the reference memory block, there is no need to manually set scanning parameters, avoiding invalid operations and resource waste. In this embodiment, the change in the test results of the reference memory block (from pass to failure) is used as a preset convergence condition. The test stops when the test results of the reference memory block change from pass to failure, and the test voltage when the test results of the reference memory block change is used as the reference working voltage. Only a limited number of voltage convergence tests need to be performed on a reference memory block to provide a reasonable starting test voltage for the subsequent global testing of the entire wafer, which reduces the test time and the amount of test data log generated, and helps to release the memory resources of the test equipment.

[0072] In some embodiments, step S113 involves testing and voltage adjustment of the reference memory block until the test result of the reference memory block changes, and the test voltage at which the test result of the reference memory block changes is used as the reference operating voltage. Referring to Figures 3 and 4, this includes:

[0073] Step S1131: Based on the initial test results, determine the direction of the first-stage voltage adjustment for the reference memory block and set the first-stage test voltage.

[0074] In this embodiment, the first-stage voltage adjustment direction is determined based on the initial test results of the reference memory block. If the initial test result is a pass, the first-stage voltage adjustment direction is downward, and the first-stage test voltage is set lower than the initial test voltage. If the initial test result is a failure, the first-stage voltage adjustment direction is upward, and the first-stage test voltage is set higher than the initial test voltage. By setting the first-stage test voltage, it is possible to quickly determine whether the critical operating voltage of the reference memory block is located on the lower or higher side of the initial test voltage, thereby reducing the number of subsequent tests.

[0075] For example, the initial test voltage is set to 0.8Vdd; if the initial test result is pass, the first-stage voltage adjustment direction is downward, and the first-stage test voltage is set to 0.75Vdd; if the initial test result is failure, the first-stage voltage adjustment direction is upward, and the first-stage test voltage is set to 0.9Vdd.

[0076] Step S1132: Test the reference memory block using the first-level test voltage. If the test result of the reference memory block under the first-level test voltage changes state relative to the initial test result, then set the second-level test voltage between the initial test voltage and the first-level test voltage according to the step strategy, and continue to approach the reference working voltage with the fine-tuning strategy.

[0077] When the reference memory block is tested using the first-level test voltage, if the test result of the first-level test voltage changes compared to the test result under the initial test voltage (e.g., initially passed but the first-level test becomes a failure, or initially failed but the first-level test becomes a pass), it indicates that the minimum reference operating voltage falls within the voltage range between the initial test voltage and the first-level test voltage. At this point, a stepping strategy (e.g., selecting the median voltage between the initial test voltage and the first-level test voltage) is used to set the second-level test voltage, narrowing the search range. Within this narrowed voltage range, a fine-tuning strategy (e.g., step-wise adjustments with small voltage amplitudes) is further employed to continue approaching the boundary test voltage until the boundary test voltage where a state change occurs (i.e., from pass to failure, or vice versa) is locked, and this boundary test voltage is used as the reference operating voltage.

[0078] In this embodiment, setting the second-level test voltage between the initial test voltage and the first-level test voltage according to a step strategy includes: using the intermediate voltage value between the initial test voltage and the first-level test voltage as the second-level test voltage.

[0079] Step S1133: If the test result of the reference memory block under the first-level test voltage has not changed relative to the initial test result, then continue to adjust the test voltage along the first-level voltage adjustment direction and according to the fine-tuning strategy until the test result of the reference memory block changes.

[0080] When the reference memory block is tested using the first-level test voltage, if the test result remains the same as the result under the initial test voltage (e.g., initially passed and the first-level test also passed, or initially failed and the first-level test also failed), it indicates that the minimum operating voltage of the reference is not within the range between these two voltage levels. Therefore, along the adjustment direction of the first-level voltage, a fine-tuning strategy is continuously used to gradually adjust the test voltage and test the reference memory block. This process is repeated until the test result changes (i.e., from pass to failure, or from failure to pass), and the test voltage at which the test result changes is taken as the reference operating voltage.

[0081] In this embodiment, the first-stage voltage adjustment direction and the first-stage test voltage are determined based on the initial test results, eliminating the need for manual prediction or setting of scanning parameters. When the test results change under the first-stage test voltage, a stepping strategy is used to narrow the search range, reducing the number of tests for the reference operating voltage. Simultaneously, after the stepping strategy or when the test results do not change under the first-stage test voltage, the system switches to a fine-tuning strategy for testing. This ensures the accuracy of the reference operating voltage test and avoids missing critical voltages due to excessively large voltage step sizes. Thus, the reference operating voltage can be determined by performing only a limited number of tests on the reference memory block, providing a reasonable starting voltage for subsequent tests on other memory blocks.

[0082] In some embodiments, step S113 continues to approximate the reference operating voltage using a fine-tuning strategy, as shown in Figure 4, including steps S13-1 to S13-3.

[0083] Step S13-1: If the test result of the reference memory block changes state relative to the initial test result, then take the second-level test voltage as the starting point, determine the fine-tuning direction based on the test result of the reference memory block under the second-level test voltage, and gradually adjust the test voltage with the first step length.

[0084] When it is determined that the test result at the first-level test voltage has changed relative to the initial test result, it indicates that the reference operating voltage falls within the range formed by the initial test voltage and the first-level test voltage. At this point, the second-level test voltage is set according to the step strategy, and the second-level test voltage is used as the starting voltage for the fine-tuning phase.

[0085] After determining the starting point for fine-tuning, the reference memory block is tested using the second-level test voltage. The subsequent fine-tuning direction is determined based on the test results. If the test result at the second-level test voltage is passed, it indicates that the current voltage can still ensure the normal operation of the reference memory block. The critical voltage is below the second-level test voltage, therefore the fine-tuning direction is determined to be downward voltage adjustment.

[0086] If the test result at the second-level test voltage is a failure, it means that the second-level test voltage is insufficient to drive the reference memory block to work. The critical voltage is above the second-level test voltage, so the fine-tuning direction is determined to be upward voltage adjustment.

[0087] After determining the fine-tuning direction, the test voltage is gradually adjusted along the fine-tuning direction with a preset first step length, and the reference memory block is tested once each time the test voltage is adjusted.

[0088] Step S13-2: If the test result of the reference memory block has not changed relative to the initial test result, then maintain the first-stage voltage adjustment direction and gradually adjust the test voltage with the first step length.

[0089] In this application, the first step length refers to the voltage adjustment step size used to accurately approximate the critical boundary of the reference operating voltage during the fine-tuning stage of voltage convergence testing of the reference memory block. The first step length is smaller than the difference between the first-stage test voltage and the initial test voltage.

[0090] If the test result at the first-level test voltage is the same as the initial test result (e.g., the initial result was a pass and the first-level test result is also a pass, or the initial result was a failure and the first-level test result is also a failure), then the reference operating voltage is not within the range between the initial test voltage and the first-level test voltage. In this case, there is no need to use a stepping strategy. Instead, the previously determined first-level voltage adjustment direction (i.e., adjusting the voltage downwards or upwards) is maintained, and the test voltage is adjusted sequentially along the voltage adjustment direction with a preset first step length. Each time the test voltage is adjusted, the reference memory block is tested once.

[0091] Step S13-3: Continue until the test result of the reference memory block changes again, and use the boundary test voltage at the time of the change as the reference operating voltage.

[0092] During the fine-tuning process following steps S13-1 or S13-2, the test results under adjacent test voltages are monitored and compared in real time. When a state change is detected in the test result of the reference memory block (i.e., from pass to failure, or from failure to pass), it is determined that the critical boundary has been approached, the fine-tuning test is stopped, and the boundary test voltage at the time of the state change (which can be the voltage of the last pass state before the change or the voltage of the first pass state after the change) is determined as the reference operating voltage.

[0093] It is understood that in this embodiment, regardless of whether the reference storage block changes state relative to the initial test result under the first-level test voltage in step S1013-2, or does not change state in step S1013-3, the above-mentioned fine-tuning strategy is uniformly adopted to continue the approximation process in the subsequent approximation of the reference working voltage.

[0094] To further illustrate the above-mentioned fine-tuning strategy, the following examples are provided (wherein, the voltage values ​​are merely examples and do not constitute a limitation on the scope of protection of this application).

[0095] The reference memory block was tested with an initial test voltage of 0.8Vdd, and the test result was a pass. Using a downward voltage adjustment direction, the first-stage test voltage was set to 0.75Vdd, and the reference memory block was tested again, resulting in a failure. Since the test result represents a change in state compared to the initial test result, the reference operating voltage should be between 0.8Vdd and 0.75Vdd. Following a step-by-step strategy, the midpoint between these two values, 0.775Vdd, was used as the second-stage test voltage, i.e., the fine-tuning starting point.

[0096] The reference memory block was tested with a second-stage test voltage of 0.775Vdd, and the result was a pass. Therefore, the fine-tuning direction was determined to be downward voltage adjustment. The first step length was set to 0.025Vdd. The first fine-tuning voltage was 0.775Vdd - 0.025Vdd = 0.75Vdd. Since 0.75Vdd has already been confirmed as the test result, if the test result changes state between 0.775Vdd and 0.75Vdd (from pass to failure), then the convergence condition is satisfied, fine-tuning stops, and the boundary test voltage of 0.775Vdd before the change is determined as the reference operating voltage.

[0097] For example, the reference memory block is tested with an initial test voltage of 0.8Vdd, and the test result is a pass. The first-stage test voltage of 0.75Vdd also passes (no state change occurs). Following the path of step S1013-3, the process directly enters the fine-tuning stage. Maintaining the downward voltage adjustment direction, the test is performed sequentially with the first-stage voltage of 0.025Vdd: the reference memory block is tested with 0.725Vdd, and the test result is a pass; the reference memory block is tested with 0.70Vdd, and the test result is a failure. If a change is found between the adjacent 0.725Vdd and 0.70Vdd values, the test is stopped, and 0.725Vdd is determined as the reference operating voltage.

[0098] This embodiment employs a fine-tuning strategy. If the test result of the reference storage block changes relative to the initial test result, differentiated fine-tuning paths are set, starting from the second-level test voltage and the first-level voltage adjustment direction, respectively. This allows the fine-tuning process to start directly from the known position closest to the critical boundary, reducing the number of tests. A fixed first step length is used for unidirectional fine-tuning, avoiding the extra number of tests caused by backtracking while ensuring accuracy. At the same time, the convergence condition is used by the recurrence of state changes in the test result. Once the critical boundary is reached, the test stops immediately, effectively controlling the total test time of the fine-tuning phase.

[0099] In some embodiments, step S120 uses a reference operating voltage to test other memory blocks in the static random access memory besides the reference memory block, and filters out the failed memory blocks. Referring to FIG4, this includes steps S121-S122.

[0100] Step S121: Use the reference operating voltage as the test voltage to perform read and write tests on other memory blocks.

[0101] In this embodiment, after obtaining the reference operating voltage of the reference memory block, the operating voltage applied to the static random access memory by the test equipment is set as the reference operating voltage. Under fixed voltage conditions, all other memory blocks in the static random access memory (e.g., Block 2-Block 32) except for the reference memory block are sequentially traversed, and read / write tests are performed on each other memory block to determine whether there are weak memory blocks caused by process deviations or other factors.

[0102] Step S122: Based on the read and write test results of other storage blocks, the storage blocks with a failure bit value greater than zero are identified as failed storage blocks.

[0103] Based on the number of failure bits after read / write tests of other memory blocks, if the number of failure bits for any other memory block in Blocks 2-32 is zero, then this memory block is determined to be able to operate normally under the reference operating voltage, and no further testing is required. If the number of failure bits for any other memory block in Blocks 2-32 is greater than zero, then the minimum operating voltage of this memory block is determined to be higher than the current reference operating voltage, meaning this memory block is a weak memory block in the entire wafer. Memory blocks with a failure bit greater than zero are identified as failed memory blocks.

[0104] In this way, by testing all memory blocks except the reference block at a single reference operating voltage, the distribution of weak points in all memory blocks of the entire wafer can be determined, reducing the number of tests and shortening the testing time. Failed memory blocks that cannot function properly at the reference operating voltage are identified by using the number of failures. These failed memory blocks are the weak points that limit the minimum operating voltage of the wafer. Subsequent testing only targets these failed memory blocks, eliminating the need to waste testing resources on memory blocks that have already passed testing, thus balancing testing efficiency and reliability.

[0105] In some embodiments, step S130 performs voltage iteration testing on the failed memory blocks until all the selected failed memory blocks meet the preset pass conditions, referring to Figure 4, including steps S131-S133.

[0106] Step S131: Starting from the reference working voltage, increase the test voltage according to the second step size.

[0107] In this embodiment, if a failed memory block is selected, the reference operating voltage is used as the starting point for the rise, and the test voltage is raised according to the preset second step size to set a higher next test voltage.

[0108] The value of the second step length can be the same as or different from the first step length. Furthermore, the first step length and the second step length can be flexibly set.

[0109] In this application, the second step size refers to the voltage adjustment step size used during the voltage rise phase of the voltage iteration test on the failed memory block to quickly increase the test voltage and restore the failed memory block to normal operation. The second step size is larger than the first step size and is used to unidirectionally rise the test voltage based on the reference operating voltage to accelerate the convergence process of the failed memory block.

[0110] Step S132: Use the increased test voltage to perform read and write tests on the failed memory block.

[0111] In this embodiment, the increased test voltage is used as the current test voltage. The test machine performs read and write tests on the selected failed memory blocks to verify whether the failed memory blocks can recover normal read and write operations under the new test voltage.

[0112] Step S133: If there are still failed memory blocks that do not meet the preset pass conditions, continue to execute the step of raising the test voltage according to the second step length and using the raised test voltage to perform read and write tests on the failed memory blocks; until all failed memory blocks meet the preset pass conditions.

[0113] After completing the test in step S132, if at least one failed memory block still has a failure bit count greater than zero (i.e., the preset pass condition is still not met), the test loop returns to steps S131 and S132. Based on the current test voltage, the voltage is increased again by the second step size, and the failed memory blocks that still fail are tested according to the new increased voltage. This process is repeated iteratively until all previously marked failed memory blocks have a failure bit count of zero at the increased voltage. At this point, the current test voltage becomes the minimum operating voltage that ensures all memory blocks of the static random access memory (SRAM) function normally.

[0114] In some embodiments, step S103 uses the test voltage that meets the preset pass conditions as the minimum operating voltage of the static random access memory, including: if there are no failed memory blocks under the reference operating voltage, then the reference operating voltage is used as the minimum operating voltage of the static random access memory; if there are failed memory blocks under the reference operating voltage, then the test voltage that meets the preset pass conditions for all failed memory blocks is used as the minimum operating voltage of the static random access memory.

[0115] If, in the test of step S120, all other memory blocks except the reference memory block pass the read / write test at the reference operating voltage (i.e., all failure bits are 0), it indicates that there is no memory block weaker than the reference memory block in the entire wafer; that is, the reference memory block is the weakest memory block. In this case, no voltage boosting operation is required, and the reference operating voltage is directly determined as the minimum operating voltage of the static random access memory.

[0116] If any faulty memory blocks fail during the test in step S120, then the voltage iterative boost test in steps S131 to S133 must be performed. When all the faulty memory blocks that were originally faulty meet the preset pass conditions after gradual boosting, the current boosted test voltage is the minimum operating voltage of the entire static random access memory wafer.

[0117] In this way, only the selected failed memory blocks are subjected to voltage boosting tests, rather than repeated full-range tests on all memory blocks, reducing the number of tests and saving testing time. By using a second step to unidirectionally boost the test voltage, all failed memory blocks pass the convergence condition of stopping the test, avoiding unnecessary overvoltage testing. At the same time, the presence of failed memory blocks in the initial state is directly determined, ensuring that whether it is a good chip or a chip with process deviations, the final minimum operating voltage can be directly output with the simplest judgment path. It can also be used to evaluate the minimum operating voltage of static random access memory at different temperatures.

[0118] The aforementioned minimum operating voltage testing method, by using a reference operating voltage to test other memory blocks besides the reference memory block and screening out the failed memory blocks, can quickly locate the weakest failed memory blocks among all memory blocks. Voltage iteration testing is performed only on the screened failed memory blocks until all failed memory blocks meet the preset pass conditions, and the test voltage when the conditions are met is taken as the minimum operating voltage of the static random access memory. There is no need to set multiple scan voltage points for point-by-point testing, which greatly shortens the overall test time, improves test efficiency, reduces the amount of data logs generated, and frees up the memory space of the test equipment.

[0119] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0120] Based on the same inventive concept, this application also provides a minimum operating voltage testing device for implementing the minimum operating voltage testing method described above. The solution provided by this device is similar to the solution described in the above method; therefore, the specific limitations in one or more minimum operating voltage testing device embodiments provided below can be found in the limitations of the minimum operating voltage testing method described above, and will not be repeated here.

[0121] According to an exemplary embodiment, this embodiment provides a test apparatus for minimum operating voltage, such as... Figure 5 As shown, the minimum operating voltage testing device includes a reference test module 201, a screening module 202, and a determination module 203.

[0122] The benchmark test module 201 is used to set an initial test voltage, and to perform voltage convergence test on the reference storage block of the static random access memory starting from the set initial test voltage. Based on the test results of the reference storage block, the test voltage that meets the preset convergence condition is used as the reference operating voltage of the reference storage block.

[0123] The screening module 202 is used to test other memory blocks in the static random access memory (SRAM) except for the reference memory block using a reference operating voltage, and to screen out the failed memory blocks.

[0124] The determination module 203 performs voltage iteration tests on the failed memory blocks based on the reference operating voltage until all the selected failed memory blocks meet the preset pass conditions, and takes the test voltage when the preset pass conditions are met as the minimum operating voltage of the static random access memory.

[0125] In some embodiments, the benchmark module 201 includes an initial test unit and an approximation test unit.

[0126] The initial test unit is used to test the reference memory block using the initial test voltage as the test voltage, and obtain the initial test results of the reference memory block under the initial test voltage.

[0127] The approximation test unit is used to determine the adjustment direction of the test voltage based on the initial test results, and to determine the next test voltage according to the preset voltage adjustment strategy; the test and voltage adjustment of the reference memory block are repeated until the test results of the reference memory block change, and the test voltage when the test results of the reference memory block change is used as the reference working voltage.

[0128] In some embodiments, the approximation test unit includes a first-level test subunit and a fine-tuning subunit.

[0129] The first-level test subunit is used to determine the direction of the first-level voltage adjustment of the reference memory block based on the initial test results, and to set the first-level test voltage to test the reference memory block.

[0130] The fine-tuning subunit is used to set the second-level test voltage between the initial test voltage and the first-level test voltage according to a step strategy if the test result of the reference memory block under the first-level test voltage changes relative to the initial test result, and to continue to approach the reference working voltage with a fine-tuning strategy; if the test result of the reference memory block under the first-level test voltage does not change relative to the initial test result, the test voltage is adjusted along the first-level voltage adjustment direction and according to the fine-tuning strategy until the test result of the reference memory block changes.

[0131] The fine-tuning subunit is used to adjust the test voltage step by step, starting from the second-level test voltage, if the test result of the reference memory block changes state relative to the initial test result, and determines the fine-tuning direction based on the test result of the reference memory block under the second-level test voltage. If the test result of the reference memory block does not change state relative to the initial test result, the first-level voltage adjustment direction is maintained, and the test voltage is adjusted step by step, until the test result of the reference memory block changes again, and the boundary test voltage at the time of the change is used as the reference operating voltage.

[0132] Furthermore, the fine-tuning subunit includes a second-level test subunit, which is used to take the intermediate voltage value between the initial test voltage and the first-level test voltage as the second-level test voltage.

[0133] In some embodiments, the screening module 202 is used to perform read and write tests on other memory blocks using a reference operating voltage as the test voltage; and to determine memory blocks with a failure bit greater than zero as failure memory blocks based on the read and write test results of each other memory block.

[0134] In some embodiments, the determining module 203 is used to start from the reference operating voltage and increase the test voltage according to the second step size; use the increased test voltage to perform read and write tests on the failed memory blocks; if there are still failed memory blocks that do not meet the preset pass conditions, the steps of increasing the test voltage according to the second step size and using the increased test voltage to perform read and write tests on the failed memory blocks continue to be executed until all failed memory blocks meet the preset pass conditions.

[0135] In some embodiments, the determining module 203 is configured to, if there are no failed memory blocks under the reference operating voltage, use the reference operating voltage as the minimum operating voltage of the static random access memory; if there are failed memory blocks under the reference operating voltage, use the test voltage when all failed memory blocks meet the preset pass conditions as the minimum operating voltage of the static random access memory.

[0136] Each module in the aforementioned minimum operating voltage testing device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in a computer device, or stored in the memory of a computer device as software, so that the processor can call and execute the corresponding operations of each module.

[0137] In one exemplary embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 6 As shown, the computer device includes a processor, memory, input / output (I / O) interfaces, and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system, computer programs, and a database. The internal memory provides an environment for the operation of the operating system and computer programs stored in the non-volatile storage medium. The database stores test data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements the minimum operating voltage test method of the above embodiment.

[0138] Those skilled in the art will understand that Figure 6 The structure shown is only a block diagram of a part of the structure related to the present application and does not constitute a limitation on the computer device on which the present application is applied. The specific computer device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0139] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the test method for the minimum operating voltage of the above embodiments.

[0140] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the test method for the minimum operating voltage of the above embodiments.

[0141] It should be noted that the information (including but not limited to equipment information, test information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the client or fully authorized by all parties, and the collection, use and processing of related data must comply with relevant regulations.

[0142] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0143] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0144] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for testing minimum operating voltage, characterized in that, The method includes: An initial test voltage is set, and a voltage convergence test is performed on the reference memory block of the static random access memory starting from the set initial test voltage. Based on the test results of the reference memory block, the test voltage that meets the preset convergence condition is taken as the reference operating voltage of the reference memory block. Using the reference operating voltage, other memory blocks in the static random access memory, excluding the reference memory block, are tested to screen out failed memory blocks; Based on the reference operating voltage, voltage iteration tests are performed on the failed memory blocks until all the selected failed memory blocks meet the preset pass conditions, and the test voltage when the preset pass conditions are met is taken as the minimum operating voltage of the static random access memory.

2. The method for testing the minimum operating voltage according to claim 1, characterized in that, The step of performing a voltage convergence test on a reference memory block of a static random access memory (SRAM) starting from a predetermined initial test voltage, and then using the test results of the reference memory block to determine the test voltage that meets a preset convergence condition as the reference operating voltage of the reference memory block, includes: Using the initial test voltage as the test voltage, the reference memory block is tested to obtain the initial test result of the reference memory block under the initial test voltage; The direction of the test voltage adjustment is determined based on the initial test results, and the next test voltage is determined based on the preset voltage adjustment strategy. Repeatedly test and adjust the voltage of the reference memory block until the test result of the reference memory block changes, and take the test voltage when the test result of the reference memory block changes as the reference working voltage.

3. The method for testing the minimum operating voltage according to claim 2, characterized in that, The step of testing and adjusting the voltage of the reference memory block until the test result of the reference memory block changes, and using the test voltage at which the test result of the reference memory block changes as the reference operating voltage, includes: Based on the initial test results, determine the first-stage voltage adjustment direction for the reference memory block and set the first-stage test voltage; The reference memory block is tested using a first-level test voltage. If the test result of the reference memory block under the first-level test voltage changes state relative to the initial test result, a second-level test voltage is set between the initial test voltage and the first-level test voltage according to a step strategy, and a fine-tuning strategy is used to continue to approach the reference operating voltage. If the test result of the reference memory block under the first-level test voltage does not change relative to the initial test result, the test voltage is adjusted along the first-level voltage adjustment direction and according to the fine-tuning strategy until the test result of the reference memory block changes.

4. The test method for minimum operating voltage according to claim 3, characterized in that, The step of continuing to approximate the reference operating voltage using a fine-tuning strategy includes: If the test result of the reference memory block changes state relative to the initial test result, then starting from the second-level test voltage, the fine-tuning direction is determined according to the test result of the reference memory block under the second-level test voltage, and the test voltage is gradually adjusted in steps. If the test result of the reference storage block does not change relative to the initial test result, then the first-stage voltage adjustment direction is maintained, and the test voltage is gradually adjusted with the first step length. The test results of the reference memory block change again, and the boundary test voltage at the point of change is taken as the reference operating voltage.

5. The test method for minimum operating voltage according to claim 3, characterized in that, Setting the second-level test voltage between the initial test voltage and the first-level test voltage using a step strategy includes: using the intermediate voltage value between the initial test voltage and the first-level test voltage as the second-level test voltage.

6. The test method for minimum operating voltage according to claim 1, characterized in that, The step of using the reference operating voltage to test other memory blocks in the static random access memory (SRAM) besides the reference memory block to screen out failed memory blocks includes: The reference operating voltage was used as the test voltage to perform read and write tests on the other memory blocks. Based on the read / write test results of the other storage blocks, the storage blocks with a failure bit value greater than zero are identified as the failed storage blocks.

7. The method for testing the minimum operating voltage according to claim 1, characterized in that, The step of performing voltage iteration testing on the failed memory blocks based on the reference operating voltage until all the selected failed memory blocks meet the preset pass conditions includes: Starting from the reference operating voltage, the test voltage is increased according to the second step size; The failed memory block was subjected to read / write tests using the increased test voltage. If there are still failed memory blocks that do not meet the preset pass conditions, then continue to execute the step of raising the test voltage according to the second step size and using the raised test voltage to perform read and write tests on the failed memory blocks; until all failed memory blocks meet the preset pass conditions.

8. The method for testing the minimum operating voltage according to claim 1, characterized in that, The step of using the test voltage that meets the preset pass condition as the minimum operating voltage of the static random access memory includes: If no failed memory block exists at the reference operating voltage, then the reference operating voltage shall be used as the minimum operating voltage of the static random access memory. If a failed memory block exists at the reference operating voltage, the test voltage at which all failed memory blocks meet the preset pass condition shall be taken as the minimum operating voltage of the static random access memory.

9. A testing device for minimum operating voltage, characterized in that, The device includes: The benchmark testing module is used to set an initial test voltage, and to perform voltage convergence testing on the benchmark memory block of the static random access memory starting from the set initial test voltage. Based on the test results of the benchmark memory block, the test voltage that meets the preset convergence condition is used as the benchmark operating voltage of the benchmark memory block. The screening module is used to test other memory blocks in the static random access memory, excluding the reference memory block, using the reference operating voltage, and to screen out the failed memory blocks. The determination module is used to perform voltage iteration tests on the failed memory blocks based on the reference operating voltage until all the selected failed memory blocks meet the preset pass conditions, and the test voltage when the preset pass conditions are met is taken as the minimum operating voltage of the static random access memory.

10. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the test method for the minimum operating voltage as described in any one of claims 1 to 8.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the test method for the minimum operating voltage as described in any one of claims 1 to 6.

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