A stability test method and system for a dram grain

Abstract

The application discloses a kind of stability test method and system of DRAM particle, it is related to memory stability test technical field, solve the problem that current memory stability test method is difficult to reflect the influence of different working conditions on DRAM particle stability in actual use process, method is: to vehicle whether abnormal state is judged, and actual time voltage curve is constructed, and whether the power supply abnormal risk of vehicle exists is judged in combination with standard time voltage curve;Memory unit is read and write test, and whether the stability test of memory unit passes is judged based on the result of read and write test;Test group and control group of memory unit are constructed, and aging test is carried out to test group and control group, and then the standard test data of control group in aging test process and the test experimental data of test group are summarized;Whether the stability test of all test group memory unit passes is judged, and the stability test of DRAM particle is realized under different operating conditions in the application.

Description

Technical Field

[0001] This invention belongs to the field of memory stability testing technology, specifically a method and system for testing the stability of DRAM chips. Background Technology

[0002] DRAM chips are dynamic random access memory chips used for temporary data storage. Internally, they consist of a large array of memory cells, storing binary data through capacitors and maintaining the data state through a periodic refresh mechanism. DRAM chips are characterized by high read / write speeds, high integration density, and large capacity. They are commonly used as running memory in electronic devices and are widely applied in computers, smartphones, automotive systems, and industrial control equipment. LPDDR4X chips belong to the low-power branch of DRAM chips and are primarily used in mobile terminals and automotive electronic systems where power consumption and operational stability are critical.

[0003] In the existing technology, the existing memory stability testing method is to perform static read and write tests in a fixed environment to verify the function of DRAM chips. It usually only tests the basic read and write capabilities and short-term operating status, which is difficult to reflect the impact of operating conditions such as instantaneous power supply fluctuations, dynamic read and write switching and different operating temperature environments on the stability of DRAM chips during actual use. Therefore, this invention proposes a method and system for testing the stability of DRAM chips. Summary of the Invention

[0004] In view of the shortcomings of the existing technology, the purpose of this invention is to provide a method and system for testing the stability of DRAM chips.

[0005] The technical problem to be solved by this invention is: How to conduct stability tests on DRAM chips under different operating conditions.

[0006] To achieve the above objectives, the present invention adopts the following technical solution: A stability testing method for DRAM chips, the method comprising: Step S1: Determine whether the vehicle is in an abnormal state based on the static working voltage and real-time voltage value of the low-voltage power supply bus. Then, construct the actual time voltage curve by collecting the detection voltage value of the corresponding memory unit of the vehicle in the startup time interval, and combine it with the standard time voltage curve to determine whether there is a risk of power supply abnormality in the vehicle. Step S2: Perform read and write tests on the memory cells using random verification data, and determine whether the stability test of the memory cells passes based on the results of the read and write tests; Step S3: Construct test groups and control groups for memory units based on the operating temperature range, and conduct aging tests on the test groups and control groups. Then, summarize the standard test data of the control group and the test experimental data of the test group during the aging test. Step S4: Determine whether the memory cell stability test of all test groups passes based on standard test data and test experimental data.

[0007] Further, step S1 includes the following sub-steps: Step S11: Obtain the vehicle's operating status; When the vehicle is in the off-state, the real-time voltage value of the low-voltage power supply bus in the vehicle's on-board electrical equipment is collected, and the process proceeds to step S12. When the vehicle is in the started state, change the vehicle's running state to the stopped state, then collect the real-time voltage value of the low-voltage power supply bus in the vehicle's on-board electrical equipment, and proceed to step S12. Step S12: Obtain the static operating voltage of the low-voltage power supply bus in the vehicle's on-board electrical equipment, and compare the real-time voltage value with the static operating voltage. When the real-time voltage values ​​at all time points are less than or equal to the static operating voltage, proceed to step S13; If the real-time voltage value at any time point is greater than the static operating voltage, the vehicle is determined to be in an abnormal state and no further testing will be conducted. Step S13: Extend the preset test duration backward from the current time node to obtain the termination time node, change the vehicle's running status at the current time node to the started state, and obtain the real-time voltage values ​​of all time nodes within the preset test duration. Step S14: Construct the start-up time interval from the vehicle's non-started state to its started state; Step S15: Obtain the detection voltage values ​​of the corresponding memory units of the vehicle system of the vehicle-mounted electrical equipment at all time points within the startup time interval.

[0008] Furthermore, step S1 also includes the following sub-steps: Step S16: Using time nodes as the horizontal axis and the detected voltage value as the vertical axis, construct the actual time-voltage curve of the memory unit during the vehicle startup process. Step S17: Obtain the standard time voltage curve during vehicle startup. Subtract the detected voltage values ​​of the two curves at the same time point and take the absolute value to calculate the voltage deviation value of the two curves at the same time point. Step S18: Count the total number of time nodes where the voltage deviation value is greater than or equal to the preset deviation value, and divide the total number of time nodes by the number of all time nodes within the startup time interval to calculate the voltage deviation ratio of the memory unit. When the voltage deviation ratio is less than the ratio threshold, it is determined that there is no risk of power supply abnormality in the vehicle, and proceed to step S2; When the voltage deviation ratio is greater than or equal to the ratio threshold, the vehicle is at risk of power supply abnormality and no further testing will be conducted.

[0009] Further, step S14 includes the following sub-steps: Step S1401: Subtract the real-time voltage values ​​of all time points from the static working voltage one by one to calculate the voltage difference at each time point, and take the time point when the voltage difference is first greater than or equal to the first difference threshold as the vehicle start-up time point. Step S1402: The time node when the voltage difference first becomes less than or equal to the second difference threshold is taken as the vehicle start-up completion time node; Step S1403: The time interval formed by the start time node and the start completion time node is taken as the vehicle's start time interval.

[0010] Furthermore, the random verification data consists of random characters generated by a random function.

[0011] Further, step S2 includes the following sub-steps: Step S21: Obtain random verification data, repeatedly write the random verification data to different cache areas of the memory unit, and read the random verification data in the corresponding cache area after each writing is completed. Record the read random verification data as test read data. Step S22: Obtain the first character length of the experimental reading data and the second character length of the random verification data, and compare the first character length and the second character length; If the length of the first character is equal to the length of the second character, proceed to step S26; If the length of the first character is not equal to the length of the second character, the stability test of the corresponding memory unit is deemed to have failed, and the test is stopped. Step S23: Compare the test data bit by bit with the random verification data; If all the characters in the test data are the same as the corresponding characters in the random verification data, proceed to step S3; If any character in the test data read is different from the corresponding character in the random verification data, the stability test of the corresponding memory unit is deemed to have failed, and the test is stopped.

[0012] Further, step S3 includes the following sub-steps: Step S31: Obtain the operating temperature range of the memory cell, take the midpoint value of the operating temperature range as the standard temperature of the memory cell, and take the memory cell and the corresponding standard temperature as the control group of the aging test. Step S32: Divide the working temperature range into a fixed number of temperature sub-ranges, and take the midpoint value of each temperature sub-range as the test temperature, and count the number of temperature sub-ranges. Step S33: Set a corresponding number of test groups according to the number of temperature sub-intervals. Each test group uses the test temperature of the corresponding temperature sub-interval as the test temperature of the memory unit. All test groups are used together as the test group for aging test, and the test groups are numbered in order of increasing test temperature.

[0013] Furthermore, step S3 includes the following sub-steps: Step S34: Perform aging tests on memory cells in the test group and control group for the same duration, while maintaining the same frequency of data read and write operations on all memory cells in the test group and control group. Step S35: Obtain the standard voltage drop recovery time and standard minimum voltage value corresponding to the memory cell of the control group, and at the same time obtain the test voltage drop recovery time and test minimum voltage value corresponding to the memory cell of all test groups in the test group; Step S36: Record the standard voltage drop recovery time and standard minimum voltage value corresponding to the memory cell as the standard test data of the control group, and at the same time, record the test voltage drop recovery time and test minimum voltage value corresponding to the memory cell of all test groups in the test group as the test experimental data of the test group.

[0014] Further, step S4 includes the following sub-steps: Step S41: Subtract the standard voltage drop recovery time from the experimental voltage drop recovery time for each memory cell in the test group, and calculate the voltage drop recovery time difference between the memory cells in all test groups and the memory cells in the control group. Step S42: Subtract the standard minimum voltage value from the minimum voltage value corresponding to the memory cell of each test group, and calculate the minimum voltage difference between the memory cells of each test group and the memory cells of the control group. If the difference in voltage drop recovery time corresponding to the memory cells of all test groups is less than or equal to zero, and the minimum voltage difference is less than or equal to zero, then proceed to step S43. If the difference in voltage drop recovery time of memory cells in any test group is greater than zero, or the difference in minimum voltage is greater than zero, then the memory cell stability test of the corresponding test group is deemed unqualified. Step S43: After the aging test is completed, restore all memory cells in the test group to the standard temperature, and repeat steps S21 to S23 to perform read and write tests on the memory cells of all test groups. If the read / write test of any memory cell in any test group fails, the memory cell stability test of the corresponding test group is deemed to have failed. When all memory cells in the test group pass the read / write test, proceed to step S44. Step S44: Increase the test temperature of the memory cells in all test groups by a fixed temperature, and set the test temperature of the last test group to the test temperature of the first test group before the temperature adjustment. Step S45: Repeat steps S33 to S43 to perform aging tests and read / write tests on all memory cells in the test group and the memory cells in the control group. When all test groups pass the aging test and read / write test, repeat step S44 until all test group numbers are the same as before the initial adjustment, then stop the test and determine that all memory cells have passed the stability test. If any test group fails either the aging test or the read / write test, the memory cell stability test of the corresponding test group is deemed to have failed.

[0015] The present invention also provides a stability testing system for DRAM chips, including a data acquisition module, a database module, a status determination module, a read / write test module, an aging test module, and a test determination module; The database module is used to store the static operating voltage of the low-voltage power supply bus and send it to the status determination module. It is also used to store the running cache data and send it to the read and write test module. The data acquisition module is used to acquire the real-time voltage value of the low-voltage power supply bus in the vehicle, as well as the detection voltage value of the corresponding memory unit of the vehicle system in the vehicle electrical equipment, and send it to the status determination module. The status determination module is used to determine the current operating status of the vehicle based on the real-time voltage value and the static operating voltage, and then to determine whether there is a risk of power supply abnormality in the vehicle based on the detected voltage value. When there is no risk of power supply abnormality, a test pass signal is generated and sent to the read and write test module. The read / write test module is used to determine whether the read / write test of the memory unit is qualified based on the running cache data. When the read / write test is unqualified, the result of the stability test is directly output. When the read / write test is qualified, the read / write test qualified signal is sent to the aging test module. The aging test module is used to divide the test group and the control group according to the operating temperature range, and to complete the aging test of the memory chip at different temperatures. At the same time, it sends the standard voltage drop recovery time and standard minimum voltage value of the memory cell of the control group, as well as the test voltage drop recovery time and test minimum voltage value of the memory cell of all test groups in the test group, to the test judgment module. The test judgment module is used to determine whether the aging test of the memory cells in the test group is qualified based on the standard voltage drop recovery time, the standard minimum voltage value, the test voltage drop recovery time, and the test minimum voltage value. At the same time, after the aging test is completed, read and write tests are carried out again on all memory cells in the test group. The results of the two tests are combined to finally determine whether the stability test of the corresponding memory cells is qualified.

[0016] Compared with the prior art, the beneficial effects of the present invention are: 1. This invention first determines whether a vehicle is in an abnormal state based on the static working voltage and real-time voltage value of the low-voltage power supply bus. Then, it constructs an actual time voltage curve by collecting the detection voltage value of the corresponding memory unit of the vehicle during the startup time interval, and combines it with the standard time voltage curve to determine whether there is a risk of power supply abnormality in the vehicle. This is beneficial for identifying vehicle operation faults caused by substandard power supply stability of DRAM chips in advance, and improving the accuracy of DRAM chip stability screening.

[0017] 2. This invention performs read and write tests on memory cells using random verification data. Based on the results of the read and write tests, it determines whether the stability test of the memory cell has passed. Then, it constructs test groups and control groups of memory cells according to the operating temperature range, and conducts aging tests on the test groups and control groups. It summarizes the standard test data of the control group and the test experimental data of the test group during the aging test. Finally, it determines whether the stability test of the memory cells in all test groups has passed based on the standard test data and the test experimental data. By testing DRAM chips under dynamic operating conditions in actual use, it achieves stability screening of DRAM chips under dynamic operating conditions, effectively reducing the probability of DRAM chip failure. Attached Figure Description

[0018] To facilitate understanding by those skilled in the art, the present invention will be further described below with reference to the accompanying drawings.

[0019] Figure 1 This is a flowchart of the method of the present invention; Figure 2 This is an example diagram of the back side of a single DRAM chip in this invention; Figure 3 This is a flowchart of the method for conducting aging tests on memory cells in this invention; Figure 4This is an overall system block diagram of the present invention. Detailed Implementation

[0020] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] Example 1: Please refer to Figures 1-3 As shown, the technical solution provided by this invention is as follows: a stability testing method for DRAM chips, including DDR SDRAM, LPDDR SDRAM, GDDR SDRAM, and HBM dynamic random access memory types; the method first adjusts the vehicle's operating state to an unstarted state, and then determines whether the vehicle is in an abnormal state by using the static operating voltage and real-time voltage value of the low-voltage power supply bus. When the vehicle is in an abnormal state, no further operations are performed; when the vehicle is not in an abnormal state, the vehicle's operating state is changed to a start-up state, and a start-up time interval is constructed. Then, the detection voltage values ​​of the memory cells at all time points within the start-up time interval are obtained, and an actual time-voltage curve is constructed based on the detection voltage values. Combined with the standard time-voltage curve, it is determined whether there is a power supply risk to the vehicle; read and write tests are performed on the memory cells according to the determination results; when the read and write tests of the memory cells pass, test groups and control groups of the memory cells are constructed according to the operating temperature range, and aging tests are performed on the test groups and control groups. Then, the standard test data of the control group and the test experimental data of the test group are summarized during the aging test; finally, based on the standard test data and the test experimental data, it is determined whether the stability test of the memory cells in all test groups in the test group passes. In this embodiment, the method includes the following steps: Step S1: Determine whether the vehicle is in an abnormal state based on the static working voltage and real-time voltage value of the low-voltage power supply bus. Then, construct the actual time voltage curve by collecting the detection voltage value of the corresponding memory unit of the vehicle in the startup time interval, and combine it with the standard time voltage curve to determine whether there is a risk of power supply abnormality in the vehicle. It should be noted that when the vehicle is not started, the vehicle's battery supplies power to the vehicle's on-board electrical equipment through the low-voltage power supply bus. The static operating voltage is the DC voltage output by the battery to the on-board electrical equipment through the low-voltage power supply bus when the vehicle is not started; in practice, the static operating voltage can be 12.5 volts. When the vehicle is not started and the battery supplies power to the on-board electrical equipment, the voltage value in the low-voltage power supply bus fluctuates, and the static operating voltage is the maximum value of the voltage in the low-voltage power supply bus within a fixed recording period. In this embodiment, step S1 includes the following sub-steps: Step S11: Obtain the vehicle's operating status; When the vehicle is in the off-state, the real-time voltage value of the low-voltage power supply bus in the vehicle's on-board electrical equipment is collected, and the process proceeds to step S12. When the vehicle is in the started state, change the vehicle's running state to the stopped state, then collect the real-time voltage value of the low-voltage power supply bus in the vehicle's on-board electrical equipment, and proceed to step S12. The vehicle's operating status can be determined by reading the vehicle's status information through the vehicle's OBD interface; the vehicle's operating status includes the non-started state and the started state; real-time voltage values ​​can be collected through voltage sensors; the low-voltage power supply bus is specifically used to transmit the electrical energy generated by the battery or generator to the vehicle's on-board electrical equipment. Step S12: Obtain the static operating voltage of the low-voltage power supply bus in the vehicle's on-board electrical equipment, and compare the real-time voltage value with the static operating voltage. When the real-time voltage values ​​at all time points are less than or equal to the static operating voltage, proceed to step S13; If the real-time voltage value at any time point is greater than the static operating voltage, the vehicle is determined to be in an abnormal state and no further testing will be conducted. Step S13: Extend the preset test duration backward from the current time node to obtain the termination time node, change the vehicle's running status at the current time node to the started state, and obtain the real-time voltage values ​​of all time nodes within the preset test duration. Step S14: Construct the start-up time interval from the vehicle's non-started state to its started state. The specific construction process is as follows: Step S1401: Subtract the real-time voltage values ​​of all time points from the static working voltage one by one to calculate the voltage difference at each time point, and take the time point when the voltage difference is first greater than or equal to the first difference threshold as the vehicle start-up time point. In practice, the first difference threshold can be set by those skilled in the art according to actual testing needs; it should be specifically noted that during the vehicle startup process, the real-time voltage value of the low-voltage power supply bus first decreases and then increases. Therefore, when the real-time voltage value decreases and the decrease is greater than the first difference threshold, it can be determined that the vehicle is starting. Step S1402: The time node when the voltage difference first becomes less than or equal to the second difference threshold is taken as the vehicle start-up completion time node; Among them, the first difference threshold is greater than zero, and the second difference threshold is less than zero; Step S1403: The time interval formed by the start time node and the start completion time node is taken as the vehicle's start time interval; Step S15: Obtain the detection voltage values ​​of the corresponding memory units of the vehicle system of the vehicle-mounted electrical equipment at all time points within the startup time interval; In practice, a memory cell consists of at least one DRAM chip, and each DRAM chip is equipped with at least one voltage detection terminal. The detection voltage value of each DRAM chip is obtained through the voltage detection terminal, and the detection voltage values ​​of all DRAM chips at the same time point are used as the detection voltage value of the corresponding time point; the detection voltage value is less than the real-time voltage value. Step S16: Using time nodes as the horizontal axis and the detected voltage value as the vertical axis, construct the actual time-voltage curve of the memory unit during the vehicle startup process. Step S17: Obtain the standard time voltage curve during vehicle startup. Subtract the detected voltage values ​​of the two curves at the same time point and take the absolute value to calculate the voltage deviation value of the two curves at the same time point. Step S18: Count the total number of time nodes where the voltage deviation value is greater than or equal to the preset deviation value, and divide the total number of time nodes by the number of all time nodes within the startup time interval to calculate the voltage deviation ratio of the memory unit. When the voltage deviation ratio is less than the ratio threshold, it is determined that there is no risk of power supply abnormality in the vehicle, and proceed to step S2; When the voltage deviation ratio is greater than or equal to the ratio threshold, the vehicle is at risk of power supply abnormality and no further testing will be conducted. It should be noted that if the voltage received by the memory cell is abnormal during vehicle startup, it may cause the stored data inside the memory cell to jump, which may lead to abnormalities when the DRAM chip is tested for stability.

[0022] Step S2: Perform read and write tests on the memory cells using random verification data, and determine whether the stability test of the memory cells passes based on the results of the read and write tests; Specifically, the random check data consists of random characters generated by a random function. The random characters can be one or more random combinations of uppercase English letters, lowercase English letters, Arabic numerals, and special symbols. The length of the random check data matches the storage capacity of the corresponding cache area. In this embodiment, step S2 includes the following sub-steps: Step S21: Obtain random verification data, repeatedly write the random verification data to different cache areas of the memory unit, and read the random verification data in the corresponding cache area after each writing is completed. Record the read random verification data as test read data. The memory unit includes multiple cache areas, and each cache area stores a type of cache field. Step S22: Obtain the first character length of the experimental reading data and the second character length of the random verification data, and compare the first character length and the second character length; If the length of the first character is equal to the length of the second character, proceed to step S26; If the length of the first character is not equal to the length of the second character, the stability test of the corresponding memory unit is deemed to have failed, and the test is stopped. Step S23: Compare the experimental data bit by bit with the random verification data; If all the characters in the test data are the same as the corresponding characters in the random verification data, proceed to step S3; If any character in the test data read is different from the corresponding character in the random verification data, the stability test of the corresponding memory unit is deemed to have failed, and the test is stopped.

[0023] Step S3: Construct test groups and control groups for memory units based on the operating temperature range, and conduct aging tests on the test groups and control groups. Then, summarize the standard test data of the control group and the test experimental data of the test group during the aging test. In practice, the operating temperature range is the safe temperature range for memory cells during normal operation. The operating temperature range of memory cells can be [-25℃, 85℃]. In this embodiment, step S3 includes the following sub-steps: Step S31: Obtain the operating temperature range of the memory cell, take the midpoint value of the operating temperature range as the standard temperature of the memory cell, and take the memory cell and the corresponding standard temperature as the control group of the aging test. Step S32: Divide the working temperature range into a fixed number of temperature sub-ranges, and take the midpoint value of each temperature sub-range as the test temperature, and count the number of temperature sub-ranges. Step S33: Set a corresponding number of test groups according to the number of temperature sub-intervals. Each test group uses the test temperature of the corresponding temperature sub-interval as the test temperature of the memory unit. All test groups are used together as the test group for aging test. The test groups are numbered according to the order of test temperature from small to large. For example, the operating temperature range is divided into [-25℃, -15℃), [-25℃, -15℃), [-25℃, -15℃), ..., [75℃, 85℃], and then the midpoint value of the temperature in each temperature sub-range is taken as the test temperature of the memory unit. The test temperatures are -20℃, -10℃, 0℃, ..., 80℃, respectively. The test temperature can be adjusted by a temperature regulator installed in the vehicle. In reality, the memory cells used in the test group and the control group were of the same specifications; the memory cells in both the test group and the control group were located in vehicles. Step S34: Perform aging tests on memory cells in the test group and control group for the same duration, while maintaining the same frequency of data read and write operations on all memory cells in the test group and control group. Step S35: Obtain the standard voltage drop recovery time and standard minimum voltage value corresponding to the memory cell of the control group, and at the same time obtain the test voltage drop recovery time and test minimum voltage value corresponding to the memory cell of all test groups in the test group; In practice, the voltage drop recovery time can be measured using a digital oscilloscope; specifically, the voltage drop recovery time is the length of time it takes for the voltage to drop from the operating voltage corresponding to the test temperature to the stable voltage after the aging test is completed; the minimum voltage value is the minimum value of the memory cell output voltage during the voltage drop recovery process; Step S36: Record the standard voltage drop recovery time and standard minimum voltage value corresponding to the memory cell as the standard test data of the control group, and at the same time, record the test voltage drop recovery time and test minimum voltage value corresponding to the memory cell of all test groups in the test group as the test experimental data of the test group.

[0024] Step S4: Determine whether the memory cell stability test of all test groups passes based on standard test data and test experimental data; In this embodiment, step S4 includes the following sub-steps: Step S41: Subtract the standard voltage drop recovery time from the experimental voltage drop recovery time for each memory cell in the test group, and calculate the voltage drop recovery time difference between the memory cells in all test groups and the memory cells in the control group. Step S42: Subtract the standard minimum voltage value from the minimum voltage value corresponding to the memory cell of each test group, and calculate the minimum voltage difference between the memory cells of each test group and the memory cells of the control group. If the difference in voltage drop recovery time corresponding to the memory cells of all test groups is less than or equal to zero, and the minimum voltage difference is less than or equal to zero, then proceed to step S43. If the difference in voltage drop recovery time of memory cells in any test group is greater than zero, or the difference in minimum voltage is greater than zero, then the memory cell stability test of the corresponding test group is deemed unqualified. Step S43: After the aging test is completed, restore all memory cells in the test group to the standard temperature, and repeat steps S21 to S23 to perform read and write tests on the memory cells of all test groups. If the read / write test of any memory cell in any test group fails, the memory cell stability test of the corresponding test group is deemed to have failed. When all memory cells in the test group pass the read / write test, proceed to step S44. Step S44: Increase the test temperature of the memory cells in all test groups by a fixed temperature, and set the test temperature of the last test group to the test temperature of the first test group before the temperature adjustment. For example, the first test group was numbered 1 before the adjustment, and the test temperature was -20℃. After the test temperature was increased to a fixed temperature of -10℃, the number of the first test group was 2. The last test group was numbered N before the adjustment, and the test temperature was 80℃. After the test temperature was set to the test temperature of the first test group before the temperature adjustment, it was -20℃. The number of the last test group was 1. Step S45: Repeat steps S33 to S43 to perform aging tests and read / write tests on all memory cells in the test group and the memory cells in the control group. When all test groups pass the aging test and read / write test, repeat step S44 until all test group numbers are the same as before the initial adjustment, then stop the test and determine that all memory cells have passed the stability test. If any test group fails either the aging test or the read / write test, the memory cell stability test of the corresponding test group is deemed to have failed.

[0025] Example 2: Please refer to Figure 4 As shown, based on another concept of the same invention, a stability testing system for DRAM chips is proposed, including a data acquisition module, a database module, a status determination module, a read / write test module, an aging test module, and a test determination module. The database module is used to store the static operating voltage of the low-voltage power supply bus and send it to the status determination module. It is also used to store the running cache data and send it to the read and write test module. The data acquisition module is used to acquire the real-time voltage value of the low-voltage power supply bus in the vehicle, as well as the detection voltage value of the corresponding memory unit of the vehicle system in the vehicle electrical equipment, and send it to the status determination module. The status determination module is used to determine the current operating status of the vehicle based on the real-time voltage value and the static operating voltage, and then to determine whether there is a risk of power supply abnormality in the vehicle based on the detected voltage value. When there is no risk of power supply abnormality, a test pass signal is generated and sent to the read and write test module. The read / write test module is used to determine whether the read / write test of the memory unit is qualified based on the running cache data. When the read / write test is unqualified, the result of the stability test is directly output. When the read / write test is qualified, the read / write test qualified signal is sent to the aging test module. The aging test module is used to divide the test group and the control group according to the operating temperature range, and to complete the aging test of the memory chip at different temperatures. At the same time, it sends the standard voltage drop recovery time and standard minimum voltage value of the memory cell of the control group, as well as the test voltage drop recovery time and test minimum voltage value of the memory cell of all test groups in the test group, to the test judgment module. The test judgment module is used to determine whether the aging test of the memory cells in the test group is qualified based on the standard voltage drop recovery time, the standard minimum voltage value, the test voltage drop recovery time, and the test minimum voltage value. At the same time, after the aging test is completed, read and write tests are carried out again on all memory cells in the test group. The results of the two tests are combined to finally determine whether the stability test of the corresponding memory cells is qualified.

[0026] The preferred embodiments of the present invention disclosed above are merely illustrative of the invention. These preferred embodiments do not exhaustively describe all details, nor do they limit the invention to any specific implementation. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for testing the stability of DRAM chips, characterized in that, The methods include: Step S1: Determine whether the vehicle is in an abnormal state based on the static working voltage and real-time voltage value of the low-voltage power supply bus. Then, construct the actual time voltage curve by collecting the detection voltage value of the corresponding memory unit of the vehicle in the startup time interval, and combine it with the standard time voltage curve to determine whether there is a risk of power supply abnormality in the vehicle. Step S2: Perform read and write tests on the memory cells using random verification data, and determine whether the stability test of the memory cells passes based on the results of the read and write tests; Step S3: Construct test groups and control groups for memory units based on the operating temperature range, and conduct aging tests on the test groups and control groups. Then, summarize the standard test data of the control group and the test experimental data of the test group during the aging test. Step S4: Determine whether the memory cell stability test of all test groups passes based on standard test data and test experimental data.

2. The stability testing method for DRAM chips according to claim 1, characterized in that, Step S1 includes the following sub-steps: Step S11: Obtain the vehicle's operating status; When the vehicle is in the off-state, the real-time voltage value of the low-voltage power supply bus in the vehicle's on-board electrical equipment is collected, and the process proceeds to step S12. When the vehicle is in the started state, change the vehicle's running state to the stopped state, then collect the real-time voltage value of the low-voltage power supply bus in the vehicle's on-board electrical equipment, and proceed to step S12. Step S12: Obtain the static operating voltage of the low-voltage power supply bus in the vehicle's on-board electrical equipment, and compare the real-time voltage value with the static operating voltage. When the real-time voltage values ​​at all time points are less than or equal to the static operating voltage, proceed to step S13; If the real-time voltage value at any time point is greater than the static operating voltage, the vehicle is determined to be in an abnormal state and no further testing will be conducted. Step S13: Extend the preset test duration backward from the current time node to obtain the termination time node, change the vehicle's running status at the current time node to the started state, and obtain the real-time voltage values ​​of all time nodes within the preset test duration. Step S14: Construct the start-up time interval from the vehicle's non-started state to its started state; Step S15: Obtain the detection voltage values ​​of the corresponding memory units of the vehicle system of the vehicle-mounted electrical equipment at all time points within the startup time interval.

3. The stability testing method for DRAM chips according to claim 2, characterized in that, Step S1 further includes the following sub-steps: Step S16: Using time nodes as the horizontal axis and the detected voltage value as the vertical axis, construct the actual time-voltage curve of the memory unit during the vehicle startup process. Step S17: Obtain the standard time voltage curve during vehicle startup. Subtract the detected voltage values ​​of the two curves at the same time point and take the absolute value to calculate the voltage deviation value of the two curves at the same time point. Step S18: Count the total number of time nodes where the voltage deviation value is greater than or equal to the preset deviation value, and divide the total number of time nodes by the number of all time nodes within the startup time interval to calculate the voltage deviation ratio of the memory unit. When the voltage deviation ratio is less than the ratio threshold, it is determined that there is no risk of power supply abnormality in the vehicle, and proceed to step S2; When the voltage deviation ratio is greater than or equal to the ratio threshold, the vehicle is at risk of power supply abnormality and no further testing will be conducted.

4. The stability testing method for DRAM chips according to claim 2, characterized in that, Step S14 includes the following sub-steps: Step S1401: Subtract the real-time voltage values ​​of all time points from the static working voltage one by one to calculate the voltage difference at each time point, and take the time point when the voltage difference is first greater than or equal to the first difference threshold as the vehicle start-up time point. Step S1402: The time node when the voltage difference first becomes less than or equal to the second difference threshold is taken as the vehicle start-up completion time node; Step S1403: The time interval formed by the start time node and the start completion time node is taken as the vehicle's start time interval.

5. The stability testing method for DRAM chips according to claim 1, characterized in that, The random verification data consists of random characters generated by a random function.

6. The stability testing method for DRAM chips according to claim 5, characterized in that, Step S2 includes the following sub-steps: Step S21: Obtain random verification data, repeatedly write the random verification data to different cache areas of the memory unit, and read the random verification data in the corresponding cache area after each writing is completed. Record the read random verification data as test read data. Step S22: Obtain the first character length of the experimental reading data and the second character length of the random verification data, and compare the first character length and the second character length; If the length of the first character is equal to the length of the second character, proceed to step S26; If the length of the first character is not equal to the length of the second character, the stability test of the corresponding memory unit is deemed to have failed, and the test is stopped. Step S23: Compare the test data bit by bit with the random verification data; If all the characters in the test data are the same as the corresponding characters in the random verification data, proceed to step S3; If any character in the test data read is different from the corresponding character in the random verification data, the stability test of the corresponding memory unit is deemed to have failed, and the test is stopped.

7. The stability testing method for DRAM chips according to claim 1, characterized in that, Step S3 includes the following sub-steps: Step S31: Obtain the operating temperature range of the memory cell, take the midpoint value of the operating temperature range as the standard temperature of the memory cell, and take the memory cell and the corresponding standard temperature as the control group of the aging test. Step S32: Divide the working temperature range into a fixed number of temperature sub-ranges, and take the midpoint value of each temperature sub-range as the test temperature, and count the number of temperature sub-ranges. Step S33: Set a corresponding number of test groups according to the number of temperature sub-intervals. Each test group uses the test temperature of the corresponding temperature sub-interval as the test temperature of the memory unit. All test groups are used together as the test group for aging test, and the test groups are numbered in order of increasing test temperature.

8. The stability testing method for DRAM chips according to claim 7, characterized in that, Step S3 includes the following sub-steps: Step S34: Perform aging tests on memory cells in the test group and control group for the same duration, while maintaining the same frequency of data read and write operations on all memory cells in the test group and control group. Step S35: Obtain the standard voltage drop recovery time and standard minimum voltage value corresponding to the memory cell of the control group, and at the same time obtain the test voltage drop recovery time and test minimum voltage value corresponding to the memory cell of all test groups in the test group; Step S36: Record the standard voltage drop recovery time and standard minimum voltage value corresponding to the memory cell as the standard test data of the control group, and at the same time record the test voltage drop recovery time and test minimum voltage value corresponding to the memory cell of all test groups in the test group as the test experimental data of the test group.

9. The stability testing method for DRAM chips according to claim 1, characterized in that, Step S4 includes the following sub-steps: Step S41: Subtract the standard voltage drop recovery time from the experimental voltage drop recovery time for each memory cell in the test group, and calculate the voltage drop recovery time difference between the memory cells in all test groups and the memory cells in the control group. Step S42: Subtract the standard minimum voltage value from the minimum voltage value corresponding to the memory cell of each test group, and calculate the minimum voltage difference between the memory cells of each test group and the memory cells of the control group. If the difference in voltage drop recovery time corresponding to the memory cells of all test groups is less than or equal to zero, and the minimum voltage difference is less than or equal to zero, then proceed to step S43. If the difference in voltage drop recovery time of any memory cell in the test group is greater than zero, or the difference in minimum voltage is greater than zero, then the memory cell stability test of the corresponding test group is deemed unqualified. Step S43: After the aging test is completed, restore all memory cells in the test group to the standard temperature, and repeat steps S21 to S23 to perform read and write tests on the memory cells of all test groups. If the read / write test of any memory cell in any test group fails, the memory cell stability test of the corresponding test group is deemed to have failed. When all memory cells in the test group pass the read / write test, proceed to step S44; Step S44: Increase the test temperature of the memory cells in all test groups by a fixed temperature, and set the test temperature of the last test group to the test temperature of the first test group before the temperature adjustment. Step S45: Repeat steps S33 to S43 to perform aging tests and read / write tests on all memory cells in the test group and the memory cells in the control group. When all test groups pass the aging test and read / write test, repeat step S44 until all test group numbers are the same as before the initial adjustment, then stop the test and determine that all memory cells have passed the stability test. If any test group fails either the aging test or the read / write test, the memory cell stability test of the corresponding test group is deemed to have failed.

10. A stability testing system for DRAM chips, characterized in that, A stability testing method for DRAM chips according to any one of claims 1-9 includes a data acquisition module, a database module, a status determination module, a read / write test module, an aging test module, and a test determination module; The database module is used to store the static operating voltage of the low-voltage power supply bus and send it to the status determination module. It is also used to store the running cache data and send it to the read and write test module. The data acquisition module is used to acquire the real-time voltage value of the low-voltage power supply bus in the vehicle, as well as the detection voltage value of the corresponding memory unit of the vehicle system in the vehicle electrical equipment, and send it to the status determination module. The status determination module is used to determine the current operating status of the vehicle based on the real-time voltage value and the static operating voltage, and then to determine whether there is a risk of power supply abnormality in the vehicle based on the detected voltage value. When there is no risk of power supply abnormality, a test pass signal is generated and sent to the read and write test module. The read / write test module is used to determine whether the read / write test of the memory unit is qualified based on the running cache data. When the read / write test is unqualified, the result of the stability test is directly output. When the read / write test is qualified, the read / write test qualified signal is sent to the aging test module. The aging test module is used to divide the test group and the control group according to the operating temperature range, and to complete the aging test of the memory chip at different temperatures. At the same time, it sends the standard voltage drop recovery time and standard minimum voltage value of the memory cell of the control group, as well as the test voltage drop recovery time and test minimum voltage value of the memory cell of all test groups in the test group, to the test judgment module. The test judgment module is used to determine whether the aging test of the memory cells in the test group is qualified based on the standard voltage drop recovery time, the standard minimum voltage value, the test voltage drop recovery time, and the test minimum voltage value. At the same time, after the aging test is completed, read and write tests are carried out again on all memory cells in the test group. The results of the two tests are combined to finally determine whether the stability test of the corresponding memory cells is qualified.

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