A method, medium and apparatus for eMMC data retention capability prediction

Abstract

The application discloses a kind of for the prediction method of eMMC data retention capability, medium and equipment, it is related to storage device test technical field, the method includes: the preset data mode is written into eMMC test block, then its initial bit error rate is checked;eMMC test block is placed in the environment of preset temperature, and it is baked by thermostat;Every other preset fixed time, eMMC test block is taken out, and cooled to room temperature, the data of eMMC test block is read, compared with preset data mode, second bit error rate is calculated and recorded;Repeat step until second bit error rate reaches preset bit error rate threshold, or complete measurement at multiple time points;Second bit error rate of different preset temperature and different preset fixed time is collected, and prediction model is established, and the data retention life of eMMC test block is predicted.The present application provides accurate life prediction.

Description

Technical Field

[0001] This invention relates to the field of storage device testing technology, and more specifically to a method, medium, and device for predicting the data retention capability of eMMC. Background Technology

[0002] In the development of storage devices (such as eMMC), data retention period is one of the core performance indicators for measuring product reliability. Current technologies typically use simulated charge decay processes under real-world usage conditions for data retention period testing. However, this method has significant drawbacks: because the charge decay process of storage devices in real-world environments is extremely slow, the data retention period often lasts for several years, requiring a corresponding testing cycle to extend for several years as well. With the rapid development of the electronics and information industry, the pace of storage device updates and iterations is accelerating, and product development cycles are being significantly compressed. The aforementioned long data retention period testing is no longer sufficient to meet current product development needs. Excessively long testing cycles not only extend product development cycles and delay market launches, leading to missed market opportunities, but also significantly increase testing, warehousing, and management costs during the R&D process, hindering the efficient development of the storage device industry. Therefore, there is an urgent need for an accelerated aging testing method that simulates long-term data retention through high-temperature stress and combines it with electrical performance testing to rapidly predict data retention life. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method, medium and device for predicting the data retention capability of eMMC.

[0004] The objective of this invention is achieved through the following technical solution:

[0005] In a first aspect, this application discloses a method for predicting eMMC data retention capability, comprising:

[0006] Write the preset data pattern into the eMMC test block, and then verify its initial bit error rate;

[0007] The eMMC test block with the preset data pattern is placed in an environment with a preset temperature and baked in a constant temperature oven, wherein the preset temperature and the oven baking temperature are both higher than room temperature.

[0008] Every preset fixed time interval, the eMMC test block is removed from the preset temperature environment and cooled to room temperature. The data of the eMMC test block is read and compared with the preset data pattern. The second bit error rate is calculated and recorded. This step is repeated until the second bit error rate reaches the preset bit error rate threshold, or the measurement at multiple time points is completed.

[0009] The second bit error rate at different preset temperatures and different preset fixed times is collected, and a prediction model is established to predict the data retention lifetime of the eMMC test block.

[0010] Based on the first aspect, the preset data pattern includes a predefined and stored deterministic sequence.

[0011] Based on the first aspect, the preset data pattern also includes a data pattern for identifying bit errors through logical comparison, wherein the logical comparison includes bitwise XOR operation.

[0012] Based on the first aspect, the difference between the initial bit error rate and zero is within a preset range, which is used to determine that the preset data mode has been correctly written.

[0013] Based on the first aspect, the prediction model is ,in This represents the second bit error rate at a preset temperature of T and a preset fixed time of t, where A represents the proportionality constant and p represents the time power-law factor. This represents the activation energy, and k represents the Boltzmann constant. This represents the initial bit error rate.

[0014] Based on the first aspect, the prediction of the data retention lifetime of the eMMC test block includes: ,in Indicates data retention capability, This indicates the preset bit error rate threshold. Indicates the operating temperature.

[0015] Secondly, this application discloses a computer storage medium storing a computer program, which is executed by a processor to implement the method described above.

[0016] Thirdly, this application discloses an electronic device, the electronic device comprising:

[0017] Memory, which stores executable instructions;

[0018] A processor that executes the executable instructions in the memory to implement the method described above.

[0019] The beneficial effects of this invention are:

[0020] 1) This application combines high-temperature baking with periodic interruption electrical performance testing to form a standardized process, which avoids equipment damage caused by continuous testing and improves testing efficiency.

[0021] 2) The bit error rate prediction formula proposed in this application introduces a time power law factor, which overcomes the limitation of the standard Arrhenius model's assumption of linear time dependence, and more accurately describes the nonlinear behavior of charge decay. At the same time, through multi-temperature point testing and nonlinear regression, the model parameters can be accurately fitted, thereby improving the reliability of prediction.

[0022] 3) This application is applicable to various storage devices (such as NAND Flash, eMMC, UFS, etc.) and can be integrated into the product development cycle to quickly evaluate data retention capabilities. Attached Figure Description

[0023] Figure 1 This is a flowchart illustrating a method for predicting eMMC data retention capability according to an embodiment of the present invention. Detailed Implementation

[0024] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] This application discloses a method for predicting the data retention capability of eMMC. Through steps such as writing a known data pattern, applying high-temperature stress, periodic interruption and verification, and establishing a prediction model, it achieves accelerated aging testing and lifetime prediction of data retention capability. It combines high-temperature baking with electrical performance testing and introduces a constructed bit error rate prediction model to form a standardized accelerated lifetime testing process. A flowchart of the method is shown below. Figure 1 As shown, the method specifically includes:

[0026] Write a preset data pattern (e.g., alternating "0" and "1" patterns, or pseudo-random sequences) into an eMMC test block (e.g., multiple storage blocks), and then verify its initial bit error rate.

[0027] The eMMC test block with the preset data pattern is placed in an environment with a preset temperature and baked in a constant temperature oven. The preset temperature is higher than room temperature, for example, the preset temperature is 125°C. The baking temperature of the constant temperature oven is also higher than room temperature but lower than the device damage limit, for example, 150°C. According to the Arrhenius model principle, high temperature will accelerate charge decay, thereby simulating long-term data retention. However, this application does not directly use the standard Arrhenius model, but makes predictions through an original formula.

[0028] Every preset fixed time interval (e.g., 24 hours, 48 ​​hours, etc.), the eMMC test block is removed from the preset temperature environment and cooled to room temperature. The data of the eMMC test block is read and compared with the preset data pattern. The second bit error rate is calculated and recorded. This step is repeated until the second bit error rate reaches the preset bit error rate threshold, or the measurement at multiple time points is completed.

[0029] Collect the second bit error rate at different preset temperatures (e.g., 105°C, 125°C, etc.) and different preset fixed times, establish a prediction model, and predict the data retention lifetime of the eMMC test block.

[0030] The following annotations are provided for the proper nouns used in this application:

[0031] eMMC (embedded MultiMediaCard): An embedded storage device widely used in mobile devices.

[0032] Data retention period: The length of time that data can be correctly retained in a storage device.

[0033] Bit Error Rate (BER): The proportion of erroneous bits to the total number of bits, used to quantify the degree of data error.

[0034] Arrhenius model: A model that describes the relationship between chemical reaction rate and temperature, often used for accelerated aging tests.

[0035] High Temperature Stress: Test conditions that accelerate device aging through high-temperature environments.

[0036] Activation energy (Ea): In the Arrhenius model, this is a parameter representing the energy required for a reaction, reflecting the material's sensitivity to temperature.

[0037] Boltzmann constant (k): a physical constant, approximately equal to eV / K is used for temperature-related calculations.

[0038] Specifically, the preset data pattern should cover all possible states to simulate actual data.

[0039] For example, this includes a predefined and stored deterministic sequence, specifically: a data sequence that is specifically designed (predefined) for the testing system, is regular or predictable, and can effectively expose charge leakage or state flipping in storage cells; its purpose is to quickly and accurately identify which bits have errors during read verification, thereby calculating the bit error rate.

[0040] The content of the pattern is completely determined before testing. For example, it might be "all zeros," "alternating between 0x55 and 0xAA," or a pseudo-random sequence generated from a fixed seed. The test system holds a complete copy of the pattern or can regenerate it in real time. Although a "pseudo-random" sequence may be used to simulate randomness, its generation algorithm and initial conditions are fixed, so the exact same pattern can be written in any test using the same parameters. This ensures the comparability of results between different test batches and different devices.

[0041] This sequence is not user-generated application data, but rather a "test vector" designed for testing purposes as a benchmark reference. The tester knows and records in advance the "expected correct value" written to each memory cell. This is the absolute benchmark for subsequent error detection and bit error rate calculation. If unknown, arbitrary data is written, it is impossible to determine its correctness upon reading.

[0042] Specifically, the preset data patterns also include data patterns that identify bit errors through logical comparison, whereby the logical comparison includes a bitwise XOR operation. Specifically, when a bit error occurs (such as a 0 flipping to 1, or a 1 flipping to 0), it can be efficiently and unambiguously detected through a simple logical comparison or verification algorithm. This is achieved by performing a bitwise XOR operation between the read data and the original expected pattern; the number of bits with '1' in the XOR result is the number of erroneous bits. To achieve this efficient comparison, the data patterns include, but are not limited to: all-0 / all-1 patterns, alternating patterns with a fixed period, and pseudo-random sequences generated based on deterministic algorithms. These patterns achieve high error detection efficiency while effectively simulating the impact of actual data load on different charge states of storage cells. Commonly used patterns and their easily detectable mechanisms are shown in the table.

[0043] Table 1: Common Patterns and Their Easily Detectable Mechanisms

[0044]

[0045] Specifically, the difference between the initial bit error rate and zero is within a preset range (close to zero), which is used to determine that the preset data pattern has been correctly written.

[0046] Specifically, an original formula is used to fit the relationship between bit error rate and time and temperature. Based on charge decay theory, a time power-law factor is introduced to improve prediction accuracy; the prediction model considers time nonlinearity effects and temperature dependence, providing... ,in This represents the second bit error rate at a preset temperature of T and a preset fixed time of t. A represents the proportionality constant (related to device characteristics), and p represents the time power-law factor. The activation energy is represented by eV, and k represents the Boltzmann constant. This represents the initial bit error rate. The standard Arrhenius model typically assumes that the bit error rate is linearly related to time (i.e., p=1), but the prediction model constructed in this application captures the nonlinear behavior of charge decay by introducing a time power-law factor, which is more consistent with the actual data retention characteristics.

[0047] Specifically, predicting the data retention lifetime of eMMC test blocks includes: ,in Indicates data retention capability, This indicates the preset bit error rate threshold. Indicates the operating temperature.

[0048] For example, an eMMC device is used as an example for testing, including data collection, parameter fitting, and lifetime prediction to ensure reliability.

[0049] Test settings:

[0050] Component: A certain brand of eMMC 5.1 component, with a capacity of 32GB.

[0051] Test block: Select 100 storage blocks, each 4MB in size, and write a pseudo-random data pattern.

[0052] High-temperature stress points: 105°C and 125°C.

[0053] Measurement time point: The test is interrupted every 24 hours to measure BER, lasting for 120 hours (5 days).

[0054] Data collection:

[0055] At each temperature point, record the change in bit error rate over time. Reference data is shown in Table 2 (actual data should be based on experimental records).

[0056] Table 2: Reference Data

[0057]

[0058] Parameter fitting:

[0059] Fitting using nonlinear regression methods (such as the Levenberg-Marquardt algorithm) The parameters in.

[0060] Assumption =0, fit A, p, from the data ;

[0061] Example of fitting results (based on simulated data):

[0062] A=0.0012, p=1.2, =0.7 eV;

[0063] Goodness-of-fit assessment: Calculate the R² value (e.g., 0.98), which shows that the model fits the data well.

[0064] Life expectancy prediction:

[0065] set up =10 −3 (i.e., 0.001).

[0066] For operating temperature =25°C=298 K, calculate the lifespan: ;

[0067] Calculation steps:

[0068] Calculation of the index:

[0069] exp(0.7 / 0.0257)=exp(27.24)≈6.5×10¹¹; Note: A calculator is required for actual calculation.

[0070] Calculate the value within the parentheses: 0.001 / 0.0012×6.5×10¹¹≈5.42×10¹¹.

[0071] Taking 1 / 1.2 to the power of: (5.42 × 10¹¹)⁰.⁸³³ ≈ 1.2 × 10 9 Hour.

[0072] Converted to years: 1.2 × 10⁹ / 24 × 365 ≈ 137,000 years.

[0073] Note: The above calculations are for illustrative purposes only; actual values ​​need to be adjusted based on the fitting parameters. This result shows the predicted data retention lifetime at 25°C.

[0074] In summary, this solution provides an efficient and accurate method for accelerating and predicting data retention capabilities. Through original formulas and detailed testing procedures, the long-term data retention lifespan of storage devices can be predicted in a short time, meeting product development needs.

[0075] For example, this application also discloses a computer storage medium storing a computer program that is executed by a processor to implement the methods described above.

[0076] For example, this application also discloses an electronic device, the electronic device comprising:

[0077] Memory, which stores executable instructions;

[0078] A processor that executes the executable instructions in the memory to implement the method described above.

[0079] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A method for predicting eMMC data retention capability, characterized in that, include: Write the preset data pattern into the eMMC test block, and then verify its initial bit error rate; The eMMC test block with the preset data pattern is placed in an environment with a preset temperature and baked in a constant temperature oven, wherein the preset temperature and the oven baking temperature are both higher than room temperature. Every preset fixed time interval, the eMMC test block is removed from the preset temperature environment and cooled to room temperature. The data of the eMMC test block is read and compared with the preset data pattern. The second bit error rate is calculated and recorded. This step is repeated until the second bit error rate reaches the preset bit error rate threshold, or the measurement at multiple time points is completed. The second bit error rate at different preset temperatures and different preset fixed times is collected, and a prediction model is established to predict the data retention lifetime of the eMMC test block.

2. The method for predicting eMMC data retention capability according to claim 1, characterized in that: The preset data pattern includes a predefined and stored deterministic sequence.

3. The method for predicting eMMC data retention capability according to claim 1, characterized in that: The preset data pattern also includes a data pattern that identifies bit errors through logical comparison, wherein the logical comparison includes bitwise XOR operation.

4. The method for predicting eMMC data retention capability according to claim 1, characterized in that: The difference between the initial bit error rate and zero is within a preset range, which is used to determine that the preset data pattern has been written correctly.

5. The method for predicting eMMC data retention capability according to claim 1, characterized in that: The prediction model is: ,in This represents the second bit error rate at a preset temperature of T and a preset fixed time of t, where A represents a proportionality constant and p represents the time power-law factor. This represents the activation energy, and k represents the Boltzmann constant. This represents the initial bit error rate.

6. The method for predicting eMMC data retention capability according to claim 5, characterized in that, Predicting the data retention lifetime of eMMC test blocks includes: ,in Indicates data retention capability, This indicates the preset bit error rate threshold. Indicates the operating temperature.

7. A computer storage medium, characterized in that, The medium stores a computer program, which is executed by a processor to implement the method according to any one of claims 1-6.

8. An electronic device, characterized in that, The electronic device includes: Memory, which stores executable instructions; A processor that executes the executable instructions in the memory to implement the method of any one of claims 1-6.

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