An interlayer structure of a laminated chip inductor

Abstract

The application relates to the technical field of laminated chip inductors, and particularly discloses an interlayer structure of a laminated chip inductor, which comprises a plurality of laminated units, the laminated unit comprises an insulating layer, a coil layer and two pads, the insulating layer is provided with two connecting holes, the two pads are located at the head and tail of the coil layer, the two pads and the two connecting holes are in one-to-one correspondence, the width W1 of the pad is less than the width W2 of the coil layer, the inner side boundary of the pad does not exceed the inner side boundary of the coil layer, the connecting hole is in the shape of a strip, the width W1 of the pad, the width W3 of the connecting hole, and W3=W1-2*DeltaP are satisfied, wherein DeltaP is the distance between the outer edge of the connecting hole and the outer edge of the pad in the width direction, and the length L of the connecting hole satisfies W1<=L<=3*W1. The interlayer structure of the laminated chip inductor can improve the effective area of the coil layer under the condition of improving the reliability of the interlayer connection.

Description

Technical Field

[0001] This invention relates to the field of multilayer chip inductor technology, and in particular to an interlayer structure for multilayer chip inductors. Background Technology

[0002] The prior art publication number CN101763934A discloses a non-polar multilayer chip inductor, which is formed by stacking and sintering multiple multilayer units. Each multilayer unit includes an insulating layer and a coil layer. The coils between adjacent layers are electrically connected through the connection holes that penetrate the insulating layer.

[0003] In existing technologies, to improve the reliability of interlayer connections, pads larger than the width of the coil layer are typically placed at both ends of the coil layer. These pads are circular or elliptical in shape on a plane. Their purpose is to ensure that even if a certain positional deviation occurs during processes such as laser drilling, conductive paste printing, lamination alignment, or exposure and development, the connection hole can still fall within the effective area of ​​the pad, thereby ensuring the yield of interlayer conductivity.

[0004] However, with the miniaturization of electronic components, higher demands are being placed on the inductance or impedance of multilayer chip inductors. To fully utilize the limited internal space of the product, the margin between the outer edge of the coil layer and the outer boundary of the insulation layer (i.e., the width of the non-magnetic region) is typically compressed to the limit of current process capabilities. Under this constraint, in order to set up pads larger than the width of the coil layer, these pads cannot be extended outwards but must instead encroach on the effective area towards the inner coil of the coil layer. The effective magnetic flux area enclosed by the inner coil of the coil layer decreases, leading to a series of deteriorations in electrical performance: a decrease in inductance, a reduction in the quality factor, and an increase in DC resistance due to the limited effective cross-section of the conductive path. Summary of the Invention

[0005] The purpose of this invention is to provide an interlayer structure for a multilayer chip inductor that increases the effective area of ​​the coil layer while improving the reliability of interlayer connections.

[0006] To achieve the above objectives, the present invention provides an interlayer structure for a multilayer chip inductor. The multilayer chip inductor includes multiple stacked units, each of which includes an insulating layer, a coil layer, and two pads. The insulating layer has two connection holes. The two pads are located at the beginning and end of the coil layer, and each pad corresponds to one of the two connection holes. The width W1 of the pad is less than or equal to the width W2 of the coil layer, and the inner boundary of the pad does not exceed the inner boundary of the coil layer. The connection hole is elongated. The width W1 of the pad and the width W3 of the connection hole satisfy W3 = W1 - 2 × ΔP, where ΔP is the distance between the outer edge of the connection hole and the outer edge of the pad along the width direction. The length L of the connection hole satisfies W1 ≤ L ≤ 3 × W1.

[0007] In some embodiments, the connecting hole includes a rectangular portion and semicircular portions disposed on both sides of the rectangular portion.

[0008] In some embodiments, the diameter of the semicircular portion is equal to the width of the rectangular portion.

[0009] In some embodiments, the size of the connecting hole satisfies 2×W3≤L≤4×W3.

[0010] In some embodiments, the connection hole is formed by laser cutting or exposure masking.

[0011] In some embodiments, the width W2 of the coil layer ranges from 80 to 120 μm.

[0012] In some embodiments, the distance ΔP between the outer edge of the connecting hole and the outer edge of the pad ranges from 20 to 40 μm.

[0013] In some embodiments, the coil layer and the pads are printed, and the pads extend into the connection hole.

[0014] In some embodiments, the orthographic projection of the connection hole on the insulating layer falls entirely within the orthographic projection range of the pad on the insulating layer.

[0015] In some embodiments, the distance between the outer edge of the connecting hole and the outer edge of the pad along the length direction is ΔP.

[0016] This invention provides an interlayer structure for a multilayer chip inductor, which has the following advantages compared to the prior art: By setting the width W1 of the pad to be less than or equal to the width W2 of the coil layer, and ensuring that the inner boundary of the pad does not exceed the inner boundary of the coil layer, the pad no longer encroaches further into the inner coil space within the limited electrode layer space. This maximizes the effective magnetic flux area enclosed by the inner coil of the coil layer. Compared to existing technologies that use large pads to compensate for process deviations, resulting in a forced reduction in the inner coil area, this invention significantly improves the inductance of multilayer chip inductors, enhances the quality factor, and effectively suppresses the increase in DC resistance.

[0017] By designing the connecting hole as an elongated shape, and determining the width W3 and length L of the connecting hole based on the width W1 of the pad, such that W3 = W1 - 2 × ΔP and W1 ≤ L ≤ 3 × W1, compared to the circular or elliptical connecting holes of the prior art, the elongated connecting hole, under the condition that the width of the pad is limited (cannot be expanded outward), can obtain sufficient conductive area along the length direction while being compressed in the width direction by reasonably extending the length dimension of the hole, thereby ensuring that the reliability of the interlayer electrical connection is not reduced due to the narrowing of the pad. Attached Figure Description

[0018] Figure 1 This is a plan view of the interlayer structure of a multilayer chip inductor provided for some embodiments of the present invention.

[0019] In the diagram: 1. Stacked unit; 11. Insulating layer; 11a. Connecting hole; 12. Coil layer; 13. Solder pad. Detailed Implementation

[0020] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0021] It should be understood that in the description of this application, the terms "upper," "lower," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are used solely for the convenience of describing this application and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. That is, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Furthermore, unless otherwise stated, "a plurality of" means two or more.

[0022] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0023] like Figure 1 As shown, the multilayer chip inductor includes multiple multilayer units 1. Each multilayer unit 1 includes an insulating layer 11, a coil layer 12, and two pads 13. The insulating layer 11 has two connection holes 11a, and the two pads 13 are located at the beginning and end of the coil layer 12, with each pad 13 corresponding to one of the two connection holes 11a. In this way, the coil layers 12 of adjacent multilayer units 1 achieve interlayer electrical conduction through the connection holes 11a and the material of the pads 13 filled therein.

[0024] The width W1 of the pad 13 is less than or equal to the width W2 of the coil layer 12, and the inner boundary of the pad 13 does not exceed the inner boundary of the coil layer 12. Specifically, the pad 13 does not protrude into the inner circle of the coil layer 12 in the width direction. Thus, the pad 13 does not encroach further into the inner circle of the coil layer 12 within the limited space of the stacked unit 1, thereby maximizing the effective magnetic flux area enclosed by the inner circle of the coil layer 12. Compared to the prior art solution of setting a large pad 13 to compensate for process deviations, which forces a reduction in the inner circle area of ​​the coil layer 12, this embodiment of the invention can significantly improve the inductance of the multilayer chip inductor, while improving the quality factor and effectively suppressing the increase in DC resistance.

[0025] In this embodiment, the width W2 of the coil layer 12 ranges from 80 to 120 μm. This range covers the typical linewidth design of coil conductors in current miniaturized multilayer chip inductors, and has wide applicability. When W2 is less than 80 μm, the cross-sectional area of ​​the coil layer 12 is too small, which leads to an increase in DC resistance; when W2 is greater than 120 μm, it is difficult to arrange the coil layer 12 within the limited product space to achieve the target inductance. Limiting W2 to this range can meet the dual requirements of low DC resistance and high inductance.

[0026] The connecting hole 11a is elongated. Compared with the circular or elliptical connecting holes used in the prior art, the elongated structure can maintain or increase the conduction area by extending the length dimension when the width direction is limited.

[0027] The width W1 of pad 13 and the width W3 of connecting hole 11a satisfy W3=W1-2×ΔP, where ΔP is the distance between the outer edge of connecting hole 11a and the outer edge of pad 13 along the width direction. The length L of connecting hole 11a satisfies W1≤L≤3×W1.

[0028] Through the above steps, the connecting hole 11a is compressed in the width direction to match the narrowed width W1 of the pad, while obtaining sufficient conductive area in the length direction, thereby ensuring that the reliability of the interlayer electrical connection is not reduced due to the narrowing of the pad 13. If L < W1, the effective conductive area of ​​the connecting hole 11a is insufficient, the interlayer contact resistance increases, and the electrical performance is affected; if L > 3 × W1, the connecting hole 11a is too long, which weakens the structural strength of the insulating layer 11 on the one hand, and is prone to cracking due to uneven shrinkage during sintering on the other hand. Limiting L to the range of W1 to 3 × W1 can achieve a balance between conductive area and structural reliability.

[0029] In addition, by limiting W3=W1-2×ΔP, a reasonable alignment deviation margin is reserved for processes such as laser drilling, printing, lamination and exposure. Even when the width of the pad 13 is compressed to be close to the width of the coil layer 12, it can still be ensured that the connection hole 11a falls completely within the coverage area of ​​the pad 13, avoiding interlayer open circuit defects caused by process offset.

[0030] In some embodiments, the distance ΔP between the outer edge of the connecting hole 11a and the outer edge of the pad 13 ranges from 20 to 40 μm. When ΔP is less than 20 μm, the process tolerance margin is insufficient, and the connecting hole 11a may fall outside the pad 13 due to hole misalignment, resulting in poor interlayer conductivity. When ΔP is greater than 40 μm, it means that the width W3 of the connecting hole 11a is too small, the conductive cross-sectional area is severely reduced, and the interlayer contact resistance increases significantly. Limiting ΔP to the range of 20-40 μm can balance the dual requirements of process tolerance and conductive area.

[0031] like Figure 1 As shown, in some embodiments, the connecting hole 11a includes a rectangular portion and semicircular portions on both sides of the rectangular portion. This shape of the connecting hole 11a can avoid stress concentration at the corners of a pure rectangular hole. At the same time, compared with a pure elliptical hole, the middle rectangular segment can provide a larger effective conductive area, and the smooth transition of the semicircular portions at both ends is conducive to releasing thermal stress during sintering and reducing the risk of cracking of the insulating layer 11.

[0032] like Figure 1 As shown, in some embodiments, the diameter of the semicircular portion is equal to the width of the rectangular portion. This creates a smooth tangential transition between the rectangular portion and the semicircular portion, eliminating stress concentration points at sharp corners and further improving the stress distribution around the connecting hole 11a, thus contributing to improved product reliability.

[0033] In some embodiments, the dimensions of the connecting hole 11a satisfy 2×W3≤L≤4×W3. This proportional limitation ensures that the length extension of the connecting hole 11a matches its width, preventing it from being too long and thin or too short and thick. When 2×W3>L, the elongated shape is not prominent, making it difficult to fully utilize the advantage of increased conductive area along the length direction; when L>4×W3, the connecting hole 11a is too long and thin, increasing the difficulty of forming during laser cutting or exposure development, and making it difficult to guarantee the uniformity of the conductive paste filling inside the hole. The dimension range of the connecting hole 11a in this embodiment achieves better forming processability and filling effect.

[0034] In some embodiments, the connecting hole 11a is formed by laser cutting or photomask processing. Laser cutting offers advantages such as high processing precision, a small heat-affected zone, and no contact stress, making it suitable for processing connecting holes 11a on thin insulating layers 11. For example, ultraviolet lasers (UV lasers) are used for cutting, as their shorter wavelength allows for more precise ablation of the insulating layer 11 material, resulting in connecting holes 11a with neat edges and accurate dimensions. Alternatively, the connecting hole 11a can be formed by photomask processing, where photoresist is coated onto the green insulating layer 11, exposed and developed using a photomask, and then etched or developed to remove unprotected areas, thereby forming the connecting hole 11a. Photomask processing is suitable for mass production and offers advantages such as high efficiency, good consistency, and high hole wall perpendicularity.

[0035] In some embodiments, the coil layer 12 and the pads 13 are printed, with the pads 13 extending into the connection holes 11a. Specifically, after the connection holes 11a are formed on the insulating layer 11, conductive paste is filled into the connection holes 11a by screen printing or stencil printing, while a coil pattern is formed in the region of the coil layer 12. The pads 13 are integrally printed with the coil layer 12, and the conductive paste in the region of the pads 13 flows naturally into and fills the connection holes 11a during the printing process, forming conductive pillars penetrating the insulating layer 11 after sintering, thus achieving reliable electrical connection of the coil layers 12 of adjacent stacked units 1. This process requires no additional filling steps and has high manufacturing efficiency.

[0036] In some embodiments, the orthographic projection of the connector hole 11a onto the insulating layer 11 falls entirely within the orthographic projection range of the pad onto the insulating layer. Thus, the entire opening area of ​​the connector hole 11a is covered by the pad 13, and there is no situation where the connector hole 11a extends beyond the edge of the pad 13. This ensures that the conductive material filling the connector hole 11a forms a complete circumferential contact interface with the pad 13, resulting in a lower interlayer contact resistance.

[0037] In some embodiments, the distance between the outer edge of the connecting hole 11a and the outer edge of the pad 13 along the length direction is ΔP. ​​Thus, based on the aforementioned ΔP allowance in the width direction, this embodiment further allows an equal ΔP distance at both ends in the length direction. This causes the entire outer contour of the connecting hole 11a (including both the width and length directions) to be recessed by ΔP relative to the outer contour of the pad 13, forming a uniform-width process allowance band around the connecting hole 11a. This provides the same tolerance space for any directional offset of the connecting hole 11a in the two-dimensional plane, further improving the tolerance for process deviations and ensuring high conductivity yield under mass production conditions.

[0038] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.

Claims

1. An interlayer structure for a multilayer chip inductor, the multilayer chip inductor comprising multiple stacked units, each stacked unit comprising an insulating layer, a coil layer, and two pads, the insulating layer having two connection holes, the two pads being located at the beginning and end of the coil layer, the two pads corresponding one-to-one with the two connection holes, characterized in that, The width W1 of the pad is less than or equal to the width W2 of the coil layer, and the inner boundary of the pad does not exceed the inner boundary of the coil layer. The connecting hole is elongated. The width W1 of the pad and the width W3 of the connecting hole satisfy W3 = W1 - 2 × ΔP, where ΔP is the distance between the outer edge of the connecting hole and the outer edge of the pad along the width direction. The length L of the connecting hole satisfies W1 ≤ L ≤ 3 × W1.

2. The interlayer structure of the multilayer chip inductor according to claim 1, characterized in that, The connecting hole includes a rectangular portion and semicircular portions on both sides of the rectangular portion.

3. The interlayer structure of the multilayer chip inductor according to claim 2, characterized in that, The diameter of the semicircular portion is equal to the width of the rectangular portion.

4. The interlayer structure of the multilayer chip inductor according to claim 1, characterized in that, The dimensions of the connecting hole satisfy 2×W3≤L≤4×W3.

5. The interlayer structure of the multilayer chip inductor according to claim 1, characterized in that, The connecting hole is formed by laser cutting or exposure masking.

6. The interlayer structure of the multilayer chip inductor according to claim 1, characterized in that, The width W2 of the coil layer ranges from 80 to 120 μm.

7. The interlayer structure of the multilayer chip inductor according to claim 1, characterized in that, The distance ΔP between the outer edge of the connecting hole and the outer edge of the pad ranges from 20 to 40 μm.

8. The interlayer structure of the multilayer chip inductor according to claim 1, characterized in that, The coil layer and the pads are printed, and the pads extend into the connection holes.

9. The interlayer structure of the multilayer chip inductor according to claim 1, characterized in that, The orthographic projection of the connection hole on the insulating layer falls completely within the orthographic projection range of the pad on the insulating layer.

10. The interlayer structure of the multilayer chip inductor according to claim 1, characterized in that, The distance between the outer edge of the connecting hole and the outer edge of the pad along the length direction is ΔP.

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