Wide-temperature-range 660nm red light vcsele epitaxial structure and preparation method thereof

Abstract

The application relates to the field of semiconductor optoelectronics, and particularly relates to a wide-temperature-range 660nm red light VCSEL epitaxial structure and a preparation method thereof. The 660nm red light VCSEL epitaxial structure comprises, in sequence along an epitaxial growth direction, a GaAs substrate, a buffer layer, an n-DBR layer, an active region, an oxidation limiting layer, a p-DBR layer and an ohmic contact layer, the active region comprises first quantum well layers and second quantum well layers which are alternately grown in sequence; wherein dlambda1 / dT of the first quantum well layers is less than dlambda2 / dT of the second quantum well layers, and dlambda2 / dT-dlambda1 / dT is greater than or equal to 0.03nm / K. The application makes the comprehensive gain spectrum non-uniformly stretch with temperature, realizes dynamic matching of gain and cavity mode in a wide temperature range of-20-85 DEG C, the device output power fluctuation is less than 15%, the process is compatible with the existing mass production production line, and has good industrial application value.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronics technology, specifically to a 660nm red VCSEL epitaxial structure with a wide temperature range and its fabrication method. Background Technology

[0002] 660nm red vertical-cavity surface-emitting lasers (VCSELs) have wide applications in plastic fiber optic communication, laser displays, biomedical detection, laser printing, and barcode scanning due to their advantages such as small size, high beam quality, high coupling efficiency, and low manufacturing cost. These devices typically employ AlGaInP or AlGaAs materials, and the gain characteristics of their active quantum wells are highly sensitive to temperature changes. In actual operation, current injection causes the active region temperature to rise, and the bandgap of the quantum well material decreases with increasing temperature, resulting in a redshift of the peak gain wavelength. Simultaneously, the resonant cavity mode wavelength of the VCSEL also drifts with temperature changes. The two exhibit significant differences in temperature drift rates: the gain peak wavelength temperature drift coefficient dλ / dT of the red InGaP quantum well is 0.20~0.35nm / K, while the cavity mode wavelength temperature drift coefficient determined by the DBR mirror is only 0.06~0.08nm / K. The redshift rate of the gain peak is much faster than that of the cavity mode, resulting in a severe mismatch between the gain and cavity mode within the operating temperature range, and a significant decrease in output power. This has become a key technical bottleneck restricting the stable operation of the device in a wide temperature range.

[0003] To address the gain peak and resonant cavity mode mismatch caused by temperature rise, the industry has proposed two optimization schemes: one is to adopt a negative detuning compensation design, which sets the gain peak wavelength at room temperature to be shorter than the resonant cavity mode wavelength, and utilizes the faster redshift rate of the gain peak to enable the device to achieve a gain-cavity mode matching state at a preset operating temperature point; the other is a chirped multiple quantum well (MQW) static broadening design, which broadens the gain spectrum at room temperature to more than 10 nm by adjusting the thickness or composition parameters of different quantum wells, thereby increasing the device's tolerance range to temperature fluctuations.

[0004] However, negative mistuning compensation designs can only achieve optimal matching around a single design temperature, covering a relatively narrow effective temperature range (typically 30-40°C). When the ambient temperature deviates from the design point, the mismatch between gain and cavity mode intensifies rapidly. In the MQW static broadening scheme, the temperature drift coefficients of the peak gain wavelength of each quantum well remain largely consistent. When the temperature changes, the broadened gain spectrum shifts as a whole. As the temperature continues to rise, the entire gain spectrum redshifts and gradually crosses the resonant cavity mode, eventually causing the cavity mode to fall into the low-gain edge of the gain spectrum, resulting in a significant decrease in device output power. Both of these schemes optimize based on static wavelength or spectral width parameters, failing to change the inherent law of the gain spectrum shifting as a whole with temperature, making it difficult to maintain gain-cavity mode matching continuously over a wide temperature range. Summary of the Invention

[0005] To address the technical problem that the temperature drift rate of the peak gain wavelength of existing red VCSELs is much greater than that of the resonant cavity mode drift rate, and that existing negative detuning compensation and chirped multi-quantum-well schemes cannot change the overall shift of the gain spectrum with temperature, resulting in severe mismatch between gain and cavity mode and a significant decrease in output power over a wide temperature range, this invention provides a 660nm red VCSEL epitaxial structure with a wide temperature range and its fabrication method.

[0006] The technical solution of this invention is as follows: In a first aspect, the present invention provides a 660nm red VCSEL epitaxial structure with a wide temperature range, comprising, along the epitaxial growth direction, a GaAs substrate, a buffer layer, an n-DBR layer, an active region, an oxide confinement layer, a p-DBR layer, and an ohmic contact layer. The active region comprises a first quantum well layer and a second quantum well layer that are alternately grown in sequence. Wherein, dλ1 / dT of the first quantum well layer is less than dλ2 / dT of the second quantum well layer, and dλ2 / dT-dλ1 / dT ≥ 0.03nm / K. Wherein, dλ2 / dT-dλ1 / dT represents the difference between dλ2 / dT and dλ1 / dT.

[0007] Furthermore, 0.20nm / K≤dλ1 / dT≤0.26nm / K.

[0008] Furthermore, 0.28nm / K≤dλ2 / dT≤0.34nm / K.

[0009] Furthermore, the material of the first quantum well layer is In. x1 Ga 1-x1 P, where 0.30≤x1≤0.38; the thickness of the first quantum well layer is 6~8nm.

[0010] Furthermore, the material of the second quantum well layer is In. x2 Ga 1-x2P, where 0.42≤x2≤0.5; the thickness of the second quantum well layer is 4~6nm.

[0011] Furthermore, x2-x1≥0.05.

[0012] Furthermore, a barrier layer is provided between the first quantum well layer and the second quantum well layer, and the material of the barrier layer is AlGaInP or AlGaAs.

[0013] Furthermore, the total number of the first quantum well layer and the second quantum well layer is 4 to 8.

[0014] Furthermore, the ratio of the number of first quantum well layers to the number of second quantum well layers is (1:1) to (3:2).

[0015] Secondly, the present invention provides a method for fabricating the above-mentioned wide-temperature-range 660nm red VCSEL epitaxial structure, which is carried out by metal-organic chemical vapor deposition (MOCVD) technology, and a buffer layer, an n-DBR layer, an active region, an oxide confinement layer, a p-DBR layer and an ohmic contact layer are grown sequentially on a GaAs substrate.

[0016] The beneficial effects of this invention are as follows: 1. The 660nm red VCSEL epitaxial structure with a wide temperature range provided by the present invention, by setting a first quantum well layer and a second quantum well layer in the active region with the temperature drift coefficient of the gain peak wavelength satisfying dλ2 / dT-dλ1 / dT≥0.03nm / K, causes the comprehensive gain spectrum to undergo non-uniform stretching with temperature change, realizes dynamic adaptive matching between the gain spectrum and the cavity mode, and can control the output power fluctuation within 15% in the ambient temperature range of -20℃~85℃, significantly improving the stability of the device in wide temperature range operation.

[0017] 2. The 660nm red VCSEL epitaxial structure with a wide temperature range provided by the present invention solves the problem of excessive local gain wavelength shift caused by uneven temperature distribution in the active region by arranging the second quantum well layer with a higher temperature drift coefficient near the heat-generating side of the p-DBR layer and the first quantum well layer with a lower temperature drift coefficient near the heat-dissipating side of the n-DBR layer. This allows the wavelength drift of the quantum wells at each position to be precisely matched with the local temperature rise, and the deviation between the gain peak and the cavity mode wavelength in the entire temperature range can be controlled within 1.5nm, thus maintaining a high gain output state. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a cross-sectional schematic diagram of the 660nm red VCSEL epitaxial structure with a wide temperature range provided by the present invention.

[0020] Figure 2 The experimental curves show the output power fluctuations under different In component differences.

[0021] In the figure, 101 is the GaAs substrate, 102 is the buffer layer, 103 is the n-DBR layer, 104 is the active region, 1041 is the first quantum well layer, 104 is the second quantum well layer, 1043 is the barrier layer, 105 is the oxide confinement layer, 106 is the p-DBR layer, and 107 is the ohmic contact layer. Detailed Implementation

[0022] This invention is based on the discovery that the temperature drift coefficient dλ / dT of the gain peak wavelength of InGaP quantum wells is positively correlated with its In composition. When the In composition linearly increases from 30% to 50%, dλ / dT linearly increases from approximately 0.22 nm / K to approximately 0.34 nm / K. Utilizing this principle, this invention provides a wide-temperature-range 660 nm red VCSEL epitaxial structure, such as... Figure 1 As shown, along the epitaxial growth direction, it includes a GaAs substrate 101, a buffer layer 102, an n-DBR layer 103, an active region 104, an oxide confinement layer 105, a p-DBR layer 106, and an ohmic contact layer 107.

[0023] The active region 104 of the present invention comprises a first quantum well layer 1041 and a second quantum well layer 1042 grown alternately in sequence; wherein, the material of the first quantum well layer 1041 is In. x1 Ga 1-x1 P, 0.30≤x1≤0.38, 0.20nm / K≤dλ1 / dT≤0.26nm / K; the material of the second quantum well layer 1042 is In. x2 Ga 1-x2 P, where 0.42≤x2≤0.5; the thickness of the second quantum well layer 1042 is 4~6nm; the total number of the first quantum well layer 1041 and the second quantum well layer 1042 is 6, and the ratio of the number of the first quantum well layer 1041 to the number of the second quantum well layer 1042 is 1:1; a barrier layer 1043 is provided between the first quantum well layer 1041 and the second quantum well layer 1042, and the material of the barrier layer 1043 is (Al). 0.5 Ga 0.5 ) 0.5 In 0.5P, the thickness of a single barrier layer 1043 is 8 nm. Quantum wells with significantly different dλ / dT are integrated within the same active region 104, with the quantum well with higher dλ / dT located near the heating side of the active region 104, i.e., the p-DBR layer 106. This causes the combined gain spectrum to undergo non-uniform stretching rather than overall translation when the temperature changes, thereby minimizing the mismatch between the cavity mode and the gain spectrum across the entire temperature range.

[0024] The overall gain spectrum of the active region 104 is the envelope superposition of the gain spectra of all quantum well sub-gain peaks. As the temperature increases, the second quantum well layer 1042 (high In composition), located near the heat source, experiences both a large local temperature rise and a high dλ² / dT value, resulting in the largest redshift of its sub-gain peak. The first quantum well layer 1041 (low In composition), located near the heat dissipation side, experiences a smaller local temperature rise and a lower dλ¹ / dT value, resulting in the smallest redshift of its sub-gain peak. The redshifts of the quantum wells in the middle transition sequentially. After the differential redshifts of multiple sub-gain peaks are superimposed, the overall gain spectrum exhibits a faster extension rate on the long-wavelength side and a slower extension rate on the short-wavelength side. Macroscopically, this manifests as a non-uniform stretching of the spectrum shape, rather than the overall translation effect resulting from the synchronous shift of all sub-gain peaks in a traditional structure.

[0025] In addition to confining charge carriers, the barrier layer 1043 described in this invention also serves to compensate for the strain in the active region 104. The second quantum well layer 1042 (high In composition) experiences compressive strain relative to the GaAs substrate 101, with the higher the In composition, the stronger the compressive strain; the first quantum well layer 1041 (low In composition) experiences relatively weaker compressive strain. The material of the barrier layer 1043 described in this invention is (Al... 0.5 Ga 0.5 ) 0.5 In 0.5 P can form tensile strain that is opposite in direction and matches the magnitude of the strain in the quantum well, so that the total strain of the entire active region 104 cancels each other out, avoiding dislocations and crystal defects caused by lattice mismatch, ensuring the crystal quality and luminescence efficiency of the quantum well, while avoiding additional wavelength temperature drift interference introduced by strain, ensuring that dλ / dT is precisely controlled only by the In composition.

[0026] The temperature drift rate of the VCSEL resonant cavity mode stabilizes at 0.06~0.08 nm / K. The gain spectrum needs to be adjusted through non-uniform stretching to bring the equivalent temperature drift rate at the center of the spectrum closer to the cavity mode temperature drift rate. When the difference in dλ / dT between the two types of quantum wells (i.e., dλ2 / dT - dλ1 / dT) < 0.02 nm / K, the difference in redshift of each sub-gain peak is less than the full width at half maximum (FWHM) of the gain spectrum itself. After superposition, the spectrum shape is approximately shifted as a whole, and the equivalent center temperature drift rate of the combined gain spectrum is still much higher than the cavity mode temperature drift rate, making effective matching impossible. When dλ2 / dT - dλ1 / dT > 0.03 nm / K, the difference in redshift of each sub-gain peak is sufficient to change the envelope shape of the gain spectrum, reducing the equivalent center temperature drift rate of the combined gain spectrum to a level close to that of the cavity mode. Therefore, the wide-temperature power stability of the device exhibits a critical abrupt change effect.

[0027] The n-DBR layer 103 and p-DBR layer 106 described in this invention together constitute the upper and lower reflectors of the VCSEL, which is the core structure for the device to form laser oscillations. Both DBR layers are made of alternating stacks of semiconductor materials with high and low refractive indices. The optical thickness of each layer is one-quarter of the target wavelength. Through the Bragg interference effect, extremely high reflectivity is achieved in the 660nm red light band, allowing photons radiated from the active region 104 to be repeatedly reflected and continuously stimulated amplified within the cavity, ultimately forming a stable laser output. The wavelength of the resonant cavity mode is determined by the effective refractive index of the DBR and the physical cavity length of the resonant cavity. Since the refractive index of the semiconductor material changes only slightly with temperature, the temperature drift coefficient of the cavity mode wavelength is only 0.06~0.08nm / K, which is much lower than the temperature drift rate of the quantum well gain peak. This is the core physical reason for the mismatch between the gain peak and the cavity mode. Meanwhile, the p-DBR layer 106 has a much lower hole mobility than electrons and a larger series resistance, resulting in more concentrated Joule heat during operation. It is one of the main heat-generating areas of the device. The n-DBR layer 103 is directly connected to the highly thermally conductive GaAs substrate 101, forming the main heat dissipation channel of the device. This provides the objective conditions for the non-uniform stretching and contraction of the integrated gain spectrum when the temperature changes.

[0028] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0029] Example 1 A wide-temperature-range 660nm red VCSEL epitaxial structure includes, along the epitaxial growth direction, a GaAs substrate 101, a buffer layer 102, an n-DBR layer 103, an active region 104, an oxide confinement layer 105, a p-DBR layer 106, and an ohmic contact layer 107. The GaAs substrate 101 is n-type doped and has a thickness of 350 μm; the buffer layer 102 is made of GaAs, has a thickness of 200 nm, is n-type doped, and has a doping concentration of 2 × 10⁻⁶. 18 cm -3 n-DBR layer 103 consists of 30 pairs of Al atoms grown alternately in sequence. 0.9 Ga 0.1 As and Al 0.5 Ga 0.5 Composed of As, each layer has an optical thickness of λ / 4 (λ=660nm), n-type doped, with a doping concentration of 3×10⁻⁶. 18 cm -3 ; The active region 104 includes a first quantum well layer 1041 and a second quantum well layer 1042 that are grown alternately in sequence. The material of the first quantum well layer 1041 is In. 0.35 Ga 0.65 P has a thickness of 7 nm and dλ1 / dT = 0.22 nm / K; the second quantum well layer 1042 is made of In. 0.45 Ga 0.55 P has a thickness of 5 nm and dλ2 / dT = 0.31 nm / K; that is, dλ2 / dT - dλ1 / dT = 0.09 nm / K; the total number of the first quantum well layer 1041 and the second quantum well layer 1042 is 6, and the ratio of the number of the first quantum well layer 1041 to the number of the second quantum well layer 1042 is 1:1; a barrier layer 1043 is provided between the first quantum well layer 1041 and the second quantum well layer 1042, and the material of the barrier layer 1043 is (Al). 0.5 Ga 0.5 ) 0.5 In 0.5 P, the thickness of a single barrier layer is 8nm (1043); The material of the oxide confinement layer 105 is Al. 0.98 Ga 0.02 As, thickness 30nm; p-DBR layer 106, composed of 22 pairs of sequentially alternating Al atoms 0.9 Ga 0.1 As and Al 0.5 Ga 0.5 As composition, p-type doped, doping concentration 4 × 10⁻⁶ 18 cm -3 ; The ohmic contact layer 107 is made of GaAs, with a thickness of 20 nm, and is p-type doped with a doping concentration of 1 × 10⁻⁶.19 cm -3 .

[0030] The fabrication method of the above-mentioned wide-temperature-range 660nm red VCSEL epitaxial structure is carried out using MOCVD and includes the following steps: (1) Under the conditions of 680℃ and 100mbar growth pressure, TMGa and AsH3 are introduced to grow a buffer layer 102 on GaAs substrate 101. (2) Maintain a temperature of 680°C, introduce TMAl, TMGa and AsH3, and grow an n-DBR layer 103 on the buffer layer 102 by controlling the flow rate of TMAl; (3) When growing the active region 104, TMA1, TMAGa and AsH3 are introduced to grow a barrier layer 1043 on the n-DBR layer 103. Then TMAIn, TMAGa and AsH3 are introduced to grow a first quantum well layer 1041 on the barrier layer 1043. Then TMAIn is switched to TMA1 to grow a barrier layer 1043 on the first quantum well layer 1041. Then TMA1 is switched to TMAIn to grow a second quantum well layer 1042 on the barrier layer 1043. The growth is repeated for 3 cycles. (4) Introduce TMAl, TMGa and AsH3 to grow an oxide confinement layer 105 on the active region 104; (5) Introduce TMAl, TMGa and AsH3, and grow p-DBR layer 106 on oxide confinement layer 105 by controlling the TMAl flow rate; (6) Introduce TMGa and AsH3 to grow an ohmic contact layer 107 on the p-DBR layer 106.

[0031] Example 2 A wide-temperature-range 660nm red VCSEL epitaxial structure includes, along the epitaxial growth direction, a GaAs substrate 101, a buffer layer 102, an n-DBR layer 103, an active region 104, an oxide confinement layer 105, a p-DBR layer 106, and an ohmic contact layer 107. The GaAs substrate 101 is n-type doped and has a thickness of 350 μm; the buffer layer 102 is made of GaAs, has a thickness of 200 nm, is n-type doped, and has a doping concentration of 2 × 10⁻⁶. 18 cm -3 n-DBR layer 103 consists of 30 pairs of Al atoms grown alternately in sequence. 0.9 Ga 0.1 As and Al 0.5 Ga 0.5 Composed of As, each layer has an optical thickness of λ / 4 (λ=660nm), n-type doped, with a doping concentration of 3×10⁻⁶. 18 cm -3 ; The active region 104 includes a first quantum well layer 1041 and a second quantum well layer 1042 that are grown alternately in sequence. The material of the first quantum well layer 1041 is In. 0.28 Ga 0.72 P has a thickness of 8 nm and dλ1 / dT = 0.18 nm / K; the second quantum well layer 1042 is made of In. 0.42 Ga 0.58 P, with a thickness of 6 nm, dλ2 / dT = 0.28 nm / K; only the difference can be written, i.e., dλ2 / dT - dλ1 / dT = 0.1 nm / K; the total number of the first quantum well layer 1041 and the second quantum well layer 1042 is 5, and the ratio of the number of the first quantum well layer 1041 to the number of the second quantum well layer 1042 is 3:2; a barrier layer 1043 is provided between the first quantum well layer 1041 and the second quantum well layer 1042, and the material of the barrier layer 1043 is (Al). 0.5 Ga 0.5 ) 0.5 In 0.5 P, the thickness of a single barrier layer is 8nm (1043); The material of the oxide confinement layer 105 is Al. 0.98 Ga 0.02 As, thickness 30nm; p-DBR layer 106, composed of 22 pairs of sequentially alternating Al atoms 0.9 Ga 0.1 As and Al 0.5 Ga 0.5 As composition, p-type doped, doping concentration 4 × 10⁻⁶ 18 cm -3 ; The ohmic contact layer 107 is made of GaAs, with a thickness of 20 nm, and is p-type doped with a doping concentration of 1 × 10⁻⁶. 19 cm -3 .

[0032] The fabrication method of the above-mentioned wide-temperature-range 660nm red VCSEL epitaxial structure is carried out using MOCVD and includes the following steps: (1) Under the conditions of 680℃ and 100mbar growth pressure, TMGa and AsH3 are introduced to grow a buffer layer 102 on GaAs substrate 101. (2) Maintain a temperature of 680°C, introduce TMAl, TMGa and AsH3, and grow an n-DBR layer 103 on the buffer layer 102 by controlling the flow rate of TMAl; (3) When growing the active region 104, TMA1, TMAGa and AsH3 are introduced to grow a barrier layer 1043 on the n-DBR layer 103. Then TMAIn, TMAGa and AsH3 are introduced to grow a first quantum well layer 1041 on the barrier layer 1043. Then TMAIn is switched to TMA1 to grow a barrier layer 1043 on the first quantum well layer 1041. Then TMA1 is switched to TMAIn to grow a second quantum well layer 1042 on the barrier layer 1043. The growth is repeated for 3 cycles. (4) Introduce TMAl, TMGa and AsH3 to grow an oxide confinement layer 105 on the active region 104; (5) Introduce TMAl, TMGa and AsH3, and grow p-DBR layer 106 on oxide confinement layer 105 by controlling the TMAl flow rate; (6) Introduce TMGa and AsH3 to grow an ohmic contact layer 107 on the p-DBR layer 106.

[0033] Example 3 A wide-temperature-range 660nm red VCSEL epitaxial structure includes, along the epitaxial growth direction, a GaAs substrate 101, a buffer layer 102, an n-DBR layer 103, an active region 104, an oxide confinement layer 105, a p-DBR layer 106, and an ohmic contact layer 107. The GaAs substrate 101 is n-type doped and has a thickness of 350 μm; the buffer layer 102 is made of GaAs, has a thickness of 200 nm, is n-type doped, and has a doping concentration of 2 × 10⁻⁶. 18 cm -3 n-DBR layer 103 consists of 30 pairs of Al atoms grown alternately in sequence. 0.9 Ga 0.1 As and Al 0.5 Ga 0.5 Composed of As, each layer has an optical thickness of λ / 4 (λ=660nm), n-type doped, with a doping concentration of 3×10⁻⁶. 18 cm -3 ; The active region 104 includes a first quantum well layer 1041 and a second quantum well layer 1042 that are grown alternately in sequence. The material of the first quantum well layer 1041 is In. 0.38 Ga 0.62 P has a thickness of 6 nm and dλ1 / dT = 0.26 nm / K; the second quantum well layer 1042 is made of In. 0.5 Ga 0.5P has a thickness of 4 nm and dλ2 / dT = 0.34 nm / K; that is, dλ2 / dT - dλ1 / dT = 0.12 nm / K; the total number of the first quantum well layer 1041 and the second quantum well layer 1042 is 4, and the ratio of the number of the first quantum well layer 1041 to the number of the second quantum well layer 1042 is 1:1; a barrier layer 1043 is provided between the first quantum well layer 1041 and the second quantum well layer 1042, and the material of the barrier layer 1043 is (Al). 0.5 Ga 0.5 ) 0.5 In 0.5 P, the thickness of a single barrier layer is 8nm (1043); The material of the oxide confinement layer 105 is Al. 0.98 Ga 0.02 As, thickness 30nm; p-DBR layer 106, composed of 22 pairs of sequentially alternating Al atoms 0.9 Ga 0.1 As and Al 0.5 Ga 0.5 As composition, p-type doped, doping concentration 4 × 10⁻⁶ 18 cm -3 ; The ohmic contact layer 107 is made of GaAs, with a thickness of 20 nm, and is p-type doped with a doping concentration of 1 × 10⁻⁶. 19 cm -3 .

[0034] The fabrication method of the above-mentioned wide-temperature-range 660nm red VCSEL epitaxial structure is carried out using MOCVD and includes the following steps: (1) Under the conditions of 680℃ and 100mbar growth pressure, TMGa and AsH3 are introduced to grow a buffer layer 102 on GaAs substrate 101. (2) Maintain a temperature of 680°C, introduce TMAl, TMGa and AsH3, and grow an n-DBR layer 103 on the buffer layer 102 by controlling the flow rate of TMAl; (3) When growing the active region 104, TMA1, TMAGa and AsH3 are introduced to grow a barrier layer 1043 on the n-DBR layer 103. Then TMAIn, TMAGa and AsH3 are introduced to grow a first quantum well layer 1041 on the barrier layer 1043. Then TMAIn is switched to TMA1 to grow a barrier layer 1043 on the first quantum well layer 1041. Then TMA1 is switched to TMAIn to grow a second quantum well layer 1042 on the barrier layer 1043. The growth is repeated for 3 cycles. (4) Introduce TMAl, TMGa and AsH3 to grow an oxide confinement layer 105 on the active region 104; (5) Introduce TMAl, TMGa and AsH3, and grow p-DBR layer 106 on oxide confinement layer 105 by controlling the TMAl flow rate; (6) Introduce TMGa and AsH3 to grow an ohmic contact layer 107 on the p-DBR layer 106.

[0035] Comparative Example 1 A 660nm red VCSEL epitaxial structure comprises, along the epitaxial growth direction, a GaAs substrate, a buffer layer, an n-DBR layer, an active region, an oxide confinement layer, a p-DBR layer, and an ohmic contact layer. The GaAs substrate is n-type doped and has a thickness of 350 μm; the buffer layer is also made of GaAs, with a thickness of 200 nm, n-type doped, and a doping concentration of 2 × 10⁻⁶. 18 cm -3 The n-DBR layer consists of 30 pairs of Al atoms grown alternately in sequence. 0.9 Ga 0.1 As and Al 0.5 Ga 0.5 Composed of As, each layer has an optical thickness of λ / 4 (λ=660nm), n-type doped, with a doping concentration of 3×10⁻⁶. 18 cm -3 ; The active region consists of alternating barrier layers and quantum well layers, with an alternation period of 6. The quantum well layers are made of In. 0.4 Ga 0.6 P, with a thickness of 6 nm and dλ / dT = 0.27 nm / K; the material of the barrier layer is (Al). 0.5 Ga 0.5 ) 0.5 In 0.5 P, the thickness of a single barrier layer is 8 nm; The material of the oxide confinement layer is Al 0.98 Ga 0.02 As, thickness 30nm; p-DBR layer, composed of 22 pairs of sequentially alternating Al atoms. 0.9 Ga 0.1 As and Al 0.5 Ga 0.5 As composition, p-type doped, doping concentration 4 × 10⁻⁶ 18 cm -3 ; The ohmic contact layer is made of GaAs, with a thickness of 20 nm, p-type doped, and a doping concentration of 1 × 10⁻⁶. 19 cm -3 .

[0036] The fabrication method of the above-mentioned wide-temperature-range 660nm red VCSEL epitaxial structure is carried out using MOCVD and includes the following steps: (1) At a temperature of 680℃ and a growth pressure of 100mbar, TMGa and AsH3 were introduced to grow a buffer layer on a GaAs substrate. (2) Maintain a temperature of 680℃, introduce TMAl, TMGa and AsH3, and grow an n-DBR layer on the buffer layer by controlling the flow rate of TMAl; (3) When growing the active region, TMAl, TMGa and AsH3 are introduced to grow a barrier layer on the n-DBR layer, and then TMIn, TMGa and AsH3 are introduced to grow a quantum well layer on the barrier layer; then TMIn is switched to TMAl to grow a barrier layer on the quantum well layer; the growth is repeated for 3 cycles. (4) Introduce TMAl, TMGa and AsH3 to grow an oxide confinement layer on the active region; (5) Introduce TMAl, TMGa and AsH3, and grow a p-DBR layer on the oxide confinement layer by controlling the TMAl flow rate; (6) Introduce TMGa and AsH3 to grow an ohmic contact layer on the p-DBR layer.

[0037] Comparative Example 2 A 660nm red VCSEL epitaxial structure comprises, along the epitaxial growth direction, a GaAs substrate, a buffer layer, an n-DBR layer, an active region, an oxide confinement layer, a p-DBR layer, and an ohmic contact layer. The GaAs substrate is n-type doped and has a thickness of 350 μm; the buffer layer is also made of GaAs, with a thickness of 200 nm, n-type doped, and a doping concentration of 2 × 10⁻⁶. 18 cm -3 The n-DBR layer consists of 30 pairs of Al atoms grown alternately in sequence. 0.9 Ga 0.1 As and Al 0.5 Ga 0.5 Composed of As, each layer has an optical thickness of λ / 4 (λ=660nm), n-type doped, with a doping concentration of 3×10⁻⁶. 18 cm -3 ; The active region comprises alternating barrier layers and quantum well layers, with an alternation period of 6; the quantum well layer is made of In. 0.4 Ga 0.6 P, the thickness of a single quantum well layer increases linearly from 6 nm to 8 nm from bottom to top, dλ / dT = 0.27 nm / K; the material of the barrier layer is (Al). 0.5 Ga 0.5 ) 0.5 In 0.5 P, the thickness of a single barrier layer is 8 nm; The material of the oxide confinement layer is Al 0.98 Ga0.02 As, thickness 30nm; p-DBR layer, composed of 22 pairs of sequentially alternating Al atoms. 0.9 Ga 0.1 As and Al 0.5 Ga 0.5 As composition, p-type doped, doping concentration 4 × 10⁻⁶ 18 cm -3 ; The ohmic contact layer is made of GaAs, with a thickness of 20 nm, p-type doped, and a doping concentration of 1 × 10⁻⁶. 19 cm -3 .

[0038] The fabrication method of the above-mentioned wide-temperature-range 660nm red VCSEL epitaxial structure is carried out using MOCVD and includes the following steps: (1) At a temperature of 680℃ and a growth pressure of 100mbar, TMGa and AsH3 were introduced to grow a buffer layer on a GaAs substrate. (2) Maintain a temperature of 680℃, introduce TMAl, TMGa and AsH3, and grow an n-DBR layer on the buffer layer by controlling the flow rate of TMAl; (3) When growing the active region, TMAl, TMGa and AsH3 are introduced to grow a barrier layer on the n-DBR layer, and then TMIn, TMGa and AsH3 are introduced to grow a quantum well layer on the barrier layer; then TMIn is switched to TMAl to grow a barrier layer on the quantum well layer; the growth is repeated for 3 cycles. (4) Introduce TMAl, TMGa and AsH3 to grow an oxide confinement layer on the active region; (5) Introduce TMAl, TMGa and AsH3, and grow a p-DBR layer 106 on the oxide confinement layer by controlling the TMAl flow rate; (6) Introduce TMGa and AsH3 to grow an ohmic contact layer on the p-DBR layer 106.

[0039] Comparative Example 3 A 660nm red VCSEL epitaxial structure comprises, along the epitaxial growth direction, a GaAs substrate, a buffer layer, an n-DBR layer, an active region, an oxide confinement layer, a p-DBR layer, and an ohmic contact layer. The GaAs substrate is n-type doped and has a thickness of 350 μm; the buffer layer is also made of GaAs, with a thickness of 200 nm, n-type doped, and a doping concentration of 2 × 10⁻⁶. 18 cm -3 The n-DBR layer consists of 30 pairs of Al atoms grown alternately in sequence. 0.9 Ga 0.1 As and Al 0.5 Ga 0.5Composed of As, each layer has an optical thickness of λ / 4 (λ=660nm), n-type doped, with a doping concentration of 3×10⁻⁶. 18 cm -3 ; The active region comprises a first quantum well layer and a second quantum well layer grown alternately in sequence. The material of the first quantum well layer is In. 0.38 Ga 0.62 P has a thickness of 7 nm and dλ1 / dT = 0.26 nm / K; the material of the second quantum well layer is In. 0.42 Ga 0.58 P has a thickness of 5 nm and dλ2 / dT = 0.28 nm / K; that is, dλ2 / dT - dλ1 / dT = 0.02 nm / K; the total number of the first and second quantum well layers is 6, and the ratio of the number of the first quantum well layers to the number of the second quantum well layers is 1:1; a barrier layer is provided between the first and second quantum well layers, and the material of the barrier layer is (Al). 0.5 Ga 0.5 ) 0.5 In 0.5 P, the thickness of a single barrier layer is 8 nm; The material of the oxide confinement layer is Al 0.98 Ga 0.02 As, thickness 30nm; p-DBR layer, composed of 22 pairs of sequentially alternating Al atoms. 0.9 Ga 0.1 As and Al 0.5 Ga 0.5 As composition, p-type doped, doping concentration 4 × 10⁻⁶ 18 cm -3 ; The ohmic contact layer is made of GaAs, with a thickness of 20 nm, p-type doped, and a doping concentration of 1 × 10⁻⁶. 19 cm -3 .

[0040] The fabrication method of the above-mentioned wide-temperature-range 660nm red VCSEL epitaxial structure is carried out using MOCVD and includes the following steps: (1) At a temperature of 680℃ and a growth pressure of 100mbar, TMGa and AsH3 were introduced to grow a buffer layer on a GaAs substrate. (2) Maintain a temperature of 680℃, introduce TMAl, TMGa and AsH3, and grow an n-DBR layer on the buffer layer by controlling the flow rate of TMAl; (3) When growing the active region, TMAl, TMGa and AsH3 are introduced to grow a barrier layer 1043 on the n-DBR layer. Then, TMIn, TMGa and AsH3 are introduced to grow the first quantum well layer on the barrier layer. Subsequently, TMIn is switched to TMAl to grow a barrier layer on the first quantum well layer. Then, TMAl is switched to TMIn to grow the second quantum well layer on the barrier layer. This process is repeated for 3 cycles. (4) Introduce TMAl, TMGa and AsH3 to grow an oxide confinement layer on the active region; (5) Introduce TMAl, TMGa and AsH3, and grow a p-DBR layer on the oxide confinement layer by controlling the TMAl flow rate; (6) Introduce TMGa and AsH3 to grow an ohmic contact layer on the p-DBR layer.

[0041] Comparative Example 4 A wide-temperature-range 660nm red VCSEL epitaxial structure includes, along the epitaxial growth direction, a GaAs substrate, a buffer layer, an n-DBR layer, an active region, an oxide confinement layer, a p-DBR layer, and an ohmic contact layer. The GaAs substrate is n-type doped and has a thickness of 350 μm; the buffer layer is also made of GaAs, with a thickness of 200 nm, n-type doped, and a doping concentration of 2 × 10⁻⁶. 18 cm -3 The n-DBR layer consists of 30 pairs of Al atoms grown alternately in sequence. 0.9 Ga 0.1 As and Al 0.5 Ga 0.5 Composed of As, each layer has an optical thickness of λ / 4 (λ=660nm), n-type doped, with a doping concentration of 3×10⁻⁶. 18 cm -3 ; The active region comprises a second quantum well layer and a first quantum well layer grown alternately in sequence, wherein the material of the second quantum well layer is In. 0.45 Ga 0.55 P has a thickness of 5 nm and dλ² / dT = 0.31 nm / K; the material of the first quantum well layer is In. 0.35 Ga 0.65 P has a thickness of 7 nm and dλ1 / dT = 0.22 nm / K; that is, dλ2 / dT - dλ1 / dT = -0.09 nm / K; the total number of the first and second quantum well layers is 6, and the ratio of the number of the first quantum well layers to the number of the second quantum well layers is 1:1; a barrier layer is provided between the first and second quantum well layers, and the material of the barrier layer is (Al). 0.5 Ga 0.5 ) 0.5 In 0.5P, the thickness of a single barrier layer is 8 nm; The material of the oxide confinement layer is Al 0.98 Ga 0.02 As, thickness 30nm; p-DBR layer, composed of 22 pairs of sequentially alternating Al atoms. 0.9 Ga 0.1 As and Al 0.5 Ga 0.5 As composition, p-type doped, doping concentration 4 × 10⁻⁶ 18 cm -3 ; The ohmic contact layer is made of GaAs, with a thickness of 20 nm, p-type doped, and a doping concentration of 1 × 10⁻⁶. 19 cm -3 .

[0042] The fabrication method of the above-mentioned wide-temperature-range 660nm red VCSEL epitaxial structure is carried out using MOCVD and includes the following steps: (1) At a temperature of 680℃ and a growth pressure of 100mbar, TMGa and AsH3 were introduced to grow a buffer layer on a GaAs substrate. (2) Maintain a temperature of 680℃, introduce TMAl, TMGa and AsH3, and grow an n-DBR layer on the buffer layer by controlling the flow rate of TMAl; (3) When growing the active region, TMAl, TMGa and AsH3 are introduced to grow a barrier layer on the n-DBR layer, and then TMIn, TMGa and AsH3 are introduced to grow a second quantum well layer on the barrier layer; then TMIn is switched to TMAl to grow a barrier layer on the second quantum well layer, and then TMAl is switched to TMIn to grow a first quantum well layer on the barrier layer; this process is repeated for 3 cycles. (4) Introduce TMAl, TMGa and AsH3 to grow an oxide confinement layer on the active region; (5) Introduce TMAl, TMGa and AsH3, and grow a p-DBR layer on the oxide confinement layer by controlling the TMAl flow rate; (6) Introduce TMGa and AsH3 to grow an ohmic contact layer on the p-DBR layer.

[0043] Test Example 1 The VCSEL devices prepared in Example 1 and Comparative Examples 1-4 were packaged and their output optical power was tested at ambient temperatures ranging from -20°C to 85°C. The test results are shown in Table 1.

[0044] Table 1 Output optical power of VCSEL devices in ambient temperatures ranging from -20°C to 85°C

[0045] As shown in Table 1, the VCSEL device fabricated in Example 1 consistently exhibits a full width at half maximum (FWHM) of gain greater than 9 nm within an ambient temperature range of -20°C to 85°C, with a gain peak deviation from the cavity mode of less than 1.2 nm. The VCSEL device fabricated in Comparative Example 1, employing a traditional MQW structure, has a FWHM of approximately 5 nm at room temperature, but a gain peak deviation from the cavity mode of more than 4 nm at 85°C. The VCSEL device fabricated in Comparative Example 2, using a chirped MQW structure, has a FWHM of approximately 10 nm at room temperature, but after an overall redshift at 85°C, the gain peak deviation from the cavity mode of more than 4 nm is observed. The mode deviation reaches 2.5 nm, and the gain spectrum shape is distorted; the VCSEL device fabricated in Comparative Example 3 has an active region dλ / dT difference of <0.02 nm / K, x2-x1<0.05, and the gain peak deviation from the cavity mode is about 2.0 nm at 85 °C, with power fluctuation still higher than 25%; the VCSEL device fabricated in Comparative Example 4 has the second quantum well in the active region close to the n-DBR layer, and the first quantum well layer in the active region close to the p-DBR layer 106. Its gain peak deviation from the cavity mode is about 2.8 nm at 85 °C, with power fluctuation higher than 35%.

[0046] Figure 2 The output power fluctuation curves of VCSEL devices fabricated under different In composition differences between the first and second quantum well layers (i.e., different differences in dλ2 / dT and dλ1 / dT) are shown in the ambient temperature range of -20℃ to 85℃. The figure clearly shows that when the In composition difference is less than 0.05 (i.e., dλ2 / dT - dλ1 / dT < 0.02 nm / K), the power fluctuation is higher than 25%; when the In composition difference reaches 0.05 (i.e., dλ2 / dT - dλ1 / dT ≈ 0.03 nm / K), the power fluctuation drops sharply to below 15%; further increasing the In composition difference does not significantly improve the power fluctuation.

[0047] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the present invention by those skilled in the art without departing from the spirit and essence of the invention, and such modifications or substitutions should all be within the scope of the present invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should also be covered within the protection scope of the present invention.

Claims

1. A 660nm red VCSEL epitaxial structure with a wide temperature range, comprising, sequentially along the epitaxial growth direction, a GaAs substrate, a buffer layer, an n-DBR layer, an active region, an oxide confinement layer, a p-DBR layer, and an ohmic contact layer, characterized in that, The active region comprises a first quantum well layer and a second quantum well layer that are grown alternately in sequence; wherein, dλ1 / dT of the first quantum well layer is less than dλ2 / dT of the second quantum well layer, and dλ2 / dT-dλ1 / dT≥0.03nm / K.

2. The 660nm red VCSEL epitaxial structure as described in claim 1, characterized in that, 0.20nm / K≤dλ1 / dT≤0.26nm / K.

3. The 660nm red VCSEL epitaxial structure as described in claim 1, characterized in that, 0.28nm / K≤dλ2 / dT≤0.34nm / K.

4. The 660nm red VCSEL epitaxial structure as described in claim 1, characterized in that, The material of the first quantum well layer is In x1 Ga 1-x1 P, where 0.30≤x1≤0.38, and the thickness of the first quantum well layer is 6~8nm.

5. The 660nm red VCSEL epitaxial structure as described in claim 4, characterized in that, The material of the second quantum well layer is In x2 Ga 1-x2 P, where 0.42≤x2≤0.5, and the thickness of the second quantum well layer is 4~6nm.

6. The 660nm red VCSEL epitaxial structure as described in claim 5, characterized in that, x2-x1≥0.

05.

7. The 660nm red VCSEL epitaxial structure as described in claim 1, characterized in that, A barrier layer is provided between the first quantum well layer and the second quantum well layer, and the material of the barrier layer is AlGaInP or AlGaAs.

8. The 660nm red VCSEL epitaxial structure with a wide temperature range as described in claim 1, characterized in that, The total number of the first quantum well layer and the second quantum well layer is 4 to 8.

9. The 660nm red VCSEL epitaxial structure as described in claim 1, characterized in that, The ratio of the number of first quantum well layers to the number of second quantum well layers is (1:1) to (3:2).

10. A method for fabricating a 660nm red VCSEL epitaxial structure as described in any one of claims 1 to 9, characterized in that, The process was carried out using metal-organic chemical vapor deposition (MOCVD), in which a buffer layer, an n-DBR layer, an active region, an oxide confinement layer, a p-DBR layer, and an ohmic contact layer were sequentially grown on a GaAs substrate.

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