Code division multiple access-based microgrid harmonic injection active protection method and related device

Abstract

The embodiment of the application provides a kind of microgrid harmonic injection active protection method based on code division multiple access and related equipment, belong to microgrid protection technical field.The application makes all inverter interface distributed power supply share same carrier frequency, and distinguishes each power supply by mutually orthogonal Walsh code;After three-phase current is extracted by SOGI positive sequence, Park transformation and low-pass filtering in monitoring point, complex observation matrix is formed by using ideal square wave sliding correlation to realize accurate positioning and normalization;Least square method is used to obtain the despreading coefficient of each power supply when fault occurs, and precise synchronization is realized by energy-difference joint criterion;Double-end coefficient difference direction criterion is used for main feeder, and single-end difference sign consistency criterion is used for branch feeder, and protection device executes trip or lock according to criterion.The application does not need additional harmonic compensation loop, supports plug and play, and has good selectivity and reliability under symmetric and asymmetric fault.

Description

Technical Field

[0001] This application relates to the field of power system microgrid protection technology, and in particular to a microgrid harmonic injection active protection method and related equipment based on Code Division Multiple Access (CDMA). Background Technology

[0002] With the large-scale application of distributed generation technology in distribution networks, the penetration rate of Inverter Interfaced Distributed Generators (IIDGs) in microgrids is rapidly increasing. Due to the limited fault current amplitude and flexible topology of IIDGs, traditional overcurrent and directional protection methods struggle to guarantee selectivity and speed. To address this issue, a harmonic injection protection method based on frequency division multiple access (FDMA) has been proposed, where each IIDG distinguishes itself by injecting harmonics of different frequencies after a fault. However, this approach requires additional harmonic compensation loops and point of common coupling (PCC) frequency-selective filters to suppress the shunting effect of non-injection sources on harmonic signals, leading to complex system hardware, increased costs, and limited frequency resources. Adding new IIDGs necessitates replanning, making "plug-and-play" difficult. Therefore, a simplified, flexible, and reliable active protection scheme for microgrids is urgently needed. Summary of the Invention

[0003] The main objective of this application is to propose a microgrid harmonic injection active protection method, system, electronic device, storage medium, and program product based on code division multiple access, aiming to solve the technical problems of existing frequency division multiple access harmonic injection protection schemes, which require additional configuration of harmonic compensation circuits and PCC filters, have complex systems, limited frequency resources, and poor scalability.

[0004] To achieve the above objectives, one aspect of this application proposes a microgrid harmonic injection active protection method based on code division multiple access, the method comprising: Step S1: Fault detection and injection start-up - The distributed power supply of each inverter interface monitors the grid connection point voltage in real time. When the start-up criteria are met, wait for the current fundamental cycle to end, and start harmonic injection synchronously at the next fundamental voltage zero crossing point. Step S2: Spread spectrum signal generation and injection—All inverter interface distributed power sources share the same carrier frequency, allocate mutually orthogonal Walsh codes as spread spectrum sequences, and use binary phase shift keying modulation to generate Walsh code modulated harmonic currents and inject them into the microgrid; Step S3: Monitoring point signal separation - The monitoring point collects three-phase current, which is extracted in positive sequence by a second-order generalized integrator, Park transform and low-pass filtered to obtain a smooth DC Walsh code signal that reflects the contribution of distributed power sources at each inverter interface. Step S4: Template generation and normalization - Sequentially inject the harmonic current modulated by Walsh code into the distributed power supply of each inverter interface, extract the Walsh code signal through signal separation; use ideal square wave sliding correlation to achieve accurate positioning and extract the template, and then perform phase alignment and energy normalization to form a complex observation matrix. Step S5: Multi-IIDG Despreading and Joint Criterion – Despreading is performed using the least squares method to obtain the instantaneous despreading coefficients of the distributed power sources at each inverter interface; an energy-difference joint criterion is constructed to determine the chip start time, and the instantaneous despreading coefficients of the distributed power sources at each inverter interface are output at the specified time. Step S6: Protection criterion execution—For the main feeder, the direction criterion of the double-ended coefficient difference is used; for the branch feeder, the consistency criterion of the sign of the coefficient difference before and after the fault is used; the protection device executes trip or block command according to the criterion result.

[0005] In some embodiments, the start-up criterion in step S1 is: the positive sequence voltage amplitude at the grid connection point of the distributed power supply at the inverter interface is lower than the positive sequence lower limit coefficient of the rated phase voltage amplitude, or the negative sequence voltage amplitude is higher than the negative sequence upper limit coefficient of the rated phase voltage amplitude.

[0006] In some embodiments, the length of the Walsh code in step S2 is set according to the total number of distributed power sources at the inverter interface in the microgrid. Each distributed power source at the inverter interface is assigned mutually orthogonal Walsh codewords. The chip symbol "+1" corresponds to a carrier phase of 0°, and the chip symbol "-1" corresponds to a carrier phase of 180°.

[0007] In some embodiments, step S3 specifically includes: The three-phase currents collected from the monitoring points were subjected to Clarke transformation to obtain... Axial components and Axial components; To each Axial components and The axial component is used with a second-order generalized integrator whose center angular frequency is equal to the carrier frequency to obtain the in-phase component and the quadrature component. Calculation of positive sequence based on instantaneous symmetric component method Quantity; Park transform is performed with the synchronous rotational angular frequency equal to the carrier frequency; The residual broadband noise is filtered out by low-pass filtering to obtain a smooth DC Walsh code signal.

[0008] In some embodiments, the precise positioning achieved by utilizing ideal square wave sliding correlation in step S4 specifically includes: An ideal DC square wave reference is generated based on the Walsh chip symbols of the current inverter interface distributed power supply. Calculate the sliding correlation value between the ideal DC square wave reference and the Walsh code signal obtained after signal separation; The position of the maximum correlation value is taken as the start time of the chip.

[0009] In some embodiments, the phase alignment in step S4 specifically includes: calculating the average phase of the original template in the central region of the chip using the chip start time, and rotating the entire template in reverse to the average phase; the energy normalization specifically includes: dividing the phase-aligned template by its own norm to obtain a unit norm normalized template.

[0010] In some embodiments, the energy-difference joint criterion in step S5 is: when both the energy term and the difference term are greater than the first threshold, it is determined that precise synchronization has been achieved; wherein, for the main feeder, the difference term is the spatial difference between the instantaneous despreading coefficients of the two-end monitoring points; for the branch feeder, the difference term is the difference between the instantaneous despreading coefficients of the single-end monitoring point before and after the fault.

[0011] In some embodiments, the direction criterion for the difference between the two ends of the coefficient in step S6 is specifically as follows: at the precise synchronization moment, the despreading coefficients of the upstream monitoring point and the downstream monitoring point are obtained respectively; the difference between the sum of the coefficients of the upstream monitoring point belonging to the distributed power source set of the upstream inverter interface and the sum of the coefficients of the downstream monitoring point belonging to the distributed power source set of the upstream inverter interface, and the difference between the sum of the coefficients of the downstream monitoring point belonging to the distributed power source set of the downstream inverter interface and the sum of the coefficients of the upstream monitoring point belonging to the distributed power source set of the downstream inverter interface; when both differences are greater than a set threshold, it is determined that the fault occurs between the two monitoring points.

[0012] In some embodiments, the consistency criterion for the sign of the coefficient difference before and after the fault in step S6 is specifically as follows: obtain the despreading coefficient before the fault and the despreading coefficient after the fault at the monitoring point at the beginning of the branch feeder, calculate the sign of the coefficient difference of the distributed power supply of each inverter interface before and after the fault, and if the coefficient difference of the distributed power supply of all inverter interfaces is positive, then it is determined that the fault occurred inside the branch feeder.

[0013] To achieve the above objectives, another aspect of this application proposes a microgrid harmonic injection active protection system based on code division multiple access, comprising: Multiple inverter interface distributed power supplies are provided, and each inverter interface distributed power supply is equipped with a controller. The controller includes a voltage monitoring unit, a start-up judgment unit, a spread spectrum modulation unit, and a synchronization injection unit. It is used to start synchronously at the zero-crossing point of the fundamental voltage when a fault is detected, and to generate harmonic currents by modulating with Walsh codes that share a common carrier frequency and are mutually orthogonal to inject into the microgrid. Multiple monitoring points are set at both ends of the main feeder and the beginning of the branch feeder. Each monitoring point includes a three-phase current sampling unit, a signal separation unit, a template storage unit, a despreading unit, and a criterion unit. The protection device, connected to the monitoring point, is used to receive trip or lockout commands from the criterion unit and perform corresponding operations. The system executes the method described in any of the above technical solutions.

[0014] In some embodiments, the signal separation unit includes: a Clarke transform module, a second-order generalized integrator positive sequence extraction module, a Park transform module, and a low-pass filter; the despreading unit includes a least-squares despreading module and an energy-difference joint criterion module; the criterion unit includes a main feeder double-ended coefficient difference direction criterion module and a branch feeder single-ended difference sign consistency criterion module.

[0015] To achieve the above objectives, another aspect of this application provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the method described above.

[0016] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described above.

[0017] To achieve the above objectives, another aspect of the embodiments of this application proposes a computer program product, including a computer program that, when executed by a processor, implements the method described above.

[0018] Compared with the prior art, this application has the following beneficial effects: 1) All IIDGs share the same carrier frequency and are distinguished by orthogonal codes, which fundamentally eliminates the problem of non-injection source shunting. There is no need to install harmonic compensation circuits and PCC narrowband filters, resulting in a simple system structure and significantly reduced costs.

[0019] 2) Abundant orthogonal code resources (order can be extended to N, corresponding to N IIDGs). Adding a new IIDG only requires allocating a new orthogonal Walsh codeword, without modifying existing hardware or replanning frequency resources, truly achieving plug-and-play functionality.

[0020] 3) The joint criterion (energy-difference) is used to achieve precise cipher chip synchronization, which can accurately lock the injection window under strong power frequency and harmonic interference. At the same time, SOGI positive sequence extraction and low-pass filtering effectively suppress negative sequence components and high-frequency noise caused by asymmetric faults.

[0021] 4) Two-end criteria and single-end criteria are designed for the main feeder and branch feeder respectively, fully exploring the physical characteristics of the changes in each IIDG coefficient before and after the fault, and exhibiting excellent selectivity and reliability under both symmetrical and asymmetrical faults.

[0022] 5) Each monitoring point independently completes signal separation and despreading, eliminating the need for real-time high-speed communication between monitoring points (only upstream and downstream IIDG sets need to be configured during the calibration phase), thus reducing communication synchronization requirements. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of a 10kV microgrid in an embodiment of this application.

[0024] Figure 2 This is a flowchart of the active protection method for harmonic injection in microgrids based on code division multiple access in the embodiments of this application.

[0025] Figure 3 This is a schematic diagram of the hardware structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0028] Before providing a detailed description of the embodiments of this application, some of the nouns and terms involved in the embodiments of this application will be explained first. The nouns and terms involved in the embodiments of this application are subject to the following interpretations.

[0029] 1) Inverter-Interfaced Distributed Generation (IIDG) refers to distributed generation units that convert DC power into AC power through power electronic converters (inverters) and connect to the distribution network. This type of power source mainly includes photovoltaic, wind power, and energy storage systems. Its core characteristics are "weak inertia" and "controllability," posing new requirements for the power quality, stability, and protection mechanisms of the power grid.

[0030] 2) Walsh code is a synchronous orthogonal code, mainly used in CDMA communication systems to distinguish between channels and users. It is generated based on the Hadamard matrix and can guarantee that signals do not interfere with each other.

[0031] Scholars have proposed a harmonic injection protection method based on Frequency Division Multiple Access (FDMA). The basic principle of this method is that after each IIDG detects a fault, it injects harmonic currents of different frequencies into the microgrid. The direction and segment of the fault are determined by detecting the amplitude changes of the harmonic components at different frequency points. However, this type of scheme has the following inherent drawbacks: 1) Complex hardware and high cost: In order to avoid the shunting effect of non-injection sources (such as other IIDGs, loads, etc.) on harmonics of specific frequencies, it is necessary to install additional harmonic compensation circuits and common point of coupling (PCC) frequency selective filters, which leads to complex system hardware structure and significantly increases engineering implementation costs.

[0032] 2) Limited frequency resources: Each IIDG requires an independent harmonic frequency, but the number of available harmonic frequencies in a microgrid (usually integer multiples of the power frequency) is limited. Furthermore, as the number of IIDGs increases, the frequency spacing must be reduced, which increases the difficulty of filter design and signal separation.

[0033] 3) Poor expansion flexibility: When adding a new IIDG, frequency resources need to be replanned, or even filters need to be replaced or added, which cannot achieve "plug and play".

[0034] 4) Insufficient anti-interference capability: Under asymmetrical faults or non-characteristic harmonic interference, the frequency domain filtering effect decreases, which can easily lead to misjudgment or failure to operate.

[0035] In view of this, this application provides a microgrid harmonic injection active protection method, system, electronic device, storage medium, and program product based on code division multiple access. All inverter interface distributed generation (IIDG) sources share the same carrier frequency, and multi-source differentiation is achieved through mutually orthogonal Walsh codes. The monitoring point performs SOGI positive sequence extraction, Park transformation, and low-pass filtering on the three-phase current to obtain a smooth DC Walsh code signal. During the calibration stage, the individual injection signals of each IIDG are sequentially positioned and the template is extracted using ideal square wave sliding correlation, and then phase alignment and energy normalization are performed to form a complex observation matrix. During the fault protection stage, the harmonic injection coefficients of each IIDG are despread using the complex observation matrix and least squares despreading, and a precise code chip synchronization is achieved using an energy-difference joint criterion. A double-ended coefficient difference direction criterion is used for the main feeder, and a single-ended difference sign consistency criterion is used for the branch feeder. The protection device executes trip or block command according to the criterion result. This solution fundamentally eliminates the problem of non-injection source shunting, requires no additional harmonic compensation circuit, and can adaptively distinguish each IIDG, achieving reliable identification of fault direction and section.

[0036] The 10kV microgrid model on which a code division multiple access microgrid harmonic injection active protection method is based is as follows: Figure 1 As shown. Figure 1 For a typical 10kV microgrid system, the capacity of IIDG1~IIDG4 is uniformly set to 2 MVA. Monitoring points A2 and B1 are configured for the main feeder protection example F1, and monitoring point D4 is configured for the branch feeder protection example F2.

[0037] An active protection method for harmonic injection in microgrids based on code division multiple access (CDMA) specifically includes the following steps: Step 1: Fault detection and injection startup.

[0038] Preferably, the activation criterion specifically includes monitoring whether the amplitude of the positive-sequence voltage or negative-sequence voltage at the IIDG terminal falls outside the specified boundary:

[0039] In the formula, The lower limit coefficient of the positive sequence is used as the trigger criterion. Negative order upper limit coefficient , This is the rated phase voltage amplitude. When... At that time, wait for the current fundamental frequency cycle to end, and then synchronously start harmonic injection at the next fundamental frequency voltage zero crossing point.

[0040] Step 2: Spread spectrum signal generation and injection.

[0041] Preferably, a carrier frequency is selected. The Walsh code is 4 bits long, corresponding to 4 IIDGs, specifically including:

[0042] In the formula, the chip period Chip rate The total duration of the injected signal is The chip symbol "+1" corresponds to a carrier phase of 0°, and "-1" corresponds to a carrier phase of 180°. The mathematical model for the injection current of an IIDG is as follows:

[0043] In the formula, For the first The first IIDG Chip value (+1 or 1), Represents a rectangular pulse function with unit amplitude. This represents the injected current amplitude, which will automatically shut off after injection is complete.

[0044] Step 3: Separate the monitoring point signals.

[0045] Preferably, the three-phase current collected at the monitoring point Performing the Clarke transform specifically includes:

[0046] In the formula, and They are respectively shaft and The components of the axis are used for preprocessing in SOGI forward extraction. and Applying center angular frequency respectively The SOGI integrator has the following continuous-domain transfer function:

[0047] in, Generates a d-axis component in phase with the input. It produces a q-axis component that lags by 90°; This is the damping coefficient, which affects the filter bandwidth and dynamic response speed. When the input is... shaft current At that time, two outputs are obtained. , When the input is shaft current At that time, two outputs are obtained. , The positive-sequence αβ components are calculated based on the instantaneous symmetric component method. A Park transform is performed with a synchronous rotation angle of 400Hz, and a low-pass filter is used to remove residual broadband noise to obtain the Walsh code signal. .

[0048] Step 4: Template generation and normalization.

[0049] Each IIDG was sequentially injected with its own Walsh code modulated 400Hz spread spectrum harmonic current, while the other IIDGs remained silent. The Walsh signals of each IIDG were obtained after signal separation processing at the monitoring points. Preferably, by utilizing the symbol polarity of the central region of the chip to maintain consistency with the ideal square wave, an ideal DC square wave reference corresponding to the IIDG is generated, specifically including:

[0050] In the formula, Number of sampling points per chip For this The Each chip symbol (±1). Calculate the sliding correlation value. Specifically, it includes:

[0051] In relevant values Maximum position This is the precise start time of the chip. And from... Begin, extract The Walsh code signal of the point is used as the original template of this IIDG. Using the start time Calculate the average phase of the original template in the center region of the chip, and then rotate the entire template in reverse:

[0052] In the formula, The central area of ​​the chip, This is the template after phase alignment. Due to differences in line impedance and distance from the monitoring point, the absolute amplitude of the templates varies significantly among different IIDGs. This amplitude difference directly affects the absolute value of the despreading coefficient, thus interfering with the fixed threshold setting of the protection criterion. Therefore, the template after phase alignment... Energy normalization includes:

[0053] After normalization, the template It has a unit norm, that is The four IIDGs constitute a complex observation matrix. .

[0054] Step 5: Joint criteria and multi-IIDG despreading.

[0055] After a fault occurs, the monitoring point can roughly determine the starting time range of the injection window based on the local fault detection time and the phase-locked loop phase information. However, there may be a certain deviation between the estimated starting time and the precise alignment point of the actual chip center region. Preferably, the pseudo-inverse of the complex observation matrix is ​​used. Performing least-squares despreading yields the instantaneous despreading coefficients within this window:

[0056] In the formula, by Capture within the initial 40ms window The signal vector. Definition: Energy Item: By using the despreading coefficient, the window is aligned with the injection segment.

[0057] Difference item: For the main feeder, it is the spatial difference between the coefficients at both ends; for the branch feeder, it is the difference between the coefficients before and after the fault.

[0058] Joint criteria: It simultaneously satisfies the two conditions of "high energy" and "large difference", thereby obtaining a deterministic peak value in complex interference environments and thus achieving precise synchronization.

[0059] In the formula and For the main feeder, these are the instantaneous despreading coefficients for upstream and downstream monitoring points, respectively; for the branch feeder, these are the instantaneous despreading coefficients for single-end monitoring points before and after the fault, respectively. Joint criterion. The maximum value moment is when the window and the chip achieve precise synchronization, and the instantaneous coefficient is output at this moment. .

[0060] Step 6: Protect the execution of the criterion.

[0061] For the main feeder, the despreading coefficients of the upstream and downstream monitoring points are obtained at the precise synchronization time. and downstream Set the upstream IIDG set. and downstream IIDG collection Difference threshold Calculate and judge the difference in coefficients between upstream and downstream, specifically including:

[0062] When a fault occurs between two monitoring points, the upstream IIDG set The generated harmonic current is shunted at the fault point, affecting the upstream monitoring point. The IIDG coefficient of the ensemble is enhanced, and downstream monitoring points The IIDG coefficients of the set weaken; similarly, the downstream IIDG set... The harmonic current coefficient decreases at the upstream monitoring point and increases at the downstream monitoring point, thus indicating a fault. The protection device executes trip or block commands based on the judgment result.

[0063] For branch feeders, use monitoring points Despreading coefficients before and after the fault and Identify fault location by analyzing changing characteristics. Set a difference threshold. Similarly, calculate the difference in coefficients before and after the fault, specifically including:

[0064] When a fault occurs within a branch, the fault point introduces a path to ground at the branch end. All harmonic currents generated by IIDGs flow to this branch, increasing the IIDG coefficients at the monitoring point at the branch's beginning, thus indicating a fault. The protection device executes tripping or blocking commands based on the judgment result.

[0065] The overall flow of the method in this embodiment is as follows: Figure 2 As shown, the specific implementation process is as follows: (1) Initialization phase: The initialization phase is performed after the microgrid planning and construction are completed or after a topology change, and mainly completes the following tasks: First, based on the total number of distributed power sources at the inverter interfaces within the microgrid, a set of mutually orthogonal Walsh codewords is assigned to each IIDG as a spreading sequence. This embodiment uses four IIDGs as an example, employing a 4th-order Walsh code with a code length of 4, and each IIDG has its own unique codeword. Each codeword consists of "+1" and "+1". The codewords are arranged in a specific pattern, with the inner product of the four codewords being zero, ensuring that they do not interfere with each other under strict synchronization conditions. The code length and the number of codewords can be flexibly expanded to 5, 6, 7, etc., depending on the scale of the microgrid.

[0066] Second, monitoring points are installed at key nodes such as both ends of the main feeder and the beginning of branch feeders. These monitoring points are equipped with high-frequency sampling, real-time signal processing, and communication capabilities. The configuration of the monitoring points also includes predefined upstream and downstream IIDG sets for the main feeder, as well as threshold parameters for various protection criteria.

[0067] Third, each IIDG can be enabled by the startup criterion flag. Then, harmonic injection is initiated synchronously at the next fundamental voltage zero-crossing point.

[0068] (2) Calibration stage: The calibration phase involves acquiring the normalized complex response template for each IIDG at each monitoring point, as well as the baseline coefficients for that monitoring point under conditions of no injection and no faults. Calibration can be scheduled to be completed centrally before system commissioning, or it can be automatically repeated periodically to track line aging or topology changes. The main tasks include: First, each IIDG is sequentially injected with its own Walsh code modulated 400Hz spread spectrum harmonic current, while the other IIDGs remain silent and do not receive any injection.

[0069] Second, the monitoring points sequentially perform signal separation processing on the collected three-phase currents to obtain Walsh code signals. .

[0070] Third, the start time of the chip is determined using ideal square wave sliding correlation, and the Walsh code signal is analyzed. Extract the original template The original template was then phase-aligned and normalized to obtain the complex observation matrix. .

[0071] After the calibration phase is completed, each monitoring point has stored the following data: its own complex observation matrix. The data includes the pre-fault reference Walsh code signal, the upstream and downstream IIDG set definitions, and various threshold parameters. These data form the basis for all calculations during the fault protection phase.

[0072] (4) Fault protection phase: The fault protection phase begins when the microgrid is operating normally and continues continuously. This phase consists of seven steps executed sequentially.

[0073] First, the positive and negative sequence voltages at the IIDG grid connection point are monitored in real time, and faults are detected based on the startup criteria. Upon fault confirmation, the IIDG local controller sets its internal fault flag and synchronously triggers injection at the next zero-crossing point. All IIDGs that have detected faults synchronously begin injecting their respective pre-allocated Walsh-modulated 400Hz spread-spectrum harmonic currents. Injection automatically stops upon completion, and the controller resets the injection flag.

[0074] Second, each monitoring point performs the same signal separation processing as the calibration phase on the collected three-phase currents to obtain Walsh code signals. This signal contains contribution information from each IIDG.

[0075] Third, the Walsh code signal is observed using a pre-stored complex observation matrix. Least-squares multi-IIDG despreading is performed to obtain an instantaneous despreading coefficient containing four IIDGs. The instantaneous despreading coefficient of each IIDG represents the contribution intensity of the harmonic current injected by that IIDG after propagation through the line at that monitoring point. Precise synchronization of the monitoring points is achieved using a joint criterion. For double-ended monitoring points on the main feeder, synchronization is achieved using both upstream and downstream signals. For single-ended monitoring points on branch feeders, synchronization is achieved using a pre-stored reference coefficient before the fault and the signal after the fault.

[0076] Fourth, based on the feeder section type where the monitoring point is located, the obtained contribution coefficient modulus values ​​of each IIDG are input into the corresponding protection criteria to determine the fault direction or section and decide whether to issue a trip command. The protection device executes the trip or blocking command according to the criterion result. After the system returns to normal operation, each monitoring point and IIDG returns to the real-time monitoring state. The dynamic update of the reference coefficients also resumes, making full preparations for the next fault event.

[0077] Through the orderly coordination of the initialization, calibration, and fault protection phases described above, this application achieves reliable separation of different IIDG injected signals and accurate identification of fault direction and segment without requiring any additional harmonic compensation circuits. Simulation results show that under symmetrical and asymmetrical faults within the transition resistance range of 0 to 50 ohms, each monitoring point can correctly execute the protection logic, demonstrating excellent selectivity, speed, and plug-and-play capability.

[0078] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-described method. This electronic device can be any smart terminal, including tablet computers, in-vehicle computers, etc.

[0079] It is understood that the content of the above method embodiments is applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0080] Please see Figure 3 , Figure 3 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes: The processor 301 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 302 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 302 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 302 and is called and executed by the processor 301 using the methods described above in the embodiments of this application. Input / output interface 303 is used to implement information input and output; The communication interface 304 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 305 transmits information between various components of the device (e.g., processor 301, memory 302, input / output interface 303, and communication interface 304); The processor 301, memory 302, input / output interface 303, and communication interface 304 are connected to each other within the device via bus 305.

[0081] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described method.

[0082] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0083] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0084] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method.

[0085] It is understood that the content of the above method embodiments is applicable to the embodiments of this program product. The specific functions implemented in the embodiments of this program product are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments. The executable computer program code or "code" used to perform the various embodiments can be written in high-level programming languages ​​such as C, C++, Python, Smalltalk, Java, JavaScript, Visual Basic, Structured Query Language (e.g., Transact-SQL), Perl, or in various other programming languages.

[0086] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0087] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0088] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0089] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0090] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0091] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0092] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0093] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0094] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0095] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0096] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A microgrid harmonic injection active protection method based on code division multiple access, characterized in that, The method includes the following steps: Step S1: Fault detection and injection start-up - The distributed power supply of each inverter interface monitors the grid connection point voltage in real time. When the start-up criteria are met, wait for the current fundamental cycle to end, and start harmonic injection synchronously at the next fundamental voltage zero crossing point. Step S2: Spread spectrum signal generation and injection—All inverter interface distributed power sources share the same carrier frequency, allocate mutually orthogonal Walsh codes as spread spectrum sequences, and use binary phase shift keying modulation to generate Walsh code modulated harmonic currents and inject them into the microgrid; Step S3: Monitoring point signal separation - The monitoring point collects three-phase current, which is extracted in positive sequence by a second-order generalized integrator, Park transform and low-pass filtered to obtain a smooth DC Walsh code signal that reflects the contribution of distributed power sources at each inverter interface. Step S4: Template generation and normalization - Sequentially inject the harmonic current modulated by Walsh code into the distributed power supply of each inverter interface, extract the Walsh code signal through signal separation; use ideal square wave sliding correlation to achieve accurate positioning and extract the template, and then perform phase alignment and energy normalization to form a complex observation matrix. Step S5: Multi-IIDG Despreading and Joint Criterion – Despreading is performed using the least squares method to obtain the instantaneous despreading coefficients of the distributed power sources at each inverter interface; an energy-difference joint criterion is constructed to determine the chip start time, and the instantaneous despreading coefficients of the distributed power sources at each inverter interface are output at the specified time. Step S6: Protection criterion execution—For the main feeder, the direction criterion of the double-ended coefficient difference is used; for the branch feeder, the consistency criterion of the sign of the coefficient difference before and after the fault is used; the protection device executes trip or block command according to the criterion result.

2. The method according to claim 1, characterized in that, The start-up criterion in step S1 is: the positive sequence voltage amplitude at the grid connection point of the distributed power supply at the inverter interface is lower than the positive sequence lower limit coefficient of the rated phase voltage amplitude, or the negative sequence voltage amplitude is higher than the negative sequence upper limit coefficient of the rated phase voltage amplitude.

3. The method according to claim 1, characterized in that, The length of the Walsh code in step S2 is set according to the total number of distributed power sources at the inverter interface in the microgrid. Each distributed power source at the inverter interface is assigned mutually orthogonal Walsh codewords. The chip symbol "+1" corresponds to a carrier phase of 0°, and the chip symbol "-1" corresponds to a carrier phase of 180°.

4. The method according to claim 1, characterized in that, Step S3 specifically includes: The three-phase currents collected from the monitoring points were subjected to Clarke transformation to obtain... Axial components and Axial components; To each Axial components and The axial component is used with a second-order generalized integrator whose center angular frequency is equal to the carrier frequency to obtain the in-phase component and the quadrature component. Calculation of positive sequence based on instantaneous symmetric component method Quantity; Park transform is performed with the synchronous rotational angular frequency equal to the carrier frequency; The residual broadband noise is filtered out by low-pass filtering to obtain a smooth DC Walsh code signal.

5. The method according to claim 1, characterized in that, Step S4, which describes achieving precise positioning using ideal square wave sliding correlation, specifically includes: An ideal DC square wave reference is generated based on the Walsh chip symbols of the current inverter interface distributed power supply. Calculate the sliding correlation value between the ideal DC square wave reference and the Walsh code signal obtained after signal separation; The position of the maximum correlation value is taken as the start time of the chip.

6. The method according to claim 5, characterized in that, The phase alignment in step S4 specifically includes: calculating the average phase of the original template in the central region of the chip using the chip start time, and rotating the entire template in reverse to the average phase; the energy normalization specifically includes: dividing the phase-aligned template by its own norm to obtain a normalized template with unit norm.

7. The method according to claim 1, characterized in that, The energy-difference joint criterion in step S5 is as follows: when both the energy term and the difference term are greater than the first threshold, it is determined that precise synchronization has been achieved; wherein, for the main feeder, the difference term is the spatial difference between the instantaneous despreading coefficients of the two-end monitoring points; for the branch feeder, the difference term is the difference between the instantaneous despreading coefficients of the single-end monitoring point before and after the fault.

8. The method according to claim 1, characterized in that, The direction criterion for the difference between the two ends of the coefficients in step S6 is as follows: at the precise synchronization moment, the despreading coefficients of the upstream monitoring point and the downstream monitoring point are obtained respectively. The difference between the sum of the coefficients of the upstream monitoring point belonging to the distributed power source set of the upstream inverter interface and the sum of the coefficients of the downstream monitoring point belonging to the distributed power source set of the upstream inverter interface, and the difference between the sum of the coefficients of the downstream monitoring point belonging to the distributed power source set of the downstream inverter interface and the sum of the coefficients of the upstream monitoring point belonging to the distributed power source set of the downstream inverter interface, is calculated. When both differences are greater than the set threshold, it is determined that the fault occurs between the two monitoring points.

9. The method according to claim 1, characterized in that, The consistency criterion for the sign of the coefficient difference before and after the fault in step S6 is as follows: obtain the despreading coefficient before and after the fault at the monitoring point at the beginning of the branch feeder, calculate the sign of the coefficient difference of the distributed power supply of each inverter interface before and after the fault, and if the coefficient difference of the distributed power supply of all inverter interfaces is positive, then it is determined that the fault occurred inside the branch feeder.

10. An electronic device, characterized in that, The electronic device includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method according to any one of claims 1 to 9.

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