Capacitive electric energy equalization circuit and battery device based thereon

Abstract

The application relates to a capacitive electric energy equalization circuit, wherein the capacitive electric energy equalization circuit comprises a half-bridge driving circuit, a half-bridge switching circuit, an equalization switching capacitor group and a control unit MCU; the half-bridge switching circuit is electrically connected with n battery cell units and the half-bridge driving circuit; the equalization switching capacitor group is electrically connected with the half-bridge switching circuit; the control unit MCU is electrically connected with a battery management system BMS and the half-bridge driving circuit; the first battery cell unit B1 is subjected to voltage sampling, and the output pulse frequency of the half-bridge driving circuit is controlled based on the obtained sampling voltage, so as to control the start, stop and switching frequency of the capacitive electric energy equalization circuit. Through the application, the control unit MCU can flexibly adjust the equalization working mode according to the battery state, so that the equalization efficiency is ensured and unnecessary energy consumption is reduced.

Description

Technical Field

[0001] This application relates to the field of energy storage technology, and in particular to capacitor-type power balancing circuits and battery devices based thereon. Background Technology

[0002] With the widespread application of battery energy storage systems in areas such as power peak shaving, distributed energy access, and new energy vehicles, the operational performance and lifespan of these systems have gradually become a key focus of the industry. Among these factors, the consistency of battery cells is one of the critical factors affecting the overall performance of a battery energy storage system.

[0003] To mitigate the adverse effects of battery cell inconsistencies on battery pack performance, existing technologies typically employ battery balancing techniques to adjust the state of charge (SOC) of each cell. Depending on the energy processing method, battery balancing techniques generally include passive balancing and active balancing. Passive balancing typically dissipates excess energy from high-capacity cells through resistive dissipation. While its circuit structure is relatively simple, it suffers from low energy utilization, significant heat generation, and low balancing efficiency. In contrast, active balancing utilizes energy storage elements to transfer energy between battery cells, effectively improving energy conversion efficiency and balancing speed.

[0004] Currently, active balancing technologies mainly include inductive, capacitive, and transformer topologies. Among them, capacitive balancing circuits have received considerable attention due to their relatively simple topology and ease of implementation. However, existing capacitive balancing circuits still have certain shortcomings in practical applications. For example, the driving circuits of capacitor switches are usually quite complex, generating additional energy losses during driving and switching, and potentially introducing additional imbalances, thus affecting the balancing effect and overall system efficiency. Therefore, how to reduce the energy consumption of capacitive balancing circuits while ensuring balancing performance has become an urgent technical problem to be solved in this type of balancing technology. Summary of the Invention

[0005] This application provides a capacitor-type power balancing circuit and a battery device based thereon, so as to provide a solution that can realize voltage balancing between battery cells and improve energy conversion efficiency, so that it can be widely used in large and medium-sized energy storage systems.

[0006] In a first aspect, embodiments of this application provide a capacitor-type energy balancing circuit applied to a battery pack. The battery pack comprises n battery cells connected in series, including a first battery cell B1, a second battery cell B2, ..., an nth battery cell Bn, where n ≥ 2. One side of the first battery cell is at a low potential. The battery pack is electrically connected to a battery management system (BMS). The BMS is equipped with an analog front-end sampling module (AFE) for acquiring the sampling voltage of each battery cell in the battery pack. The circuit includes: Half-bridge drive circuit A half-bridge switching circuit is electrically connected to the n battery cell units and electrically connected to the half-bridge drive circuit. A balanced switching capacitor bank is electrically connected to the half-bridge switching circuit, and the balanced switching capacitor bank includes n-1 balanced switching capacitors. The control unit MCU is electrically connected to the battery management system (BMS) and the half-bridge drive circuit. The first cell unit B1 supplies power to the control unit MCU. At the same time, the low voltage detector (LVD) in the control unit MCU samples the voltage of the first cell unit B1, omitting the independent analog-to-digital converter (ADC). Based on the obtained sampled voltage, the control unit MCU controls the output pulse frequency of the output to the half-bridge drive circuit to control the start, stop, and switching frequency of the capacitive power balancing circuit.

[0007] In some embodiments, the control unit MCU is configured to: If the sampling voltage is higher than a first predetermined voltage V1, the output pulse frequency is configured to a first output pulse frequency FH ​​to improve equalization efficiency by increasing the equalization current, shortening the equalization time. Conversely, the output pulse frequency is configured to the second output pulse frequency FL, where the first output pulse frequency FH ​​is greater than the second output pulse frequency FL, in order to reduce the operating power consumption of the equalization circuit.

[0008] In some embodiments, the control unit MCU is further configured to: If the sampling voltage is lower than a second predetermined voltage V2, the output pulse frequency is configured to a second output pulse frequency FL, and the output pulse is output intermittently. The second predetermined voltage V2 is lower than the first predetermined voltage V1. Specifically, the intermittent output can be based on setting a first period t1 and a second period t2. After operating at the second output pulse frequency FL for the first period t1, it enters the second period t2 to shut down, and then cycles through operating and shutting down, that is, cycling through the first period t1 and the second period t2.

[0009] In some embodiments, the control unit MCU is further configured to: If the sampling voltage is lower than a third predetermined voltage V3, the control unit MCU enters standby state STB, where the third predetermined voltage V3 is lower than the second predetermined voltage V2. In standby state, the output pulse is turned off, and the output level is low, further reducing the circuit power consumption of the control unit MCU.

[0010] In some embodiments, when the power supply voltage VDD of the control unit MCU is lower than the low voltage reset voltage LVR (Low Voltage Reset, abbreviated as LVR), the control unit MCU enters the standby state STB (short for Standby), the control unit MCU output pulse is turned off, and the output level is low, further reducing the power consumption of the MCU circuit.

[0011] In some embodiments, the control unit MCU is further configured to: The voltage of n battery cells is sampled by the battery management system (BMS), and the voltage difference between any two battery cells is calculated. The maximum voltage difference of the battery pack is determined based on the maximum value of the voltage difference. Determine whether the maximum voltage difference is higher than a fourth predetermined voltage V4. If so, configure the output pulse frequency to the first output pulse frequency FH. Otherwise, the output pulse frequency is configured to the second output pulse frequency FL.

[0012] In some embodiments, the control unit MCU is further configured to: when the maximum voltage difference is lower than a fifth predetermined voltage V5, the output pulse is turned off and the output level is low, at which time the control unit MCU enters standby state STB.

[0013] In the above embodiment, to reduce the static energy consumption of the half-bridge drive circuit, a power switch for the half-bridge drive circuit is provided, which is electrically connected between the half-bridge drive circuit and the power supply of the half-bridge drive circuit.

[0014] In some embodiments, the half-bridge switching circuit includes: n half-bridge switches are electrically connected in sequence to n battery cell units and electrically connected to the half-bridge drive circuit; The n-1 equalizing switching capacitors are electrically connected to the midpoints of two adjacent half-bridge switches.

[0015] In some embodiments, each of the n half-bridge switches includes a dual N-channel field-effect transistor (NMOS), the high-side output terminal HO of the half-bridge drive circuit is electrically connected to the upper arm of the half-bridge switch, and the low-side output terminal LO of the half-bridge drive circuit is electrically connected to the lower arm of the half-bridge switch.

[0016] In other embodiments, each of the n half-bridge switches comprises: An N-channel field-effect transistor (NMOS) is used as the upper arm of a half-bridge switch. A P-channel field-effect transistor (PMOS) is used as the lower arm of a half-bridge switch. The low-side output terminal LO of the half-bridge drive circuit is electrically connected to the gate of the N-channel field-effect transistor (NMOS) and the gate of the P-channel field-effect transistor (PMOS) in the half-bridge switch.

[0017] In another embodiment, of the n half-bridge switches, The first half-bridge switch includes a dual N-channel field-effect transistor (NMOS); The second to the nth half-bridge switches include: An N-channel field-effect transistor (NMOS) is used as the upper arm of a half-bridge switch. A P-channel field-effect transistor (PMOS) is used as the lower arm of a half-bridge switch. The high-side output terminal HO of the half-bridge drive circuit is electrically connected to the upper arm of the first half-bridge switch and the second half-bridge switch to the gate of the N-channel field-effect transistor (NMOS) and the gate of the P-channel field-effect transistor (PMOS) of the nth half-bridge switch. The low-side output terminal LO of the half-bridge drive circuit is electrically connected to the lower arm of the first half-bridge switch. The sources of each transistor are connected together to form the midpoint of the half-bridge, and corresponding equalization switching capacitors are connected thereto.

[0018] In some embodiments, the half-bridge switching circuit includes: 2(n-1) half-bridge switches are electrically connected to the battery pack and electrically connected to the half-bridge drive circuit; In this configuration, the high-voltage terminal of each half-bridge switch is connected in parallel between the low-voltage terminal of the second cell unit and the high-voltage terminal of the battery pack, and the low-voltage terminal of each half-bridge switch is connected in parallel between the two ends of the first cell unit. The n-1 equalization switching capacitors are electrically connected to the midpoint of 2(n-1) half-bridge switches.

[0019] Based on this, n-1 equalizing switching capacitors are alternately connected in parallel to the two ends of the first cell unit and n-1 other cell units to achieve equalization of the power of the n cells.

[0020] In some embodiments, the capacitor-type power balancing circuit further includes: An auxiliary balancing switching capacitor Cb is connected to both ends of the balancing switching capacitor group to perform power balancing between non-adjacent battery cells.

[0021] In some embodiments, the capacitor-type power balancing circuit further includes: An LED indicator circuit is connected to the output terminal of the half-bridge drive circuit to indicate the power supply and drive output pulses of the half-bridge drive circuit.

[0022] Secondly, embodiments of this application provide a battery device including the capacitor-type power balancing circuit described in the first aspect above.

[0023] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0024] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings: Figure 1 This is a structural block diagram of a capacitor-type power balancing circuit according to an embodiment of this application; Figure 2 This is a schematic diagram of the circuit principle of the capacitor-type power balancing circuit according to an embodiment of this application; Figure 3 This is another circuit principle diagram of the capacitor-type power balancing circuit according to an embodiment of this application; Figure 4 This is another circuit principle diagram of the capacitor-type power balancing circuit according to an embodiment of this application; Figure 5 This is another circuit principle diagram of the capacitor-type power balancing circuit according to an embodiment of this application; Figure 6 This is a schematic diagram of the control principle of a capacitor-type power balancing circuit according to an embodiment of this application; Figure 7 This is another control principle schematic diagram of the capacitor-type power balancing circuit according to an embodiment of this application.

[0025] In the picture: 1. Battery pack; 2. Control unit (MCU); 3. Half-bridge drive circuit; 4. Half-bridge drive circuit power switch; 5. Half-bridge switching circuit; 6. Equalizing switch capacitor bank; 7. Battery Management System (BMS); 51. First half-bridge switch; 52. Second half-bridge switch; 53. Third half-bridge switch; 54. Fourth half-bridge switch. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this application clearer, the application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application.

[0027] Obviously, the accompanying drawings described below are merely some examples or embodiments of this application. Those skilled in the art can apply this application to other similar scenarios based on these drawings without any inventive effort. Furthermore, it is understood that although the efforts made in this development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, any changes to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0028] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0029] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application refers to two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship. The terms "first," "second," and "third" used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.

[0030] Figure 1 This is a block diagram of a capacitor-type power balancing circuit according to an embodiment of this application. (Refer to...) Figure 1 As shown in the figure, this application provides a capacitor-type power balancing circuit for battery packs.

[0031] The battery pack comprises n energy storage cells connected in series, including a first cell B1, a second cell B2, ..., an nth cell Bn, where n ≥ 2. One side of the first cell is at a low potential. The battery pack is electrically connected to a battery management system (BMS). The BMS is equipped with an analog front-end sampling module (AFE) to acquire the sampling voltage of each cell in the battery pack. This allows the BMS to perform overcharge, over-discharge, and over-temperature protection on the lithium battery pack, ensuring that the battery pack operates within a safe range. The circuit includes: Half-bridge drive circuit A half-bridge switching circuit is electrically connected to the n battery cell units and electrically connected to the half-bridge drive circuit. The equalizing switched capacitor bank is electrically connected to the half-bridge switching circuit, and the equalizing switched capacitor bank includes n-1 equalizing switched capacitors, such as... Figure 2 As shown, when two battery cell units are configured, the equalization switching capacitor bank includes capacitor CB, which is connected between the first battery cell unit B1 and the second battery cell unit; in another embodiment, as... Figure 3 As shown, when four battery cell units are set, the equalization switching capacitor group includes, but is not limited to, adjacent series-connected equalization switching capacitors CB1, CB2 and CB3. The control unit MCU is electrically connected to the battery management system (BMS) and the half-bridge drive circuit. The first cell unit B1 supplies power to the control unit MCU. At the same time, the low voltage detector (LVD) in the control unit MCU samples the voltage of the first cell unit B1, omitting the independent analog-to-digital converter (ADC). Based on the obtained sampled voltage, the control unit MCU controls the output pulse frequency of the output to the half-bridge drive circuit to control the start, stop, and switching frequency of the capacitive power balancing circuit.

[0032] Based on the above structure, this embodiment of the application achieves precise control of the charging and discharging path of the equalization switching capacitor through the cooperation of the half-bridge drive circuit and the half-bridge switching circuit, making the energy transfer process more stable and controllable, thereby improving the equalization accuracy and consistency. The control unit MCU is powered by the first cell unit B1 and completes voltage sampling through the built-in low voltage detector LVD, omitting the independent ADC module, reducing the system hardware complexity and cost, while reducing the number of peripheral circuits and improving the system reliability and integration. By adjusting the output pulse frequency, the equalization speed is dynamically controlled, enabling the control unit MCU to flexibly adjust the equalization working mode according to the battery status, reducing unnecessary energy consumption while ensuring equalization efficiency and improving overall operating efficiency.

[0033] Furthermore, this solution is easy to integrate with existing battery management systems (BMS), and can achieve active balancing while meeting overcharge, over-discharge, and over-temperature protection requirements, thereby enhancing battery pack safety and lifespan and improving the system's market competitiveness.

[0034] In some embodiments, the half-bridge switching circuit includes: n half-bridge switches are electrically connected sequentially to n battery cell units, and are also electrically connected to the half-bridge drive circuit; for example... Figure 3 As shown, the lower arm of the first half-bridge switch 51 is connected to the first battery cell unit B1, the upper arm of the first half-bridge switch 51 and the upper arm of the second half-bridge switch 52 are connected to the second battery cell unit B2, and so on.

[0035] The n-1 equalizing switching capacitors are electrically connected to the midpoints of two adjacent half-bridge switches.

[0036] In some embodiments, reference Figure 2 , Figure 3As shown, among the n half-bridge switches, each half-bridge switch includes a dual N-channel field-effect transistor (NMOS). The high-side output terminal HO of the half-bridge drive circuit is electrically connected to the upper arm of the half-bridge switch, and the low-side output terminal LO of the half-bridge drive circuit is electrically connected to the lower arm of the half-bridge switch.

[0037] In actual operation, the half-bridge drive circuit alternately drives the HO and LO terminals to output control signals according to the pulse signals output by the control unit MCU, causing the upper arm NMOS and the lower arm NMOS to turn on or off according to a predetermined timing sequence. By reasonably setting the dead time, the simultaneous conduction of the upper and lower arm NMOS is avoided, thus preventing shoot-through current and ensuring safe circuit operation.

[0038] During the switching process, by controlling the conduction state of different half-bridge switches, the midpoint potential of each cell is switched between different cells, thereby driving the equalization switching capacitor to charge and discharge between different voltages, realizing the transfer of charge between cells.

[0039] refer to Figure 2 As shown, the control unit MCU controls the half-bridge drive circuit by outputting pulse PWM, causing the half-bridge drive circuit to drive the upper and lower arms of the half-bridge switch to conduct alternately: like Figure 2 When the output pulse PWM is high, the high-side output HO of the half-bridge drive circuit is high and the low-side output LO is low, which turns on the upper arm QH1 of the first half-bridge switch and the upper arm QH2 of the second half-bridge switch, turns off the lower arm QL1 of the first half-bridge switch and the lower arm QL2 of the second half-bridge switch, and connects the equalization switching capacitor CB in parallel across the two ends of the second battery cell B2. Conversely, when the output pulse PWM is low, the high-side output HO of the half-bridge drive circuit is low and the low-side output LO is high, which turns on the lower arm QL1 of the first half-bridge switch and the lower arm QL2 of the second half-bridge switch, turns off the upper arm QH1 of the first half-bridge switch and the upper arm QH2 of the second half-bridge switch, and connects the equalization switching capacitor CB in parallel across the two ends of the first battery cell B1. During the alternating conduction process, the control equalization switch capacitor is connected in parallel to the corresponding half-bridge switch connected cell unit to exchange energy between adjacent cell units, and the equalization switch capacitor is used to average the electrical energy between adjacent cell units.

[0040] Similarly, refer to Figure 3 As shown, the control unit MCU controls the half-bridge drive circuit by outputting pulse PWM, causing the half-bridge drive circuit to drive the upper and lower arms of the half-bridge switch to conduct alternately: like Figure 3When the output pulse PWM is high, the high-side output HO of the half-bridge drive circuit is high and the low-side output LO is low, which turns on the upper arm QH1 of the first half-bridge switch 51, the upper arm QH2 of the second half-bridge switch 52, the upper arm QH3 of the third half-bridge switch 53 and the upper arm QH4 of the fourth half-bridge switch 54. At the same time, the lower arm QL1 of the first half-bridge switch 51, the lower arm QL2 of the second half-bridge switch 52, the lower arm QL3 of the third half-bridge switch 53 and the lower arm QL4 of the fourth half-bridge switch 54 are turned off. At this time, the equalizing switching capacitors CB1, CB2 and CB3 are connected in parallel to the two ends of the second battery cell B2, the third battery cell B3 and the fourth battery cell B4 respectively. Conversely, when the output pulse PWM is low, the high-side output HO of the half-bridge drive circuit is low and the low-side output LO is high, causing the lower arm QL1 of the first half-bridge switch 51, the lower arm QL2 of the second half-bridge switch 52, the lower arm QL3 of the third half-bridge switch 53, and the lower arm QL4 of the fourth half-bridge switch 54 to be turned on, while the upper arm QH1 of the first half-bridge switch 51, the upper arm QH2 of the second half-bridge switch 52, the upper arm QH3 of the third half-bridge switch 53, and the upper arm QH4 of the fourth half-bridge switch 54 are turned off. At this time, the equalizing switching capacitors CB1, CB2, and CB3 are connected in parallel across the first battery cell B1, the second battery cell B2, and the third battery cell B3, respectively. During the alternating conduction process, the control equalization switching capacitors CB1, CB2, and CB3 are alternately connected in parallel to the corresponding half-bridge switch connected cell units. When there is a voltage difference between adjacent cell units, the equalization switching capacitors continuously charge and discharge to generate equalization current, making the voltage of adjacent cell units tend to be consistent.

[0041] In other embodiments, each of the n half-bridge switches comprises: An N-channel field-effect transistor (NMOS) is used as the upper arm of a half-bridge switch. A P-channel field-effect transistor (PMOS) is used as the lower arm of a half-bridge switch. The low-side output terminal LO of the half-bridge drive circuit is electrically connected to the gate of the N-channel MOSFET (NMOS) and the gate of the P-channel MOSFET (PMOS) in the half-bridge switch. When the LO output is high, the NMOS gate-source voltage is positive, turning the NMOS on; simultaneously, the PMOS gate-source voltage approaches zero or is positive, turning the PMOS off, thus achieving a state where the upper arm is on and the lower arm is off. When the LO output is low, the NMOS gate-source voltage drops to the off state, while the PMOS gate-source voltage is negative, turning the PMOS on, thus achieving a state where the lower arm is on and the upper arm is off.

[0042] Through the aforementioned complementary conduction, the midpoint potential of the half-bridge is switched between high and low potentials, thereby cooperating with the balancing switching capacitor to complete the switching of the charging and discharging paths and realize energy transfer between cells. By adopting a half-bridge structure combining NMOS and PMOS, the upper and lower arm switches can achieve complementary control through a single drive signal, reducing the number of drive signals, simplifying the control logic, and improving dead-time immunity.

[0043] In another embodiment, reference is made to... Figure 5 As shown, among the n half-bridge switches, The first half-bridge switch includes a dual N-channel field-effect transistor (NMOS); The second to the nth half-bridge switches include: An N-channel field-effect transistor (NMOS) is used as the upper arm of a half-bridge switch. A P-channel field-effect transistor (PMOS) is used as the lower arm of a half-bridge switch. The high-side output terminal HO of the half-bridge drive circuit is electrically connected to the upper arm of the first half-bridge switch and the second half-bridge switch to the gate of the N-channel field-effect transistor (NMOS) and the gate of the P-channel field-effect transistor (PMOS) of the nth half-bridge switch. The low-side output terminal LO of the half-bridge drive circuit is electrically connected to the lower arm of the first half-bridge switch. The sources of each transistor are connected together to form the midpoint of the half-bridge, and corresponding equalization switching capacitors are connected thereto.

[0044] In the above embodiment, the first half-bridge switch uses two N-channel field-effect transistors (NMOS) to form the upper and lower arms. This structure is suitable for the lowest potential side of the battery pack (i.e., the first cell unit B1 side), where the source reference ground potential is low, facilitating the control of the lower arm NMOS using a low-side drive method. Simultaneously, the upper arm NMOS is driven through the high-side output terminal HO, achieving stable and reliable switching control. By using a combination of NMOS and PMOS structures for the remaining half-bridge switches, the complexity of the high-side drive circuit is reduced, the control logic is simplified, and dead-time immunity is improved.

[0045] In another embodiment, the half-bridge switching circuit of this application includes: 2(n-1) half-bridge switches, electrically connected to the battery pack and electrically connected to the half-bridge drive circuit; In this configuration, the high-voltage terminal of each half-bridge switch is connected in parallel between the low-voltage terminal of the second cell unit and the high-voltage terminal of the battery pack, and the low-voltage terminal of each half-bridge switch is connected in parallel between the two ends of the first cell unit. The n-1 equalizing switching capacitors are electrically connected to the midpoint of 2(n-1) half-bridge switches, as follows: Figure 4As shown, a balancing capacitor CB2 is electrically connected between the midpoints of half-bridge switches QL21 and QH21 and the midpoints of half-bridge switches QL22 and QH22. A balancing capacitor CB3 is electrically connected between the midpoints of half-bridge switches QL31 and QH31 and the midpoints of half-bridge switches QL32 and QH32. And so on. A dedicated balancing capacitor CB1 is connected in parallel across the two ends of the first cell unit B1. By increasing the number of half-bridge switches, a multi-path energy transmission network is formed, thereby improving balancing efficiency and flexibility.

[0046] refer to Figure 4 As shown, the control unit MCU controls the half-bridge drive circuit by outputting pulse PWM, causing the half-bridge drive circuit to drive the upper and lower arms of the half-bridge switch to conduct alternately: When the output pulse PWM is high, the high-side output HO of the half-bridge drive circuit is high and the low-side output LO is low, which turns on the upper arms QH21, QH22, QH31, QH32, QH41 and QH42 of multiple half-bridge switches, and turns off the lower arms QL21, QL22, QL31, QL32, QL41 and QL42 of multiple half-bridge switches. At this time, the equalization switching capacitors CB2, CB3 and CB4 are connected in parallel across the second battery cell B2, the third battery cell B3 and the fourth battery cell B4. Conversely, when the output pulse PWM is low, the high-side output HO of the half-bridge drive circuit is low and the low-side output LO is high, causing the lower arms QL21, QL22, QL31, QL32, QL41 and QL42 of multiple half-bridge switches to be turned on, and the upper arms QH21, QH22, QH31, QH32, QH41 and QH42 of multiple half-bridge switches to be turned off. At this time, the equalization switching capacitors CB2, CB3 and CB4 are connected in parallel across the first battery cell unit B1 and its dedicated equalization switching capacitor CB1. During the alternating conduction process, the control equalization switching capacitors CB2, CB3, and CB4 are alternately connected in parallel to the corresponding half-bridge switch connected cell units. When there is a voltage difference between the first cell unit B1 and the second cell unit B2, the third cell unit B3, and the fourth cell unit B4, the equalization switching capacitors continuously charge and discharge to generate an equalization current, making it consistent with the voltage of the first cell unit B1, further improving the accuracy and efficiency of simultaneous equalization of non-adjacent cell units.

[0047] Based on this, n-1 equalizing switching capacitors are alternately connected in parallel to the two ends of the first cell unit and n-1 other cell units to achieve equalization of the power of the n cells.

[0048] Based on the above structure, the capacitor-type power balancing circuit of this application is used to achieve power balance among battery cells, so that all battery cells reach the charging and discharging cutoff conditions as synchronously as possible, thereby bringing the battery pack close to its theoretical maximum capacity, improving the charging and discharging capacity of the battery pack, and extending the battery pack life.

[0049] In some embodiments, reference Figure 3 As shown, the capacitor-type power balancing circuit also includes: an auxiliary balancing switching capacitor Cb and an LED indicator circuit. The auxiliary balancing switching capacitor Cb is connected in parallel across the two ends of the balancing switching capacitor group to perform power balancing between non-adjacent battery cells. The LED indicator circuit is connected to the output terminal of the half-bridge drive circuit to indicate the power supply and drive output pulse of the half-bridge drive circuit.

[0050] By setting up an LED indicator circuit, users can intuitively observe the working status of the half-bridge drive circuit without the need for an oscilloscope or other testing equipment. This helps to quickly determine whether the equalization circuit is operating normally, improves maintainability, and increases debugging efficiency.

[0051] Optionally, the control unit MCU is a microampere-level low-power microcontroller that operates at a low clock frequency ILRC (Internal Low-Speed ​​RC Oscillator). The frequency of its output pulse is a division of the clock frequency ILRC, and it adopts period mode with a duty cycle of 50%.

[0052] For example, but not limited to, the chip models used in the above half-bridge driver circuit can be Infineon's IR2183, IR2184, 2ED2103, 2ED2183, etc.

[0053] In another embodiment, the output pulse frequency can be fixed or obtained by voltage sampling modulation of the battery pack; in another embodiment, a control unit (MCU) with ADC input can be used, with one end of the sampled voltage electrically connected to the positive terminal of the first cell unit B1.

[0054] In some embodiments, the control unit MCU of this application embodiment can be integrated into the controller of the battery management system BMS.

[0055] In some embodiments, reference Figure 6 As shown, the control unit MCU is configured as follows: If the sampling voltage VS is higher than a first predetermined voltage V1, the output pulse frequency f is configured to the first output pulse frequency FH ​​to improve the equalization efficiency by increasing the equalization current, shortening the equalization time. In this embodiment, the reference value of the first predetermined voltage V1 is configured as the nominal voltage of the cell unit, the cell unit platform voltage, or the voltage value VCO corresponding to the SOC being in the range of 50% to 80%. The nominal voltage is the rated voltage of the cell unit under standard conditions, and the SOC is the percentage of the remaining capacity of the battery. The voltage change is relatively smooth in the range of 50% to 80% of the SOC, which can more stably reflect that the battery is in a medium-high charge state. At this time, the battery voltage is close to the end of the charging platform or the beginning of the discharging platform, and has the characteristics of the platform area. Conversely, the output pulse frequency f is configured as the second output pulse frequency FL, and the first output pulse frequency FH ​​is greater than the second output pulse frequency FL, so as to reduce the operating power consumption of the equalization circuit.

[0056] In the above embodiments, the value of the first output pulse frequency FH ​​is any value between 10kHz and 60kHz, and the value of the second output pulse frequency FL can be configured as a preset ratio of the first output pulse frequency FH, such as 1 / 2, 1 / 4 or 1 / 8.

[0057] When the sampled voltage VS is higher than the first predetermined voltage V1, it indicates that the first cell unit B1 is in a high energy state and has a strong energy transfer capability. At this time, the control unit MCU sets the output pulse frequency f to a higher first output pulse frequency FH, so that the half-bridge drive circuit drives the half-bridge switching circuit at a higher frequency, thereby accelerating the charging and discharging cycle frequency of the equalization switching capacitor, improving the charge transfer rate, and achieving rapid equalization. When the sampled voltage VS is lower than or equal to the first predetermined voltage V1, it indicates that the cell energy level is low or in the non-plateau region. If high-frequency operation continues, it may lead to decreased efficiency or unnecessary energy loss. At this time, the control unit MCU switches the output pulse frequency f to a lower second output pulse frequency FL to reduce switching losses and drive power consumption, while maintaining basic equalization function.

[0058] Based on this, the first output pulse frequency FH ​​and the second output pulse frequency FL are used to enable the equalization circuit to automatically adjust the operating frequency under different battery conditions, thereby achieving adaptive control. When the cell voltage is high, a high-frequency equalization strategy is adopted, which significantly improves the equalization current and energy transfer efficiency, shortens the equalization time, and improves the response speed. When the cell voltage is low or in a non-ideal equalization range, the switching frequency is automatically reduced, which effectively reduces the switching losses of the switching devices and the power consumption of the drive circuit, thereby reducing the overall energy consumption and improving the energy utilization rate.

[0059] In some embodiments, the aforementioned control unit MCU is further configured to: If the sampling voltage VS is lower than a second predetermined voltage V2, the output pulse frequency f is configured to a second output pulse frequency FL, and the output pulse is output intermittently. Since the second predetermined voltage V2 is lower than the first predetermined voltage V1, an intermittent oscillation mode is entered. Specifically, the intermittent output can be based on setting a first period t1 and a second period t2. The system operates at the second output pulse frequency FL for the first period t1, then enters a shutdown period t2, and so on, cycling through the first period t1 and the second period t2.

[0060] Specifically, the MCU controls the equalization process according to preset time parameters as follows: During the first cycle t1, the half-bridge drive circuit drives the half-bridge switching circuit according to the second output pulse frequency FL, enabling the equalization switching capacitor bank to perform normal charging and discharging energy transfer; During the second cycle t2, the MCU stops outputting drive pulses, causing the half-bridge drive circuit to be in the off state, and the equalization process is paused. The above working cycle alternates between t1 and t2 to achieve an intermittent operation mode of working and stopping.

[0061] This method reduces energy consumption and device losses caused by continuous switching under low voltage conditions, while avoiding excessive energy extraction from low-charge cells, thus achieving safer and more reasonable balanced control. No complex hardware is required; intermittent control can be achieved solely through software strategies, reducing system implementation costs and facilitating parameter adjustment and functional expansion.

[0062] In some embodiments, the control unit MCU is further configured to: If the sampled voltage VS is lower than a third predetermined voltage V3, it indicates that the battery is in an extremely low energy state. The control unit MCU then enters standby mode (STB) and ceases equalization control. The third predetermined voltage V3 is lower than the second predetermined voltage V2. In standby mode, the output pulse is turned off, and the output level is low, significantly reducing the static power consumption of the control unit MCU and peripheral circuits, thereby reducing energy consumption and improving overall energy utilization efficiency. This keeps the half-bridge switching circuit completely off, the equalization switching capacitor bank stops working, and the entire capacitor-type power equalization circuit enters a low-power operation mode, retaining only necessary monitoring functions or completely shutting down unnecessary modules, thus avoiding additional load under low voltage conditions.

[0063] In this embodiment, the reference value of the third predetermined voltage can be configured as the voltage value VCO corresponding to the SOC being in the range of 5% to 10%. This voltage is usually higher than the over-discharge protection voltage of the cell unit, so that control measures can be taken in advance before entering the protection zone to avoid triggering the hardware-level protection mechanism and improve the stability and reliability of operation.

[0064] Based on the aforementioned multiple predetermined voltages, a segmented output pulse control is constructed, which allows the circuit to gradually reduce its operating intensity according to the battery voltage state, and completely stop equalization control at extremely low voltages, thereby achieving refined energy management.

[0065] In some embodiments, when the power supply voltage VDD of the control unit MCU is lower than the low-voltage reset voltage LVR, the control unit MCU enters standby state STB, the control unit MCU output pulse is turned off, and the output level is low, so as to realize automatic shutdown and low power consumption operation when the power supply of the control unit is insufficient, and further reduce the power consumption of the MCU circuit.

[0066] This embodiment complements the voltage hierarchical control based on the first predetermined voltage V1, the second predetermined voltage V2, and the third predetermined voltage V3: the former achieves hierarchical adjustment based on logic control, while the latter achieves forced protection based on the power supply voltage, thereby constructing a dual safety guarantee system.

[0067] In some embodiments, the control unit MCU is configured with I 2 C communication interface, this interface is connected to the battery management system (BMS) I. 2 The C-type communication interface is connected to obtain the voltage information of each cell in the battery pack.

[0068] In some embodiments, reference Figure 7 As shown, the control unit MCU is also configured to: The battery management system (BMS) samples the voltage of n battery cells and calculates the voltage difference between any two battery cells. Based on the maximum value of the voltage difference, the maximum voltage difference ΔV of the battery pack is determined. This maximum voltage difference ΔV reflects the worst case of internal consistency of the battery pack and is used to determine whether enhanced equalization is needed. Determine whether the maximum voltage difference ΔV is higher than a fourth predetermined voltage V4. If so, configure the output pulse frequency f to the first output pulse frequency FH. Otherwise, the output pulse frequency f is configured as the second output pulse frequency FL. In this embodiment, the reference value of the fourth predetermined voltage V4 is configured as the nominal voltage of the cell unit, the cell unit platform voltage, or the voltage value VCO corresponding to a SOC in the range of 50% to 80%.

[0069] In the above embodiments, when the maximum voltage difference ΔV is higher than the fourth predetermined voltage V4, it indicates that there is a significant inconsistency within the battery pack. At this time, the control unit MCU configures the output pulse frequency f to the first output pulse frequency FH, causing the half-bridge drive circuit to drive the half-bridge switching circuit at a higher frequency. This accelerates the charging and discharging cycle of the equalizing switching capacitor bank, thereby enhancing energy transfer capability and rapidly reducing the voltage difference. When the maximum voltage difference ΔV is lower than or equal to the fourth predetermined voltage V4, it indicates that the battery pack has good consistency and does not require high-intensity equalization operation. At this time, the control unit MCU adjusts the output pulse frequency f to the second output pulse frequency FL to reduce power consumption while maintaining necessary equalization capability.

[0070] This control logic can work in conjunction with the aforementioned hierarchical control based on the first predetermined voltage V1, the second predetermined voltage V2, and the third predetermined voltage V3 to form a two-dimensional control system combining individual voltage and group voltage difference, thereby achieving more precise and efficient balanced regulation.

[0071] In some embodiments, the control unit MCU is further configured to: when the maximum voltage difference ΔV is lower than a fifth predetermined voltage V5, turn off the output pulse and output a low level. At this time, the control unit MCU enters a standby state STB, realizing the shutdown of equalization when the battery pack is generally balanced or in a low energy state, effectively reducing the power consumption of the control unit MCU and the drive circuit, thereby extending the battery pack's battery life. In this embodiment, the reference value of the fifth predetermined voltage can be configured as the voltage value VCO corresponding to a SOC in the range of 5% to 10%, or the over-discharge protection voltage of the cell unit. In other embodiments, it can be adjusted according to different battery systems or application requirements, for example, expanded to the SOC range of 3% to 15%.

[0072] In addition, in order to reduce energy consumption, refer to Figure 2 , Figure 3 As shown, the control unit MCU is also provided with an enable switch input terminal EN and a status output terminal STA; Among them, reference Figure 2 As shown, the internal bias resistor switch of the enable switch input terminal EN is set to be neither pulled up nor pulled down, and is connected to the power supply terminal and ground terminal of the control unit MCU after being connected to a single-pole double-throw switch. Thus, the output pulse of the output pulse terminal can be manually turned off by using the single-pole double-throw switch, so that the control unit MCU enters a sleep state, that is, a standby state STB, thereby realizing the forced shutdown function under manual intervention. This method can achieve rapid shutdown without relying on software control, enhancing controllability.

[0073] The status output terminal STA is electrically connected to the half-bridge drive circuit via a power switch, or directly to the half-bridge drive circuit. When the control unit MCU shuts off the output pulse, the power supply to the half-bridge drive circuit is turned off to reduce circuit power consumption. (Reference) Figure 3 As shown, when the status output terminal STA is directly connected to the half-bridge driver circuit for its switching control, the half-bridge driver chip with ultra-low power SD function saves the power switch setting of the half-bridge driver circuit and simplifies the circuit structure.

[0074] In the above embodiments, when the control unit MCU shuts off its output pulse, enters standby state STB, or determines that equalization is not needed, if the half-bridge drive circuit remains powered on, it will still consume static current and cause additional energy consumption even if it does not output a valid drive signal. To reduce the static energy consumption of the half-bridge drive circuit, a power switch for the half-bridge drive circuit is provided, which is electrically connected between the half-bridge drive circuit and its power supply.

[0075] For details, please refer to Figure 2 As shown, the power switch of the half-bridge drive circuit includes a pair of complementary switching transistors, which can be transistors or MOSFETs. For example, but not limited to, it can include an N-type transistor and a P-type transistor. The N-type transistor (NMOS) is connected to the status output terminal or pulse output terminal of the control unit MCU, or via a voltage detection circuit, to the status output terminal or pulse output terminal of the control unit MCU. When the control unit MCU outputs a pulse, its status output terminal or pulse output terminal will turn on the N-type transistor, thereby driving the P-type transistor to turn on, connecting the power supply to the half-bridge drive circuit, and enabling the circuit to enter normal operation. Conversely, when the output pulse of the control unit MCU is turned off, the status output terminal, pulse output terminal, or voltage detection circuit will turn off the N-type transistor, driving the P-type transistor to turn off, and disconnecting the power supply to the half-bridge drive circuit.

[0076] Figure 2 Taking the N-type transistor NMOS connected to the status output terminal STA as an example, the P-type transistor PMOS is connected between the power supply terminal VCC and the power supply of the half-bridge drive circuit. When the control unit MCU outputs a pulse, its status output terminal STA outputs a high level, which turns on the N-type transistor NMOS and drives the P-type transistor PMOS to turn on. After turning on, the power supply terminal VCC of the half-bridge drive circuit is connected to its power supply, so that the half-bridge drive circuit is powered and controlled by the control unit MCU to perform power balancing control. When the control unit MCU outputs a pulse and turns off, its status output terminal STA outputs a low level, which turns off the N-type transistor NMOS and the P-type transistor PMOS, so that the half-bridge drive circuit is de-energized.

[0077] By placing a power switch between the half-bridge driver circuit and its power supply, the half-bridge driver circuit can be completely powered off when not in operation, thereby significantly reducing static power consumption and standby power consumption. By controlling the power supply level of the half-bridge driver circuit, rather than just shutting it down at the signal level, continuous power consumption by the bias circuit and reference circuit inside the driver chip can be avoided, improving energy efficiency.

[0078] In another embodiment, the enable switch input terminal EN can be connected to the output terminal of the control unit MCU to replace the single-pole double-throw switch.

[0079] In some of these embodiments, reference continues. Figure 2 As shown, the enable switch input terminal EN can also be electrically connected to the over-discharge output terminal DSG of the analog front-end sampling module AFE. When the analog front-end sampling module AFE detects over-discharge of the battery cell, it controls the control unit MCU to enter a sleep state via the enable switch input terminal EN to reduce power consumption.

[0080] When the over-amplifier output terminal DSG outputs a high-level signal, this high-level signal pulls up the enable switch input terminal EN, which is clamped to the power supply terminal of the control unit MCU by the diode, causing the control unit MCU to enter the working state; when the over-amplifier output terminal DSG outputs a low-level signal, or when the enable switch input terminal EN is closed to the ground terminal, the control unit MCU enters the standby state STB.

[0081] In addition, this application also provides a battery device, including a capacitor-type power balancing circuit as described in the above embodiments.

[0082] It should be noted that the above modules can be functional modules or program modules, and can be implemented through software or hardware. For modules implemented through hardware, the above modules can reside in the same processor; or the above modules can be located in different processors in any combination.

[0083] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A capacitor-type energy balancing circuit, applied to a battery pack, the battery pack comprising n battery cells connected in series, including a first battery cell B1, a second battery cell B2, ..., an nth battery cell Bn, where n ≥ 2, the battery pack being electrically connected to a battery management system (BMS), characterized in that... The circuit includes: Half-bridge drive circuit A half-bridge switching circuit is electrically connected to the n battery cell units and electrically connected to the half-bridge drive circuit. A balanced switching capacitor bank is electrically connected to the half-bridge switching circuit, and the balanced switching capacitor bank includes n-1 balanced switching capacitors. The control unit MCU is electrically connected to the battery management system (BMS) and the half-bridge drive circuit. It samples the voltage of the first cell unit B1 and controls the output pulse frequency of the control unit MCU to the half-bridge drive circuit based on the obtained sampled voltage.

2. The capacitor-type power balancing circuit according to claim 1, characterized in that, The control unit (MCU) is configured as follows: If the sampling voltage is higher than a first predetermined voltage V1, then the output pulse frequency is configured to a first output pulse frequency FH: Conversely, the output pulse frequency is configured as the second output pulse frequency FL, where the first output pulse frequency FH ​​is greater than the second output pulse frequency FL.

3. The capacitor-type power balancing circuit according to claim 2, characterized in that, The control unit MCU is also configured to: If the sampling voltage is lower than a second predetermined voltage V2, the output pulse frequency is configured to a second output pulse frequency FL, and the output pulse is output intermittently, wherein the second predetermined voltage V2 is lower than the first predetermined voltage V1.

4. The capacitor-type power balancing circuit according to claim 3, characterized in that, The control unit MCU is also configured to: If the sampling voltage is lower than a third predetermined voltage V3, the control unit MCU enters standby state STB, where the third predetermined voltage V3 is lower than the second predetermined voltage V2.

5. The capacitor-type power balancing circuit according to any one of claims 2 to 4, characterized in that, The control unit MCU is also configured to: The voltage of n battery cells is sampled, and the voltage difference between any two battery cells is calculated. The maximum voltage difference of the battery pack is determined based on the maximum value of the voltage difference. Determine whether the maximum voltage difference is higher than a fourth predetermined voltage V4. If so, configure the output pulse frequency to the first output pulse frequency FH. Otherwise, the output pulse frequency is configured to the second output pulse frequency FL.

6. The capacitor-type power balancing circuit according to claim 5, characterized in that, The half-bridge switching circuit includes: n half-bridge switches are electrically connected in sequence to n battery cell units and electrically connected to the half-bridge drive circuit; The n-1 equalizing switching capacitors are electrically connected to the midpoints of two adjacent half-bridge switches.

7. The capacitor-type power balancing circuit according to claim 5, characterized in that, The half-bridge switching circuit includes: 2(n-1) half-bridge switches are electrically connected to the battery pack and electrically connected to the half-bridge drive circuit; In this configuration, the high-voltage terminal of each half-bridge switch is connected in parallel between the low-voltage terminal of the second cell unit and the high-voltage terminal of the battery pack, and the low-voltage terminal of each half-bridge switch is connected in parallel between the two ends of the first cell unit. The n-1 equalization switching capacitors are electrically connected to the midpoint of 2(n-1) half-bridge switches.

8. The capacitor-type power balancing circuit according to claim 6 or 7, characterized in that, Also includes: An auxiliary equalizing switching capacitor Cb is connected to both ends of the equalizing switching capacitor group.

9. The capacitor-type power balancing circuit according to claim 8, characterized in that, Also includes: The LED indicator circuit is connected to the output terminal of the half-bridge drive circuit.

10. A battery device, characterized in that, It includes a battery pack and a capacitor-type power balancing circuit as described in any one of claims 1 to 9.

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