Dual input power supply circuit

Abstract

The application relates to the technical field of direct current conversion, and discloses a double-input power supply power supply circuit which comprises a plurality of voltage output ends, a direct current-direct current conversion circuit which comprises a plurality of voltage output branches, each voltage output branch supplies power to a corresponding voltage output end, a plurality of linear voltage stabilizing circuits, each linear voltage stabilizing circuit supplies power to a corresponding voltage output end, and the double-input power supply power supply circuit works in a direct current-direct current conversion power supply mode or a linear voltage stabilizing power supply mode based on a power supply switching signal. The application preferentially supplies power to the heaviest load when linear voltage stabilizing is switched to direct current-direct current conversion, and / or the direct current-direct current converter output is gradually reduced after the load is jointly borne when direct current-direct current conversion is switched to linear voltage stabilizing, the output voltage undershoot problem in the power supply switching process is eliminated from the root, the rear-stage circuit is ensured to stably work, and the normal state is restored after the switching is completed, so that the steady-state performance of the system is not affected.

Description

Technical Field

[0001] This invention relates to the field of DC-DC conversion technology, and more specifically to a dual-input power supply circuit. Background Technology

[0002] In the power management system of portable electronic devices, a dual-input power selection circuit is usually formed by combining a single-inductor DC-DC converter (SIMODCDC) with multiple low-dropout linear regulators (LDOs). This circuit switches the power supply path according to changes in the power source, so as to give full play to the advantages of the two types of converters in different scenarios.

[0003] However, existing switching schemes have two drawbacks: First, when switching from LDO to SIMO DCDC, the power supply sequence follows the jump power supply logic based on overvoltage protection (OVP) status. The power-on sequence is random, and the output path that is prioritized for power supply is exactly the power supply interruption point when the DCDC switched to LDO last time. This can easily lead to the heavy-load output path being delayed in power supply, resulting in severe voltage undershoot, which may trigger the subsequent circuit to crash or degrade in performance. Second, when switching from DCDC to LDO, traditional schemes often use the method of directly turning off the DCDC to instantly hand over the load to the LDO to bear independently. However, the LDO op-amp requires time to set up and has insufficient response capability when facing sudden load current changes. The output voltage is very easy to drop significantly, making it difficult to ensure power supply continuity. A few schemes that introduce a brief overlapping conduction time also do not actively and stepwise transfer the load capacity of the DCDC to the LDO, resulting in an insufficiently smooth load transfer. Summary of the Invention

[0004] In view of this, the present invention provides a dual-input power supply circuit to solve the problem of output voltage undershoot caused by sudden load changes and random power supply sequence during power supply switching between DC-DC converters and linear regulators in the prior art.

[0005] This invention provides a dual-input power supply circuit, comprising: multiple voltage output terminals; a DC-DC conversion circuit including multiple voltage output branches, each voltage output branch supplying power to a corresponding voltage output terminal; and multiple linear voltage regulator circuits, wherein each linear voltage regulator circuit supplies power to a corresponding voltage output terminal. The dual-input power supply circuit operates in either a DC-DC conversion power supply mode or a linear voltage regulator power supply mode based on a power switching signal; or, when the dual-input power supply circuit switches from a DC-DC conversion power supply mode to a linear voltage regulator power supply mode, the multiple linear voltage regulator circuits are activated and, together with the already operating DC-DC conversion circuit, supply power to the multiple voltage output terminals for a predetermined duration, and the DC-DC conversion circuit and the multiple linear voltage regulator circuits... While the voltage regulator circuits are supplying power to multiple voltage output terminals, the load-carrying capacity of the DC-DC converter circuit is gradually reduced until the DC-DC converter circuit is shut down. After that, multiple linear voltage regulator circuits supply power to multiple voltage output terminals individually. When the dual-input power supply circuit switches from linear voltage regulation mode to DC-DC conversion mode, multiple linear voltage regulator circuits stop supplying power to multiple voltage output terminals. At the same time, the DC-DC converter circuit starts up and supplies power to multiple voltage output terminals sequentially according to the principle of heavy load priority. Then, it resumes the normal state of supplying power to multiple voltage output terminals based on the overvoltage protection status of each voltage output terminal. The principle of heavy load priority is to supply power to the voltage output terminal with the heavier load first, and then supply power to the voltage output terminal with the lighter load.

[0006] The dual-input power supply circuit provided by this invention, when switching from DC-DC conversion power supply mode to linear regulation power supply mode, avoids the output voltage drop caused by the linear regulator directly bearing the load change by first allowing both inputs to carry the load and gradually reducing the load-carrying capacity of the DC-DC conversion circuit. When switching from linear regulation power supply mode to DC-DC conversion power supply mode, it first supplies power to each output according to the heavy load priority principle, and then restores the conventional overvoltage protection switching logic, effectively avoiding the large downsurge caused by the heavy load output path being delayed due to random power supply sequence. This invention achieves a smooth transition of output power in both positive and negative switching directions, effectively suppressing the output voltage fluctuation during switching transients, ensuring the power supply continuity and operational reliability of subsequent circuits, and the above control strategy only takes effect during the switching process and does not affect the normal normal operation performance of the system after it enters steady state.

[0007] In one optional implementation, when the power switching signal changes from a first logic level to a second logic level, the dual-input power supply circuit switches from a DC-DC conversion power supply mode to a linear regulated power supply mode; when the power switching signal changes from a second logic level to a first logic level, the dual-input power supply circuit switches from a linear regulated power supply mode to a DC-DC conversion power supply mode.

[0008] In one optional embodiment, the DC-DC conversion circuit includes: a first power switch, a second power switch, an inductor, and a logic control circuit. The logic control circuit controls the first and second power switches to be turned on alternately, causing the inductor to charge and discharge alternately. When the inductor current reaches the overcurrent protection threshold, the inductor is discharged. When switching from DC-DC conversion power supply mode to linear regulated power supply mode, the logic control circuit gradually lowers the overcurrent protection threshold at predetermined intervals to gradually reduce the load capacity of the DC-DC conversion circuit.

[0009] In one alternative implementation, the logic control circuit also controls the first power switch to turn on and the second power switch to turn off when the inductor current is less than or equal to the valley current threshold, so as to charge the inductor.

[0010] In one optional embodiment, the DC-DC conversion circuit further includes: multiple voltage hysteresis comparators and multiple branch switches, wherein each branch switch is connected between the inductor and the corresponding voltage output terminal, and only one branch switch is turned on at any given time; each voltage hysteresis comparator is used to compare the feedback voltage of the corresponding voltage output terminal with the two corresponding hysteresis reference voltages, and outputs an effective overvoltage protection signal when the feedback voltage is higher than the larger hysteresis reference voltage, indicating that the output terminal does not need power supply, and outputs an invalid overvoltage protection signal when the feedback voltage is lower than the smaller hysteresis reference voltage, indicating that the output terminal needs power supply; when switching from linear regulated power supply mode to DC-DC conversion power supply mode, the logic control circuit first controls the conduction sequence of each branch switch according to the heavy load priority principle to supply power to each voltage output terminal in sequence, and then controls the conduction sequence of each branch switch based on each overvoltage protection signal.

[0011] In one optional implementation, the system further includes: a load sequencing circuit, which samples and quantizes the load current of each voltage output terminal to obtain the load quantized voltage of each voltage output terminal in the linear regulated power supply mode, and obtains the load priority ranking result based on the load quantized voltage of each voltage output terminal; when the dual-input power supply circuit switches from the linear regulated power supply mode to the DC-DC conversion power supply mode, the DC-DC conversion circuit supplies power to multiple voltage output terminals sequentially according to the heavy load priority principle and the load priority ranking result.

[0012] In one optional implementation, the load sorting circuit includes: a current sampling unit, a comparison unit, and a latch output unit. The current sampling unit is used to sample the load current at each voltage output terminal and convert it into a load quantized voltage. The comparison unit is used to compare each load quantized voltage in pairs to generate a load priority ranking result. The latch output unit is used to latch the comparison result in the linear regulated power supply mode and output the load priority ranking result.

[0013] In one optional implementation, when the DC-DC conversion circuit supplies power to multiple voltage output terminals sequentially according to the principle of heavy load priority and the result of load weight ranking, after startup, it supplies power to each voltage output terminal for one power supply cycle in the order of heavy load to light load, until all voltage output terminals have completed one power supply cycle.

[0014] In one optional embodiment, the linear regulator circuit includes: an error amplifier, a pass switch, and a power transistor. The output terminal of the error amplifier is connected to the control terminal of the power transistor via the pass switch. The first connection terminal of the power transistor is connected to the input power supply, and the second connection terminal is connected to the corresponding voltage output terminal. The first input terminal of the error amplifier is connected to the corresponding reference voltage, and the second input terminal of the error amplifier receives the feedback voltage from the corresponding voltage output terminal. A power switching signal is used to control the conduction or disconnection of each pass switch. When the power switching signal changes from a first logic level to a second logic level, the power switching signal controls the conduction of each pass switch; when the power switching signal changes from a second logic level to a first logic level, the power switching signal controls the disconnection of each pass switch.

[0015] In one optional implementation, the first power switch of the DC-DC converter circuit is a PMOS transistor, and the second power switch of the DC-DC converter circuit is an NMOS transistor; the first drive control terminal of the logic control circuit is connected to the gate of the PMOS transistor, and the second drive control terminal of the logic control circuit is connected to the gate of the NMOS transistor; the source of the PMOS transistor is connected to the power supply terminal, the drain of the PMOS transistor is connected to the drain of the NMOS transistor, and the source of the NMOS transistor is grounded. Attached Figure Description

[0016] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a detailed circuit diagram of a dual-input power supply circuit according to an embodiment of the present invention; Figure 2 This is a specific circuit diagram of the load sorting circuit according to an embodiment of the present invention; Figure 3 This is a specific circuit diagram of the heavy-load priority power supply control logic according to an embodiment of the present invention; Figure 4 This is a detailed circuit diagram of the stepped current limiting control circuit according to an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It is understood that before using the technical solutions disclosed in the various embodiments of the present invention, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in the present invention and their authorization should be obtained in accordance with relevant laws and regulations through appropriate means.

[0020] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] In this invention, terms such as "connection," "linked," "connected," and "joined" that indicate electrical connection, unless otherwise specified, refer to direct or indirect electrical connections. A direct electrical connection indicates a direct connection between two or more objects without any intervening objects, while an indirect electrical connection indicates a connection between two or more objects with one or more intervening objects (such as electrical components or units like resistors, capacitors, inductors, switches, and filters).

[0022] This embodiment provides a dual-input power supply circuit, such as Figure 1 As shown, it includes: multiple voltage output terminals (VOUT1~VOUT3); a DC-DC conversion circuit 1, which includes multiple voltage output branches, each voltage output branch supplying power to a corresponding voltage output terminal; multiple linear voltage regulator circuits (21~23), wherein each linear voltage regulator circuit supplies power to a corresponding voltage output terminal; and a dual-input power supply circuit that operates in DC-DC conversion power supply mode or linear voltage regulation power supply mode based on a power switching signal.

[0023] Figure 1In the process, when the dual-input power supply circuit switches from DC-DC conversion power supply mode to linear voltage regulation power supply mode, multiple linear voltage regulator circuits start up and work together with the already working DC-DC conversion circuit to supply power to multiple voltage output terminals for a predetermined time. During the period when the DC-DC conversion circuit and multiple linear voltage regulator circuits jointly supply power to multiple voltage output terminals, the load capacity of the DC-DC conversion circuit is gradually reduced until the DC-DC conversion circuit is turned off. After that, multiple linear voltage regulator circuits supply power to multiple voltage output terminals individually.

[0024] Specifically, when the power switching signal controls the dual-input power supply circuit to switch from DC-DC conversion power supply mode to linear regulation power supply mode (for example, the power switching signal changes from high level to low level), multiple linear regulator circuits immediately start. At this time, the DC-DC conversion circuit does not immediately shut down, but continues to operate, so that multiple linear regulator circuits and the already operating DC-DC conversion circuit jointly supply power to multiple voltage output terminals. The reason for setting this joint power supply stage is that the error amplifier and its feedback loop inside the linear regulator circuit need a certain settling time after power-on to enter a stable operating state. At the same time, its output power transistor and compensation network also need to complete charging (or power supply) to have normal load-carrying capacity. If the linear regulator circuit is required to independently bear the entire load current at the moment of startup, its not-yet-fully-established feedback loop will not be able to respond to the sudden load demand in time, resulting in a significant drop in output voltage.

[0025] Optionally, the term "charging" in this embodiment should be interpreted broadly, and its specific manifestation may vary depending on the application scenario. The process by which a DC-DC converter stores energy through an inductor and transfers energy to each output branch in the form of pulses is called "charging." This process can also be regarded as replenishing the energy of the load capacitors at each output terminal and the subsequent circuits. Therefore, when describing this energy transfer behavior, "charging" and "power supply" can be used interchangeably depending on the context, and both encompass the technical meaning of delivering electrical energy to the output terminal for the load to use.

[0026] Specifically, during shared power supply, the DC-DC converter achieves a smooth transfer of load current by gradually reducing its own load-carrying capacity. In practice, the logic control module inside the DC-DC converter gradually lowers its overcurrent protection threshold (OCP threshold) in multiple stages at preset intervals (e.g., every few microseconds to hundreds of microseconds). As the overcurrent protection threshold decreases, the maximum allowable output current of the DC-DC converter gradually decreases, and its contribution to the power supply of each voltage output terminal gradually weakens. Multiple linear regulator circuits synchronously and incrementally take over the gradually transferred load current. Since the reduction of the overcurrent protection threshold is designed to be a small step value each time, the transfer of load current is distributed in multiple small-scale redistributions. During each transfer, the linear regulator circuit only needs to cope with a small increase in load, and its feedback loop is fully capable of completing the adjustment and establishing a new steady state within a single transfer time.

[0027] Specifically, after the aforementioned stepped load reduction process, the load-carrying capacity of the DC-DC converter circuit is reduced to near zero. Subsequently, the DC-DC converter circuit is completely shut down (e.g., by turning off its power switch via a delayed control signal). At this point, all load current has been smoothly transferred to multiple linear regulator circuits, which individually provide low-noise, low-ripple power to each voltage output terminal. During this process, the load current is transferred from the DC-DC converter circuit to the linear regulator circuit in a gradual manner. The linear regulator circuits never need to deal with large load jumps, thus fundamentally eliminating the occurrence of output voltage drops.

[0028] Figure 1 In the process of switching from linear voltage regulation mode to DC-DC conversion mode in the dual-input power supply circuit, multiple linear voltage regulator circuits stop supplying power to multiple voltage output terminals. At the same time, the DC-DC conversion circuit starts up and supplies power to multiple voltage output terminals sequentially according to the principle of heavy load priority. Then, it resumes the normal state of supplying power to multiple voltage output terminals based on the overvoltage protection status of each voltage output terminal. The principle of heavy load priority means that the voltage output terminal with the heavier load is supplied first, and then the voltage output terminal with the lighter load is supplied.

[0029] Specifically, when the power switching signal controls the dual-input power supply circuit to switch from linear regulation mode to DC-DC conversion mode (e.g., the power switching signal changes from low to high), multiple linear regulator circuits immediately stop supplying power to multiple voltage output terminals (e.g., by disconnecting the circuit switch between the error amplifier output terminal and the power transistor gate in the linear regulator circuit, setting the power transistor gate to a high level to turn it off). Simultaneously, the DC-DC conversion circuit starts and begins supplying power to each voltage output terminal. Initially, the DC-DC conversion circuit does not directly enter the conventional rotating power supply mode based on overvoltage protection; instead, it first executes a power supply sequence based on the heavy load priority principle.

[0030] Specifically, the heavy-load priority principle prioritizes powering the voltage output terminal with the heaviest load, followed by the voltage output terminal with the lightest load. In one example, this heavy-load priority principle could mean that in the first inductor current pulse cycle after startup, the voltage output terminal with the heaviest load is powered first; in the second inductor current pulse cycle, the voltage output terminal with the next heaviest load is powered; and so on, until all voltage output terminals have been powered once. The reason for this mechanism is that if the DC-DC conversion circuit directly enters the switching power supply mode based on overvoltage protection status after startup, the power supply order of its outputs will depend on the random combination of the overvoltage protection statuses at the end of the previous round of operation. Under this random order, the output circuit with the heaviest load may be placed in a later power supply sequence. Since the output capacitor of the heavy-load output circuit experiences the fastest voltage drop rate under continuous load current extraction, an excessively long waiting time will cause its output voltage to drop below the normal operating threshold of the subsequent circuit, thereby triggering a reset or performance abnormality of the subsequent circuit. In this embodiment, the DC-DC conversion circuit first supplies power to each output terminal sequentially according to the load order from heaviest to lightest. This ensures that the heavily loaded output circuit receives the highest priority energy replenishment at startup, allowing its output voltage to be maintained promptly during switching and eliminating the risk of undervoltage due to prolonged waiting. In the example above, during the power supply to each voltage output terminal based on the heavy load priority principle, one inductor current pulse cycle is supplied to each voltage output terminal. In other examples, multiple inductor current pulse cycles can also be supplied to each voltage output terminal based on the heavy load priority principle.

[0031] Specifically, after each of the aforementioned voltage output terminals has completed one power supply cycle, the DC-DC conversion circuit immediately switches to a normal operating mode that alternates power supply based on the overvoltage protection status of each voltage output terminal. That is, it determines whether a power supply is needed based on whether the overvoltage protection of each output voltage has been triggered, and cycles through the required output terminals according to a preset shift register sequence. This method is the conventional control logic for steady-state operation of the DC-DC conversion circuit and has high conversion efficiency. Since heavy-load priority power supply is only executed in the first or first few power supply cycles after switching, once each output terminal has completed one or more power replenishments, the system returns to the normal operating mode. Therefore, this mechanism has no impact on the steady-state operating efficiency of the system, achieving precise intervention in switching transients and zero interference in steady-state operation.

[0032] For example, Figure 1 In the process, when the power switching signal bypass changes from the first logic level (e.g., high level) to the second logic level (e.g., low level), the dual-input power supply circuit switches from DC-DC conversion power supply mode to linear voltage regulation power supply mode; when the power switching signal bypass changes from the second logic level (e.g., low level) to the first logic level (e.g., high level), the dual-input power supply circuit switches from linear voltage regulation power supply mode to DC-DC conversion power supply mode.

[0033] It should be noted that, in one specific embodiment, the present invention may employ a method where, when switching from a DC-DC converter power supply mode to a linear regulated power supply mode, both power supplies are initially allowed to carry the load while the load-carrying capacity of the DC-DC converter circuit is gradually reduced. This method differs from the method where, when switching from a linear regulated power supply mode to a DC-DC converter power supply mode, power is supplied to each output sequentially according to the heavy load priority principle, and then the conventional overvoltage protection switching logic is restored. In another embodiment, the present invention may employ a method where, when switching from a linear regulated power supply mode to a DC-DC converter power supply mode, power is supplied to each output sequentially according to the heavy load priority principle, and then the conventional overvoltage protection switching logic is restored. This method differs from the method where, when switching from a DC-DC converter power supply mode to a linear regulated power supply mode, both power supplies are initially allowed to carry the load while the load-carrying capacity of the DC-DC converter circuit is gradually reduced.

[0034] The dual-input power supply circuit provided in this embodiment, when switching from DC-DC conversion power supply mode to linear regulation power supply mode, avoids the output voltage drop caused by the linear regulator directly bearing the load change by first allowing both to carry the load and gradually reducing the load-carrying capacity of the DC-DC conversion circuit. When switching from linear regulation power supply mode to DC-DC conversion power supply mode, it first supplies power to each output according to the heavy load priority principle, and then restores the normal overvoltage protection switching logic, effectively avoiding the large downsurge caused by the heavy load output path being delayed due to random power supply sequence. This invention achieves a smooth transition of output power in both positive and negative switching directions, effectively suppresses the output voltage fluctuation during switching transients, ensures the power supply continuity and operational reliability of subsequent circuits, and the above control strategy only takes effect during the switching process and does not affect the normal normal operation performance of the system after entering steady state.

[0035] In some alternative implementations, such as Figure 1 As shown, when the dual-input power supply circuit switches from DC-DC conversion power supply mode to linear regulated power supply mode, the DC-DC conversion circuit 1 gradually reduces the overcurrent protection threshold of the DC-DC conversion circuit by progressively lowering it at predetermined intervals, thereby gradually reducing the load capacity of the DC-DC conversion circuit 1. The DC-DC conversion circuit 1 includes a first power switch (PMOS transistor) PM1, a second power switch (NMOS transistor) NM1, an inductor L, and a logic control circuit LOGIC. The logic control circuit LOGIC controls the on and off states of the first power switch PM1 and the second power switch NM1. When the first power switch PM1 is on and the second power switch NM1 is off, power is supplied to the inductor L through the first power switch PM1. When the second power switch NM1 is on and the first power switch PM1 is off, power is discharged to the inductor through the second power switch NM1. When the current of the inductor L is greater than or equal to the overcurrent protection threshold, the logic control circuit LOGIC controls the second power switch NM1 to be on and the first power switch PM1 to be off, thus discharging the inductor L.

[0036] Specifically, Figure 1In this circuit, the logic control circuit LOGIC controls the on / off state of PM1 and NM1 via PDRV and NDRV signals. When PM1 is on and NM1 is off, the power supply charges inductor L through PM1. When NM1 is on and PM1 is off, inductor L discharges to ground through NM1, transferring energy to the output. The logic control circuit LOGIC monitors the inductor current in real time. When the inductor current rises to a level greater than or equal to the overcurrent protection threshold, it triggers overcurrent protection, turns off PM1 and turns on NM1, allowing inductor L to enter the discharge phase, thereby limiting the peak inductor current. During the switch from DC-DC conversion power supply mode to linear regulated power supply mode, the logic control circuit LOGIC gradually lowers the overcurrent protection threshold at predetermined intervals. With each level of reduction, the peak current allowed by the inductor decreases by one step, and the single-transmission energy and total output capacity of DC-DC conversion circuit 1 gradually weaken, thus achieving a smooth decrease in load capacity and creating conditions for a smooth transfer of load current to the linear regulated circuit.

[0037] In some alternative implementations, such as Figure 1 As shown, when the current in inductor L is less than or equal to the valley current threshold, the logic control circuit LOGIC controls the first power switch PM1 to turn on and the second power switch NM1 to turn off, supplying power to inductor L. The DC-DC conversion circuit 1 also includes multiple voltage hysteresis comparators (COMP1~COMP3). Each output branch includes a branch switch (SW1~SW3) connected between the inductor and the corresponding voltage output terminal. The first power switch PM1 and the second power switch NM1 are connected in series between the power supply terminal and the ground terminal. One end of inductor L is connected to the intermediate node between the first power switch PM1 and the second power switch NM1, and the other end of inductor L is connected to the corresponding voltage output terminal through each branch switch. Each voltage hysteresis comparator compares the feedback voltage (FB1~FB3) of the corresponding voltage output terminal with the corresponding two hysteresis reference voltages (VREF1~VREF3). (and VREF1_H~VREF3_H). When the feedback voltage is higher than the larger of the two hysteresis reference voltages, an effective overvoltage protection signal is output; when the feedback voltage is lower than the smaller of the two hysteresis reference voltages, an invalid overvoltage protection signal is output. An effective overvoltage protection signal indicates that the corresponding voltage output terminal does not require power, while an invalid overvoltage protection signal indicates that the corresponding voltage output terminal requires power. At the same time, only one branch switch controlled by the logic control circuit is turned on. When the dual-input power supply circuit switches from linear regulated power supply mode to DC-DC conversion power supply mode, the logic control circuit first controls the conduction sequence of each branch switch according to the heavy load priority principle to supply power to multiple voltage output terminals sequentially. Subsequently, the logic control circuit controls the conduction sequence of each branch switch based on the overvoltage protection signal to supply power to the corresponding voltage output terminal.

[0038] Specifically, Figure 1 In the circuit, the logic control circuit LOGIC also uses a valley current detection mechanism to control the switching timing: when the current of inductor L drops to less than or equal to the valley current threshold, LOGIC controls the first power switch PM1 to turn on and the second power switch NM1 to turn off, so that inductor L re-enters the charging stage, thereby maintaining the inductor current to fluctuate periodically between the set valley and peak values, and realizing stable energy transmission in the discontinuous conduction mode.

[0039] Specifically, Figure 1 In this system, each voltage hysteresis comparator monitors the voltage status of its corresponding output branch. The comparator compares the feedback voltages FB1-FB3 at the corresponding output terminal with two hysteresis reference voltages, one high and one low. The higher reference voltage is the upper hysteresis limit (VREF1_H~VREF3_H), and the lower reference voltage is the lower hysteresis limit (VREF1~VREF3). When the feedback voltage is higher than the higher hysteresis reference voltage, the comparator outputs a valid overvoltage protection signal OVP, indicating that the output voltage of that branch has reached the required level and no further power supply is needed. When the feedback voltage is lower than the lower hysteresis reference voltage, the comparator outputs an invalid overvoltage protection signal, indicating that the output voltage of that branch is insufficient and power supply is required. The hysteresis window introduced by the hysteresis comparator prevents frequent switching of the OVP signal when the feedback voltage fluctuates near the reference voltage, improving the system's anti-interference capability.

[0040] Specifically, Figure 1 In this system, the logic control circuit LOGIC controls only one of the branch switches SW1~SW3 to conduct at any given time. This means that inductor L supplies energy to only one output at a time, and each output receives power sequentially in a time-division multiplexing manner. When switching from linear regulated power supply mode to DC-DC conversion power supply mode, LOGIC first determines the initial conduction sequence of each branch switch based on the heavy load priority principle, ensuring that the output branch with the heaviest load receives inductor current pulse power first. After each output has completed one power supply cycle, LOGIC switches the branch switch conduction control to a conventional rotation logic based on the OVP signal. That is, according to the active / inactive state of each OVP, the output branches requiring power are sequentially turned on according to a preset shift sequence. Under steady-state operation, the power supply priority of each output branch is dynamically determined by its respective voltage demand, thus ensuring optimal conversion efficiency after the system enters steady state.

[0041] In some alternative implementations, such as Figure 2As shown, the dual-input power supply circuit further includes a load sequencing circuit. In linear regulated power supply mode, the load sequencing circuit samples and quantizes the load current at each voltage output terminal to obtain the load-quantized voltage at each voltage output terminal, and obtains a load priority ranking result based on the load-quantized voltage at each voltage output terminal. When the dual-input power supply circuit switches from linear regulated power supply mode to DC-DC conversion power supply mode, the DC-DC conversion circuit supplies power to multiple voltage output terminals sequentially according to the heavy load priority principle and the load priority ranking result. The load sequencing circuit includes a current sampling unit, a comparison unit, and a latching output unit. The current sampling unit samples the load current at each voltage output terminal and converts it into a load-quantized voltage. The comparison unit compares each load-quantized voltage pairwise to generate a load priority ranking result. The latching output unit latches the comparison result in linear regulated power supply mode and outputs the load priority ranking result. When the DC-DC conversion circuit supplies power to multiple voltage output terminals sequentially according to the principle of heavy load priority and the result of load weight ranking, it supplies power to the voltage output terminal with the heaviest load in the first power supply cycle after startup, supplies power to the voltage output terminal with the second heaviest load in the second power supply cycle, and so on, until each voltage output terminal has completed one power supply.

[0042] Specifically, Figure 2In this circuit, the load sequencing circuit is used to pre-acquire the load status information of each output branch while the system is still operating in linear regulated power supply mode, providing a sequencing basis for prioritizing heavy load power supply when switching to DC-DC conversion power supply mode. The load sequencing circuit includes a current sampling unit, a comparison unit, and a latched output unit. When each LDO branch is operating under normal load, the current sampling unit samples the load current at each voltage output terminal VOUT1~VOUT3 in real time, converting the current signal into a proportionally proportional quantized voltage CS1~CS3. The quantized voltages CS1~CS3 are respectively fed into the three comparators COMP1, COMP2, and COMP3 of the comparison unit for pairwise comparison, generating three original comparison results: Y1_Pre, Y2_Pre, and Y3_Pre, representing the relative relationship of load intensity among each branch. Y1_Pre, Y2_Pre, and Y3_Pre are fed into the LG_EN logic unit. After enabling and filtering by the branch enable signals DCEN1, DCEN2, and DCEN3, they are output to the DIFF differential latch flip-flop. The flip-flop synchronously receives the synchronization clock IHIGH_SYN_CLK, the linear regulator shutdown signal OFF_LDOS_BUCK, and the reset signal RST. After latching, it outputs the Y1_SYN, Y2_SYN, and Y3_SYN synchronization comparison signals, which are sent to the core logic module LOGIC1. LOGIC1 receives the three synchronization comparison signals, the fault signal ERROR, and the pre-enable signal IHIGH1_PRE. It works with OR gates, multi-level logic units LG2 and LG3, AND gates, NOR gates, and inverters INV to complete multi-channel logic operations. Finally, it generates a 3-bit load priority encoding bus IHIGH1<1:3>, IHIGH2<1:3>, and IHIGH3<1:3>, as well as the fault inverted signal ERROR, and outputs the priority results of each load sorted by current magnitude.

[0043] Specifically, Figure 2 In this circuit, the latch output unit is controlled by the synchronous clock HIGH_SYN_CLK. This clock generates a latch pulse at a preset time (e.g., 50ns before the switch) before the bypass signal transitions from low to high (i.e., the system switches from linear regulated power supply mode to DC-DC conversion power supply mode). This latches the outputs Y1_Pre, Y2_Pre, and Y3_Pre from the comparison unit into Y1_SYN, Y2_SYN, and Y3_SYN, respectively. After being decoded by the logic combination unit LOGIC1, the latched Y1_SYN, Y2_SYN, and Y3_SYN are finally output as the sorting results of the three loads from heaviest to lightest, represented by a three-digit digital signal. For example, IHIGH1<1:3>=100 indicates that the first output has the heaviest load and should be powered first; IHIGH2<1:3>=010 indicates that the second load is next; and IHIGH3<1:3>=001 indicates that the third load is the lightest.

[0044] Considering that some output branches may be off in LDO operating mode (e.g., outputs controlled by the enable signal LG_EN are forcibly shut down), these off branches should not participate in the sorting competition. Therefore, the load sorting circuit also includes forced sorting logic, placing the sorting position of the disabled outputs directly after all enabled outputs. Simultaneously, to avoid comparator output instability or contradictory sorting results due to excessively close load currents, a default order arbitration mechanism is also included. When logical conflicts occur in the comparison results (e.g., pairwise comparison results cannot form a total order relationship), the ERROR signal forces a switch to the preset default order SW1→SW2→SW3, ensuring the sorting results are reliable and effective under any operating condition.

[0045] Specifically, Figure 2 In the middle, the sorting result was changed at the moment of switching. Figure 3 The heavy-load priority power supply control logic shown determines the conduction sequence of SW1~SW3 in the first three inductor current pulses after switching: the first power supply cycle supplies power to the voltage output terminal with the heaviest load, the second power supply cycle supplies power to the voltage output terminal with the next heaviest load, and so on, until each voltage output terminal has completed one power supply cycle. It is worth mentioning that the load sequencing circuit only continuously samples and compares while the system is operating in LDO mode, and its results are only latched and used during the switching transient. Once the system completes the switch to DC-DC conversion power supply mode, the output of this circuit no longer affects the steady-state switching logic of the DC-DC conversion circuit, thus achieving accurate perception of the load state during the switching process and complete decoupling from steady-state operation.

[0046] In some alternative implementations, such as Figure 1 As shown, the linear regulator circuit includes: an error amplifier (EA1, EA2, or EA3), a path switch (SW4, SW5, or SW6), and a power transistor (PM2, PM3, or PM4). The output of the error amplifier is connected to the control terminal of the power transistor via the path switch. The first connection terminal of the power transistor is connected to the input power supply, and the second connection terminal is connected to the corresponding voltage output terminal. The first input terminal of the error amplifier is connected to the corresponding reference voltage, and the second input terminal of the error amplifier receives the feedback voltage from the corresponding voltage output terminal. A power switching signal is used to control the conduction or disconnection of each path switch. When the power switching signal changes from the first logic level to the second logic level, the power switching signal controls each path switch to conduct; when the power switching signal changes from the second logic level to the first logic level, the power switching signal controls each path switch to disconnect. The power transistor is a PMOS transistor.

[0047] Specifically, Figure 1In this example, the VOUT1 branch is used as an example; the VOUT2 and VOUT3 branches have identical structures. The linear regulator circuit includes an error amplifier EA1, a pass switch SW6, and a power transistor PM4. The non-inverting input of the error amplifier EA1 receives the output voltage feedback signal FB1 (from the voltage divider network at the output of VOUT1), the inverting input is connected to the reference voltage VREF1, and the output is connected to the gate (control terminal) of the power transistor PM4 via the pass switch SW6. The source (first connection terminal) of PM4 is connected to the input power supply Vin, and the drain (second connection terminal) is connected to the voltage output terminal VOUT1. When the pass switch SW6 is turned on, the output signal of the error amplifier EA1 directly drives the gate of PM4, forming a closed-loop voltage regulation circuit: when VOUT1 decreases due to increased load, FB1 decreases accordingly, the output voltage of EA1 rises, the gate-source voltage Vgs of PM4 increases, the on-resistance of PM4 decreases, and the output VOUT1 rises again until FB1 equals VREF1; conversely, when VOUT1 rises, the output voltage of EA1 decreases, the on-resistance of PM4 increases, and the output VOUT1 falls back. Through this negative feedback mechanism, the linear voltage regulator circuit stabilizes the output voltage at the target value set by VREF1. The VOUT2 branch corresponds to the error amplifier EA2, the pass switch SW5, and the power transistor PM3; the VOUT3 branch corresponds to the error amplifier EA3, the pass switch SW4, and the power transistor PM2. These three branches are independent and can be set with different output voltages. Power transistors PM2, PM3, and PM4 are all PMOS transistors, with their sources connected to the input power supply Vin and their drains connected to their respective voltage output terminals.

[0048] Specifically, Figure 1 In this system, the switching of circuit breakers SW4-SW6 is uniformly controlled by the power switching signal bypass. When bypass is low, all SW4-SW6 are turned on, and the outputs of each error amplifier are connected to the gates of their respective power transistors, establishing a three-way LDO loop, and the system operates in linear regulated power supply mode. When bypass is high, all SW4-SW6 are turned off, the outputs of each error amplifier are disconnected from the gates of their respective power transistors, and the gates of each power transistor are pulled up to a high level through pull-up resistors, completely turning off PM2, PM3, and PM4, and completely cutting off the LDO branches, so the system operates in DC-DC conversion power supply mode. By controlling the switching on and off of the three LDOs simultaneously with a single bypass signal, the control logic is simple, ensuring that only one of the two power supply systems is in an effective working state at any given time (except for the common power supply phase when switching from DC-DC conversion power supply mode to linear regulated power supply mode, in which the DC-DC converter is delayed and turned off by the bypass delay signal bypass_delay, while the LDOs are already started and in operation).

[0049] For example, Figure 3 This is the circuit diagram for the heavy-load priority power supply control logic. This logic controls the conduction sequence of branch selection switches SW1, SW2, and SW3 when the system switches from linear regulated power supply mode to DC-DC conversion power supply mode, ensuring that the output branch with the heaviest load receives power first.

[0050] like Figure 3 As shown, the core of this control logic is a four-level selection link consisting of MUX0, MUX1, MUX2, and MUX3. The input signals include... Figure 2 The output load priority ranking results are IHIGH1<1:3>, IHIGH2<1:3>, and IHIGH3<1:3>, the bypass signal, and the three pulse end marker signals START1, START2, and START3; among them, in the signal IHIGH1<1:3>, <1:3> represents the 3-bit priority encoding bus width, including IHIGH1 <1> 、IHIGH1 <2> 、IHIGH1 <3> The three sets of single-bit signals, IHIGH2<1:3> and IHIGH3<1:3>, are processed similarly. The global synchronization clock IHIGH_SYN_CLK generates a bypass signal after a 50ns delay, and its inverted signal bypassb is also present. The 50ns delay is used to reserve timing setup time to ensure... Figure 2 After the output sorting code is stably latched, sorting charging is started again. At the same time, the circuit also introduces the global overvoltage gate signal GATE_CTRL_OVP output from the DC-DC converter module, the timing latch unit DIFF differential flip-flop and OR gate. The DIFF differential flip-flop and OR gate generate the EN_LG branch enable signal. GATE_CTRL_OVP is connected to the input of the four-stage DIFF differential flip-flop. When any output branch is overvoltaged, this signal can block the output of the timing flip-flop to immediately terminate the branch charging.

[0051] The output signals are S1, S2, and S3, which are used to drive the gates of SW1, SW2, and SW3, respectively. When the bypass signal changes from low to high (the switching instruction is valid), MUX3 first determines the enable status (LG_EN signal) of each output branch: for the disabled output branch, its corresponding gating switch is forcibly turned off and does not participate in the power supply sequencing; the enabled output branch enters the subsequent selection link.

[0052] During the initial switching phase, MUX0 is in heavy-load priority mode, and its selection reference is the output of MUX2. Based on the states of START1 and START2, MUX2 sequentially selects IHIGH1, IHIGH2, and IHIGH3 as the turn-on sequence. Specifically, during the first inductor current pulse after switching, both START1 and START2 are low. MUX2 outputs IHIGH1 (corresponding to the heaviest load output path) to MUX0. After selection by MUX0, it outputs S1~S3, controlling the corresponding selection switches to turn on, supplying power to the heaviest load output path. At the end of this pulse, START1 flips to a high level, and MUX2 switches to output IHIGH2 (corresponding to the second heaviest load output path). The second pulse supplies power to the second heaviest load output path. At the end of this pulse, START2 flips to a high level, and MUX2 switches to output IHIGH3 (corresponding to the lightest load output path). The third pulse supplies power to the lightest load output path. When the third pulse ends, START3 flips to a high level. This signal controls MUX1 to switch the control of SW1~SW3 from the heavy load priority mode to the switching power supply logic based on the OVP state (that is, the input of MUX0 is switched from the output of MUX2 to OVP1_SEL, OVP2_SEL, OVP3_SEL). After that, the conduction sequence of the selector switches is dynamically determined by the overvoltage protection signal of each output.

[0053] The switching power supply logic based on the OVP state is the standard control method for DC-DC converter circuits in steady-state operation: the power supply sequence of each output is dynamically determined according to the state of the overvoltage protection signals OVP1, OVP2, and OVP3. The conduction sequence of SW1, SW2, and SW3 is controlled by a set of shift registers, which cycle according to the pattern 100→010→001→100... and automatically skip the output branches that have triggered OVP, switching only between the branches that need power supply.

[0054] In summary, the heavy-load priority power supply control logic only intervenes in the conduction sequence of SW1~SW3 during the first three inductor current pulses after switching. Once all three outputs have completed one power supply (i.e. START3 flips to a high level), the control is completely returned to the conventional OVP switching power supply logic, achieving fine intervention in the switching transient and zero interference in steady-state operation.

[0055] For example, Figure 4 This is a detailed circuit diagram of the stepped current limiting control circuit. The stepped current limiting control circuit is used to gradually lower the overcurrent protection threshold (OCP threshold) of the DC-DC converter circuit in stages when the system switches from DC-DC power supply mode to linear regulated power supply mode, thereby gradually reducing its load-carrying capacity and achieving a smooth transfer of load current to the linear regulated circuit.

[0056] like Figure 4 As shown, the core of this circuit is a multi-level adjustable resistor network and an OCP comparator. The circuit also includes a multi-stage FALL_Delay falling edge delay unit chain, LOGIC<1:n> sequential logic units, an AND<1:n> multi-channel AND gate array, a power supply VDD, and a constant pull-down current source. These units work together to complete timing generation, logic operations, and reference voltage output. The input bypass signal is fed into the cascaded FALL_Delay unit, outputting segmented timing signals D stage by stage. <1> ~D <n>The final output is the total delay signal bypass_delay; the LOGIC<1:n> unit receives the timing signals D<1:n> and bypass_delay, and generates the threshold reduction pre-control signal OCP_D<1:n> for each gear position; the and<1:n> array performs a bitwise AND operation on OCP_D<1:n> and the system steady-state gear position configuration signal MIOCP<1:n>, and outputs the final gear position control signal D_MIOCP<1:n>; VDD, digitally controlled adjustable resistor, and constant pull-down current source are connected in series to form the reference branch, and the intermediate node outputs the OCPREF reference voltage to the OCP comparator.

[0057] An adjustable resistor network is connected to the reference input of the OCP comparator, and its equivalent resistance is determined by the control signal D_MIOCP<1:n>. Specifically, when D_MIOCP... <1> To D_MIOCP <n>When all levels are high, all resistors in the adjustable resistor network are connected, resulting in the maximum equivalent resistance. The reference voltage OCPREF of the OCP comparator is at its minimum, and the corresponding OCP threshold is at its highest level, allowing the DC-DC converter circuit to output the maximum peak current. When the control signal for a certain level flips from high to low, the corresponding resistor is short-circuited, the equivalent resistance decreases, OCPREF increases, the OCP threshold decreases by one level, and the output capability of the DC-DC converter circuit weakens accordingly. This is achieved by using D_MIOCP... <1> To D_MIOCP <n>By sequentially switching to a low level at preset intervals, the OCP threshold can be adjusted in a stepwise manner.

[0058] In terms of timing control, when the bypass signal transitions from high to low, the system switches from DC-DC conversion power supply mode to linear regulation power supply mode. The falling edge of the bypass signal immediately activates the linear regulator circuit (SW4~SW6 are turned on, and the LDO loop is engaged), and simultaneously generates a delay control signal, bypass_delay. Before the bypass_delay signal flips, the DC-DC conversion circuit remains operational, working together with the linear regulator circuit to supply power to the various voltage output terminals, providing sufficient setup time for the linear regulator circuit.

[0059] During the shared power supply period, D_MIOCP<1:n> toggles to low level sequentially at preset intervals. Taking three levels as an example: at the end of the first delay, D_MIOCP... <1> Toggles to low level (if MIOCP) <1> Initially low level, so no change in this range); the OCP threshold decreases by one level, the output capability of the DC-DC converter circuit weakens, and part of the load it bears is transferred to the linear regulator circuit; at the end of the second delay, D_MIOCP <2> When the level is toggled low, the OCP threshold decreases by one level; this process continues until D_MIOCP is reached. <n>When the bypass_delay switches to low, the OCP threshold drops to its lowest level, weakening the load-carrying capacity of the DC-DC converter to near zero. With each level reduction, the load current undergoes only a small shift, allowing the linear regulator's feedback loop ample time to adjust, resulting in minimal output voltage fluctuations. When bypass_delay finally switches to low, the load transfer is complete, the DC-DC converter is completely shut down, and the system enters a steady-state operating mode with the linear regulator powered solely. Simultaneously, D_MIOCP<1:n> automatically reverts to its initial setting (i.e., the OCP threshold level during steady-state operation) to ensure the overcurrent protection threshold is correctly set the next time the system switches back to DC-DC power supply mode.

[0060] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.< / n> < / n> < / n> < / n>

Claims

1. A dual-input power supply circuit, characterized in that, include: Multiple voltage output terminals; A DC-DC converter circuit includes multiple voltage output branches, each of which supplies power to a corresponding voltage output terminal. Multiple linear voltage regulator circuits, each of which supplies power to a corresponding voltage output terminal; The dual-input power supply circuit operates in either DC-DC conversion power supply mode or linear regulated power supply mode based on the power switching signal. When the dual-input power supply circuit switches from DC-DC conversion power supply mode to linear voltage regulation power supply mode, the multiple linear voltage regulator circuits start up and, together with the already operating DC-DC conversion circuit, supply power to the multiple voltage output terminals for a predetermined period of time. During the period when the DC-DC conversion circuit and the multiple linear voltage regulator circuits jointly supply power to the multiple voltage output terminals, the load-carrying capacity of the DC-DC conversion circuit is gradually reduced until the DC-DC conversion circuit is turned off. Afterwards, the multiple linear voltage regulator circuits supply power to the multiple voltage output terminals individually; or... When the dual-input power supply circuit switches from linear voltage regulation mode to DC-DC conversion mode, the multiple linear voltage regulator circuits stop supplying power to the multiple voltage output terminals. At the same time, the DC-DC conversion circuit starts up and first supplies power to the multiple voltage output terminals sequentially according to the heavy load priority principle. Then, it resumes the normal state of supplying power to the multiple voltage output terminals based on the overvoltage protection state of each voltage output terminal. The heavy load priority principle means that the voltage output terminal with the heavier load is supplied first, and then the voltage output terminal with the lighter load is supplied.

2. The dual-input power supply circuit according to claim 1, characterized in that, When the power switching signal changes from the first logic level to the second logic level, the dual-input power supply circuit switches from DC-DC conversion power supply mode to linear regulated power supply mode. When the power switching signal changes from the second logic level to the first logic level, the dual-input power supply circuit switches from linear voltage regulation mode to DC-DC conversion power supply mode.

3. The dual-input power supply circuit according to claim 1, characterized in that, The DC-DC conversion circuit includes: a first power switch, a second power switch, an inductor, and a logic control circuit, wherein, The logic control circuit controls the first power switch and the second power switch to be turned on alternately, so that the inductor is charged and discharged alternately, and the inductor is discharged when the inductor current reaches the overcurrent protection threshold. When switching from DC-DC conversion power supply mode to linear regulated power supply mode, the logic control circuit gradually lowers the overcurrent protection threshold at predetermined intervals to gradually reduce the load capacity of the DC-DC conversion circuit.

4. The dual-input power supply circuit according to claim 3, characterized in that, The logic control circuit also controls the first power switch to turn on and the second power switch to turn off when the current of the inductor is less than or equal to the valley current threshold, so as to charge the inductor.

5. The dual-input power supply circuit according to claim 3 or 4, characterized in that, The DC-DC conversion circuit further includes: multiple voltage hysteresis comparators and multiple branch switches, wherein, Each branch switch is connected between the inductor and the corresponding voltage output terminal, and only one branch switch is turned on at any given time. Each voltage hysteresis comparator is used to compare the feedback voltage of the corresponding voltage output terminal with the two corresponding hysteresis reference voltages. When the feedback voltage is higher than the larger hysteresis reference voltage, it outputs an effective overvoltage protection signal, indicating that the output terminal does not need power supply. When the feedback voltage is lower than the smaller hysteresis reference voltage, it outputs an invalid overvoltage protection signal, indicating that the output terminal needs power supply. When switching from linear regulated power supply mode to DC-DC conversion power supply mode, the logic control circuit first controls the conduction sequence of each branch switch according to the heavy load priority principle to supply power to each voltage output terminal in sequence, and then controls the conduction sequence of each branch switch based on each overvoltage protection signal.

6. The dual-input power supply circuit according to claim 1, characterized in that, Also includes: The load sorting circuit, in the linear regulated power supply mode, samples and quantizes the load current of each voltage output terminal to obtain the load quantized voltage of each voltage output terminal, and obtains the load priority ranking result based on the load quantized voltage of each voltage output terminal. When the dual-input power supply circuit switches from linear regulated power supply mode to DC-DC conversion power supply mode, the DC-DC conversion circuit supplies power to multiple voltage output terminals sequentially according to the principle of heavy load priority and the result of the load weight ranking.

7. The dual-input power supply circuit according to claim 6, characterized in that, The load sequencing circuit includes: a current sampling unit, a comparison unit, and a latch output unit, wherein... The current sampling unit is used to sample the load current at each of the voltage output terminals and convert it into the load quantized voltage. The comparison unit is used to compare the quantized voltages of each load in pairs to generate the load weight ranking result. The latch output unit is used to latch the comparison result in the linear regulated power supply mode and output the load weight ranking result.

8. The dual-input power supply circuit according to claim 6, characterized in that, When the DC-DC conversion circuit supplies power to multiple voltage output terminals sequentially according to the heavy load priority principle and the load weight ranking result, after startup, it supplies power to each voltage output terminal for one power supply cycle according to the order of heavy load to light load, until all voltage output terminals have completed one power supply cycle.

9. The dual-input power supply circuit according to claim 2, characterized in that, The linear voltage regulator circuit includes an error amplifier, a pass switch, and a power transistor. The output terminal of the error amplifier is connected to the control terminal of the power transistor via the pass switch. The first terminal of the power transistor is connected to the input power supply, and the second terminal is connected to the corresponding voltage output terminal. The first input terminal of the error amplifier is connected to the corresponding reference voltage, and the second input terminal of the error amplifier receives the feedback voltage of the corresponding voltage output terminal. The power switching signal is used to control the switching of each path to be turned on or off. When the power switching signal changes from the first logic level to the second logic level, the power switching signal controls the switching of each path to be turned on; When the power switching signal changes from the second logic level to the first logic level, the power switching signal controls the switches of each path to open.

10. The dual-input power supply circuit according to claim 5, characterized in that, The first power switch of the DC-DC conversion circuit is a PMOS transistor, and the second power switch of the DC-DC conversion circuit is an NMOS transistor; The first drive control terminal of the logic control circuit is connected to the gate of the PMOS transistor, and the second drive control terminal of the logic control circuit is connected to the gate of the NMOS transistor. The source of a PMOS transistor is connected to the power supply terminal, the drain of a PMOS transistor is connected to the drain of an NMOS transistor, and the source of an NMOS transistor is grounded.

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