Front porch blanking circuit, switching power supply controller and switching power supply system

Abstract

The application discloses a front porch blanking circuit, a switching power supply controller and a switching power supply system, and relates to the technical field of switching power supplies. The switching power supply system comprises a power tube, and the front porch blanking circuit comprises a front porch blanking signal generation module connected with the controlled end of the power tube. The front porch blanking signal generation module is used for detecting the voltage output to the controlled end of the power tube, starting a delay from the moment when the controlled voltage of the power tube is detected, outputting a front porch blanking signal during the delay, and stopping the output of the front porch blanking signal until the delay time reaches a preset delay time. A signal processing module is connected with the first input end of the front porch blanking signal generation module, and receives an overcurrent protection signal at the second input end. The signal processing module is used for shielding the overcurrent protection signal within the delay time according to the received front porch blanking signal. The application solves the problem that the fixed front porch blanking time cannot completely shield current spikes and mis-trigger overcurrent protection due to the increase of the power tube.

Description

Technical Field

[0001] This invention relates to the field of switching power supply technology, and in particular to a leading-edge blanking circuit, a switching power supply controller, and a switching power supply system. Background Technology

[0002] In AC-DC switching power supply systems, the moment a power transistor (such as a MOSFET) turns on, parasitic capacitance and transformer leakage inductance in the circuit generate a spike current. This causes a momentary voltage spike across the current sampling resistor, exceeding the overcurrent protection threshold. This triggers a misjudgment by the control chip, causing it to prematurely shut down the power transistor, resulting in system malfunction. Therefore, switching power supply systems typically require advanced blanking technology to briefly shield the current detection signal at the moment the power transistor turns on, preventing erroneous protection actions caused by conduction spikes.

[0003] In existing technologies, leading-edge blanking is typically controlled by internal chip timing logic, generating a fixed-duration shielding window. During this fixed time after the power transistor is turned on, the voltage across the current detection sampling resistor is forcibly shielded. However, since the leading-edge blanking time is fixed, when the power transistor switches from a lower power level to a higher power level, the gate capacitance of the power transistor increases proportionally, and the duration of the voltage spike at the moment of turn-on becomes longer. The fixed leading-edge blanking time is insufficient to completely shield the current spike, and it may still falsely trigger the overcurrent protection. As a result, the chip turns off the power transistor immediately after the leading-edge blanking ends in each switching cycle, and cannot output the normal conduction pulse width to transfer energy.

[0004] The above content is only used to help understand the technical solution of this application and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main objective of this invention is to provide a leading-edge blanking circuit, a switching power supply controller, and a switching power supply system, aiming to solve the technical problem that a fixed leading-edge blanking time cannot be adaptively adjusted according to changes in the size of the power transistor, resulting in the current spike at the moment of high-power transistor conduction not being completely shielded.

[0006] This invention proposes a leading-edge blanking circuit for use in a switching power supply system, wherein the switching power supply system includes a power transistor, and the leading-edge blanking circuit includes: A leading-edge blanking signal generation module is connected to the controlled terminal of the power transistor. The leading-edge blanking signal generation module is used to detect the voltage output to the controlled terminal of the power transistor. It starts to delay from the moment the controlled voltage of the power transistor is detected, and outputs the leading-edge blanking signal during the delay period until the delay time reaches the preset delay time and then stops outputting the leading-edge blanking signal. The signal processing module has a first input terminal connected to the leading-edge blanking signal generation module, and a second input terminal receiving the overcurrent protection signal generated by the switching power supply system. The signal processing module is used to shield the overcurrent protection signal within the delay time according to the received leading-edge blanking signal.

[0007] In one embodiment, the leading edge blanking signal generation module includes a voltage detection circuit and a delay circuit. The output terminal of the voltage detection circuit is connected to the input terminal of the delay circuit. The voltage detection circuit is used to start the delay circuit when a preset voltage threshold is detected, and to stop outputting the leading edge blanking signal after the delay time reaches the preset delay time.

[0008] In one embodiment, the voltage detection circuit includes a resistor divider network and a first comparator. The input terminal of the resistor divider network is connected to the controlled terminal of the power transistor, the output terminal of the resistor divider network is connected to the inverting input terminal of the first comparator, the non-inverting input terminal of the first comparator receives a leading-edge blanking reference voltage, and the output terminal of the first comparator is connected to the delay circuit; wherein, The resistor divider network divides the voltage at the controlled terminal of the power transistor and outputs the divided voltage to the inverting input terminal of the first comparator. The leading-edge blanking reference voltage is greater than the voltage obtained by dividing the Miller plateau voltage of the power transistor through the resistor divider network, and less than the high-level voltage obtained by dividing the voltage of the controlled terminal of the power transistor through the resistor divider network.

[0009] In one embodiment, the resistor divider network includes a first resistor and a second resistor. A first end of the first resistor is connected to the controlled terminal of the power transistor, and a second end of the first resistor is connected to the first end of the second resistor. The second end of the second resistor is grounded, and the second end of the first resistor is also connected to the inverting input terminal of the first comparator.

[0010] In one embodiment, the delay circuit includes a second comparator, a flip-flop, a first capacitor, and a charge / discharge control circuit. The reset terminal of the flip-flop is connected to the output terminal of the first comparator, the set terminal of the flip-flop is connected to the signal processing module, the output terminal of the flip-flop is connected to the input terminal of the charge / discharge control circuit, the output terminal of the charge / discharge control circuit is connected to the first terminal of the first capacitor, the second terminal of the first capacitor is grounded, the inverting input terminal of the second comparator is connected to the output terminal of the charge / discharge control circuit, and the non-inverting input terminal of the second comparator receives the leading-edge blanking reference voltage. The trigger is configured to output a charge / discharge control signal to the charge / discharge control circuit when it receives the turn-on control signal output by the signal processing module, so as to trigger the charge / discharge control circuit to discharge the first capacitor; the trigger is also configured to output a charge / discharge control signal to the charge / discharge control circuit when it receives the first control signal, so as to trigger the charge / discharge control circuit to charge the first capacitor, wherein the levels of the first control signal and the turn-on control signal are in different states at the same time; The second comparator is used to output the second control signal to the signal processing module when the voltage on the first capacitor is greater than the leading-edge blanking reference voltage.

[0011] In one embodiment, the charge / discharge control circuit includes a first electronic switch, a second electronic switch, and a current source. The first electronic switch and the second electronic switch are complementary switch pairs connected in series between the power supply and ground. The controlled terminal of the first electronic switch is connected to the controlled terminal of the second electronic switch, and the controlled terminal of the first electronic switch is also connected to the output terminal of the trigger. The first electronic switch and the second electronic switch are switched on and off alternately under the control of the trigger, charging the first capacitor during the leading edge blanking time and discharging the first capacitor during the power transistor turn-off period; The second terminal of the first electronic switch is connected to the current source, and the third terminal of the first electronic switch is grounded through the first capacitor and connected to the second terminal of the second electronic switch to form an output terminal. The third terminal of the second electronic switch is grounded.

[0012] In one embodiment, the signal processing module includes a NAND gate, an AND gate, and a flip-flop. The first input of the NAND gate is connected to the output of the leading-edge blanking signal generation module, the second input of the NAND gate is connected to the output of the flip-flop, the first input of the AND gate is connected to the output of the NAND gate, the second input of the AND gate receives the overcurrent protection signal, the reset terminal of the flip-flop is connected to the output of the AND gate, and the set terminal of the flip-flop receives the power transistor turn-on signal output by the switching power supply system. The NAND gate is used to output an OCP shielding signal during the blanking period at the leading edge of the power transistor's conduction. The AND gate is used to shield the overcurrent protection signal when the OCP shielding signal is received, and the AND gate outputs a turn-off signal; The trigger outputs the turn-on control signal. The trigger is used to control the turn-on and turn-off of the power transistor. The trigger turns off the power transistor when it receives the turn-off signal and turns on the power transistor when it receives the power transistor turn-on signal.

[0013] In one embodiment, the leading-edge blanking circuit further includes a power transistor driving module and a power supply management module. The first input terminal of the power transistor driving module is connected to the output terminal of the flip-flop. The enable terminal of the power transistor driving module is connected to the power supply management module to receive an enable signal. The output terminal of the power transistor driving module is connected to the controlled terminal of the power transistor. The input terminal of the power supply management module is connected to the power supply pin in the switching power supply system. The output terminal of the power supply management module is connected to an internal node of the leading-edge blanking circuit, the internal node including a power supply node and other voltage signal nodes. The power transistor drive module is used to output a power transistor drive voltage to the controlled terminal of the power transistor when receiving the enable signal and the turn-on control signal, thereby controlling the turn-on and turn-off of the power transistor. The power supply management module is used to convert the power supply voltage provided by the power supply pin of the switching power supply system into the leading edge blanking reference voltage, the enable signal and the internal power supply voltage, and output the leading edge blanking reference voltage to the first comparator and the second comparator, output the enable signal to the enable terminal of the power transistor drive module, and output the internal power supply voltage to the leading edge blanking circuit to power the leading edge blanking circuit.

[0014] The present invention also proposes a switching power supply controller, comprising: The leading-edge blanking circuit described above; A constant voltage / constant current module detects signals from the switching power supply system and provides power transistor turn-on signals and overcurrent protection signals to the leading-edge blanking circuit. A current detection circuit is provided, wherein the input terminal of the current detection circuit is connected to the current output path of the power transistor, and the output terminal of the current detection circuit is connected to the constant voltage / constant current module. The current detection circuit is used to detect the current signal flowing through the power transistor and output the current detection signal to the constant voltage / constant current module.

[0015] The present invention also proposes a switching power supply system, including the switching power supply controller described above.

[0016] This invention uses a leading-edge blanking signal generation module to detect the voltage V output to the controlled terminal of power transistor M1. GATE And automatically detect the controlled voltage V of the power transistor GATEThe delay begins at a specific time, during which a leading-edge blanking signal is output to the signal processing module. This continues until the preset delay time is reached. Based on the received leading-edge blanking signal, the signal processing module shields the overcurrent protection signal OCP during the delay time. After the delay time ends, it normally receives the overcurrent protection signal and turns off the power transistor when the overcurrent protection signal arrives. This invention solves the technical problem that a fixed leading-edge blanking time TLEB cannot adaptively adjust with changes in power transistor size, resulting in the inability to completely shield the current spike at the moment of high-power transistor turn-on. This is achieved by adjusting the gate voltage V of the power transistor... GATE Rise to the leading edge blanking reference voltage V REF_LEB The required time TR is incorporated into the leading-edge blanking time TLEB, so that the leading-edge blanking time TLEB can completely cover the time when the current spike occurs. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a signal flow diagram of an embodiment of the front blanking circuit of the present invention; Figure 2 This is a signal flow diagram of another embodiment of the front blanking circuit of the present invention; Figure 3 This is a schematic diagram of the circuit structure of an embodiment of the front blanking circuit of the present invention; Figure 4 This is a schematic diagram of the circuit structure of an embodiment of the front blanking circuit of the present invention applied to a primary-side feedback switching power supply system; Figure 5 This is a schematic diagram of the circuit structure of an embodiment of the front blanking circuit of the present invention applied to a secondary-side feedback switching power supply system; Figure 6 This is the leading-edge blanking control timing waveform of an embodiment of the primary-side feedback switching power supply system of the present invention.

[0020] Explanation of icon numbers: 10. Switching power supply system; 10A, primary-side feedback switching power supply system; 10B, Secondary-side feedback switching power supply system; 100, Switching power supply controller; 100A, Primary-side feedback switching power supply controller; 100B, Secondary-side feedback switching power supply controller; D3, bridge rectifier circuit; TX1, transformer; Lp, primary winding; Ls, secondary winding; La, auxiliary winding; M1, power transistor; R4, sampling resistor; C3, filter capacitor; V FB Feedback voltage; V CS Sampling voltage; VDD, power supply pin; Vaux, voltage of auxiliary winding; CV / CC, constant voltage / constant current module; 200, leading edge blanking circuit; 201. Leading edge blanking signal generation module; 201A. Voltage detection circuit; 201B. Delay circuit; 202. Signal processing module; DRV and power transistor driver module; 19. Power supply management module; V GATE Power transistor drive voltage; V G_DIV Power transistor gate voltage divider; V REF_LEB 1. Leading-edge blanking reference voltage; 11. First comparator; TR_EN, first control signal; 13, flip-flop; 13A, 13B, NAND gates that constitute the flip-flop; TON, conduction control signal; I0, current source; Q1, charge / discharge control signal; 17. Charge / discharge control circuit; K1, K2, electronic switches; C21, first capacitor; V B 12. Voltage of the first capacitor; 13. Second comparator; 14. ENA, second control signal; 15. NAND gate; 16. OCP shielding signal; 17. OCP overcurrent protection signal; 18. AND gate; ENB, Off signal; 14, RS flip-flop; QR, Valley turn-on signal; EN, Enable signal; TLEB, leading edge blanking time; TR, first delay time; T LEB1 Second delay time; LEB, leading edge blanking signal; 300, secondary side feedback circuit.

[0021] The purpose, features, and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0023] It should be noted that if the embodiments of the present invention involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0024] Furthermore, if the embodiments of this invention involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of the various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by this invention.

[0025] This invention proposes a leading-edge blanking circuit 200, which is applied in a switching power supply system 10.

[0026] In this embodiment, the switching power supply system 10 includes a switching power supply controller 100, a bridge rectifier circuit D3, a power transistor M1, and a transformer TX1.

[0027] The switching power supply controller 100 is used to detect the status of the switching power supply system 10 and control the on and off states of the power transistor M1. The input terminals of the bridge rectifier circuit D3 are connected to the neutral wire N and the live wire L, respectively, to receive the external AC input voltage V. acThe output terminal is grounded through the filter capacitor C3. The output terminal of the bridge rectifier circuit D3 is also connected to the power supply pin VDD after passing through the resistor R3. The power supply pin VDD supplies power to the leading-edge blanking circuit 200 through the power management module 19. The input terminal of the transformer TX1 is connected to the output terminal of the bridge rectifier circuit D3. It has a primary winding Lp, a secondary winding Ls, and an auxiliary winding La. The secondary winding Ls is used as the output of the switching power supply system 10 after passing through the half-wave rectifier filter circuit. The output voltage of the switching power supply system 10 is Vout, the output current is Iout, and the current flowing through the secondary winding Ls is Isk. The half-wave rectifier filter circuit includes a diode D1, a capacitor C1, and a resistor R1. The first terminal of the secondary winding Ls is connected to the anode of the diode D1, the cathode of the diode D1 is connected to the first terminal of the capacitor C1, the second terminal of the capacitor C1 is grounded, and the second terminal of the capacitor C1 is also grounded to the second terminal of the secondary winding Ls. The resistor R1 is connected in parallel across the two terminals of the capacitor C1. The voltage Vaux of the auxiliary winding is divided by feedback resistors R5 and R6 to obtain the feedback voltage V. FB The voltage is input to the constant voltage / constant current module CV / CC of the switching power supply controller 100. The drain of the power transistor M1 is connected to the primary winding Lp, and its gate receives the power transistor drive voltage V. GATE The source is grounded through the sampling resistor R4.

[0028] An RCD snubber circuit is connected in parallel across the primary winding Lp of transformer TX1. This circuit includes a resistor R2, a capacitor C2, and a diode D2. The resistor R2 and capacitor C2 are connected in parallel and then in series with diode D2. The current flowing through the primary winding Lp is Ipk. The RCD snubber circuit absorbs the voltage spike generated by the leakage inductance of transformer TX1 when power transistor M1 is turned off, clamping the voltage across the primary winding Lp within a safe threshold, thus protecting power transistor M1 from overvoltage breakdown and reducing electromagnetic interference. During demagnetization, transformer TX1 undergoes flyback demagnetization. The secondary winding Ls and auxiliary winding La release the magnetic energy stored in transformer TX1 during the conduction of power transistor M1. This magnetic energy is released to the output through the secondary winding Ls and to the power supply pin VDD through the auxiliary winding La, thus transferring energy. The auxiliary winding La is connected to the power supply pin VDD after passing through diode D4. At the end of demagnetization, the voltage Vaux of the auxiliary winding is a periodic ringing waveform, which can be proportionally transmitted to the feedback voltage V. FB Above, when the ringing waveform reaches its lowest point, the feedback voltage V FB A voltage waveform of -0.3 to -0.6V appears, and the time is approximately 1 / 4 of the ringing cycle of transformer TX1. After the constant voltage / constant current module CV / CC detects this, it outputs the valley detection signal QR.

[0029] As a preferred embodiment, the switching power supply system 10 is a primary-side feedback switching power supply system 10A ( Figure 4In a primary-side feedback switching power supply system 10A, the feedback voltage V FB The voltage Vaux is directly taken from the auxiliary winding, eliminating the need for secondary-side optocouplers, resulting in low cost and simple structure.

[0030] As a preferred embodiment, the power transistor M1 is a silicon carbide (SiC) power transistor. SiC power transistors offer faster switching speeds and lower switching losses. The peak voltage generated during the turn-on transient is shorter in duration and lower in energy, which helps reduce the switching stress and power consumption of the power transistor itself. Simultaneously, due to the smaller gate capacitance of the SiC power transistor, the rise time TR of its gate drive voltage is correspondingly shortened. This allows the leading-edge blanking time TLEB generated by this invention to be compressed to the minimum necessary width while effectively shielding the turn-on spike. This, in turn, prevents false triggering of the overcurrent protection signal OCP while maximizing the system's response sensitivity to real overcurrent events. Furthermore, the high withstand voltage and low on-resistance characteristics of the SiC power transistor enable the switching power supply system 10 using this invention to reliably adapt to a wider range of output power levels, making it particularly suitable for demanding applications such as high-frequency and high-power-density applications.

[0031] In a preferred embodiment, the power transistor turn-on signal is the valley conduction signal QR, and the switching power supply system 10 operates in discontinuous conduction mode (DCM). The core trigger signal of the control logic of this invention is the valley conduction signal QR. Its physical premise is that the transformer TX1 undergoes free resonance after demagnetization, generating a periodic ringing waveform. After the constant voltage / constant current module CV / CC detects the ringing waveform, it outputs the valley conduction signal QR. After the valley conduction signal QR is received by the set terminal of the RS flip-flop 14, it triggers a new round of conduction of the power transistor M1.

[0032] Reference Figures 1 to 6 In one embodiment of the present invention, the leading-edge blanking circuit 200 includes: The leading-edge blanking signal generation module 201 is connected to the controlled terminal of the power transistor M1. The leading-edge blanking signal generation module 201 is used to detect the voltage V output to the controlled terminal of the power transistor. GATE Since the detection of the controlled terminal voltage V of the power transistor GATE The delay begins from the moment when the leading edge blanking signal LEB is output, and the output of the leading edge blanking signal LEB stops when the delay time reaches the preset delay time. The signal processing module 202 has its first input terminal connected to the leading edge blanking signal generation module 201, and its second input terminal receiving the overcurrent protection signal OCP generated by the switching power supply system 10. The signal processing module 202 is used to shield the overcurrent protection signal OCP within the delay time according to the received leading edge blanking signal LEB.

[0033] In this embodiment, the specific implementation of the leading-edge blanking signal generation module 201 can be flexibly selected: one is to implement it using hardware circuitry, for example, through voltage detection circuit 201A and delay circuit 201B (which can be built from discrete components or integrated into a dedicated chip); the other is to use software timing, that is, to use the MCU to detect the voltage V at the controlled terminal of the power transistor. GATE When the voltage reaches a preset value, the MCU internally delays the signal output for a certain period of time. In this embodiment, a hardware circuit solution is adopted, which can be implemented using integrated chips or a combination of discrete components.

[0034] The leading-edge blanking signal generation module 201 is used to enable the power transistor M1 (power transistor drive voltage V). GATE When the voltage exceeds the Miller plateau voltage, the leading-edge blanking signal LEB shields the conduction spike current caused by the parasitic capacitance of power transistor M1, avoiding erroneous protection actions due to conduction spikes. The leading-edge blanking time TLEB is the preset delay time of the leading-edge blanking signal generation module 201. The preset delay time must completely cover the duration of the conduction spike of power transistor M1. In some embodiments, the preset delay time is set between approximately 200ns and 650ns. The preset delay time includes a first delay time TR and a second delay time T. LEB1 The first delay time TR is the power transistor drive voltage V. GATE From low level to leading-edge blanking reference voltage V REF_LEB The time, the second delay time T LEB1 It is a fixed delay time, where the power transistor drive voltage V GATE The rise time is affected by the gate capacitance of power transistor M1, and the power transistor drive voltage V GATE The rise time is proportional to the total resistance of the drive circuit and the input capacitance of the power transistor. Under the same charging voltage, the power transistor with a larger gate capacitance will have a faster rise time when charged to the same leading-edge blanking reference voltage V. REF_LEB The first delay time TR required is longer, resulting in a longer total leading-edge blanking time TLEB, thus meeting the blanking requirements of different power transistors M1. The second delay time T LEB1 The setting is to ensure that the leading-edge blanking time TLEB can fully cover the duration of the conduction spike current.

[0035] In this embodiment, the specific implementation of the signal processing module 202 can be flexibly chosen: it can be implemented using digital logic gate circuits (such as NAND gates and AND gates in series), or it can be implemented using analog switches / transmission gates. This module can be integrated into the switching power supply control chip, or it can be built using discrete logic devices, working in conjunction with the leading-edge blanking signal generation module 201 to complete the blanking function. In this embodiment, digital logic gate circuits are used.

[0036] When the switching power supply system 10 is operating, the signal processing module 202 controls the power transistor M1 to turn on / off at a corresponding frequency. In DCM mode, by setting a sufficiently long turn-off time, it ensures that the inductor current rises from zero in each switching cycle and returns to zero completely before the end, allowing the circuit to sequentially experience three stages: energy storage, energy release, and discontinuous resonance. The energy from the discontinuous resonance is transferred to the switching power supply controller 100. After processing by the switching power supply controller 100, it is sent to the signal processing module 202 inside the switching power supply controller 100 to turn on the power transistor M1. When the switching power supply controller 100 detects that the current flowing through the power transistor M1 exceeds the threshold within the leading edge blanking time TLEB, it does not turn off the power transistor M1. When the switching power supply controller 100 detects that the current flowing through the power transistor M1 exceeds the threshold outside the leading edge blanking time TLEB, it generates an overcurrent protection signal OCP to the signal processing module 202 to turn off the power transistor M1.

[0037] The signal processing module 202 receives the leading-edge blanking signal LEB and the overcurrent protection signal OCP. During the leading-edge blanking signal LEB, the overcurrent protection signal OCP is shielded. If the overcurrent protection signal OCP is received after the leading-edge blanking time TLEB ends, the power transistor M1 is turned off. When the current flowing through the power transistor M1 exceeds the limit, the constant voltage / constant current module CV / CC of the switching power supply controller 100 generates the overcurrent protection signal OCP and inputs it to the signal processing module 202. Upon receiving the overcurrent protection signal OCP, the signal processing module 202 determines whether to shield the overcurrent protection signal OCP based on the leading-edge blanking signal LEB. During the leading-edge blanking time TLEB, even if the signal processing module 202 receives the overcurrent protection signal OCP, it will not turn off the power transistor M1 to shield the conduction spike current caused by the parasitic capacitance of the power transistor M1. After the leading-edge blanking time TLEB ends, upon receiving the overcurrent protection signal OCP, the power transistor M1 is immediately turned off. It is understandable that the controlled terminal voltage, the power transistor drive voltage, and the power transistor gate voltage refer to the same voltage signal.

[0038] This invention uses a leading-edge blanking signal generation module 201 to detect the voltage V output to the controlled terminal of the power transistor. GATE And automatically detect the voltage V at the controlled terminal of the power transistor. GATEThe delay begins at a certain time, during which a leading-edge blanking signal LEB is output to the signal processing module 202. This continues until the preset delay time is reached. Based on the received leading-edge blanking signal LEB, the signal processing module 202 shields the overcurrent protection signal OCP during the delay time, and normally receives the overcurrent protection signal OCP after the delay time ends. When the overcurrent protection signal OCP arrives, the power transistor M1 is turned off. This invention solves the technical problem that a fixed leading-edge blanking time TLEB cannot adaptively adjust with changes in the size of the power transistor M1, resulting in the current spike at the moment of high-power transistor turn-on not being completely shielded. This is achieved by adjusting the power transistor drive voltage V... GATE Rise to the leading edge blanking reference voltage V REF_LEB The required first delay time TR is incorporated into the leading-edge blanking time TLEB, so that the leading-edge blanking time TLEB can fully cover the time when the current spike occurs.

[0039] Please refer to Figure 1 and Figure 2 The leading edge blanking signal generation module 201 includes a voltage detection circuit 201A and a delay circuit 201B. The output terminal of the voltage detection circuit 201A is connected to the input terminal of the delay circuit 201B. The voltage detection circuit 201A is used to start the delay circuit 201B when a preset voltage threshold is detected, and to stop outputting the leading edge blanking signal LEB after the delay time reaches the preset delay time.

[0040] Voltage detection circuit 201A is used to compare the gate voltage V of the power transistor. GATE and leading edge blanking reference voltage V REF_LEB Power transistor gate voltage V GATE Rise to the leading edge blanking reference voltage V REF_LEB The required time is the first delay time TR. The delay circuit 201B delays the time by charging the first capacitor C21. The time required for the first capacitor C21 to charge to a reference voltage is the second delay time T. LEB1 The sum of the two delay times is the leading edge blanking time TLEB.

[0041] Reference Figure 3 or Figure 4 In one embodiment, the voltage detection circuit 201A includes a resistor divider network and a first comparator 11. The input terminal of the resistor divider network is connected to the controlled terminal of the power transistor M1, and the output terminal of the resistor divider network is connected to the inverting input terminal of the first comparator 11. The non-inverting input terminal of the first comparator 11 receives the leading-edge blanking reference voltage V. REF_LEB The output of the first comparator 11 is connected to the delay circuit 201B, and the first comparator 11 outputs a first control signal TR_EN; wherein, The voltage V at the controlled terminal of the power transistor via the resistor divider network GATEPerform voltage division and output the divided voltage V. G_DIV To the inverting input of the first comparator 11; Leading edge blanking reference voltage V REF_LEB The voltage is greater than the Miller plateau voltage of power transistor M1 after being divided by a resistor divider network, and less than the voltage V at the controlled terminal of the power transistor. GATE The high-level voltage after being divided by a resistor divider network.

[0042] The gate voltage V of the power transistor after voltage division by the resistor divider network in the voltage detection circuit 201A G_DIV Exceeding the leading edge blanking reference voltage V REF_LEB The time is the first delay time TR.

[0043] The function of the resistor voltage divider network is to control the voltage V at the controlled terminal of power transistor M1. GATE The voltage is typically between 12V and 20V, while the withstand voltage of the first comparator 11 is usually around 5V. The resistor divider network divides the controlled terminal voltage V of the power transistor M1. GATE Proportional reduction to the gate voltage V of the power transistor G_DIV This ensures that the voltage falls within the allowable range of the internal low-voltage circuit, protecting the first comparator 11 from being damaged by high voltage.

[0044] Leading edge blanking reference voltage V REF_LEB The voltage obtained by dividing the Miller plateau voltage of the power transistor M1 by a resistor divider network is greater than the voltage obtained by the Miller plateau voltage. This setting ensures that the leading-edge blanking time TLEB can completely cover the current spike at the moment the power transistor turns on, avoiding false triggering of overcurrent protection due to insufficient blanking coverage caused by the premature end of the first delay time TR. Leading-edge blanking reference voltage V REF_LEB Less than the gate voltage V of the power transistor G_DIV The high-level voltage is set in this way to ensure that the leading-edge blanking time TLEB is not too long, which would slow down the switching speed of the power transistor M1.

[0045] In a preferred example, the gate voltage divider V of the power transistor can be set. G_DIV With Miller platform voltage divider V P The difference between them is ΔV ≥ 2V (i.e., V G_DIV >V P +ΔV) to fully cover the effects of process angle deviation and temperature drift, ensuring that the power transistor M1 can trigger the first control signal TR_EN toggles only after it is fully turned on under various operating conditions.

[0046] In one embodiment, the resistor divider network includes a first resistor RG1 and a second resistor RG2. The first end of the first resistor RG1 is connected to the controlled terminal of the power transistor M1, the second end of the first resistor RG1 is connected to the first end of the second resistor RG2, the second end of the second resistor RG2 is grounded, and the second end of the first resistor RG1 is also connected to the inverting input terminal of the first comparator 11.

[0047] In this embodiment, the first resistor RG1 and the second resistor RG2 form a resistor divider network, which is used to divide the controlled terminal voltage V of the power transistor. GATE Proportional reduction to the gate voltage V of the power transistor G_DIV This ensures that the voltage falls within the allowable range of the internal low-voltage circuit, protecting the first comparator 11 from being damaged by high voltage.

[0048] Power transistor gate voltage divider V G_DIV and the controlled terminal voltage V of the power transistor GATE The following relationship must be satisfied: V G_DIV =V GATE ×RG2 / (RG1+RG2)

[0049] In one embodiment, the delay circuit 201B includes a second comparator 12, a flip-flop 13, a first capacitor C21, and a charge / discharge control circuit 17. The reset terminal of the flip-flop 13 is connected to the output terminal of the first comparator 11, the set terminal of the flip-flop 13 is connected to the signal processing module 202, the output terminal of the flip-flop 13 is connected to the input terminal of the charge / discharge control circuit 17, the output terminal of the charge / discharge control circuit 17 is connected to the first terminal of the first capacitor C21, the second terminal of the first capacitor C21 is grounded, the inverting input terminal of the second comparator 12 is connected to the output terminal of the charge / discharge control circuit 17, and the non-inverting input terminal of the second comparator 12 receives the leading-edge blanking reference voltage V. REF_LEB ;in, When the trigger 13 receives the turn-on control signal TON from the signal processing module 202, it outputs the charge-discharge control signal Q1 to the charge-discharge control circuit 17 to trigger the charge-discharge control circuit 17 to discharge the first capacitor C21. The trigger 13 is also used to output the charge-discharge control signal Q1 to the charge-discharge control circuit 17 when it receives the first control signal TR_EN to trigger the charge-discharge control circuit 17 to charge the first capacitor C21. The levels of the first control signal TR_EN and the turn-on control signal TON are in different states at the same time. The second comparator 12 is used to measure the voltage V across the first capacitor C21. B Greater than the leading edge blanking reference voltage V REF_LEB At that time, the second control signal ENA is output to the signal processing module 202.

[0050] In this embodiment, flip-flop 13 is an RS flip-flop coupled with two NAND gates 13A and 13B. Flip-flop 13 is used to receive the first control signal TR_EN output by the first comparator 11, when the gate voltage of the power transistor is V... G_DIV Exceeding the leading edge blanking reference voltage V REF_LEB When the delay of voltage detection circuit 201A ends, the first control signal TR_EN will flip to the active state, resetting flip-flop 13. The charge / discharge control signal Q1 output by flip-flop 13 will then become active, initiating charging of the first capacitor C21 and performing the second delay. When the voltage V on the first capacitor C21... B From the start of the rise to exceeding the leading-edge blanking reference voltage V REF_LEB The preceding period is the second delay time T. LEB1 When the delay ends, the second control signal ENA output by the second comparator 12 will become invalid, and the leading edge blanking time TLEB will end.

[0051] Reference Figure 3 In one embodiment, the charge and discharge control circuit 17 includes a first electronic switch K1, a second electronic switch K2 and a current source I0. The first electronic switch K1 and the second electronic switch K2 are complementary switch pairs connected in series between the power supply and ground. The controlled terminal of the first electronic switch K1 is connected to the controlled terminal of the second electronic switch K2. The controlled terminal of the first electronic switch K1 is also connected to the output terminal of the trigger 13. The first electronic switch K1 and the second electronic switch K2 are switched on and off alternately under the control of the trigger 13. The first capacitor C21 is charged during the leading edge blanking time TLEB and the first capacitor C21 is discharged during the period when the conduction control signal TON is low. The second terminal of the first electronic switch K1 is connected to the current source I0. The third terminal of the first electronic switch K1 is grounded through the first capacitor C21 and connected to the second terminal of the second electronic switch K2 to form an output terminal. The third terminal of the second electronic switch K2 is grounded.

[0052] The first electronic switch K1 is a P-type switch that turns on when low and off when high, and the second electronic switch K2 is an N-type switch that turns on when high and off when low. When the charge / discharge control signal Q1 is high, the first electronic switch K1 is off, the second electronic switch K2 is on, and the first capacitor C21 discharges; when the charge / discharge control signal Q1 is low, the first electronic switch K1 is on, the second electronic switch K2 is off, and the current source I0 charges the first capacitor C21. In this embodiment, the first electronic switch K1 and the second electronic switch K2 can be implemented using transistors, IGBTs, MOSFETs, or other electronic switches; no limitation is imposed here.

[0053] In this embodiment, the second delay time T LEB1 It can be calculated using the following formula: T LEB1 = (V REF_LEB ×C21) / I0 Among them, V REF_LEB I0 is the leading edge blanking reference voltage, I0 is the current provided by the current source, and C21 is the capacitance of the first capacitor.

[0054] In one embodiment, the signal processing module 202 includes a NAND gate 15, an AND gate 16, and a flip-flop 14. The first input of the NAND gate 15 is connected to the output of the leading edge blanking signal generation module 201, the second input of the NAND gate 15 is connected to the output of the flip-flop 14, the first input of the AND gate 16 is connected to the output of the NAND gate 15, the second input of the AND gate 16 receives an overcurrent protection signal OCP, the reset terminal of the flip-flop 14 is connected to the output of the AND gate 16, and the set terminal of the flip-flop 15 receives a power transistor turn-on signal output by the switching power supply system 10. NAND gate 15 is used to output the OCP masking signal during the blanking period at the leading edge of the power transistor's conduction. AND gate 16 is used to shield the overcurrent protection signal OCP when the OCP masking signal OCP Masking is received, and AND gate 16 outputs the turn-off signal ENB; Flip-flop 14 outputs a turn-on control signal TON, which is used to control the turn-on and turn-off of power transistor M1. When flip-flop 14 receives a turn-off signal ENB, it turns off power transistor M1, and when it receives a power transistor turn-on signal, it turns on power transistor M1.

[0055] During the leading-edge blanking time TLEB, both the second control signal ENA and the turn-on control signal TON received by NAND gate 15 are at a high level, outputting a low-level OCP masking signal OCP Masking to AND gate 16. At this time, regardless of whether the overcurrent protection signal OCP is valid, the turn-off signal ENB output by AND gate 16 will be at a low level. After the leading-edge blanking time TLEB ends, the OCP masking signal OCP Masking flips to a high level. At this time, the output of AND gate 16 is only determined by the overcurrent protection signal OCP. When the overcurrent protection signal OCP arrives, AND gate 16 outputs the turn-off signal ENB to RS flip-flop 14, turning off the power transistor M1. During the turn-off process of power transistor M1, when the set terminal of RS flip-flop 14 receives the valley turn-on signal QR, a new round of conduction of power transistor M1 is started. The valley turn-on signal QR is the power transistor turn-on signal.

[0056] Reference Figure 3 or Figure 4In one embodiment, the leading-edge blanking circuit 200 further includes a power transistor driver module DRV and a power management module 19. The first input terminal of the power transistor driver module DRV is connected to the output terminal of the flip-flop 14. The enable terminal of the power transistor driver module DRV is connected to the power management module 19 and receives an enable signal EN. The output terminal of the power transistor driver module DRV is connected to the controlled terminal of the power transistor M1. The input terminal of the power management module 19 is connected to the power supply pin VDD in the switching power supply system 10. The output terminal of the power management module 19 is connected to the internal nodes of the leading-edge blanking circuit 200, including power supply nodes and other voltage signal nodes. The power transistor driver module DRV is used to output the power transistor drive voltage V when receiving the enable signal EN and the turn-on control signal TON. GATE The circuit connects to the controlled terminal of power transistor M1 to control the on and off states of power transistor M1. The power management module 19 is used to convert the power supply voltage provided by the power supply pin VDD in the switching power supply system 10 into the leading-edge blanking reference voltage V. REF_LEB The enable signal EN and the internal supply voltage are used, and the leading-edge blanking reference voltage V is also used. REF_LEB The output is sent to the first comparator 11 and the second comparator 12, the enable signal EN is output to the enable terminal of the power transistor driver module DRV, and the internal power supply voltage is output to the leading edge blanking circuit 200 to power the leading edge blanking circuit 200.

[0057] When the enable signal EN is high, the power transistor driver module DRV is allowed to operate; when the enable signal EN is low, the power transistor driver module DRV is not allowed to operate, and the power transistor drive voltage V is forced. GATE When the voltage is low, power transistor M1 is off, and the switching power supply system 200 stops operating. The power management module 19 receives the power supply voltage from the power supply pin VDD and outputs a leading-edge blanking reference voltage V after the voltage exceeds the power-on threshold. REF_LEB The enable signal EN and the internal power supply voltage, which powers the internal chip, are the leading-edge blanking reference voltage V. REF_LEB The reference value can be adjusted using laser to meet the accuracy requirements.

[0058] Reference Figures 3 to 6 To better illustrate the inventive concept of this invention, the working principle of this invention will be explained below in conjunction with the above-mentioned embodiments: After the power transistor M1 is turned off, the voltage Vaux of the auxiliary winding is transferred to the feedback voltage V at the end of demagnetization. FB Above, when the ringing waveform reaches its lowest point, the feedback voltage V FBA voltage waveform of -0.3 to -0.6V appears. Upon detection by the constant voltage / constant current module CV / CC, it outputs a high-level valley detection signal QR. After receiving the valley detection signal QR, RS flip-flop 14 outputs a high-level turn-on control signal TON. Upon receiving the high-level turn-on control signal TON, the power transistor driver module DRV outputs a drive voltage to the gate of power transistor M1. The resistor divider network affects the gate voltage V of the power transistor. GATE After voltage division, the resulting gate voltage V of the power transistor is obtained. G_DIV The input is given to the inverting input of the first comparator circuit 11, and the non-inverting input of the first comparator circuit 11 receives the leading-edge blanking reference voltage V. REF_LEB At the gate of the power transistor, the voltage V is divided. G_DIV Exceeding the leading edge blanking reference voltage V REF_LEB When the first control signal TR_EN output by the first comparator 11 flips from high to low, the flip-flop 13 is reset, and the output voltage of the flip-flop 13 flips from high to low. The first electronic switch K1 is turned on, the second electronic switch K2 is turned off, and the current source I0 begins to charge the first capacitor C21. When the voltage V on the first capacitor C21... B Exceeding the leading edge blanking reference voltage V REF_LEB When this happens, the output signal of the second comparator 12, the second control signal ENA, will flip from high to low, and the gate voltage V of the power transistor will be affected. GATE The period from the start of the rise until the second control signal ENA flips to a low level is the leading-edge blanking time TLEB. During the leading-edge blanking time TLEB, the second control signal ENA is high, the turn-on control signal TON is also high, and the OCP masking signal OCP Masking output of NAND gate 15 is low. At this time, the output of AND gate 16 is clamped to a low level by the low-level OCP masking signal OCP Masking, and the output level will not change regardless of the level of the overcurrent protection signal OCP. After the leading-edge blanking time TLEB ends, the second control signal ENA is low, and the OCP masking signal OCP Masking output of NAND gate 15 is high. The output signal of AND gate 16 is determined by the overcurrent protection signal OCP. When the overcurrent protection signal OCP is received, AND gate 16 outputs a high-level turn-off signal ENB, the turn-on control signal TON of RS flip-flop 14 flips to a low level, controlling the power transistor driver module DRV to stop outputting the drive voltage to power transistor M1, power transistor M1 turns off, and the conduction cycle ends.

[0059] Reference Figure 5 The present invention proposes a switching power supply controller 100, which operates in the aforementioned switching power supply system 10, comprising: The leading-edge blanking circuit 200 as described above; The constant voltage / constant current module CV / CC detects the signals of the switching power supply system 10 and provides the power transistor turn-on signal and overcurrent protection signal OCP to the leading-edge blanking circuit 200. The current detection circuit has its input terminal connected to the current output path of the power transistor M1, and its output terminal connected to the constant voltage / constant current module CV / CC. The current detection circuit is used to detect the current signal flowing through the power transistor M1 and output the current detection signal to the constant voltage / constant current module CV / CC.

[0060] In this embodiment, when the interface FB of the constant voltage / constant current module CV / CC receives the periodic ringing waveform output by the auxiliary winding La of transformer TX1 during the demagnetization phase, it uses an internal comparator or detection circuit to accurately capture the trough position of the ringing waveform and outputs a trough conduction signal QR. When the power transistor M1 is turned on, the constant voltage / constant current module CV / CC detects the voltage V of the sampling resistor R4. CS It is compared with a preset voltage threshold inside the module, and once V is detected... CS If the voltage exceeds the limit, the constant voltage / constant current module CV / CC immediately determines that the current is too high and generates an overcurrent protection signal OCP.

[0061] The current detection circuit detects the voltage V across the sampling resistor R4 via interface CS. CS The current is then output to the constant voltage / constant current module CV / CC, which determines whether the current through the power transistor M1 exceeds the limit. If it does, an overcurrent protection signal OCP is generated and input to the leading-edge blanking circuit 200. The constant voltage / constant current module CV / CC also detects the feedback voltage Vaux after voltage division of the auxiliary winding voltage Vaux of transformer TX1. FB The valley conduction signal QR is generated and input to the leading edge blanking circuit 200. Here, the valley conduction signal QR is the power transistor turn-on signal.

[0062] In addition, the constant voltage / constant current module CV / CC is also used to control the switching power supply system 10 to operate in constant voltage mode or constant current mode. When the load resistance is large and the required current is less than the set value, the power supply operates in constant voltage mode to maintain the set voltage; when the load resistance is small and the required current exceeds the set value, the power supply operates in constant current mode, and the power supply automatically reduces the voltage to limit the current within the set value.

[0063] The present invention proposes a switching power supply system 10, including the switching power supply controller 100 as described above.

[0064] Reference Figure 1 and Figure 2In this embodiment, the switching power supply system 10 is a primary-side feedback switching power supply system 10A, and the switching power supply controller 100 is a primary-side feedback switching power supply controller A100. The power transistor M1 of the primary-side feedback switching power supply system 10A is turned on and off under the control of the primary-side feedback switching power supply controller 100, so that the primary-side feedback switching power supply system 10A operates in discontinuous conduction mode. After the power transistor M1 is turned off, the auxiliary winding La of the transformer TX1 in the primary-side feedback switching power supply system 10A generates a periodic ringing waveform during the demagnetization stage and sends it to the constant voltage / constant current module CV / CC of the switching power supply controller. After receiving the periodic ringing waveform, the constant voltage / constant current module CV / CC outputs a valley conduction signal QR to the leading edge blanking circuit 200 to start a new round of conduction. At the start of conduction, due to the leakage inductance of transformer TX1 and the parasitic capacitance of power transistor M1, a voltage spike signal will appear, which may easily trigger the overcurrent protection mechanism falsely. Therefore, a leading-edge blanking time TLEB needs to be designed to shield the overcurrent protection signal OCP within this leading-edge blanking time TLEB, keeping power transistor M1 in the conducting state. The primary-side feedback switching power supply controller 100A monitors the current flowing through power transistor M1 in real time. During the leading-edge blanking time TLEB, power transistor M1 will not be turned off due to voltage spikes. After the leading-edge blanking time TLEB ends, when the current flowing through power transistor M1 reaches the overcurrent protection threshold, power transistor M1 is turned off, ending one cycle of operation.

[0065] In some embodiments, the switching power supply system 10 is a secondary-side feedback switching power supply system 10B, and the switching power supply controller is a secondary-side feedback switching power supply controller 100B. In the secondary-side feedback switching power supply system 10B, the feedback is taken from the secondary-side feedback circuit 300. The input terminal of the secondary-side feedback circuit 300 is connected to the output terminal of the secondary-side feedback switching power supply system 10B, and the output terminal is connected to the secondary-side feedback switching power supply controller 100B, so as to feed back the current or voltage signal output by the secondary-side feedback switching power supply system 10B to the secondary-side feedback switching power supply controller 100B through the COMP interface.

[0066] The above description is only a part of the embodiments of the present invention and does not limit the patent scope of the present invention. All equivalent structural transformations made under the technical concept of the present invention using the contents of the present invention specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A leading-edge blanking circuit, characterized in that, Applied to a switching power supply system, the switching power supply system includes a power transistor, and the leading-edge blanking circuit includes: A leading-edge blanking signal generation module is connected to the controlled terminal of the power transistor. The leading-edge blanking signal generation module is used to detect the voltage output to the controlled terminal of the power transistor. It starts to delay from the moment the voltage of the controlled terminal of the power transistor is detected, and outputs the leading-edge blanking signal during the delay period until the delay time reaches the preset delay time and then stops outputting the leading-edge blanking signal. The signal processing module has a first input terminal connected to the leading-edge blanking signal generation module, and a second input terminal receiving the overcurrent protection signal generated by the switching power supply system. The signal processing module is used to shield the overcurrent protection signal within the delay time according to the received leading-edge blanking signal.

2. The leading-edge blanking circuit as described in claim 1, characterized in that, The leading edge blanking signal generation module includes a voltage detection circuit and a delay circuit. The output terminal of the voltage detection circuit is connected to the input terminal of the delay circuit. The voltage detection circuit is used to start the delay circuit when a preset voltage threshold is detected, and to stop outputting the leading edge blanking signal after the delay time reaches the preset delay time.

3. The leading-edge blanking circuit as described in claim 2, characterized in that, The voltage detection circuit includes a resistor divider network and a first comparator. The input terminal of the resistor divider network is connected to the controlled terminal of the power transistor, and the output terminal of the resistor divider network is connected to the inverting input terminal of the first comparator. The non-inverting input terminal of the first comparator receives the leading-edge blanking reference voltage, and the output terminal of the first comparator is connected to the delay circuit. The resistor divider network divides the voltage at the controlled terminal of the power transistor and outputs the divided voltage to the inverting input terminal of the first comparator. The leading-edge blanking reference voltage is greater than the voltage obtained by dividing the Miller plateau voltage of the power transistor through the resistor divider network, and less than the high-level voltage obtained by dividing the voltage of the controlled terminal of the power transistor through the resistor divider network.

4. The leading-edge blanking circuit as described in claim 3, characterized in that, The resistor divider network includes a first resistor and a second resistor. The first end of the first resistor is connected to the controlled terminal of the power transistor, the second end of the first resistor is connected to the first end of the second resistor, the second end of the second resistor is grounded, and the second end of the first resistor is also connected to the inverting input terminal of the first comparator.

5. The leading-edge blanking circuit as described in claim 2, characterized in that, The delay circuit includes a second comparator, a flip-flop, a first capacitor, and a charge / discharge control circuit. The reset terminal of the flip-flop is connected to the output terminal of the first comparator, the set terminal of the flip-flop is connected to the signal processing module, the output terminal of the flip-flop is connected to the input terminal of the charge / discharge control circuit, the output terminal of the charge / discharge control circuit is connected to the first terminal of the first capacitor, the second terminal of the first capacitor is grounded, the inverting input terminal of the second comparator is connected to the output terminal of the charge / discharge control circuit, and the non-inverting input terminal of the second comparator receives the leading-edge blanking reference voltage. The trigger is configured to output a charge / discharge control signal to the charge / discharge control circuit when it receives the turn-on control signal output by the signal processing module, so as to trigger the charge / discharge control circuit to discharge the first capacitor; the trigger is also configured to output a charge / discharge control signal to the charge / discharge control circuit when it receives the first control signal, so as to trigger the charge / discharge control circuit to charge the first capacitor, wherein the levels of the first control signal and the turn-on control signal are in different states at the same time; The second comparator is used to output the second control signal to the signal processing module when the voltage on the first capacitor is greater than the leading-edge blanking reference voltage.

6. The leading-edge blanking circuit as described in claim 5, characterized in that, The charging and discharging control circuit includes a first electronic switch, a second electronic switch, and a current source. The first electronic switch and the second electronic switch are complementary switch pairs connected in series between the power supply and ground. The controlled terminal of the first electronic switch is connected to the controlled terminal of the second electronic switch, and the controlled terminal of the first electronic switch is also connected to the output terminal of the trigger. The first electronic switch and the second electronic switch are switched on and off alternately under the control of the trigger, charging the first capacitor during the leading edge blanking time and discharging the first capacitor during the power transistor turn-off period; The second terminal of the first electronic switch is connected to the current source, and the third terminal of the first electronic switch is grounded through the first capacitor and connected to the second terminal of the second electronic switch to form an output terminal. The third terminal of the second electronic switch is grounded.

7. The leading-edge blanking circuit as described in claim 2, characterized in that, The signal processing module includes a NAND gate, an AND gate, and a flip-flop. The first input of the NAND gate is connected to the output of the leading-edge blanking signal generation module. The second input of the NAND gate is connected to the output of the flip-flop. The first input of the AND gate is connected to the output of the NAND gate. The second input of the AND gate receives the overcurrent protection signal. The reset terminal of the flip-flop is connected to the output of the AND gate. The set terminal of the flip-flop receives the power transistor turn-on signal output by the switching power supply system. The NAND gate is used to output an OCP shielding signal during the blanking period at the leading edge of the power transistor's conduction. The AND gate is used to shield the overcurrent protection signal when the OCP shielding signal is received, and the AND gate outputs a turn-off signal; The trigger outputs the turn-on control signal. The trigger is used to control the turn-on and turn-off of the power transistor. The trigger turns off the power transistor when it receives the turn-off signal and turns on the power transistor when it receives the power transistor turn-on signal.

8. The leading-edge blanking circuit as described in claim 7, characterized in that, The leading-edge blanking circuit further includes a power transistor driver module and a power supply management module. The first input terminal of the power transistor driver module is connected to the output terminal of the flip-flop. The enable terminal of the power transistor driver module is connected to the power supply management module to receive an enable signal. The output terminal of the power transistor driver module is connected to the controlled terminal of the power transistor. The input terminal of the power supply management module is connected to the power supply pin in the switching power supply system. The output terminal of the power supply management module is connected to the internal nodes of the leading-edge blanking circuit. The internal nodes include power supply nodes and other voltage signal nodes. The power transistor drive module is used to output a power transistor drive voltage to the controlled terminal of the power transistor when receiving the enable signal and the turn-on control signal, thereby controlling the turn-on and turn-off of the power transistor. The power supply management module is used to convert the power supply voltage provided by the power supply pin of the switching power supply system into the leading edge blanking reference voltage, the enable signal and the internal power supply voltage, and output the leading edge blanking reference voltage to the first comparator and the second comparator, output the enable signal to the enable terminal of the power transistor drive module, and output the internal power supply voltage to the leading edge blanking circuit to power the leading edge blanking circuit.

9. A switching power supply controller, characterized in that: Includes the leading-edge blanking circuit as described in any one of claims 1-8; A constant voltage / constant current module detects signals from the switching power supply system and provides power transistor turn-on signals and overcurrent protection signals to the leading-edge blanking circuit. A current detection circuit is provided, wherein the input terminal of the current detection circuit is connected to the current output path of the power transistor, and the output terminal of the current detection circuit is connected to the constant voltage / constant current module. The current detection circuit is used to detect the current signal flowing through the power transistor and output the current detection signal to the constant voltage / constant current module.

10. A switching power supply system, characterized in that, Includes the switching power supply controller as described in claim 9.

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