Voltage-adjustable high-voltage half-bridge high-side hardware clamping circuit

Abstract

The application discloses a voltage-adjustable high-voltage half-bridge high-side hardware clamping circuit, and relates to the field of integrated circuit design.The circuit comprises a logic control module, a pre-driving module, a driving half-bridge module and a gate-source hardware clamping module.The logic control module drives the pre-driving module according to the current type.The pre-driving module generates a high-side signal and a low-side signal, and constructs an intelligent gate drive architecture of driving mode and holding mode with the logic control module.The high-side MOS receives the high-side signal, and the low-side MOS receives the low-side signal.The gate-source hardware clamping module detects the short circuit of the phase line to the ground and the instantaneous overvoltage of the high-side MOS gate-source, and clamps the voltage, separates the voltage clamping path and the current discharge path, and additionally adds a clamping acceleration circuit to accelerate the clamping.The application can clamp the gate-source voltage difference within 50 nanoseconds in the abnormal condition, does not need to judge by the internal LOGIC module, and can adjust the clamping voltage by adjusting the resistance ratio, and has the characteristics of fast response speed, adjustable clamping voltage and wide clamping current range.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design, and particularly relates to a high-voltage half-bridge high-side hardware clamping circuit with adjustable voltage. Background Technology

[0002] In applications such as power electronics, motor drives, and switching power supplies, the half-bridge topology is widely used due to its advantages such as simple structure and high utilization of magnetic components. However, in high-side driving, the source potential of the switching transistor is floating and jumps rapidly between the DC bus voltage (e.g., several hundred volts) and ground with the switching action. This requires that the gate drive signal must be able to follow the source potential (i.e., refer to "floating ground").

[0003] During high-speed switching, especially under the influence of complex parasitic parameters (such as parasitic inductance), due to the Miller effect, when the low-side switch turns on or a sharp voltage change occurs at the midpoint of the bridge arm, a displacement current is injected into the gate through the gate-drain capacitance of the high-side switch. This current generates a voltage spike across the impedance of the gate circuit, which may cause the gate-source voltage to exceed its absolute maximum rating (typically ±20V), thereby permanently damaging the power device.

[0004] To address this issue, a fast and reliable clamping protection path must be provided between the gate and source of the high-side switching transistor. Traditional protection schemes either use a TVS diode connected in reverse parallel between the gate and source outside the chip for clamping, but this has the problem of an unadjustable clamping voltage, making it unsuitable for power devices with different gate voltage ratings, and it may also be damaged due to excessive dissipation under continuous overvoltage conditions; or a Zener diode directly connected in reverse parallel between the gate and source output terminals inside the chip, or a two-stage clamping circuit composed of Zener diodes, but the current path still needs to be discharged through the Zener diode. For high-current scenarios, the chip requires a very large area of ​​Zener diode to ensure overcurrent discharge, increasing the chip cost; or, although a voltage clamping path and gate-source current discharge are used inside the chip, The separate path solution also suffers from the problem of non-adjustable clamping voltage, making it unsuitable for power devices with different gate withstand voltages. Refer to the content disclosed in Chinese Patent Application Publication No. CN121355819A, "A Short Circuit Protection Circuit for a Half-Bridge Driver Chip"; or it integrates a simple clamping circuit based on bootstrap technology, but still suffers from problems such as non-adjustable clamping voltage and insufficient response speed, and also limits the PWM from being able to output 100% duty cycle; or it uses a clamping circuit with resistor sampling + error amplifier, but its response speed depends on the bandwidth of the error amplifier. If a response speed of 10ns is required, the circuit structure is complex and the static power consumption is large. Summary of the Invention

[0005] To address the aforementioned technical problems in related technologies, this invention proposes a high-voltage half-bridge high-side hardware clamping circuit with adjustable voltage.

[0006] To achieve the above-mentioned objectives, the present invention adopts the following technical solution: This invention provides a voltage-adjustable high-voltage half-bridge high-side hardware clamping circuit, comprising: The logic control module I1 is used to generate different control signals to drive the pre-drive module I2; The pre-driver module I2 is used to generate high-side and low-side signals based on the control signal; The driving half-bridge module I3 includes a first transistor for receiving high-side signals as a high-voltage half-bridge and a second transistor for receiving low-side signals as a low-voltage half-bridge. The gate-source hardware clamping module I4 includes a high-side gate-source voltage clamping circuit, which is connected to the gate and source of the first transistor in the driving half-bridge module I3, and is used to clamp the first transistor when the gate-source voltage is over-voltage. The high-side gate-source voltage clamping circuit includes a first diode, a second diode, a third diode, a fourth diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a third transistor, a fourth transistor, and a tenth transistor; The drain of the third transistor is connected to the gate of the first transistor, and the source is connected to the source of the first transistor. The first diode and the first resistor are connected in parallel between the gate of the third transistor and the gate of the first transistor. The cathode of the second diode is connected to the source of the tenth transistor, and the anode is connected to the gate of the third transistor. The drain of the tenth transistor is connected to the high-side pre-drive power supply through the fifth resistor, and the gate is connected to the high-side floating ground through the third diode and the second resistor in series. The anode of the fourth diode is connected to the source of the tenth transistor and the drain of the fourth transistor, and the cathode is connected to the gate of the tenth transistor and the gate of the fourth transistor, respectively. One end of the third resistor is connected to the source of the tenth transistor and the drain of the fourth transistor, respectively, and the other end is connected to the gate of the tenth transistor and the gate of the fourth transistor, respectively. The source of the fourth transistor is connected to analog ground through the fourth resistor.

[0007] Specifically, when the high-side floating ground SHX is short-circuited to ground, the voltage drop across the first resistor causes the third transistor to turn on. The drive current on the high-side signal H0X drains through the source of the third transistor to the high-side floating ground SHX, ultimately clamping the voltage of the high-side signal H0X at Vpc, as shown in the clamping voltage formula below: , Wherein, Vpc is the positive clamping voltage between the high-side signal HOX and the high-side floating ground SHX; V GS_M3 V is the gate-source voltage of the third transistor. Z_D3 V is the clamping voltage of the third diode. FR1 and R2 are the forward conduction voltages of the second diode, and the resistance values ​​of the first resistor and the second resistor are respectively.

[0008] Specifically, the high-side gate-source voltage clamping circuit further separates the gate-source voltage clamping path from the gate-source current discharge path; The gate-source voltage clamping path consists of a first resistor, a second diode, a fourth diode, a third diode, and a second resistor; the gate-source current discharge path consists of a third transistor.

[0009] Specifically, the gate-source hardware clamping module I4 also includes a clamping acceleration circuit; the clamping acceleration circuit is used to accelerate the activation speed of the high-side gate-source voltage clamping circuit. The clamping acceleration circuit consists of a current mirror bias circuit, a first capacitor, a fourth transistor, and a fourth resistor. The current mirror bias circuit includes a fifth transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor, which mirror the current IREF1 output from the reference module to provide circuit bias for the entire clamping circuit. The drains of the fifth transistor, the twelfth transistor, and the thirteenth transistor are connected to the high-side pre-drive power supply VCP, respectively. The source of the fifth transistor is connected to the source of the fourth transistor. The source of the fifth transistor is also connected to analog ground through a fourth resistor. The gate of the fifth transistor is connected to the gate of the twelfth transistor and the gate of the thirteenth transistor, respectively. Gate connection; the gate-source connection of the twelfth transistor is then connected to the gate of the thirteenth transistor; the source of the thirteenth transistor is connected to the gate of the tenth transistor; the drain of the fourteenth transistor is connected to the source of the twelfth transistor, the source is connected to the drain of the sixteenth transistor, and the gate is connected to the control signal VREF1; the gate-drain connection of the fifteenth transistor is then connected to the gate of the sixteenth transistor, the drain is also connected to the reference current IREF1 output by the reference module, and the source is connected to analog ground; the gate of the sixteenth transistor is also connected to the high-side floating ground SHX through a capacitor, and the source is connected to analog ground.

[0010] Specifically, when the high-side floating ground SHX flips from high to low, V1 decreases, the current mirror current decreases, V2 increases, the output current of the fifth transistor decreases, and V4 decreases. During normal operation, the third resistor acts as a pull-down resistor for the fourth or tenth transistor, turning off the fourth transistor. The fourth diode acts as a gate-source clamping transistor for the fourth or tenth transistor, preventing gate oxide breakdown. The reduction of the high-side floating ground SHX is controlled by the high-side signal HOX. Before the high-side floating ground SHX is reduced, the high-side signal HOX has already been reduced, and V3 will also follow the high-side signal HOX to reduce. The fourth transistor M4 remains off, while the tenth transistor M10 is turned on, providing a weak pull-up signal through the fifth resistor R5 to prevent the gate-source voltage clamping path from being accidentally turned on. When the high-side signal HOX outputs high, V4 decreases while V3 remains unchanged due to the short circuit to ground of the high-side floating ground SHX. This causes the fourth transistor to turn on, charging the input capacitor of the third transistor in advance and turning on the third transistor until the gate-source voltage clamping path is fully established, thereby reducing the turn-on time of the third transistor. Wherein, V1 is the gate-drain voltage of the fifteenth transistor, V2 is the voltage between the gate of the fifth transistor and the drain of the fourteenth transistor, V3 is the voltage between the gate of the tenth transistor and the source of the thirteenth transistor, and V4 is the voltage between the source of the fifth transistor and the source of the fourth transistor.

[0011] Specifically, the pre-drive module I2 includes a pre-drive high-side drive circuit, a pre-drive low-side drive circuit, and a level conversion circuit; The pre-drive high-side drive circuit is used to generate a high-side signal HOX according to the control signal output by the logic control module I1, and the pre-drive low-side drive circuit is used to generate a low-side signal LOX. The pre-drive high-side drive circuit includes a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; The level conversion circuit receives low-voltage control signals generated by the logic control module I1 for turning on and off the sixth, seventh, eighth, and ninth transistors, and converts them into high-voltage control signals; the high-voltage control signals include a high-side drive pull-up control signal VH1, a high-side hold pull-up control signal VH2, a high-side drive pull-down control signal VL1, and a high-side hold pull-down control signal VL2. The drain of the sixth transistor and the drain of the seventh transistor are respectively connected to the high-side pre-drive power supply VCP; the source of the sixth transistor is connected to the drain of the eighth transistor, and the source of the seventh transistor is connected to the drain of the ninth transistor. The gate of the sixth transistor is connected to the high-side drive pull-up control signal VH1; the gate of the seventh transistor is connected to the high-side hold pull-up control signal VH2; the gate of the eighth transistor is connected to the high-side drive pull-down control signal VL1; and the gate of the ninth transistor is connected to the high-side hold pull-down control signal VL2. The source of the eighth transistor is connected to the high-side floating ground SHX; the source output signal of the ninth transistor is connected to the high-side floating ground SHX.

[0012] Specifically, the logic control module I1 and the pre-drive module I2 together construct an intelligent gate drive architecture that includes drive mode and hold mode; The driving mode is triggered when the pre-drive high-side driving circuit is just turned on, and the driving mode switches to holding mode after the driving time is turned on. During the drive time, the high-side drive pull-up control signal VH1 is low, the sixth transistor is turned on, the high-side hold pull-up control signal VH2 is high, and the seventh transistor is turned off. During the drive time, a large current is output to quickly charge the input capacitor of the first transistor. After switching to hold mode, the high-side hold pull-up control signal VH2 is low, the seventh transistor is turned on, the high-side drive pull-up control signal VH1 is high, and the sixth transistor is turned off. A small current is used to maintain the hold mode until the first transistor is turned off. The drive time is obtained by configuring the time width of the transistors through a register based on the size of the transistor's input capacitor.

[0013] Specifically, the source output signal of the sixth transistor is output as the high-side signal HOX. When the high-side drive pull-up control signal VH1 is low, the sixth transistor is turned on, and the source output current of the sixth transistor is output as the large current I. Drive When the high-side signal HOX is output high, the sixth transistor is turned off, and the high-side signal HOX and the large current I are not output. Drive If the seventh transistor is also turned off at this time, the high-side signal HOX will output low. The source output signal of the seventh transistor is output as the high-side signal HOX. When the high-side pull-up control signal VH2 is low, the seventh transistor is turned on, and the source output current of the seventh transistor is output as a small current I. Hold When the high-side signal HOX is output high, and the pull-up control signal VH2 remains high, the seventh transistor M7 is turned off, and the high-side signal HOX and the small current I are not output. Hold If the sixth transistor M6 is also turned off at this time, the high-side signal HOX will be output low. The high-side drive pull-up control signal VH1 and the high-side hold pull-up control signal VH2 have a sequential control relationship. When the high-side signal HOX needs to output high, the high-side drive pull-up control signal VH1 outputs low first, and after a drive time t... Drive Afterwards, the high-side pull-up control signal VH2 is kept low, and the high-side drive pull-up control signal VH1 is pulled high to ensure that the high-side signal HOX is stably output high.

[0014] Specifically, the gate of the first transistor is connected to the high-side signal HOX, the drain is connected to the high-voltage power supply VM, and the source is connected to the drain of the second transistor; the gate of the second transistor is connected to the low-side signal LOX, and the source is connected to the power ground COM; the high-side floating ground SHX is the source potential of the first transistor.

[0015] Specifically, the first, third, and fourth diodes are all Zener diodes, and the second diode is a high-voltage diode; The first resistor, the second resistor, the third resistor, the fourth resistor, and the fifth resistor are all variable resistors; the first transistor, the second transistor, and the tenth transistor are all NMOS transistors; and the third transistor and the fourth transistor are all PMOS transistors.

[0016] This invention designs a high-voltage half-bridge high-side hardware clamping circuit with fast response speed, adjustable clamping voltage, and wide clamping current range. This circuit simultaneously separates the voltage clamping path and the gate-source current discharge path, greatly reducing chip area and heat dissipation. An acceleration module is added to improve clamping speed, enabling clamping within 50 nanoseconds even under abnormal gate-source voltage differences, eliminating the need for internal LOGIC module judgment and reducing the risk of external MOS damage. Furthermore, the intelligent gate drive architecture of sampling drive mode + hold mode further reduces clamping current and chip power consumption. It eliminates the need for complex sampling and amplification circuits, significantly reducing the static current of the clamping circuit, using fewer hardware resources, and allowing adjustment of the clamping voltage by adjusting the resistor ratio. This effectively balances various requirements such as response speed, clamping current range, low power consumption, chip cost, and application range, featuring fast response speed, adjustable clamping voltage, and wide clamping current range. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a block diagram of a technical solution for a voltage-adjustable high-voltage half-bridge high-side hardware clamping circuit according to an embodiment of the present invention.

[0019] Figure 2 This is a specific implementation circuit diagram of a voltage-adjustable high-voltage half-bridge high-side hardware clamping circuit provided by an embodiment of the present invention. Detailed Implementation

[0020] The following embodiments will provide a detailed explanation of this patent document. The purpose of this patent document is to protect all technical improvements within the scope of this invention. In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined with "first" and "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0021] To make the technical problems, technical solutions and advantages of the present invention clearer, a detailed description will be given below in conjunction with the accompanying drawings and specific embodiments.

[0022] Example 1

[0023] refer to Figure 1 The present invention provides a voltage-adjustable high-voltage half-bridge high-side hardware clamping circuit, comprising the following modules: logic control module I1, pre-drive module I2, drive half-bridge module I3, and gate-source hardware clamping module I4. The logic control module I1 is used to generate different control signals to drive the pre-drive module I2; The logic control module I1 is a LOGIC circuit, which is used to perform logical operations on the input signal according to the predefined logical operation rules, thereby outputting different control signals, and controlling the pre-drive module I2 to enter the drive mode or hold mode according to the control signals. The pre-drive module I2 is used to generate high-side signal HOX and low-side signal LOX according to the control signal; refer to Figure 2 The pre-drive module I2 includes a pre-drive high-side drive circuit that generates a high-side signal HOX, a pre-drive low-side drive circuit that generates a low-side signal LOX, and a level conversion circuit. The pre-drive low-side driving circuit and level conversion circuit that generate the low-side signal LOX are both existing mature circuits, and will not be described in detail here.

[0024] The level conversion circuit receives the low-voltage control signals generated by the logic control module I1 for turning on and off the sixth transistor M6, the seventh transistor M7, the eighth transistor M8, and the ninth transistor M9, and converts them into high-voltage control signals; the high-voltage control signals include a high-side drive pull-up control signal VH1, a high-side hold pull-up control signal VH2, a high-side drive pull-down control signal VL1, and a high-side hold pull-down control signal VL2; The pre-drive high-side drive circuit includes a sixth transistor M6, a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9, and generates a high-side signal HOX according to the control signal output by the logic control module I1. The drain of the sixth transistor M6 and the drain of the seventh transistor M7 are respectively connected to the high-side pre-drive power supply VCP. The source of the sixth transistor M6 is connected to the drain of the eighth transistor M8, and the source of the seventh transistor M7 is connected to the drain of the ninth transistor M9. The gate of the sixth transistor M6 is connected to the high-side drive pull-up control signal VH1; The gate of the seventh transistor M7 is connected to the high-side hold pull-up control signal VH2; The gate of the eighth transistor M8 is connected to the high-side drive pull-down control signal VL1; The gate of the ninth transistor M9 is connected to the high-side hold pull-down control signal VL2; The sixth transistor M6 and the seventh transistor M7 are high-voltage PMOS transistors, which are turned on under low signal. The source output signal of the sixth transistor M6 is output as the high-side signal HOX. When the high-side drive pull-up control signal VH1 is low, the sixth transistor M6 is turned on, and the source output current of the sixth transistor M6 is output as the large current I. Drive When the high-side signal HOX is output high, the sixth transistor M6 is turned off, and the high-side signal HOX and the large current I are not output. Drive If the seventh transistor M7 is also turned off at this time, the high-side signal HOX will be output low. The source output signal of the seventh transistor M7 is output as the high-side signal HOX. When the high-side pull-up control signal VH2 is low, the seventh transistor M7 is turned on, and the source output current of the seventh transistor M7 is output as a small current I. Hold When the high-side signal HOX is output high, and the pull-up control signal VH2 remains high, the seventh transistor M7 is turned off, and the high-side signal HOX and the small current I are not output. Hold If the sixth transistor M6 is also turned off at this time, the high-side signal HOX will be output low. The high-side drive pull-up control signal VH1 and the high-side hold pull-up control signal VH2 have a sequential control relationship. When the high-side signal HOX needs to output high, the high-side drive pull-up control signal VH1 outputs low first, and after a drive time t... Drive Afterwards, the high-side pull-up control signal VH2 is kept low, and the high-side drive pull-up control signal VH1 is pulled high to ensure that the high-side signal HOX is stably output high. Similarly, the control of the low-side signal LOX output being high or low is similar to that of the high-side signal HOX, and will not be repeated here.

[0025] The source of the eighth transistor M8 is connected to the high-side floating ground SHX; the source output signal of the ninth transistor M9 is connected to the high-side floating ground SHX. Wherein, the positive clamping voltage between the high-side signal HOX and the high-side floating ground SHX is V PC .

[0026] It is understandable that the outputs of the high-side drive pull-up control signal VH1, the high-side hold pull-up control signal VH2, the high-side drive pull-down control signal VL1, and the high-side hold pull-down control signal VL2 can be set to high or low according to the high or low level of their reference power supply or ground.

[0027] In this embodiment, VH1 and VH2 are high-voltage PMOS control signals, and their reference power supply is the high-side pre-drive power supply VCP. Therefore, their outputs are V... VCP When the output is considered high, the above control signal is output as V. VCP At -5V, the output is considered low; V VCP The voltage of the high-side pre-drive power supply VCP; VL1 and VL2 are high-voltage NMOS control signals, and their reference power supply is the high-side floating ground SHX. Therefore, their outputs are V... SHX When +5V is applied, the output is considered high, and the above control signal is output as V. SHX When the output is considered low, V SHX The voltage of the high-side floating ground SHX is used; the reference power supply voltage value is not used as a limitation for whether the output is high or low, and can be changed according to actual needs.

[0028] Furthermore, the logic control module I1 and the pre-drive module I2 together construct an intelligent gate drive architecture with drive mode and hold mode, which can effectively reduce the risk of half-bridge MOS breakdown and chip power consumption during trigger clamping.

[0029] The driving mode is triggered when the pre-drive high-side drive circuit is just turned on, and the driving mode is activated for a time t. Drive Then switch to hold mode; Specifically, when the pre-drive high-side drive circuit is first turned on, it is in drive mode. The high-side drive pull-up control signal VH1 is low, the sixth transistor M6 is turned on, the high-side hold pull-up control signal VH2 is high, and the seventh transistor M7 is turned off. During the drive time t... Drive Internal output high current I Drive The input capacitor (ciss) of the high-side MOS in the driver half-bridge module I3 is rapidly charged to reduce its switching losses. Drive Then, switching to hold mode, the high-side pull-up control signal VH2 is output low, the seventh transistor M7 is turned on, the high-side drive pull-up control signal VH1 is output high, the sixth transistor M6 is turned off, and a small current I is used. Hold(Ten mA level) maintained until the high-side MOS is turned off.

[0030] The eighth transistor M8 and the ninth transistor M9 are NMOS transistors, which are enabled by a high signal. The eighth transistor M8 and the ninth transistor M9 are responsible for turning off the pre-drive high-side drive circuit, which is not within the scope of this embodiment and will not be discussed in this embodiment. Therefore, in this embodiment, the high-side drive pull-down control signal VL1 and the high-side holding pull-down control signal VL2 are always output low, keeping the eighth transistor M8 and the ninth transistor M9 in the off state. Therefore, when the high-side drive pull-up control signal VH1 is low, the sixth transistor M6 is turned on and outputs the high-side signal HOX; when the high-side drive pull-up control signal VH1 is high; This ensures that the high-side MOSFET remains in hold mode for most of the turn-on phase. When a phase-to-phase short circuit triggers clamping, the probability of needing to clamp a large current is reduced. Even during the initial turn-on phase, the clamping time for the large current can be controlled within t. Drive The following measures aim to reduce chip heat dissipation and power consumption, as well as the risk of high-side MOS breakdown in the drive half-bridge module I3.

[0031] Wherein, the driving time t Drive The time width can be obtained by configuring the register based on the input capacitance (ciss) of the high-side MOS of the driving half-bridge module I3.

[0032] The driving half-bridge module I3 includes a first transistor M1 as a high-voltage half-bridge and a second transistor M2 as a low-voltage half-bridge; the gate of the first transistor M1 is connected to the high-side signal HOX, the drain is connected to the high-voltage power supply VM, and the source is connected to the drain of the second transistor M2; the gate of the second transistor M2 is connected to the low-side signal LOX, and the source is connected to the power ground COM. The high-side floating ground SHX is the source potential of the high-side MOS, that is, the source potential of the first transistor M1. The first transistor M1 is the high-side MOS driving the half-bridge module I3; the second transistor M2 is the low-side MOS driving the half-bridge module I3. In this embodiment, the high-voltage power supply VM is a 48V power supply; the high-voltage power supply VCP is an internal output of 58.5V; and the voltage of the power ground COM is 0V.

[0033] The gate-source hardware clamping module I4 is connected to the gate and source of the first transistor M1 of the driving half-bridge module I3, and is used to clamp the voltage when the gate-source voltage of the first transistor M1 is over-voltage. Specifically, the gate-source hardware clamping module I4 includes a high-side gate-source voltage clamping circuit and a clamping acceleration circuit. The high-side gate-source voltage clamping circuit is used to clamp the voltage when the gate-source voltage of the first transistor M1 is over-voltage. The clamping acceleration circuit is used to accelerate the activation speed of the high-side gate-source voltage clamping circuit.

[0034] The high-side gate-source voltage clamping circuit specifically includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a third transistor M3, a fourth transistor M4, and a tenth transistor M10. The drain of the third transistor M3 is connected to the gate of the first transistor M1 and is also connected to the high-side signal HOX. The source of the third transistor M3 is connected to the source of the first transistor M1 and is also connected to the high-side floating ground SHX. The anode of the first diode D1 and one end of the first resistor R1 are connected to the gate of the third transistor M3. The cathode of the first diode D1 and the other end of the first resistor R1 are connected to the gate of the first transistor M1. The cathode of the second diode D2 is connected to the source of the tenth transistor M10, and the anode is connected to the gate of the third transistor M3; The drain of the tenth transistor M10 is connected to the high-side pre-drive power supply VCP through the fifth resistor R5; the gate of the tenth transistor M10 is connected to the high-side floating ground SHX through the third diode D3 and the second resistor R2 in series. Specifically, the cathode of the third diode D3 is connected to the gate of the tenth transistor M10, and the anode is connected to one end of the second resistor R2; the other end of the second resistor R2 is connected to the high-side floating ground SHX. The anode of the fourth diode D4 is connected to the source of the tenth transistor M10 and the drain of the fourth transistor M4, respectively, and the cathode is connected to the gate of the tenth transistor M10 and the gate of the fourth transistor M4, respectively. One end of the third resistor R3 is connected to the source of the tenth transistor M10 and the drain of the fourth transistor M4, and the other end is connected to the gate of the tenth transistor M10 and the gate of the fourth transistor M4. The source of the fourth transistor M4 is connected to analog ground through the fourth resistor R4; In the gate-source hardware clamping module I4, the first diode D1, the second diode D2, the third diode D3, the third transistor M3, the first resistor R1, and the second resistor R2 are the key circuits that constitute the hardware clamping.

[0035] Traditional structures typically use clamping diodes for clamping protection. However, when the high-side MOS is turned on, there is an ampere-level DC drive current on the high-side signal HOX, which is difficult for the clamping diode to meet the overcurrent capacity. Therefore, in the gate-source hardware clamping module I4 circuit of this embodiment, the gate-source voltage clamping path and the gate-source current discharge path are separated. Specifically, in some implementation scenarios, the pre-drive high-side drive circuit has multiple modes of drive current; for example, the high-side turn-on phase is the drive mode, and the output drive current is in the ampere range. Drive During the stabilization phase, it operates in hold mode, with the output drive current in the milliampere range. Hold Therefore, in this embodiment, the high-side gate-source voltage clamping circuit uses a high-voltage NMOS transistor (third transistor M3) as a discharge transistor to ensure that the clamping voltage changes little when the clamping current changes over a large range. At the same time, the body diode of the NMOS transistor can be used as a negative clamp. Since SHX is a high-side floating ground, its voltage range is constantly changing from 0 to 48V. Therefore, a first diode D1 is added as a gate-source clamp for the third transistor M3 to prevent gate oxide breakdown. The first resistor R1 is a pull-up resistor to prevent the third transistor M3 from being turned on erroneously. The second diode D2 is a high-voltage diode to prevent reverse current. When the low-side signal LOX outputs high, the high-side floating ground SHX is pulled low to ground and its forward conduction does not affect the gate-source voltage clamping detection. When the high-side signal HOX outputs high, the high-side floating ground SHX outputs VM voltage and is reverse cut off to prevent the high-side floating ground SHX from discharging negative clamping current through the gate-source voltage clamping path.

[0036] The gate-source voltage clamping path consists of a first resistor R1, a second diode D2, a fourth diode D4, a third diode D3, and a second resistor R2. When the chip is working normally, the voltage difference between the high-side signal HOX and the high-side floating ground SHX is less than V. PC No current flows through the gate-source voltage clamping path composed of R1-D2-D4-D3-R2, and the third transistor M3 is turned off with no static power consumption; the gate-source current discharge path is composed of the third transistor M3. When the phase line is short-circuited to ground, the high-side floating ground SHX is short-circuited to ground, and current flows through the gate-source voltage clamping path. The voltage drop across the first resistor R1 causes the third transistor M3 to turn on. The drive current on the high-side signal H0X flows through the source drain of the third transistor M3 to the high-side floating ground SHX (gate-source current discharge path), finally clamping the voltage of the high-side signal H0X at Vpc, as shown in the clamping voltage formula below: , Wherein, Vpc is the positive clamping voltage between the high-side signal HOX and the high-side floating ground SHX, and is also the clamping voltage between the gate and source of the first transistor M1, which serves as the high-voltage half-bridge; V GS_M3 V is the gate-source voltage of the third transistor M3. Z_D3 V is the clamping voltage of the third diode D3. F R1 is the forward conduction voltage of the second diode D2, and R2 is the resistance value of the first resistor R1 and the second resistor R2, respectively.

[0037] The gate-source voltage clamping path only requires tens of microamps of current to activate M3 for gate-source clamping within hundreds of nanoseconds, which can greatly reduce chip costs. Moreover, as long as the gate-source voltage difference is detected to exceed the normal operating range, the gate-source voltage is directly clamped without the need for judgment through the logic control module I1.

[0038] Furthermore, as can be seen from the above clamping voltage formula, the present invention can adjust the clamping voltage V of the third diode D3. Z_D3 The clamping voltage is coarsely adjusted, and then the clamping voltage is finely adjusted by adjusting the ratio of the second resistor R2 to the first resistor R1, so as to achieve the effect of adjustable clamping voltage.

[0039] The gate-source hardware clamping module I4 is connected to the driving half-bridge module I3, separating the gate-source voltage clamping path from the gate-source current discharge path. This is used to address the situation where, when the phase line is short-circuited to ground and the high-side MOS gate-source experiences instantaneous overvoltage, the voltage can be clamped directly without the need for judgment by the LOGIC module.

[0040] To improve the clamping speed and accelerate the turn-on speed of the third transistor M3 during clamping, this invention also adds a clamping acceleration circuit consisting of a current mirror bias circuit, a first capacitor C1, a fourth transistor M4, and a fourth resistor R4.

[0041] The current mirror bias circuit includes a fifth transistor M5, a twelfth transistor M12, a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15, and a sixteenth transistor M16, which mirrors the current IREF1 output by the reference module and provides circuit bias for the entire clamping circuit. The drains of the fifth transistor M5, the twelfth transistor M12, and the thirteenth transistor M13 are connected to the high-side pre-drive power supply VCP, respectively; the source of the fifth transistor M5 is connected to the source of the fourth transistor M4; the source of the fifth transistor M5 is also connected to analog ground through the fourth resistor R4. The gate of the fifth transistor M5 is connected to the gate of the twelfth transistor M12 and the gate of the thirteenth transistor M13, respectively. The gate-source connection of the twelfth transistor M12 is then connected to the gate of the thirteenth transistor M13. The source of the thirteenth transistor M13 is connected to the gate of the tenth transistor M10; The drain of the fourteenth transistor M14 is connected to the source of the twelfth transistor M12, the source is connected to the drain of the sixteenth transistor M16, and the gate is connected to the 5V control signal VREF1. The gate-drain connection of the fifteenth transistor M15 is connected to the gate of the sixteenth transistor M16. The drain is also connected to the reference current IREF1 output by the reference module, and the source is connected to the analog ground. The gate of the sixteenth transistor M16 is also connected to the high-side floating ground SHX through the first capacitor C1, and the source is connected to the analog ground.

[0042] Taking advantage of the fact that the voltage across the first capacitor C1 cannot change abruptly, when the high-side floating ground SHX flips from high to low, V1 decreases, the output current of the sixteenth transistor M16 and the twelfth transistor M12 decreases, V2 increases, the output current of the fifth transistor M5 decreases, and V4 decreases. During normal operation, the third resistor R3 acts as a pull-down resistor for the fourth transistor M4 or the tenth transistor M10, turning off the fourth transistor M4 during normal operation. The fourth diode D4 acts as a gate-source clamping transistor for the fourth transistor M4 or the tenth transistor M10, preventing gate oxide breakdown. The reduction of the high-side floating ground SHX is controlled by the high-side signal HOX. That is, before the high-side floating ground SHX is reduced, the high-side signal HOX has already been reduced, and V3 will also follow the high-side signal HOX to reduce. The fourth transistor M4 remains off, while the tenth transistor M10 is turned on, providing a weak pull-up signal through the fifth resistor R5 to prevent the gate-source voltage clamping path from being accidentally turned on. When the high-side signal HOX outputs high, V4 decreases while V3 remains unchanged due to the short circuit to ground caused by the high-side floating ground SHX. This turns on the fourth transistor M4, charging the input capacitor (ciss) of the third transistor M3 in advance, until the gate-source voltage clamping path is fully established. This reduces the turn-on time of the third transistor M3 and improves the overall clamping speed.

[0043] Among them, the gate-drain voltage of the fifteenth transistor M15 is V1, the voltage between the gate of the fifth transistor M5 and the drain of the fourteenth transistor M14 is V2, the voltage between the gate of the tenth transistor M10 and the source of the thirteenth transistor M13 is V3, and the voltage between the source of the fifth transistor M5 and the source of the fourth transistor M4 is V4.

[0044] In this invention, the first diode D1, the third diode D3, and the fourth diode D4 are all Zener diodes, and the second diode D2 is a high-voltage diode; The first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, and the fifth resistor R5 are all variable resistors; The first transistor M1, the second transistor M2, the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the fourteenth transistor M14, the fifteenth transistor M15, and the sixteenth transistor M16 are all NMOS transistors; The third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the twelfth transistor M12, and the thirteenth transistor M13 are all PMOS transistors.

[0045] It is understood that the NMOS transistor described in this embodiment is an N-type MOS transistor (metal-oxide-semiconductor), and the PMOS transistor is an N-type MOS transistor (metal-oxide-semiconductor). In this embodiment, both the NMOS and PMOS transistors are high-voltage MOS transistors.

[0046] In this invention, the logic control module I1, the pre-drive module I2, and the drive half-bridge module I3 constitute a complete self-driven half-bridge circuit. The gate-source hardware clamping module I4 mainly deals with scenarios such as phase line to ground short circuit and instantaneous overvoltage of the high-side MOS gate-source. When the gate-source voltage difference is detected to exceed the normal operating range, the voltage of the gate-source is directly clamped without the need for judgment by the internal LOGIC module. Through the clamping acceleration circuit, the voltage between the gate and source can be clamped within the rated range within fifty nanoseconds to prevent the high-side MOS gate oxide from being damaged.

[0047] This invention designs a high-voltage half-bridge high-side hardware clamping circuit with fast response speed, adjustable clamping voltage, and wide clamping current range. This circuit simultaneously separates the voltage clamping path and the gate-source current discharge path, greatly reducing chip area and heat dissipation. An acceleration module is added to improve clamping speed, enabling clamping within 50 nanoseconds even under abnormal gate-source voltage differences, eliminating the need for internal LOGIC module judgment and reducing the risk of external MOS damage. Furthermore, the intelligent gate drive architecture of sampling drive mode + hold mode further reduces clamping current and chip power consumption. It eliminates the need for complex sampling and amplification circuits, significantly reducing the static current of the clamping circuit, using fewer hardware resources, and allowing adjustment of the clamping voltage by adjusting the resistor ratio. This effectively balances various requirements such as response speed, clamping current range, low power consumption, chip cost, and application range, featuring fast response speed, adjustable clamping voltage, and wide clamping current range.

[0048] It is understood that in the above embodiments, each MOS transistor can be replaced by an NMOS transistor and a PMOS transistor, and the circuit connection can be adjusted to achieve similar functions. These simple replacement methods should also fall within the protection scope of this application.

[0049] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Those skilled in the art should understand that the present invention includes, but is not limited to, the contents described in the accompanying drawings and the specific embodiments above. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention, and any modifications that do not depart from the functional and structural principles of the present invention, should be included within the protection scope of the present invention.

Claims

1. A voltage-adjustable high-voltage half-bridge high-side hardware clamping circuit, characterized in that, include: The logic control module I1 is used to generate different control signals to drive the pre-drive module I2; The pre-driver module I2 is used to generate high-side and low-side signals based on the control signal; The driving half-bridge module I3 includes a first transistor for receiving high-side signals as a high-voltage half-bridge and a second transistor for receiving low-side signals as a low-voltage half-bridge. The gate-source hardware clamping module I4 includes a high-side gate-source voltage clamping circuit, which is connected to the gate and source of the first transistor in the driving half-bridge module I3, and is used to clamp the first transistor when the gate-source voltage is over-voltage. The high-side gate-source voltage clamping circuit includes a first diode, a second diode, a third diode, a fourth diode, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a third transistor, a fourth transistor, and a tenth transistor; The drain of the third transistor is connected to the gate of the first transistor, and the source is connected to the source of the first transistor. The first diode and the first resistor are connected in parallel between the gate of the third transistor and the gate of the first transistor. The cathode of the second diode is connected to the source of the tenth transistor, and the anode is connected to the gate of the third transistor. The drain of the tenth transistor is connected to the high-side pre-drive power supply through the fifth resistor, and the gate is connected to the high-side floating ground through the third diode and the second resistor in series. The anode of the fourth diode is connected to the source of the tenth transistor and the drain of the fourth transistor, and the cathode is connected to the gate of the tenth transistor and the gate of the fourth transistor, respectively. One end of the third resistor is connected to the source of the tenth transistor and the drain of the fourth transistor, respectively, and the other end is connected to the gate of the tenth transistor and the gate of the fourth transistor, respectively. The source of the fourth transistor is connected to analog ground through the fourth resistor.

2. The voltage-adjustable high-voltage half-bridge high-side hardware clamping circuit according to claim 1, characterized in that, When the high-side floating ground SHX is short-circuited to ground, the voltage drop across the first resistor causes the third transistor to turn on. The drive current on the high-side signal H0X drains through the source of the third transistor to the high-side floating ground SHX, finally clamping the voltage of the high-side signal H0X at Vpc, as shown in the following clamping voltage formula: ， Wherein, Vpc is the positive clamping voltage between the high-side signal HOX and the high-side floating ground SHX; V GS_M3 V is the gate-source voltage of the third transistor. Z_D3 V is the clamping voltage of the third diode. F R1 and R2 are the forward conduction voltages of the second diode, and the resistance values ​​of the first resistor and the second resistor are respectively.

3. The voltage-adjustable high-voltage half-bridge high-side hardware clamping circuit according to claim 1, characterized in that, The high-side gate-source voltage clamping circuit also separates the gate-source voltage clamping path from the gate-source current discharge path. The gate-source voltage clamping path consists of a first resistor, a second diode, a fourth diode, a third diode, and a second resistor; the gate-source current discharge path consists of a third transistor.

4. The voltage-adjustable high-voltage half-bridge high-side hardware clamping circuit according to claim 3, characterized in that, The gate-source hardware clamping module I4 also includes a clamping acceleration circuit; the clamping acceleration circuit is used to accelerate the activation speed of the high-side gate-source voltage clamping circuit. The clamping acceleration circuit consists of a current mirror bias circuit, a first capacitor, a fourth transistor, and a fourth resistor. The current mirror bias circuit includes a fifth transistor, a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor, which mirror the current IREF1 output from the reference module to provide circuit bias for the entire clamping circuit. The drains of the fifth transistor, the twelfth transistor, and the thirteenth transistor are connected to the high-side pre-drive power supply VCP, respectively. The source of the fifth transistor is connected to the source of the fourth transistor. The source of the fifth transistor is also connected to analog ground through a fourth resistor. The gate of the fifth transistor is connected to the gate of the twelfth transistor and the gate of the thirteenth transistor, respectively. Gate connection; the gate-source connection of the twelfth transistor is then connected to the gate of the thirteenth transistor; the source of the thirteenth transistor is connected to the gate of the tenth transistor; the drain of the fourteenth transistor is connected to the source of the twelfth transistor, the source is connected to the drain of the sixteenth transistor, and the gate is connected to the control signal VREF1; the gate-drain connection of the fifteenth transistor is then connected to the gate of the sixteenth transistor, the drain is also connected to the reference current IREF1 output by the reference module, and the source is connected to analog ground; the gate of the sixteenth transistor is also connected to the high-side floating ground SHX through a capacitor, and the source is connected to analog ground.

5. The voltage-adjustable high-voltage half-bridge high-side hardware clamping circuit according to claim 4, characterized in that, When the high-side floating ground SHX flips from high to low, V1 decreases, the current mirror current decreases, V2 increases, the output current of the fifth transistor decreases, and V4 decreases. During normal operation, the third resistor acts as a pull-down resistor for the fourth or tenth transistor, turning off the fourth transistor; the fourth diode acts as a gate-source clamp for the fourth or tenth transistor, preventing its gate oxide from breaking down. The high-side floating ground SHX decreases under the control of the high-side signal HOX. Before the high-side floating ground SHX decreases, the high-side signal HOX has already decreased, and V3 will also decrease along with the high-side signal HOX. The fourth transistor M4 remains off, while the tenth transistor M10 is turned on. A weak pull-up signal is provided through the fifth resistor R5 to prevent the gate-source voltage clamping path from being accidentally turned on. When the high-side signal HOX outputs high, V4 decreases while V3 remains unchanged due to the short circuit to ground of the high-side floating ground SHX. This causes the fourth transistor to turn on, charging the input capacitor of the third transistor in advance and turning on the third transistor until the gate-source voltage clamping path is fully established, thereby reducing the turn-on time of the third transistor. Wherein, V1 is the gate-drain voltage of the fifteenth transistor, V2 is the voltage between the gate of the fifth transistor and the drain of the fourteenth transistor, V3 is the voltage between the gate of the tenth transistor and the source of the thirteenth transistor, and V4 is the voltage between the source of the fifth transistor and the source of the fourth transistor.

6. The voltage-adjustable high-voltage half-bridge high-side hardware clamping circuit according to claim 1, characterized in that, The pre-drive module I2 includes a pre-drive high-side drive circuit, a pre-drive low-side drive circuit, and a level conversion circuit. The pre-drive high-side drive circuit is used to generate a high-side signal HOX according to the control signal output by the logic control module I1, and the pre-drive low-side drive circuit is used to generate a low-side signal LOX. The pre-drive high-side drive circuit includes a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor; The level conversion circuit receives low-voltage control signals generated by the logic control module I1 for turning on and off the sixth, seventh, eighth, and ninth transistors, and converts them into high-voltage control signals; the high-voltage control signals include a high-side drive pull-up control signal VH1, a high-side hold pull-up control signal VH2, a high-side drive pull-down control signal VL1, and a high-side hold pull-down control signal VL2. The drain of the sixth transistor and the drain of the seventh transistor are respectively connected to the high-side pre-drive power supply VCP; the source of the sixth transistor is connected to the drain of the eighth transistor, and the source of the seventh transistor is connected to the drain of the ninth transistor. The gate of the sixth transistor is connected to the high-side drive pull-up control signal VH1; the gate of the seventh transistor is connected to the high-side hold pull-up control signal VH2; the gate of the eighth transistor is connected to the high-side drive pull-down control signal VL1; and the gate of the ninth transistor is connected to the high-side hold pull-down control signal VL2. The source of the eighth transistor is connected to the high-side floating ground SHX; the source output signal of the ninth transistor is connected to the high-side floating ground SHX.

7. The voltage-adjustable high-voltage half-bridge high-side hardware clamping circuit according to claim 6, characterized in that, The logic control module I1 and the pre-drive module I2 together construct an intelligent gate drive architecture that includes drive mode and hold mode. The driving mode is triggered when the pre-drive high-side driving circuit is just turned on, and the driving mode switches to holding mode after the driving time is turned on. During the drive time, the high-side drive pull-up control signal VH1 is low, the sixth transistor is turned on, the high-side hold pull-up control signal VH2 is high, and the seventh transistor is turned off. During the drive time, a large current is output to quickly charge the input capacitor of the first transistor. After switching to hold mode, the high-side hold pull-up control signal VH2 is low, the seventh transistor is turned on, the high-side drive pull-up control signal VH1 is high, and the sixth transistor is turned off. A small current is used to maintain the hold mode until the first transistor is turned off. The drive time is obtained by configuring the time width of the transistors through a register based on the size of the transistor's input capacitor.

8. The voltage-adjustable high-voltage half-bridge high-side hardware clamping circuit according to claim 7, characterized in that, The source output signal of the sixth transistor is output as the high-side signal HOX. When the high-side drive pull-up control signal VH1 is low, the sixth transistor is turned on, and the source output current of the sixth transistor is output as the large current I. Drive The high-side signal HOX output is high; When the high-side drive pull-up control signal VH1 is high, the sixth transistor is turned off, and the high-side signal HOX and the large current I are not output. Drive If the seventh transistor is also turned off at this time, the high-side signal HOX will output low. The source output signal of the seventh transistor is output as the high-side signal HOX. When the high-side pull-up control signal VH2 is low, the seventh transistor is turned on, and the source output current of the seventh transistor is output as a small current I. Hold The high-side signal HOX output is high; When the high-side pull-up control signal VH2 is high, the seventh transistor M7 is turned off, and the high-side signal HOX and the small current I are not output. Hold If the sixth transistor is also turned off at this time, the high-side signal HOX will output low. The high-side drive pull-up control signal VH1 and the high-side hold pull-up control signal VH2 have a sequential control relationship. When the high-side signal HOX needs to output high, the high-side drive pull-up control signal VH1 outputs low first, and after a drive time t... Drive Afterwards, the high-side pull-up control signal VH2 is kept low, and the high-side drive pull-up control signal VH1 is pulled high to ensure that the high-side signal HOX is stably output high.

9. The voltage-adjustable high-voltage half-bridge high-side hardware clamping circuit according to claim 1, characterized in that, The gate of the first transistor is connected to the high-side signal HOX, the drain is connected to the high-voltage power supply VM, and the source is connected to the drain of the second transistor; the gate of the second transistor is connected to the low-side signal LOX, and the source is connected to the power ground COM; the high-side floating ground SHX is the source potential of the first transistor.

10. The voltage-adjustable high-voltage half-bridge high-side hardware clamping circuit according to claim 1, characterized in that, The first diode, the third diode, and the fourth diode are all Zener diodes, and the second diode is a high-voltage diode; The first resistor, the second resistor, the third resistor, the fourth resistor, and the fifth resistor are all variable resistors; the first transistor, the second transistor, and the tenth transistor are all NMOS transistors; and the third transistor and the fourth transistor are all PMOS transistors.

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