A power line spike signal suppression circuit with an inrush current suppression function

Abstract

The application discloses a power line peak signal suppression circuit with an inrush current suppression function, and belongs to the technical field of circuits, comprising an inrush current suppression circuit and a power line peak signal suppression and power signal filtering circuit connected in sequence. The inrush current suppression circuit is located on a power positive line, thereby avoiding interference with a negative line level; the inrush current suppression is realized through a MOS tube and a current-limiting resistor; the power line peak signal suppression is realized through an LC filtering circuit; when the circuit is in a steady state, the low-power-consumption operation of the circuit is realized by utilizing the internal resistance of the MOS tube; and the circuit is also miniaturized.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, and in particular to a power line spike signal suppression circuit with inrush current suppression function. Background Technology

[0002] Current surge current suppression schemes can be categorized into five types: The first type utilizes the inherent resistance of inductance to current to suppress surge current. Its disadvantage is that to achieve sufficient suppression, a large inductor is required, which, when connected in series with the circuit, risks raising the output voltage. This scheme also suffers from large size, high power consumption, and uncontrollable weight. The second type involves connecting a resistor in series with the circuit to suppress surge current. To overcome the power loss caused by the series resistor, a switch (semiconductor device or relay), such as an SCR, is connected in parallel across the resistor in some cases. Its disadvantages include large size, high power consumption, high circuit complexity, high design complexity, and low reliability. The third type uses an NTC thermistor, connecting it in series with the circuit. It utilizes the characteristic that the resistance of an NTC thermistor decreases with increasing temperature to suppress surge current. Its disadvantages include the suppression function being prone to failure at high temperatures, long secondary startup time, potential circuit startup abnormalities at low temperatures, and high power loss. The fourth method involves connecting an NMOS transistor in series on the negative power line and a current-limiting resistor in parallel with the transistor. By controlling the conduction time of the MOS transistor using its conduction characteristics, the current-limiting resistor suppresses inrush current at the moment of power-on. While this circuit has advantages such as low switching losses, simple driving method, and low on-resistance, it suffers from drawbacks. The negative power line level is easily boosted, affecting the reference of downstream signals. Furthermore, in some applications, the negative power line is connected to the equipment chassis, causing the inrush current suppression function to fail. The fifth method involves connecting a PMOS transistor in series on the positive power line and a resistor in parallel with the transistor. Its circuit principle is the same as the fourth method, but the reference level is not affected, and it does not interfere with the potential reference of downstream stages. Its disadvantage is that PMOS transistors generally have high internal resistance and high cost, limiting its use to low-current equipment.

[0003] Currently, power line spike signal suppression schemes can be divided into the following four types: The first type is the series reactor and choke scheme; its disadvantage is the potential risk of resonance, as the inductance of the reactor and the distributed capacitance of the cable may resonate, generating overvoltage at the cable end. Furthermore, this scheme can only slow down the rise time of the voltage pulse, and its suppression effect is limited. The second type is the LC filter scheme; its... The disadvantages are that power inductors are large, prone to overheating, susceptible to parasitic parameters of LC components, and exhibit temperature drift when using aluminum electrolytic capacitors. The third option is a parallel RC absorption network scheme; its disadvantages include difficulty in matching circuit parameters, generally requiring temporary circuit configuration, and lack of universality. Resistors consume significant power. The fourth option is an output line optimization scheme; its disadvantages include limited application scenarios and the inability to completely eliminate interference.

[0004] Therefore, there is an urgent need for a power line spike suppression circuit that can suppress inrush current on the positive power line to avoid interference with the negative line level, while also suppressing power line spike signals, miniaturizing the circuit, operating with low power consumption, and having power signal filtering functions. Summary of the Invention

[0005] The purpose of this invention is to overcome the technical problems of existing technologies, such as level interference, poor peak suppression effect, large circuit size, high power consumption, and low reliability, and to provide a power line peak signal suppression circuit with inrush current suppression function.

[0006] To address the aforementioned technical problems, the present invention provides the following technical solution: A power line spike signal suppression circuit with inrush current suppression function includes: an inrush current suppression circuit and a power line spike signal suppression and power signal filtering circuit connected in sequence. The inrush current suppression circuit is used to suppress inrush current when the circuit is powered on and to achieve low power consumption operation when the circuit is in steady state. The power line spike signal suppression and power signal filtering circuit is used to suppress power spike signals when the circuit is powered on. The surge current suppression circuit includes resistor R1, resistor R2, capacitor C1, diode D2 and MOSFET Q1. Resistor R1, resistor R2, capacitor C1 and diode D2 constitute the driving circuit of MOSFET Q1. The driving circuit includes transient and steady-state operating states. One end of resistor R1, one end of capacitor C1, the cathode of diode D2, and the source of MOSFET Q1 are all connected to the positive terminal of the analog DC voltage source. The other end of resistor R1, the other end of capacitor C1, the anode of diode D2, and the gate of MOSFET Q1 are all connected to one end of resistor R2. The other end of resistor R2 is connected to the negative terminal of the analog DC voltage source and the second input terminal of the power line spike signal suppression and power signal filtering circuit. The drain of MOSFET Q1 is connected to the first input terminal of the power line spike signal suppression and power signal filtering circuit. In transient operation, resistors R1 and R2 form a voltage divider circuit. The voltage across resistor R2 is used to drive MOSFET Q1 to conduct in a steady state. At this time, MOSFET Q1 is fully turned on, and the back-end equipment works normally. In steady-state operation, when the analog DC voltage source outputs power, resistor R2 and capacitor C1 form an RC charging circuit and charge capacitor C1. The voltage across capacitor C1 is the driving voltage of MOSFET Q1.

[0007] As a preferred embodiment of the present invention, the MOS transistor Q1 is a P-channel MOSFET.

[0008] As a preferred embodiment of the present invention, the surge current suppression circuit further includes a current-limiting resistor R3 and a current-limiting resistor R4. The current-limiting resistor R4 and the current-limiting resistor R4 are connected in parallel, with one end connected to the cathode of the diode D2 and the other end connected to the drain of the MOS transistor Q1.

[0009] As a preferred embodiment of the present invention, the power line spike signal suppression and power signal filtering circuit includes a common-mode inductor L1, a common-mode inductor L2, capacitors C2, C3, C5, and C6. The drain of the MOSFET Q1 is connected to the first end of the common-mode inductor L1, the other end of the resistor R2 is connected to the second end of the common-mode inductor L1, one end of capacitor C2, one end of capacitor C6, and the first end of the common-mode inductor L2 are connected to the third end of the common-mode inductor L1, the other end of capacitor C6 is connected to one end of capacitor C5 and grounded, the other ends of capacitor C2 and C5 are connected to the second end of the common-mode inductor L2, the third and fourth ends of the common-mode inductor L2 are respectively the positive and negative output terminals of the circuit, and capacitor C3 is connected in parallel between the third and fourth ends of the common-mode inductor L2. In steady-state operation, the analog DC voltage source charges capacitor C2 through the current-limiting resistor R3 to suppress the inrush current.

[0010] As a preferred embodiment of the present invention, the total capacitance of capacitors C2 and C3 is 122 uF.

[0011] As a preferred embodiment of the present invention, the simulated DC voltage source is a 28V high-voltage power supply.

[0012] Compared with the prior art, the advantages of the present invention are as follows: the inrush current suppression circuit of the present invention is located on the positive line of the power supply, avoiding interference with the negative line level; inrush current suppression is achieved through MOSFET and current limiting resistor; power supply spike signal suppression is achieved by configuring LC filter circuit; when the circuit is in steady state operation, low power consumption operation is achieved by utilizing the internal resistance of MOSFET; and the circuit is also miniaturized. Attached Figure Description

[0013] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. In the drawings: Figure 1 This is a schematic diagram of a power line spike signal suppression circuit with inrush current suppression function as described in Embodiment 1 of the present invention. Detailed Implementation

[0014] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0015] Example 1 A power line spike signal suppression circuit with inrush current suppression function is provided. The circuit is set inside the housing and grounded through the housing. like Figure 1 As shown, it includes: an inrush current suppression circuit and a power line spike signal suppression and power signal filtering circuit connected in sequence; The inrush current suppression circuit suppresses inrush current through a current-limiting resistor when the circuit is powered on, and achieves low-power operation of the circuit through a MOSFET when the circuit is in steady state. The power line spike signal suppression and power signal filtering circuit suppresses power spike signals by configuring an LC filter circuit when the circuit is powered on. The surge current suppression circuit includes resistor R1, resistor R2, capacitor C1, diode D2 and MOSFET Q1. Resistor R1, resistor R2, capacitor C1 and diode D2 constitute the driving circuit of MOSFET Q1. The driving circuit has two working states: transient and steady state. The power-on process at the input terminal is the transient working state, and thereafter it is the steady state. One end of resistor R1, one end of capacitor C1, the cathode of diode D2, and the source of MOSFET Q1 are all connected to the positive terminal of analog DC voltage source Vi. The other end of resistor R1, the other end of capacitor C1, the anode of diode D2, and the gate of MOSFET Q1 are all connected to one end of resistor R2. The other end of resistor R2 is connected to the negative terminal of analog DC voltage source Vi and the second input terminal of the power line spike signal suppression and power signal filtering circuit. The drain of MOSFET Q1 is connected to the first input terminal of the power line spike signal suppression and power signal filtering circuit. In transient operation, resistors R1 and R2 form a voltage divider circuit. The voltage across resistor R2 is used to drive MOSFET Q1 to conduct in a steady state. At this time, MOSFET Q1 is fully turned on, and the back-end equipment works normally. In steady-state operation, when the simulated DC voltage source Vi outputs power, resistor R2 and capacitor C1 form an RC charging circuit to charge capacitor C1. The voltage across capacitor C1 is the driving voltage of MOSFET Q1. Due to the voltage delay effect of the RC charging circuit, the driving voltage of MOSFET Q1 will rise slowly, and MOSFET Q1 will be delayed in turning on. The delay time is determined by the time constant of resistor R1 and capacitor C1. During this process, the simulated DC voltage source Vi charges the downstream capacitor C2 through resistor R3, thereby suppressing the startup inrush current.

[0016] Furthermore, the surge current suppression circuit also includes a current-limiting resistor R3 and a current-limiting resistor R4. The current-limiting resistor R4 and the current-limiting resistor R4 are connected in parallel, with one end connected to the cathode of the diode D2 and the other end connected to the drain of the MOS transistor Q1.

[0017] Preferably, the MOSFET Q1 is a P-channel MOSFET.

[0018] Preferably, the power line spike signal suppression and power signal filtering circuit includes a common-mode inductor L1, a common-mode inductor L2, capacitors C2, C3, C5, and C6. The drain of the MOSFET Q1 is connected to the first end of the common-mode inductor L1, the other end of the resistor R2 is connected to the second end of the common-mode inductor L1, one end of capacitor C2, one end of capacitor C6, and the first end of the common-mode inductor L2 are connected to the third end of the common-mode inductor L1, the other end of capacitor C6 is connected to one end of capacitor C5 and grounded, the other ends of capacitor C2 and C5 are connected to the second end of the common-mode inductor L2, the third and fourth ends of the common-mode inductor L2 are the positive and negative output terminals of the circuit, respectively, and capacitor C3 is connected in parallel between the third and fourth ends of the common-mode inductor L2. In steady-state operation, the analog DC voltage source charges capacitor C2 through the current-limiting resistor R3 to suppress the inrush current.

[0019] The inrush current suppression circuit is located on the positive power line, avoiding interference with the negative line level; inrush current suppression is achieved through a MOSFET and a current-limiting resistor; power supply spike signal suppression is achieved by configuring an LC filter circuit; during steady-state operation, the circuit achieves low-power operation by utilizing the internal resistance of the MOSFET; and the circuit is also miniaturized.

[0020] In the specific implementation process, when the electrical equipment is powered on, the lack of a soft start function causes a sudden change in the current of the power supply line at the moment of startup. If the power supply line cannot provide a large instantaneous current supply, the voltage amplitude on the power supply line will oscillate, causing the test items to exceed the standard. In severe cases, it can cause the power supply to oscillate for a long time and burn out the power supply. The electrical equipment uses mechanical switches, and the switching device is not designed with a switch spike absorption circuit. When the switch is toggled, the switch spring vibrates and generates an electric spark, causing voltage spikes in the line, resulting in the project exceeding the standard. Based on the above principle analysis, the excessive voltage is mainly caused by power transients in the back-end equipment and switching fluctuations in the circuit. To address the voltage fluctuation problem caused by this type of issue, the solution is to use large-capacity capacitors and inductors to construct a filter circuit.

[0021] Therefore, preferably, capacitors C2 and C3 are both large-capacity capacitors with a total capacity of 122 uF. The large-capacity capacitors provide instantaneous current supply to the electrical equipment and stabilize the line voltage amplitude. The inductor can reduce the instantaneous current surge in the line and slow down the power-on process of the electrical equipment. Considering that the voltage oscillation duration may be long and the oscillation waveform has a wide bandwidth, two-stage inductors are set in the circuit design for wide bandwidth suppression.

[0022] Preferably, the simulated DC voltage source is a 28V high-voltage power supply.

[0023] The preferred embodiments of this disclosure have been described in detail above with reference to the accompanying drawings. However, this disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of this disclosure, various simple modifications can be made to the technical solutions of this disclosure, and these simple modifications all fall within the protection scope of this disclosure.

[0024] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0025] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A power line spike signal suppression circuit with inrush current suppression function, characterized in that, include: The inrush current suppression circuit and the power line spike signal suppression and power signal filtering circuit are connected in sequence. The inrush current suppression circuit is used to suppress inrush current when the circuit is powered on and to achieve low power consumption operation when the circuit is in steady state. The power line spike signal suppression and power signal filtering circuit is used to suppress power spike signals when the circuit is powered on. The surge current suppression circuit includes resistor R1, resistor R2, capacitor C1, diode D2 and MOSFET Q1. Resistor R1, resistor R2, capacitor C1 and diode D2 constitute the driving circuit of MOSFET Q1. The driving circuit includes transient and steady-state operating states. One end of resistor R1, one end of capacitor C1, the cathode of diode D2, and the source of MOSFET Q1 are all connected to the positive terminal of the analog DC voltage source. The other end of resistor R1, the other end of capacitor C1, the anode of diode D2, and the gate of MOSFET Q1 are all connected to one end of resistor R2. The other end of resistor R2 is connected to the negative terminal of the analog DC voltage source and the second input terminal of the power line spike signal suppression and power signal filtering circuit. The drain of MOSFET Q1 is connected to the first input terminal of the power line spike signal suppression and power signal filtering circuit. In transient operation, resistors R1 and R2 form a voltage divider circuit. The voltage across resistor R2 is used to drive MOSFET Q1 to conduct in a steady state. At this time, MOSFET Q1 is fully turned on, and the back-end equipment works normally. In steady-state operation, when the analog DC voltage source outputs power, resistor R2 and capacitor C1 form an RC charging circuit and charge capacitor C1. The voltage across capacitor C1 is the driving voltage of MOSFET Q1.

2. The power line spike signal suppression circuit with inrush current suppression function according to claim 1, characterized in that, The MOSFET Q1 is a P-channel MOSFET.

3. A power line spike signal suppression circuit with inrush current suppression function according to claim 1, characterized in that, The surge current suppression circuit also includes current-limiting resistors R3 and R4. One end of the current-limiting resistor R4 is connected in parallel to the cathode of the diode D2, and the other end is connected to the drain of the MOS transistor Q1.

4. A power line spike signal suppression circuit with inrush current suppression function according to claim 3, characterized in that, The power line spike signal suppression and power signal filtering circuit includes a common-mode inductor L1, a common-mode inductor L2, capacitors C2, C3, C5, and C6. The drain of the MOSFET Q1 is connected to the first terminal of the common-mode inductor L1. The other terminal of the resistor R2 is connected to the second terminal of the common-mode inductor L1. One terminal of capacitor C2, one terminal of capacitor C6, and the first terminal of the common-mode inductor L2 are connected to the third terminal of the common-mode inductor L1. The other terminal of capacitor C6 is connected to one terminal of capacitor C5 and grounded. The other terminals of capacitor C2 and C5 are connected to the second terminal of the common-mode inductor L2. The third and fourth terminals of the common-mode inductor L2 are the positive and negative output terminals of the circuit, respectively. The capacitor C3 is connected in parallel between the third and fourth terminals of the common-mode inductor L2. In steady-state operation, the analog DC voltage source charges capacitor C2 through the current-limiting resistor R3 to suppress the inrush current.

5. A power line spike signal suppression circuit with inrush current suppression function according to claim 4, characterized in that, The total capacitance of capacitors C2 and C3 is 122 uF.

6. A power line spike signal suppression circuit with inrush current suppression function according to claim 1, characterized in that, The simulated DC voltage source is a 28V high-voltage power supply.

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