A floating power rail generation circuit

Abstract

The application discloses a floating power rail generating circuit, relates to the technical field of power management, and aims to solve the technical problem that a bootstrap diode and a bootstrap capacitor required for generating a floating power rail are too large in size and are difficult to integrate in a single chip in the prior art. The floating power rail generating circuit provided by the application establishes a driving voltage between the control end of a first switch tube and a floating ground through a switch driving circuit based on an externally input oscillation signal; a first clamping circuit clamps the potential of the control end relative to the floating ground at a steady-state reference potential; the first switch tube is turned on under the action of the driving voltage, and the potential of the output end of the first switch tube follows the potential of the control end, thereby establishing a power supply path from a first power supply to the floating power rail. It can be seen that the application supplies power to the floating power rail through potential following and steady-state clamping, replaces large-size bootstrap diodes and bootstrap capacitors with low-voltage devices, and is easy to integrate in a single chip, thereby effectively improving the overall integration degree of a power supply system.

Description

Technical Field

[0001] This invention relates to the field of power management technology, and in particular to a floating power rail generation circuit. Background Technology

[0002] In power management and motor control scenarios involving high-side switching and half-bridge drives, the drive circuit typically includes two series-connected switching transistors. The transistor connected to the high-voltage power supply is called the high-side switch, and the transistor connected to ground is called the low-side switch. The circuit dedicated to controlling the high-side switch's on / off state is called the high-side drive stage circuit. During operation, the potential of the connection point between the high-side and low-side switches (i.e., the floating ground) can fluctuate significantly between ground and the high-voltage bus voltage. To ensure the high-side drive stage circuit functions correctly, it must be provided with a floating power rail with a stable voltage difference relative to the floating ground. Directly using high-voltage transistors as the main transistors in the design of this high-side drive stage circuit would result in a large chip area and high cost. The traditional approach to solving this problem is to use a bootstrap circuit composed of a bootstrap diode and a bootstrap capacitor to generate the floating power rail, thus allowing the use of low-voltage devices in the design of the high-side drive stage circuit. However, the bootstrap diode in this design needs to withstand a high reverse voltage and provide a large surge charging current, resulting in a large power rating and size. Simultaneously, to meet the continuous power supply requirements of the high-side drive stage circuit during the floating ground high potential period, the bootstrap capacitor also needs a large capacitance. These large-size devices are difficult to integrate onto a single chip and typically can only be connected off-chip as discrete components, leading to limited overall integration of the power supply system. Summary of the Invention

[0003] The purpose of this invention is to provide a floating power rail generation circuit to solve the technical problem in the prior art that relies on high-power bootstrap diodes and large-capacitance bootstrap capacitors to generate floating power rails, which requires excessively large device sizes and is difficult to integrate into a single chip.

[0004] To solve the above-mentioned technical problems, the present invention provides a floating power rail generation circuit, comprising: A switch driving circuit, the output terminal of which is connected to the control terminal of the first switch transistor and the reference terminal is connected to the floating ground, is used to establish and maintain a drive voltage between the control terminal of the first switch transistor and the floating ground based on the received oscillation signal. The first switching transistor has its input terminal connected to the first power supply and its output terminal connected to the floating power rail. It is used to turn on under the action of the driving voltage and make the potential of the output terminal follow the potential of the control terminal so as to supply power to the floating power rail. The first clamping circuit has a first end connected to the control terminal of the first switching transistor and a second end connected to the floating ground, used to clamp the potential of the control terminal relative to the floating ground at a preset steady-state reference potential.

[0005] Optionally, the switch drive circuit includes: The first capacitor has a first terminal used to receive an oscillation signal and to output a displacement current based on the oscillation signal. The first PMOS transistor is equipped with a parasitic diode. The drain of the first PMOS transistor is connected to the second terminal of the first capacitor, and the source and gate are shorted together and the common terminal is connected to the control terminal of the first switching transistor. The second capacitor has its first end connected to the control terminal of the first switching transistor and its second end connected to floating ground.

[0006] Optionally, the first clamping circuit includes: The first Zener diode has its cathode connected to the control terminal of the first switching transistor and its anode connected to floating ground.

[0007] Optional, also includes: The second clamping circuit has a first end connected to the floating power rail, a second end connected to the control terminal of the first switching transistor, and a third end connected to the floating ground. It is used to conduct the discharge path between the second and third ends when the voltage difference between the floating power rail and the floating ground is greater than a preset overvoltage threshold, so as to reduce the driving voltage and thus cause the potential of the floating power rail to drop accordingly.

[0008] Optionally, the second clamping circuit includes: The overvoltage detection circuit has its first end connected to the floating power rail and its second end connected to the floating ground. It is used to detect the voltage difference between the floating power rail and the floating ground, and outputs a conduction signal when the voltage difference is greater than the overvoltage threshold. The discharge circuit has its first terminal connected to the control terminal of the first switching transistor and its second terminal connected to the floating ground. The control terminal is connected to the output terminal of the overvoltage detection circuit and is used to discharge the charge at the control terminal of the first switching transistor based on the conduction signal.

[0009] Optionally, the overvoltage detection circuit includes: The second Zener diode, with its cathode connected to the floating power rail; The depletion-type MOSFET has its drain connected to the anode of the second Zener diode, and its gate and source are shorted to a common ground, which is used as a constant current source to provide bias current.

[0010] Optionally, the discharge circuit includes: The first NMOS transistor has its drain connected to the control terminal of the first switching transistor, its source connected to floating ground, and its gate connected to the anode of the second Zener diode to receive the turn-on signal.

[0011] Optional, also includes: The drain of the second NMOS transistor is connected to the control terminal of the first switch transistor, the source is connected to floating ground, and the gate is used to receive the externally input enable signal.

[0012] Optional, also includes: The pre-charge circuit has its input connected to a second power supply and its output connected to a floating power rail. It is used to turn on when an external start signal is received, so that the current from the second power supply flows to the floating power rail to establish an initial potential for the floating power rail.

[0013] Optionally, the pre-charge circuit includes: The third NMOS transistor has its drain connected to the second power supply, and its gate is used to receive the start signal. The fourth NMOS transistor has its drain connected to the source of the third NMOS transistor, its gate used to receive the start signal, and its source connected to the floating power rail. The second PMOS transistor is equipped with a parasitic diode. The drain of the second PMOS transistor is connected to the switch drive circuit, and the source and gate are shorted together and the common terminal is connected to the floating power rail.

[0014] This invention provides a floating power rail generation circuit, including a switch driving circuit, a first switching transistor, and a first clamping circuit. The switch driving circuit establishes and maintains a driving voltage between the control terminal of the first switching transistor and the floating ground based on an externally input oscillation signal. The first clamping circuit clamps the potential of the control terminal relative to the floating ground at a preset steady-state reference potential. The first switching transistor is turned on under the driving voltage, and its output potential follows the potential of the control terminal, establishing a controlled power supply path from the first power source to the floating power rail. This process ensures that the power supply of the high-side drive stage circuit during the high potential of the floating ground no longer solely relies on the energy storage and discharge of a large-capacity bootstrap capacitor, while also avoiding the need to rely on traditional high-power bootstrap diodes to withstand high-voltage reverse voltage and surge charging current. Therefore, the floating power rail generation circuit provided by this invention, by using low-voltage devices to replace traditional large-size bootstrap diodes and bootstrap capacitors, makes the circuit structure easier to integrate within a single chip, effectively improving the overall integration of the power system. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the prior art and embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A structural diagram of the floating power rail generation circuit provided by the present invention; Figure 2 This is a structural diagram of a traditional floating power rail bootstrap circuit. Figure 3 A waveform diagram of a floating power rail generation circuit provided by the present invention; Figure 4 A waveform diagram of another floating power rail generation circuit provided by the present invention. Detailed Implementation

[0017] The core of this invention is to provide a floating power rail generation circuit, which aims to eliminate the dependence on high-power bootstrap diodes and large-capacitance bootstrap capacitors, provide a stable and safe floating power rail for the high-side drive stage circuit, and can be integrated into a single chip to improve the overall integration of the power system.

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] This invention provides a floating power rail generation circuit, such as Figure 1 As shown, Figure 1 A structural diagram of the floating power rail generation circuit provided by the present invention. The floating power rail generation circuit includes: A switch driving circuit is provided, with its output terminal connected to the control terminal of the first switch transistor MNH_LVT_1 and its reference terminal connected to the floating ground. The circuit is used to establish and maintain a drive voltage between the control terminal of the first switch transistor MNH_LVT_1 and the floating ground based on the received oscillation signal VPULSE. The first switching transistor MNH_LVT_1 has its input terminal connected to the first power supply VS+5 and its output terminal connected to the floating power rail. It is used to turn on under the action of the driving voltage and make the potential of the output terminal follow the potential of the control terminal to supply power to the floating power rail. The first clamping circuit has its first end connected to the control terminal of the first switching transistor MNH_LVT_1 and its second end connected to the floating ground. It is used to clamp the potential of the control terminal relative to the floating ground at a preset steady-state reference potential.

[0020] First, it should be noted that the floating power rail generation circuit provided in this embodiment is typically used in power systems that include a high-side driver stage circuit, a low-side driver stage circuit, and a driver chip. In such power systems, due to the limited layout area of ​​the chip, large-capacity capacitors cannot be integrated inside the driver chip. Therefore, when the potential of the floating ground changes dramatically, how to continuously provide a stable supply voltage with a voltage drop that meets the requirements for the high-side driver stage circuit using only small-sized components inside the chip, without relying on high-power bootstrap diodes and large-capacity bootstrap capacitors, is a technical problem that urgently needs to be solved by those skilled in the art.

[0021] like Figure 2 As shown, Figure 2 This is a schematic diagram of a traditional floating power rail bootstrap circuit. In this circuit, the voltage supplied by the high-voltage bus (VS2 terminal) is converted into a 5V low-voltage DC current VDD by a low-dropout regulator (LDO). Subsequently, the low-voltage DC current VDD charges the floating power rail VDDH2 through the bootstrap diode D21. At this time, capacitor C21 is connected between the output of the LDO and the system ground GND for voltage regulation and filtering. Bootstrap capacitor C22 is connected across the floating power rail VDDH2 and the floating ground SW2. When the potential of the main circuit switching node SW2 experiences large jumps and fluctuations, the bootstrap diode D1 is reverse-biased and cut off. This scheme mainly relies on the energy storage and voltage regulation function of the bootstrap capacitor C22 itself to maintain a DC voltage difference of approximately 5V between the floating power rail VDDH2 and the switching node SW2.

[0022] However, in this traditional structure, the bootstrap diode D21 needs to withstand a high reverse voltage and a large charging current during operation, resulting in a large physical size and power rating. Simultaneously, to maintain a stable voltage drop during potential fluctuations, the bootstrap capacitor C22 must have a very large capacitance. These large components are difficult to integrate directly into a single driver chip, severely limiting the improvement of overall circuit integration.

[0023] Based on this, in this embodiment, the switch driving circuit continuously receives the input oscillation signal VPULSE and converts it into a driving voltage, which is applied between the control terminal of the first switch MNH_LVT_1 and the floating ground to drive the first switch MNH_LVT_1 to conduct. During conduction, the first clamping circuit limits the potential difference between the control terminal of the first switch MNH_LVT_1 and the floating ground to a preset steady-state reference potential. The first switch MNH_LVT_1 is equivalent to a voltage follower; the potential at its output terminal follows the potential change at the control terminal, thereby establishing and maintaining a stable DC voltage difference between the floating power rail and the floating ground. As long as the oscillation signal VPULSE is continuously input during the above process, the steady-state reference potential at the control terminal is prevented from dropping, thus ensuring continuous power supply to the floating power rail.

[0024] It should be noted that the first switching transistor MNH_LVT_1 is preferably a high-voltage, low-threshold MOSFET. Using a high-voltage, low-threshold device effectively reduces the on-resistance in the current path, ensuring a sufficiently large DC voltage difference between the floating power rail and the floating ground. When it is turned on and operating in the saturation region, it is equivalent to a source follower. The physical characteristic of this operating mode is that the source potential closely follows the gate potential, and the floating power rail potential VDDH at the output terminal satisfies the following relationship: , of which are The potential of node B at the control terminal of the first switching transistor MNH_LVT_1. The gate-source voltage of the first switching transistor MNH_LVT_1.

[0025] Furthermore, the aforementioned first clamping circuit can be implemented using a Zener diode. Its reverse breakdown characteristic limits the highest voltage at the control terminal relative to the floating ground to a specific threshold (e.g., approximately 5.5V), thereby stabilizing the relative voltage difference of the floating power rail within the expected range (e.g., around 5V). Further, the first power supply VS+5, which powers the first switching transistor, can be obtained from the second power supply VS via a charge pump, and this second power supply is directly connected to the high-voltage bus. Using a charge pump allows direct power drawing from the high-voltage bus and providing a bias input to the first switching transistor that is higher than the bus voltage, thus eliminating the need for an external, independent low-voltage power supply module. This improves the internal direct power supply path and further enhances the overall integration of the power supply system.

[0026] As can be seen, the floating power rail generation circuit provided in this embodiment utilizes the VPULSE oscillation signal drive and potential voltage follower circuit structure to achieve continuous and stable power supply to the floating power rail. This effectively overcomes the defect of traditional bootstrap circuits that are prone to power loss when operating at a large duty cycle. Furthermore, it does not rely on high-power bootstrap diodes and large-capacitance bootstrap capacitors, effectively reducing the chip layout area. This makes it easier to integrate the circuit structure within a single chip, effectively improving the overall integration of the power system and saving space on external circuit boards, which helps to reduce the overall hardware cost.

[0027] Based on the above embodiments: As an optional embodiment, the switch drive circuit includes: The first capacitor C1, the first terminal of the first capacitor C1 is used to receive the oscillation signal VPULSE, and is used to output displacement current based on the oscillation signal VPULSE; The first PMOS transistor MP1 is equipped with a parasitic diode. The drain of the first PMOS transistor MP1 is connected to the second terminal of the first capacitor C1, and the source and gate are shorted together and the common terminal is connected to the control terminal of the first switching transistor MNH_LVT_1. The second capacitor C2 has its first end connected to the control terminal of the first switching transistor MNH_LVT_1, and its second end connected to the floating ground.

[0028] Considering that when transmitting drive current to the high-voltage floating power rail where the potential may change frequently inside the switching drive circuit, using conventional high-voltage isolation diodes for rectification would not only occupy a large chip layout area, but also easily cause leakage problems when the floating potential changes.

[0029] Based on this, in this embodiment, the first terminal of the first capacitor C1 continuously receives the oscillation signal VPULSE. Utilizing the physical characteristic of a capacitor to pass AC and block DC, the continuously changing oscillation signal VPULSE is converted into a displacement current and output to the second terminal of the first capacitor C1 (i.e., node A). Simultaneously, since the source and gate of the first PMOS transistor MP1 are short-circuited, its internal parasitic diode is configured as a unidirectional conduction path to perform rectification. After the displacement current passes through the parasitic diode in the forward direction, it charges the second capacitor C2. The second capacitor C2 smooths the potential at its first terminal (i.e., the potential at node B), thereby providing a stable bias voltage for the first switching transistor MNH_LVT_1.

[0030] It should be noted that in this embodiment, the parasitic body diode of the first PMOS transistor MP1 is preferably used as the unidirectional transmission path for the displacement current. Because PMOS transistors have an additional N-well structure in semiconductor manufacturing processes, this N-well structure is equivalent to adding a physical isolation layer between the device and the common silicon substrate at the bottom of the chip. During the actual operation of this circuit, the potential of node A will fluctuate significantly following the potential of the floating ground. Utilizing this additional N-well structure of the first PMOS transistor MP1 can cut off the current flow path to the common silicon substrate at the bottom of the chip, thereby effectively avoiding leakage problems caused by the large potential variation range at this node.

[0031] Furthermore, the oscillation signal VPULSE input to the first capacitor C1 is generated by an independent oscillation circuit inside the chip, and its frequency is independent of the switching frequency of the half-bridge or full-bridge power drive circuit that uses this floating power rail generation circuit. Those skilled in the art can control the magnitude of the output displacement current by adjusting the input frequency of the oscillation signal VPULSE or the physical capacitance of the first capacitor C1, according to actual needs, to match the quiescent current required for the first switching transistor MNH_LVT_1 to turn on.

[0032] As can be seen, this embodiment achieves unidirectional energy transfer by introducing a structure that combines a low-voltage capacitor with a parasitic diode of a PMOS transistor, using easily integrated low-voltage devices, effectively avoiding the risk of leakage during potential transitions.

[0033] As an optional embodiment, the first clamping circuit includes: The cathode of the first Zener diode DZ1 is connected to the control terminal of the first switching transistor MNH_LVT_1, and the anode is connected to the floating ground.

[0034] In the floating power rail generation circuit, the first switching transistor MNH_LVT_1 is equivalent to a voltage follower, and its output voltage is directly determined by the potential of its control terminal. When the floating ground potential fluctuates frequently or drastically, the potential difference between the control terminal of the first switching transistor MNH_LVT_1 and the floating ground will fluctuate accordingly. An excessively high potential difference can cause the output voltage of the floating power rail to exceed the limit, and may even exceed the safe operating voltage boundary of the low-voltage devices in the subsequent high-side drive stage circuit, leading to device damage.

[0035] Based on this, in this embodiment, the first Zener diode DZ1 is connected in reverse parallel between the control terminal of the first switching transistor MNH_LVT_1 and the floating ground. When the upstream switching drive circuit continuously charges the control terminal of the first switching transistor MNH_LVT_1, the potential of the control terminal B relative to the floating ground SW gradually increases. Once this potential difference reaches the reverse breakdown voltage of the first Zener diode DZ1, the first Zener diode DZ1 enters the reverse breakdown state, directly discharging the excess charging current to the floating ground. Through the above process, the highest voltage difference between the control terminal B of the first switching transistor MNH_LVT_1 and the floating ground is fixed at a preset steady-state reference potential. At this time, the control terminal potential of the first switching transistor MNH_LVT_1 is... ,in, The potential of the floating ground. This is the reverse breakdown voltage of the first Zener diode DZ1. Since the first switching transistor MNH_LVT_1 is in follower mode, the DC voltage difference between the floating power rail VDDH and the floating ground SW is stabilized within the expected power supply range.

[0036] Those skilled in the art can select the first Zener diode DZ1 with the corresponding reverse breakdown voltage value and design it in conjunction with the physical characteristics of the transistor itself, based on the specific power supply requirements of the high-side drive stage circuit in practical applications. For example, since the floating power rail VDDH potential at the output of the first switching transistor MNH_LVT_1 satisfies the following relationship: , of which are This is the control terminal potential of the first switching transistor MNH_LVT_1. This is the gate-source voltage of the first switching transistor MNH_LVT_1. If the first Zener diode DZ1 with a reverse breakdown voltage of 5V is selected, the potential at its control terminal is clamped at... Simultaneously, utilizing the low threshold characteristic of the first switching transistor MNH_LVT_1, its gate-source voltage when turned on is designed to be approximately equal to 0V (i.e., In this operating mode, the output potential naturally satisfies: ,Right now Therefore, it can be seen that the relative pressure difference between the floating power rail and the floating ground is precisely stabilized within the expected power supply range.

[0037] As can be seen, this embodiment introduces the first Zener diode DZ1 and utilizes the reverse breakdown characteristics of the component itself to achieve stable clamping of the control terminal potential, effectively preventing the overvoltage risk caused by floating potential jumps and maintaining the stability of the floating power rail power supply.

[0038] As an optional embodiment, it also includes: The second clamping circuit has a first terminal connected to the floating power rail, a second terminal connected to the control terminal of the first switching transistor MNH_LVT_1, and a third terminal connected to the floating ground. It is used to conduct the discharge path between the second and third terminals when the voltage difference between the floating power rail and the floating ground is greater than the preset overvoltage threshold, so as to reduce the driving voltage and thus cause the potential of the floating power rail to drop accordingly.

[0039] Considering that transient overvoltage fluctuations may occur between the floating power rail and the floating ground when the potential of the floating ground changes drastically or when the external load changes abruptly, if we rely solely on the static bias limitation of the first clamping circuit without an active dynamic discharge path, the excessively high voltage difference will still break down and damage the low-voltage components inside the subsequent high-side drive stage circuit.

[0040] Based on this, a second clamping circuit is introduced in this embodiment. Specifically, when the voltage difference between the floating power rail and the floating ground increases and exceeds a preset overvoltage threshold, the second clamping circuit is triggered to conduct, thereby establishing a low-impedance discharge path between the control terminal of the first switching transistor MNH_LVT_1 and the floating ground. Excess charge at the control terminal is discharged to the floating ground through this path, causing the drive voltage at the control terminal to drop. Since the first switching transistor MNH_LVT_1 operates in a follower state, the potential of the floating power rail will also drop accordingly, thereby readjusting the voltage difference to a safe range.

[0041] As can be seen, the second clamping circuit provided in this embodiment achieves active overvoltage protection for the floating power rail by discharging the charge at the control terminal, thus avoiding damage to the high-side drive stage circuit caused by transient overvoltage. Furthermore, the second clamping circuit works in conjunction with the aforementioned first clamping circuit responsible for maintaining the steady-state reference potential to jointly achieve dual voltage protection for the floating power rail.

[0042] As an optional embodiment, the second clamping circuit includes: The overvoltage detection circuit has its first end connected to the floating power rail and its second end connected to the floating ground. It is used to detect the voltage difference between the floating power rail and the floating ground, and outputs a conduction signal when the voltage difference is greater than the overvoltage threshold. The discharge circuit has its first terminal connected to the control terminal of the first switching transistor MNH_LVT_1, and its second terminal connected to the floating ground. The control terminal is connected to the output terminal of the overvoltage detection circuit and is used to discharge the charge at the control terminal of the first switching transistor MNH_LVT_1 based on the conduction signal.

[0043] In integrated circuit design, if conventional operational amplifiers or comparators are used to implement overvoltage protection detection and feedback, it will not only increase additional bias power consumption, but also occupy more chip layout area. Furthermore, the signal transmission of multi-stage amplification will introduce response delay, making it difficult to cope with nanosecond-level potential jumps.

[0044] Based on this, this embodiment constructs a hardware protection response path through an overvoltage detection circuit and a discharge circuit. Specifically, the overvoltage detection circuit is connected in parallel between the floating power rail and the floating ground to detect the voltage difference between them in real time. When the voltage difference reaches a preset overvoltage threshold, the overvoltage detection circuit is triggered and outputs a conduction signal. Upon receiving the conduction signal, the discharge circuit quickly turns on, forming a low-impedance path between the control terminal of the first switching transistor MNH_LVT_1 and the floating ground, discharging excess charge from the control terminal to the floating ground.

[0045] As can be seen, this embodiment achieves fast overvoltage response and discharge with fewer components by directly connecting the overvoltage detection circuit and the discharge circuit, thus reducing the circuit complexity inside the driver chip.

[0046] As an optional embodiment, the overvoltage detection circuit includes: The cathode of the second Zener diode DZ2 is connected to the floating power rail; The depletion-type MOSFET MNDEP_1 has its drain connected to the anode of the second Zener diode DZ2. The common terminal of the depletion-type MOSFET, which is shorted between its gate and source, is connected to a floating ground and is used as a constant current source to provide bias current.

[0047] Specifically, in this embodiment, the reverse breakdown characteristic of the second Zener diode DZ2 is used to set the overvoltage threshold. When the voltage difference between the floating power rail and the floating ground exceeds the reverse breakdown voltage of the second Zener diode DZ2, the second Zener diode DZ2 breaks down and generates current. Simultaneously, the depletion-type MOSFET MNDEP_1, due to its gate-source short circuit, is equivalent to a constant current source in the circuit. This constant current source structure provides a stable bias current for the path after breakdown, thereby converting the breakdown current of the second Zener diode DZ2 into a stable voltage rise at the anode of the second Zener diode DZ2, forming a reliable turn-on signal output to the subsequent stage.

[0048] It should be noted that in the specific chip layout design, the reverse breakdown voltage of the second Zener diode DZ2 in this embodiment is designed to be slightly lower than that of the first Zener diode DZ1, and the physical area of ​​the second Zener diode DZ2 can be designed to be larger than that of the first Zener diode DZ1 in the first clamping circuit. This allows the second Zener diode DZ2 to break down preferentially over the first Zener diode DZ1 when encountering overvoltage surges, thereby initiating the discharge protection action immediately and possessing a stronger surge current discharge capability. The second Zener diode DZ2 works in conjunction with the aforementioned first Zener diode DZ1, which is responsible for maintaining the steady-state reference potential, to jointly achieve voltage protection for the floating power rail.

[0049] As can be seen, this embodiment utilizes the series combination of a Zener diode and a depletion-type MOSFET MNDEP_1 to achieve accurate detection of the overvoltage threshold and stable output of the conduction signal, thereby improving anti-interference capability.

[0050] As an optional embodiment, the discharge circuit includes: The drain of the first NMOS transistor MN1 is connected to the control terminal of the first switching transistor MNH_LVT_1, the source is connected to floating ground, and the gate is connected to the anode of the second Zener diode DZ2 to receive the turn-on signal.

[0051] Considering that after receiving the conduction signal from the overvoltage detection circuit, the device that performs charge discharge must have the characteristics of fast response speed, strong current carrying capacity and small area, so as to pull down the potential of the control terminal of the first switching transistor MNH_LVT_1 in the shortest possible time.

[0052] Based on this, in this embodiment, a first NMOS transistor MN1 is used as the discharge actuator. The first NMOS transistor MN1 can be a standard low-voltage NMOS device, and its gate is directly connected to the anode of the second Zener diode DZ2. When overvoltage occurs, the anode potential rises and exceeds the turn-on voltage of the first NMOS transistor MN1, the first NMOS transistor MN1 quickly turns on, forming a low-impedance path between the control terminal of the first switching transistor MNH_LVT_1 and the floating ground, quickly discharging the charge accumulated at the control terminal to the floating ground.

[0053] As can be seen, this embodiment utilizes the low-voltage first NMOS transistor MN1 to directly perform the discharge action, thereby achieving rapid zeroing of charge under overvoltage conditions with basic low-voltage hardware.

[0054] As an optional embodiment, it also includes: The drain of the second NMOS transistor MN2 is connected to the control terminal of the first switching transistor MNH_LVT_1, the source is connected to floating ground, and the gate is used to receive the external input enable signal EN.

[0055] Considering that in the actual operation of half-bridge or full-bridge power drive circuits, the power supply system may detect serious faults such as external load short circuits or chip overheating, it is necessary to add a scheme to forcibly disconnect the floating power rail supply from the underlying hardware for safety reasons.

[0056] Based on this, in this embodiment, a second NMOS transistor MN2 is connected in parallel between the control terminal of the first switching transistor MNH_LVT_1 and the floating ground. When the power system detects a fault or other conditions requiring emergency shutdown, it sends a high-level enable signal EN to the gate of the second NMOS transistor MN2. Driven by the enable signal EN, the second NMOS transistor MN2 is forcibly turned on, directly pulling down the potential of the control terminal of the first switching transistor MNH_LVT_1 to be flush with the floating ground. As the potential at the control terminal drops, the first switching transistor MNH_LVT_1 is quickly turned off, thereby cutting off the power supply to the floating power rail.

[0057] It should be noted that the enable signal EN has the highest intervention priority. Regardless of whether the external oscillation signal VPULSE continues to be input, as long as the enable signal EN is valid, the conduction of the second NMOS transistor MN2 will forcibly terminate the voltage follower process.

[0058] As can be seen, by introducing a second NMOS transistor MN2, this embodiment adds a reliable hardware-level fault shutdown channel to the floating power rail generation circuit, thereby improving the safety of the overall power system under abnormal operating conditions.

[0059] As an optional embodiment, it also includes: The pre-charge circuit has its input connected to the second power supply VS and its output connected to the floating power rail. It is used to turn on when it receives the external input start signal IN_LEVELSHIFT, so that the current of the second power supply VS flows to the floating power rail to establish the initial potential of the floating power rail.

[0060] Considering that during the initial power-on or startup phase of the driver chip, the floating power rail and floating ground have not yet established a potential difference, and the internal node potentials are all zero, and since the aforementioned switch driver circuit needs several clock cycles to accumulate charge and establish a steady-state reference based on the oscillation signal VPULSE, the high-side driver stage circuit may face the risk of insufficient power supply voltage during the initial startup phase without intervention.

[0061] Based on this, a pre-charge circuit is added in this embodiment. Before the high-side driver stage circuit is ready to operate, the pre-charge circuit receives a high-level start signal IN_LEVELSHIFT from an external input and turns on accordingly. At this time, the pre-charge circuit conducts between the second power supply VS and the floating power rail, and the current of the second power supply VS quickly flows to the floating power rail, providing it with an initial potential.

[0062] It should be noted that the upper limit of the high-level start signal IN_LEVELSHIFT input must be limited to the potential of the second power supply VS. This limitation can effectively avoid the risk of reverse leakage to the high-voltage side through the parasitic capacitance of the device if the potential of the floating power rail rises during subsequent operation.

[0063] As can be seen, this embodiment eliminates the power supply blind spot in the early stage of startup by intervening in advance through the pre-charging circuit, and shortens the startup setup time of the high-side drive stage circuit.

[0064] As an optional embodiment, the pre-charge circuit includes: The third NMOS transistor MN3 has its drain connected to the second power supply VS, and its gate is used to receive the start signal IN_LEVELSHIFT. The fourth NMOS transistor MN4 has its drain connected to the source of the third NMOS transistor MN3, its gate used to receive the start signal IN_LEVELSHIFT, and its source connected to the floating power rail. The second PMOS transistor MP2 is equipped with a parasitic diode. The drain of the second PMOS transistor MP2 is connected to the switch drive circuit, and the source and gate are shorted together and the common terminal is connected to the floating power rail.

[0065] Considering that the second power supply VS is usually a high-voltage bus when performing the pre-charging action, if the pre-charging path cannot be automatically cut off according to the potential change of the floating power rail, it is very easy to cause the floating power rail to be overcharged and damage the downstream circuit. At the same time, when the pre-charging ends and the floating ground potential jumps with the main circuit, if reverse isolation is not performed, the charge of the floating power rail will cause serious backflow leakage to the second power supply VS.

[0066] Based on this, in this embodiment, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 are connected in series and operate as source followers in the saturation region under the drive of the start signal IN_LEVELSHIFT. The pre-charge current flows sequentially from the second power supply VS through the third NMOS transistor MN3 and the fourth NMOS transistor MN4 to the floating power rail, and then conducts forward through the parasitic body diode of the second PMOS transistor MP2, inputting into the switch drive circuit (i.e., node A) to establish the initial potential. As the floating power rail potential continuously rises, the voltage difference between the gate and source of the third NMOS transistor MN3 and the fourth NMOS transistor MN4 gradually decreases; when this potential approaches the expected initial potential, the third NMOS transistor MN3 and the fourth NMOS transistor MN4 automatically transition to the cutoff region, thus completing the pre-charge and autonomous turn-off path. The third NMOS transistor MN3 can be a high-voltage device to withstand the system high voltage, while the fourth NMOS transistor MN4 can be a low-voltage device to reduce the on-state voltage drop.

[0067] It should be noted that the third NMOS transistor MN3 is preferably a high-voltage, low-threshold NMOS transistor. Using a high-voltage device ensures it can withstand the high voltage of the system bus, while the low-threshold characteristic helps reduce the on-state voltage drop on the pre-charge path, improving the initial potential establishment efficiency. Furthermore, the source and gate of the second PMOS transistor MP2 are shorted, allowing its parasitic body diode to be configured as a reverse blocking element, effectively preventing current from flowing back from the switching drive circuit during floating potential transitions.

[0068] As can be seen, this embodiment utilizes a multi-transistor series source follower and a body diode unidirectional isolation structure to achieve automatic cutoff during the pre-charging process and reliable reverse leakage protection, thus balancing startup speed and steady-state safety.

[0069] To further illustrate the working process and technical effects of the floating power rail generation circuit provided in the embodiments of the present invention, the following detailed explanation is provided in conjunction with simulation waveform diagrams.

[0070] like Figure 3 As shown, Figure 3 This is a waveform diagram of a floating power rail generation circuit provided by the present invention. Figure 3 In the diagram, from top to bottom, are the start signal IN_LEVELSHIFT, the oscillation signal VPULSE, the potential A-SW of the second terminal of the first capacitor relative to the floating ground, the potential B-SW of the control terminal of the first switch relative to the floating ground, and the voltage difference VDDH-SW of the floating power rail. When the start signal IN_LEVELSHIFT is valid, the switch drive circuit begins to receive the continuously toggling oscillation signal VPULSE. Through the charging and discharging of the capacitor and the rectification effect of the parasitic diode, the potential A-SW of the second terminal of the first capacitor relative to the floating ground rises in a stepped manner, accompanied by high-frequency pumping fluctuations. Charge is continuously transferred to the control terminal of the first switch, causing the potential B-SW of the control terminal of the first switch to gradually establish. When the potential B-SW of the control terminal of the first switch relative to the floating ground rises to the reverse breakdown threshold of the first clamping circuit, its potential stops rising and is precisely clamped at the steady-state reference level. During this process, the first switch fully utilizes its source follower characteristics, and its output potential VDDH-SW rises closely following the control terminal potential, eventually maintaining a stable target supply voltage difference of approximately 5V. This waveform fully demonstrates the process by which the circuit establishes a steady-state direct power supply channel during the initial startup phase.

[0071] like Figure 4 As shown, Figure 4 A waveform diagram of another floating power rail generation circuit provided by the present invention. Figure 4In the diagram, the upper waveform represents the absolute potential SW of the floating ground, and the lower waveform represents the voltage difference VDDH-SW between the floating power rail and the floating ground. Under simulated conditions of significant floating ground fluctuations, the floating ground potential SW rapidly fluctuates from 0V to approximately 28V and maintains this level before rapidly dropping back to 0V. Observing the lower waveform, it can be seen that during the period of dramatic floating ground fluctuations, thanks to the source potential following characteristics of the first switching transistor and the steady-state maintenance and dynamic discharge jointly constructed by the first and second clamping circuits, the voltage difference VDDH-SW between the floating power rail and the floating ground does not experience destructive overshoot or drop, but is always clamped within a safe range of approximately 4.9V. Therefore, the floating power rail generation circuit provided by this invention does not rely on traditional bulky bootstrap devices; it effectively shields against interference caused by dramatic floating ground potential fluctuations through the coordinated feedback of on-chip low-voltage devices, improving the continuity, safety, and reliability of the power supply to the high-side drive stage circuit.

[0072] It should be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0073] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A floating power rail generation circuit, characterized in that, include: A switch driving circuit, wherein the output terminal of the switch driving circuit is connected to the control terminal of the first switch transistor and the reference terminal is connected to the floating ground, and is used to establish and maintain a driving voltage between the control terminal of the first switch transistor and the floating ground based on the received oscillation signal; The first switching transistor has its input terminal connected to a first power supply and its output terminal connected to a floating power rail. It is used to turn on under the action of the driving voltage and make the potential of the output terminal follow the potential of the control terminal so as to supply power to the floating power rail. A first clamping circuit, wherein a first end of the first clamping circuit is connected to the control terminal of the first switching transistor, and a second end is connected to the floating ground, is used to clamp the potential of the control terminal relative to the floating ground at a preset steady-state reference potential.

2. The floating power rail generation circuit as described in claim 1, characterized in that, The switch driving circuit includes: A first capacitor, wherein a first terminal of the first capacitor is used to receive the oscillation signal and to output a displacement current based on the oscillation signal; The first PMOS transistor is equipped with a parasitic diode. The drain of the first PMOS transistor is connected to the second terminal of the first capacitor, and the source and gate are shorted together and the common terminal is connected to the control terminal of the first switching transistor. The second capacitor has its first end connected to the control terminal of the first switching transistor and its second end connected to the floating ground.

3. The floating power rail generation circuit as described in claim 1, characterized in that, The first clamping circuit includes: A first Zener diode, the cathode of which is connected to the control terminal of the first switching transistor, and the anode of which is connected to the floating ground.

4. The floating power rail generation circuit as described in claim 1, characterized in that, Also includes: The second clamping circuit has a first end connected to the floating power rail, a second end connected to the control terminal of the first switching transistor, and a third end connected to the floating ground. When the voltage difference between the floating power rail and the floating ground is greater than a preset overvoltage threshold, the discharge path between the second end and the third end is opened to reduce the driving voltage, thereby causing the potential of the floating power rail to decrease accordingly.

5. The floating power rail generation circuit as described in claim 4, characterized in that, The second clamping circuit includes: An overvoltage detection circuit is provided, wherein a first end of the overvoltage detection circuit is connected to the floating power rail and a second end is connected to the floating ground, for detecting the voltage difference between the floating power rail and the floating ground, and outputting a conduction signal when the voltage difference is greater than the overvoltage threshold. A discharge circuit is provided, wherein a first end of the discharge circuit is connected to the control terminal of the first switching transistor, a second end is connected to the floating ground, and the control terminal is connected to the output terminal of the overvoltage detection circuit, and is used to discharge the charge at the control terminal of the first switching transistor based on the conduction signal.

6. The floating power rail generation circuit as described in claim 5, characterized in that, The overvoltage detection circuit includes: A second Zener diode, the cathode of which is connected to the floating power rail; A depletion-type MOSFET, wherein the drain of the depletion-type MOSFET is connected to the anode of the second Zener diode, and the common terminal of the depletion-type MOSFET with its gate and source shorted is connected to the floating ground, for use as a constant current source to provide bias current.

7. The floating power rail generation circuit as described in claim 6, characterized in that, The discharge circuit includes: The first NMOS transistor has its drain connected to the control terminal of the first switching transistor, its source connected to the floating ground, and its gate connected to the anode of the second Zener diode to receive the turn-on signal.

8. The floating power rail generation circuit as described in claim 1, characterized in that, Also includes: The second NMOS transistor has its drain connected to the control terminal of the first switch transistor, its source connected to the floating ground, and its gate used to receive an externally input enable signal.

9. The floating power rail generation circuit as described in any one of claims 1 to 8, characterized in that, Also includes: A pre-charging circuit is provided, wherein the input terminal of the pre-charging circuit is connected to a second power supply and the output terminal is connected to the floating power rail. The pre-charging circuit is used to turn on when an external start signal is received, so that the current of the second power supply flows to the floating power rail to establish an initial potential for the floating power rail.

10. The floating power rail generation circuit as described in claim 9, characterized in that, The pre-charging circuit includes: The third NMOS transistor has its drain connected to the second power supply and its gate used to receive the start signal. The fourth NMOS transistor has its drain connected to the source of the third NMOS transistor, its gate used to receive the start signal, and its source connected to the floating power rail. The second PMOS transistor is equipped with a parasitic diode. The drain of the second PMOS transistor is connected to the switch drive circuit, and the source and gate are shorted together and the common terminal is connected to the floating power rail.

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