MOS series flyback circuit and MOS tube gate level lifting method

Abstract

The application discloses a MOS series flyback circuit and a MOS tube gate level lifting method, and aims at solving the problems of existing MOS tube gate power supply voltage drop, limited drain current output capability and influence on full load performance of the whole machine. The circuit comprises a first capacitor, a first voltage stabilizing tube, a first MOS tube, a second MOS tube and a control chip. The first capacitor is connected with a bus positive electrode, and is charged by the bus. The first end of the first capacitor is connected with the input end of the control chip through the first voltage stabilizing tube, the second end is connected with the first MOS tube, and the control chip and the first MOS tube are supplied with power respectively. The output end of the control chip is connected with the second MOS tube. The first MOS tube and the second MOS tube are connected in series, and supply power to the load by changing the conduction or off state. In the power-on starting process, the first voltage stabilizing tube is adaptively adjusted through the reverse current, the voltage drop of the first capacitor is compensated, and the voltage of the first MOS tube gate is maintained.

Description

Technical Field

[0001] This application relates to the field of switching power supply technology, and in particular to a MOS series flyback circuit and a method for boosting the gate level of a MOS transistor. Background Technology

[0002] Silicon carbide MOSFET series flyback converters, with the advantages of high voltage withstand and low switching losses of SiC devices, can be adapted to a wide range of DC bus inputs from hundreds of volts to thousands of volts. As a medium-power isolated auxiliary power supply, they have been widely used in various complex power electronic conversion systems such as photovoltaic inverters, energy storage converters, industrial frequency converters, on-board charging equipment, and high-voltage frequency conversion complete sets of equipment.

[0003] The bus voltage fluctuation range of equipment such as photovoltaic, energy storage, and high-voltage frequency converters is extremely large. The series voltage divider structure of the upper and lower SiC MOS transistors can significantly reduce the voltage load on a single transistor, adapting to the application requirements of wide voltage input. At the same time, for short-term high-current impact loads such as disconnect switches and contactor coils, the power supply only needs to output peak current for a short time during power-on startup. The gate voltage of the upper SiC MOS transistor can be maintained within the safe operating range, meeting the requirements for safe gate voltage operation during the startup phase.

[0004] However, when the equipment runs continuously at full load for a long time, the capacitor continues to discharge, causing the voltage to drop. The gate supply voltage also drops, which limits the peak drain current output capability of the MOSFET and affects the full load performance of the whole machine. Summary of the Invention

[0005] This application provides a MOS series flyback circuit and a method for boosting the gate level of a MOS transistor to solve the problem that a drop in the gate supply voltage of an existing MOS transistor would limit the peak drain current output capability and affect the full-load performance of the entire device.

[0006] This application provides a MOS series flyback circuit, including a first capacitor, a first Zener diode, a first MOS transistor, a second MOS transistor, and a control chip; The first capacitor is connected to the positive terminal of the busbar, and the busbar charges the first capacitor. The first terminal of the first capacitor is connected to the input terminal of the control chip through the first Zener diode, and the second terminal is connected to the first MOSFET, thereby supplying power to the control chip and the first MOSFET respectively. The output terminal of the control chip is connected to the second MOS transistor; The first MOSFET and the second MOSFET are connected in series, and power is supplied to the load by changing the on or off state; During the power-on startup process, the first Zener diode compensates for the voltage drop of the first capacitor by adaptively adjusting the reverse current, so as to maintain the voltage of the gate of the first MOS transistor.

[0007] In one example, the circuit also includes a third resistor and a fourth resistor; The third and fourth resistors are connected in series, with one end connected to the positive terminal of the bus and the other end connected to the first capacitor, to limit the current value passing through the first Zener diode.

[0008] In one example, the circuit further includes a first resistor and a second resistor; The first resistor and the second resistor are connected in series, with one end connected to the positive terminal of the bus and the other end connected to the first MOSFET, to assist in supplying power to the first MOSFET.

[0009] In one example, the circuit also includes a first diode and a fifth resistor; The first capacitor is connected to the gate of the first MOS transistor through the first diode and the fifth resistor.

[0010] In one example, the output of the control chip is connected to the gate of the second MOSFET via a sixth resistor to control the conduction or disconnection of the second MOSFET, so as to further control the power supply to the load by controlling the conduction or disconnection of the first MOSFET connected to the second MOSFET.

[0011] In one example, the source of the first MOS transistor is connected to the drain of the second MOS transistor, and the source of the second MOS transistor is grounded through a current sensing resistor; When the drain and source of the second MOS transistor are turned on, the first MOS transistor is grounded, and the gate and source of the first MOS transistor are turned on to store electrical energy for the load.

[0012] In one example, the circuit further includes a transformer, which includes a primary winding and a secondary winding; The opposite-named end of the primary winding is connected to the positive terminal of the bus, and the same-named end is connected to the source of the first MOS transistor. The secondary winding is connected to the load. When the first MOS transistor is turned on, it charges the primary winding. When the first MOSFET is turned off, the primary winding supplies power to the load through the secondary winding.

[0013] In one example, the corresponding terminal of the secondary winding is connected to a second diode, and the secondary winding is connected in parallel with a second capacitor and a load.

[0014] In one example, the circuit also includes a second Zener diode; One end of the second Zener diode is connected to the gate of the first MOSFET, and the other end is connected to the source of the first MOSFET.

[0015] This application provides a method for boosting the gate level of a MOS transistor in a MOS series flyback circuit, applicable to any of the aforementioned MOS series flyback circuits. The method includes: The specifications of the first Zener diode are determined based on the startup voltage of the control chip, the maximum discharge voltage drop of the first capacitor, and the required voltage of the first MOSFET. The first Zener diode is used to compensate for the voltage drop of the first capacitor through reverse current adaptive adjustment during the power-on startup process, so as to maintain the voltage of the gate of the first MOSFET. The control chip outputs a control signal to control the second MOSFET to turn on, so that the first MOSFET connected to the second MOSFET turns on to supply power to the transformer and enable the transformer to store energy. The control chip outputs a control signal to disconnect the second MOSFET, thereby disconnecting the first MOSFET and allowing the transformer to supply power to the load.

[0016] This application provides a MOS series flyback circuit and a method for boosting the gate level of a MOS transistor, which can achieve the following beneficial effects: By raising the initial voltage of the first capacitor through the first voltage regulator, and reserving a voltage margin to offset the capacitor's discharge drop, the gate voltage of the first MOSFET can be continuously and stably maintained within the optimal range. This ensures full conduction of the MOSFET, reduces conduction losses, optimizes startup energy, and makes the overall power output of the device more stable. Furthermore, this method allows the use of smaller capacitance values ​​of capacitors under the same full-load conditions, reducing material costs and shortening the power-on charging setup time. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. The accompanying drawings described herein are used to provide a further understanding of this application and constitute a part of this application. The illustrative embodiments of this application and their descriptions are used to explain this application and do not constitute an improper limitation of this application. In the accompanying drawings: Figure 1 This is a schematic diagram of the MOS series flyback circuit provided in the embodiments of this application; Figure 2 This is a schematic flowchart of the MOS transistor gate level boosting method for a MOS series flyback circuit provided in an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] Figure 1 This is a schematic diagram of the MOS series flyback circuit provided in the embodiments of this application.

[0020] like Figure 1 As shown, the MOS series flyback circuit can be divided into several parts: the first stage, the second stage, the third stage, and the fourth stage, which will be explained in detail below.

[0021] The first-stage circuit is a power-on startup circuit, including a first capacitor C1, a first Zener diode Z1, a third resistor R3, and a fourth resistor R4. One end of the first capacitor C1 is connected to the positive terminal of the bus through the third resistor R3 and the fourth resistor R4, and the other end is grounded. At the same time, the first capacitor C1 is also connected to the first Zener diode Z1.

[0022] Specifically, the DC+ positive DC bus serves as the high-voltage input DC bus for the entire power supply, providing the original input power and acting as the energy source for the power-on startup circuit and the main circuit.

[0023] The first capacitor C1 draws power from the bus and is then powered through two power supply branches. The first power supply branch connects to the control chip of the second-stage circuit via the first Zener diode Z1, supplying power to the control chip; the second power supply branch connects to the first MOSFET Q1 of the fourth-stage circuit, supplying power to the first MOSFET Q1.

[0024] The third resistor R3 and the fourth resistor R4 are series-connected starting current-limiting resistors, used to limit the inrush current of the bus charging the first capacitor C1, protect the capacitor and Zener diode from surge damage, and perform voltage division and current limiting to stabilize the charging rate of the first capacitor C1 in conjunction with the bus voltage.

[0025] The first Zener diode Z1 is used to raise the charging voltage of the first capacitor. It compensates for the voltage drop of the first capacitor C1 during the power-on process by regulating its own voltage value, so as to maintain the driving amplitude of the first capacitor C1 to the gate of the first MOSFET and ensure the full current output of the first MOSFET.

[0026] The second-stage circuit is the control circuit, which includes a control chip. The VCC pin of the control chip is connected to the first capacitor C2 through the first voltage regulator Z1, and the Vout pin is connected to the second MOSFET Q2 of the fourth-stage circuit.

[0027] Specifically, the control chip is powered by the first capacitor C1, starts up after reaching the start-up voltage, and outputs a high-frequency PWM switching drive signal through the Vout output pin to control the conduction or disconnection of the second MOSFET, so as to further control the power supply to the load.

[0028] The third-stage circuit is the gate drive circuit for the first MOSFET, including a first diode D1, a fifth resistor R5, and a second Zener diode Z2. The first diode D1 and the fifth resistor R5 are connected in series, with one end connected to the first capacitor C1 and the other end connected to the gate of the first MOSFET Q1. One end of the second Zener diode Z2 is connected to the gate of the first MOSFET Q1, and the other end is connected to the source of the first MOSFET Q1.

[0029] Specifically, the first capacitor C1 supplies power to the first MOSFET Q1 through the first diode D1 and the fifth resistor R5.

[0030] The first diode D1 conducts in one direction, allowing only the first capacitor C1 to charge the gate of the first MOSFET Q1, establishing the gate-source conduction voltage, and performing reverse isolation to prevent the gate charge from flowing back into the first capacitor C1 when the first MOSFET Q1 is turned off, thus avoiding a rapid drop in the voltage of the first capacitor C1 and maintaining a stable drive level.

[0031] The fifth resistor R5 is a buffer resistor, which can control the charging and discharging speed of the gate of the first MOSFET Q1, suppress gate voltage oscillation, match the gate capacitance, optimize the turn-on or turn-off loss, and reduce peak noise.

[0032] The second Zener diode Z2 reverse-biased breakdown occurs when the second MOSFET Q2 is turned off, forcibly clamping the gate-source voltage VGS of the first MOSFET Q1; it exits the regulation region when the second MOSFET Q2 is turned on, without affecting the normal turn-on of the first MOSFET Q1. This is used to limit the maximum VGS of the first MOSFET Q1, prevent excessive gate voltage, protect against breakdown, suppress gate oscillation, and reduce switching EMI.

[0033] The fourth-stage circuit is the main circuit, including the first MOSFET Q1, the second MOSFET Q2, the first resistor R1, the second resistor R2, the sixth resistor R6, the current sensing resistor Rs, the transformer TR1, the second diode D2, the second capacitor C2, and the load R. L In this configuration, the first MOSFET Q1 and the second MOSFET Q2 are connected in series. The source of the first MOSFET Q1 is connected to the drain of the second MOSFET Q2. The source of the second MOSFET Q2 is grounded through a current-sensing resistor Rs. The gate of the second MOSFET Q2 is connected to the output terminal of the control chip through a sixth resistor R6. The drain of the first MOSFET Q1 is connected to the primary winding of the transformer TR1. The secondary winding of the transformer TR1 is connected to the second diode D2, and is also connected to the second capacitor C2 and the load R. LParallel connection. The first resistor R1 and the second resistor R2 are connected in series, one end is connected to the positive terminal of the bus, and the other end is connected to the first MOSFET Q1 through the fifth resistor R5.

[0034] Specifically, the second MOSFET Q2 is directly driven by the PWM signal of the control chip. When the second MOSFET Q2 is turned on under the control of the control signal, it is grounded, which lowers the source potential of the first MOSFET Q1 and creates the conditions for the first MOSFET Q1 to turn on. When the second MOSFET Q2 is turned off, it cuts off the primary current loop. Thus, the first MOSFET Q1 and the second MOSFET Q2 are turned on or off synchronously.

[0035] When the first MOSFET Q1 is turned on, it connects the primary winding of transformer TR1, allowing the primary winding to store inductor energy. The opposite-named terminal of the primary winding is connected to the positive DC+ of the bus, and the same-named terminal is connected to the drain of the first MOSFET Q1, satisfying the flyback volt-second balance. When the first MOSFET Q1 is turned off, the magnetic field energy stored in the primary winding is coupled to the secondary winding to supply power to the load, achieving strong and weak current isolation.

[0036] The first resistor R1 and the second resistor R2 are used to replenish the DC+ voltage from the positive terminal of the bus when the first capacitor C1 is not fully charged and its voltage is low during the initial power-on phase, and when the first capacitor C1 is continuously discharging to the gate of the first MOSFET. This reduces the output current of the first capacitor C1, lowers its voltage drop, and also reduces the compensation requirement for the voltage regulation value of the first voltage regulator Z1, thus enhancing the compensation effect of the first voltage regulator Z1. Simultaneously, they can also act as current-limiting resistors to limit the maximum current flowing into the bus.

[0037] The sixth resistor R6 is connected in series between the output terminal of the control chip and the second MOSFET Q2. It is used to limit the gate charging and discharging current, suppress gate oscillation and spikes, adjust the switching speed, reduce EMI electromagnetic interference, and protect the output pins of the control chip to prevent the MOSFET gate capacitive current from damaging the chip.

[0038] The current sensing resistor Rs is connected in series between the source of the second MOSFET Q2 and DC-ground to achieve peak current limiting protection, prevent the transformer and the two MOSFETs from burning out due to overcurrent, and form a current closed loop to stabilize the power supply output power.

[0039] The second diode D2 is used to unidirectionally rectify the induced voltage in the winding during the transformer's magnetic reset phase, converting the AC pulse voltage into DC.

[0040] The second capacitor C2 is used to smooth the pulsating DC after rectification, reduce output ripple, and store energy to provide instantaneous energy replenishment during load transient changes and stabilize the output voltage.

[0041] Load R L Used to simulate actual electrical equipment such as control systems and contactors in the backend.

[0042] In addition, the MOS series flyback circuit also includes a third diode D3 TVS. One end of the third diode is connected to the midpoint between the first diode D1 and the fifth resistor R5, and the other end is grounded. It is used to discharge excess charge to ground in abnormal situations such as bus surges and overvoltage charging of the first capacitor C1, so as to prevent excessive voltage from damaging the first MOS transistor Q1.

[0043] In this circuit, upon power-on, power is drawn from the bus and charged to the first capacitor via an RC circuit. By adding a first voltage regulator, the initial voltage of C1 is raised, and the additional voltage margin is the compensation margin. In other words, the charging voltage of the first capacitor is equal to the sum of the control chip's startup voltage and the first voltage regulator's regulated voltage. Therefore, the voltage supplied by the first capacitor to the gate of the first MOSFET can also be equivalent to the sum of the control chip's startup voltage and the first voltage regulator's regulated voltage. When the first capacitor supplies power to the first MOSFET, its voltage drops. At this time, the first voltage regulator's regulated voltage can offset the voltage drop, keeping the gate voltage of the first MOSFET within its normal operating range, thus ensuring that the drain current of the first MOSFET has optimal output capability.

[0044] In one embodiment, the voltage regulation value of the first voltage regulator needs to be set reasonably according to the actual situation. If the voltage regulation value is too small, it will lead to insufficient compensation, causing the gate voltage of the first MOSFET to drop below the normal operating range, which will affect the drain current output capability; if the voltage regulation value is too large, the initial voltage of the first capacitor will be too high, which may cause the gate voltage of the first MOSFET to exceed the tolerance range, resulting in gate breakdown and damage. Therefore, the specifications of the first voltage regulator need to be determined based on the startup voltage of the control chip, the maximum discharge voltage drop of the first capacitor, and the required voltage of the first MOSFET.

[0045] In addition, during the power-on startup phase, the current flowing through the first voltage regulator must be greater than or equal to the minimum regulated current of the first voltage regulator; otherwise, the first voltage regulator will exit the breakdown regulation region and will not be able to compensate for the voltage drop of the first capacitor.

[0046] Therefore, based on the above requirements for the normal operation of the first voltage regulator, it is also necessary to configure other related components in the circuit.

[0047] In one embodiment, for the third and fourth resistors positioned between the bus and the first capacitor, to ensure that the current flowing through the first voltage regulator is greater than or equal to the minimum regulated current of the first voltage regulator, the maximum value of the sum of the third and fourth resistors needs to be limited based on the minimum regulated current of the first voltage regulator and the minimum input bus voltage. This prevents the resistance value from being too large, resulting in insufficient current in the circuit. Simultaneously, the minimum value of the sum of the third and fourth resistors can also be limited based on factors such as the bus voltage and the rated power of the first voltage regulator, preventing excessive current in the circuit due to insufficient resistance value.

[0048] In one embodiment, the specifications of the first capacitor also need to be set appropriately. If the capacitor is too small, the discharge speed will be faster and the voltage drop will be greater, which will place higher demands on the voltage regulation of the first regulator and may result in the gate voltage being lower than the normal operating range. However, if the capacitor is too large, it will also lead to increased volume and cost, and longer charging time. Therefore, the capacitance value of the first capacitor can be determined based on factors such as the full-load operating time and the voltage regulation value of the first regulator.

[0049] In one embodiment, the control chip may be a UC2844B, with a normal startup voltage of 16V.

[0050] In this embodiment, by raising the initial voltage of the first capacitor through a first voltage regulator and reserving a voltage margin to offset the discharge drop of the capacitor, the gate voltage of the first MOSFET can be continuously and stably maintained in the optimal range, ensuring full conduction of the MOSFET, reducing conduction losses, optimizing startup energy, and making the overall power output more stable. Furthermore, this method allows for the use of smaller capacitance values ​​under the same full-load conditions, reducing material costs and shortening the power-on charging setup time.

[0051] The above describes the MOS series flyback circuit provided in the embodiments of this application. Based on this circuit, the embodiments of this application also provide a corresponding MOS transistor gate level boosting method based on the operation of this circuit, such as... Figure 2 As shown.

[0052] Figure 2 The flowchart of the MOS gate level boosting method for the MOS series flyback circuit provided in this application embodiment specifically includes the following steps: S201: Determine the specifications of the first Zener diode based on the startup voltage of the control chip, the maximum discharge voltage drop of the first capacitor, and the required voltage of the first MOSFET; the first Zener diode is used to compensate for the voltage drop of the first capacitor through reverse current adaptive adjustment during the power-on startup process, so as to maintain the voltage of the gate of the first MOSFET. S202: The control chip outputs a control signal to control the second MOSFET to turn on, so that the first MOSFET connected to the second MOSFET turns on to supply power to the transformer and enable the transformer to store energy; S203: The control chip outputs a control signal to control the second MOSFET to turn off, thereby turning off the first MOSFET and allowing the transformer to supply power to the load.

[0053] It should be understood that the various parts disclosed in this application can be implemented using hardware, software, firmware, or a combination thereof. In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more embodiments or examples.

[0054] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the method embodiments are described simply because they are implemented based on the circuit embodiments; relevant parts can be referred to the descriptions of the circuit embodiments.

[0055] The circuits and methods provided in the embodiments of this application are corresponding. Therefore, the method also has similar beneficial technical effects as its corresponding method. Since the beneficial technical effects of the method have been described in detail above, the beneficial technical effects of the method will not be repeated here.

[0056] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using dedicated hardware combined with computer instructions. The modules described in the embodiments of this application can be implemented in software or hardware. The names of the modules do not necessarily limit the functionality of the unit itself.

[0057] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0058] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A MOS series flyback circuit, characterized in that, It includes a first capacitor, a first Zener diode, a first MOSFET, a second MOSFET, and a control chip; The first capacitor is connected to the positive terminal of the busbar, and the busbar charges the first capacitor. The first terminal of the first capacitor is connected to the input terminal of the control chip through the first Zener diode, and the second terminal is connected to the first MOSFET, thereby supplying power to the control chip and the first MOSFET respectively. The output terminal of the control chip is connected to the second MOS transistor; The first MOSFET and the second MOSFET are connected in series, and power is supplied to the load by changing the on or off state; During the power-on startup process, the first Zener diode compensates for the voltage drop of the first capacitor by adaptively adjusting the reverse current, so as to maintain the voltage of the gate of the first MOS transistor.

2. The MOS series flyback circuit according to claim 1, characterized in that, The circuit also includes a third resistor and a fourth resistor; The third and fourth resistors are connected in series, with one end connected to the positive terminal of the bus and the other end connected to the first capacitor, to limit the current value passing through the first Zener diode.

3. The MOS series flyback circuit according to claim 1, characterized in that, The circuit also includes a first resistor and a second resistor; The first resistor and the second resistor are connected in series, with one end connected to the positive terminal of the bus and the other end connected to the first MOSFET, to assist in supplying power to the first MOSFET.

4. The MOS series flyback circuit according to claim 1, characterized in that, The circuit also includes a first diode and a fifth resistor; The first capacitor is connected to the gate of the first MOS transistor through the first diode and the fifth resistor.

5. The MOS series flyback circuit according to claim 1, characterized in that, The output terminal of the control chip is connected to the gate of the second MOS transistor via a sixth resistor, which is used to control the conduction or disconnection of the second MOS transistor, so as to further control the power supply to the load by controlling the conduction or disconnection of the first MOS transistor connected to the second MOS transistor.

6. The MOS series flyback circuit according to claim 5, characterized in that, The source of the first MOS transistor is connected to the drain of the second MOS transistor, and the source of the second MOS transistor is grounded through a current sensing resistor; When the drain and source of the second MOS transistor are turned on, the first MOS transistor is grounded, and the gate and source of the first MOS transistor are turned on to store electrical energy for the load.

7. The MOS series flyback circuit according to claim 1, characterized in that, The circuit also includes a transformer, which includes a primary winding and a secondary winding; The opposite-named end of the primary winding is connected to the positive terminal of the bus, and the same-named end is connected to the source of the first MOS transistor. The secondary winding is connected to the load. When the first MOS transistor is turned on, it charges the primary winding. When the first MOSFET is turned off, the primary winding supplies power to the load through the secondary winding.

8. The MOS series flyback circuit according to claim 7, characterized in that, The secondary winding is connected to the second diode at the same terminal, and the secondary winding is connected in parallel with the second capacitor and the load.

9. The MOS series flyback circuit according to claim 1, characterized in that, The circuit also includes a second Zener diode; One end of the second Zener diode is connected to the gate of the first MOSFET, and the other end is connected to the source of the first MOSFET.

10. A method for boosting the gate level of a MOS transistor in a MOS series flyback circuit, applied to the MOS series flyback circuit according to any one of claims 1-9, the method comprising: The specifications of the first Zener diode are determined based on the startup voltage of the control chip, the maximum discharge voltage drop of the first capacitor, and the required voltage of the first MOSFET. The first Zener diode is used to compensate for the voltage drop of the first capacitor by adaptively adjusting the reverse current during the power-on startup process, so as to maintain the voltage of the gate of the first MOS transistor. The control chip outputs a control signal to control the second MOSFET to turn on, so that the first MOSFET connected to the second MOSFET turns on to supply power to the transformer and enable the transformer to store energy. The control chip outputs a control signal to disconnect the second MOSFET, thereby disconnecting the first MOSFET and allowing the transformer to supply power to the load.

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