An f a class low input bias current low noise operational amplifier

Abstract

The application discloses a kind of fA level low input bias current low noise operational amplifier, by input stage ESD protection circuit and operational amplifier main circuit composition, ESD protection circuit has the feedback clamping amplifier of rail-to-rail input output capability, make input stage ESD protection device both ends voltage approach zero, from root inhibit normal temperature reverse bias leakage, high temperature parasitic leakage and tunneling leakage, realize fA level ultra-low input bias current in rail-to-rail input voltage range.The operational amplifier main circuit adopts enhanced PMOS and depletion mode PMOS combined input fold common-source common-gate architecture, realize low noise voltage in full common mode input interval;RC frequency compensation network is also used simultaneously, to ensure that the circuit is not self-excited, stable work.Simulation shows that the application normal temperature input bias current is less than 1fA, 120 DEG C high temperature limit working condition maximum bias current is only 2.2pA;1KHz low frequency noise voltage is stably maintained at 9.7~10.3nV / √Hz, excellent performance in all conditions.

Description

Technical Field

[0001] This invention belongs to the field of analog integrated circuit operational amplifier technology, specifically relating to an fA-level low-input bias current low-noise operational amplifier suitable for low-frequency high-precision capacitance detection, weak biological signal acquisition, and high-precision sensor signal conditioning scenarios. Background Technology

[0002] Operational amplifiers are core components in the field of analog integrated circuits, widely used in various analog circuit systems such as precision detection, weak signal amplification, and sensor signal conditioning. In high-end applications such as low-frequency high-precision capacitance detection and weak bioelectrical signal acquisition, the input bias current and low-frequency noise performance of operational amplifiers directly determine the detection resolution and signal acquisition accuracy of the entire system.

[0003] Existing commercially available high-input-impedance CMOS operational amplifiers and JFET operational amplifiers typically have input bias currents in the pA range at room temperature. However, under high-temperature operating conditions, the input bias current can climb to hundreds of pA or even nA, failing to meet the stringent requirements of ultra-low input bias currents in high-precision applications, which typically operate at the fA level. This large input bias current introduces significant charge injection errors into the sensing capacitor, substantially reducing capacitance detection resolution and the accuracy of detecting weak signals, thus hindering performance improvements in precision testing equipment.

[0004] Currently, the standardized ESD protection system for 5V IO on mainstream CMOS and BCD commercial process platforms in China mainly includes three types of standardized protection devices: GGNMOS, GDPMOS, and ESD diodes. These devices can directly call standard process library cells without custom development, and have the advantages of high tape-out yield, good batch consistency, and controllable mass production costs. They are a mature and universal solution for the mass production of 5V IO in domestic integrated circuits. However, these devices generally have inherent leakage defects, which has become a core technical bottleneck restricting the development of ultra-low bias current operational amplifiers.

[0005] Specifically, GGNMOS devices rely on the avalanche breakdown mechanism of an internal parasitic lateral NPN transistor to discharge ESD current. Under high-temperature conditions, the reverse-biased PN junction at the drain of the GGNMOS generates substrate leakage current, which can form a forward bias voltage at the base of the parasitic NPN transistor. At the same time, the high-temperature environment reduces the turn-on voltage of the parasitic NPN, causing the parasitic NPN to conduct weakly, resulting in a large leakage current in the nA range after current multiplication. In addition, to ensure ESD protection capability, GGNMOS devices generally adopt a large-size design. Their Si-SiO2 interface has a large number of interface state traps and oxide layer fixed charges. Under the coupling effect of high temperature and electric field stress, the trap-assisted tunneling effect is exponentially enhanced, further aggravating the device leakage current, ultimately leading to the problem of severe excessive bias current at high temperatures in traditional operational amplifiers.

[0006] In addition, traditional rail-to-rail input operational amplifiers generally adopt a hybrid NMOS and PMOS folded input architecture. In the low common-mode input voltage range, PMOS differential pairs operate, providing good low-frequency noise performance. In the high common-mode input voltage range, they switch to NMOS differential pairs. However, because the inherent 1 / f low-frequency noise of NMOS devices is much higher than that of PMOS devices, this directly leads to a significant degradation of low-frequency noise in the high common-mode range, resulting in unbalanced noise performance across the entire common-mode voltage range, making it difficult to meet the high-precision amplification requirements of weak low-frequency signals.

[0007] In summary, existing commercial operational amplifiers generally suffer from technical defects such as high input bias current at constant and high temperatures and severe low-frequency noise degradation, making them unsuitable for high-precision applications such as high-precision low-frequency capacitor detection and weak biological signal acquisition. The industry urgently needs an operational amplifier that is compatible with standard mass production processes, has fA-level ultra-low bias current, low noise voltage, and high operating stability. Summary of the Invention

[0008] The purpose of this invention is to overcome the shortcomings of the existing technology and provide an fA-level low input bias current and low noise operational amplifier. This invention solves the technical problems of traditional operational amplifiers, such as inherent leakage current of ESD devices, high-temperature bias current surge, and low-frequency noise degradation in the high common-mode range. It achieves fA-level ultra-low input bias current and low noise voltage characteristics in the entire common-mode range, while taking into account complete ESD protection capabilities and long-term circuit stability.

[0009] The technical solution adopted in this invention is as follows: A low-input bias-current, low-noise operational amplifier of class fA, comprising an input stage ESD protection circuit and the main operational amplifier circuit, characterized in that: The input stage ESD protection circuit consists of a first ESD diode D1, a second ESD diode D2, a first GGNMOS transistor G1, a second GGNMOS transistor G2, a fourth GGNMOS transistor G4, a third GDPMOS transistor G3, a first current-limiting resistor R1, a second current-limiting resistor R2, a third current-limiting resistor R0, and a feedback clamping amplifier OP1. The positive terminal of the first ESD diode D1 and the negative terminal of the second ESD diode D2 are connected to the positive input terminal INP of the circuit. The negative terminal of the first ESD diode D1 and the positive terminal of the second ESD diode D2 are connected to the negative input terminal INN of the circuit. The negative terminals of the first ESD diode D1 and the second ESD diode D2 are connected to form a common point A. The gate and source terminals of the first GGNMOS transistor G1 and the second GGNMOS transistor G2 are connected to the substrate in parallel to the common point A. One end of the third current-limiting resistor R0 is connected to the common point A, and the other end is connected to the output terminal B of amplifier OP1; The drains of the third GDPMOS transistor G3 and the fourth GGNMOS transistor G4 are also connected at the common point A. The gate and source of the third GDPMOS transistor G3 are connected to VDD after being connected in parallel with the substrate, and the gate and source of the fourth GGNMOS transistor G4 are connected to ground after being connected in parallel with the substrate. One end of the first current-limiting resistor R1 is connected to the positive input terminal INP of the circuit, and the other end is connected to the positive input terminal OP1 of the amplifier. This end serves as an output terminal P1 of the ESD protection circuit. One end of the second current-limiting resistor R2 is connected to the negative input terminal INN of the circuit, and the other end serves as the other output terminal N1 of the ESD protection circuit.

[0010] Based on the above technical solutions, the following further technical solutions are proposed: The operational amplifier main circuit includes: (1) Rail-to-rail voltage input amplifier stage A constant current source with a common-source, common-gate structure is formed by a pair of enhancement-mode MOSFETs M1 and M2 and a current source I0. The gate of MOSFET M1 is connected to P1, and its voltage is the same as the input voltage INP of the operational amplifier. The gate of MOSFET M2 is connected to vb1, which is the reference voltage generated inside the operational amplifier. The PMOS type input differential pair transistors M3 and M4 are connected in parallel to the drain of MOS transistor M1. The PMOS type input differential pair transistors M5 and M6 are connected in parallel to the drain of MOS transistor M2. The drains of PMOS transistors M3 and M5 are connected in parallel as output point O1, and the drains of PMOS transistors M4 and M6 are connected in parallel as output point O2. (2) Low input noise voltage amplification stage The common source transistor of the operational amplifier is composed of PMOS type input differential pair transistors M13 and M14. Their gates are shorted and connected to the reference voltage vb4 generated inside the operational amplifier. The sources of transistors M13 and M14 are connected to VDD. The PMOS type input differential pair transistors M11 and M12 form the common gate transistor of the operational amplifier. Their gates are shorted and connected to the reference voltage vb3 generated inside the operational amplifier. The sources of transistors M11 and M12 are connected to the drains of the upper-stage transistors M13 and M14, respectively. The NMOS type input differential pair transistors M9 and M10 form the common gate transistor of the op-amp. Their gates are shorted and connected to the reference voltage vb2 generated inside the op-amp. The sources of transistors M9 and M10 are connected to the drains of the next-stage NMOS type input differential pair transistors M7 and M8, respectively. The gates of NMOS type input differential pair transistors M7 and M8 are shorted, their drains are connected to the output terminals O1 and O2 of the rail-to-rail voltage input amplifier stage, and their sources are connected to one end of resistors R3 and R4, respectively. The other end of resistors R3 and R4 is grounded. The differential pair transistors M7 and M8, along with resistors R3 and R4, form the common source transistor of the operational amplifier. Its gate voltage is self-biased and is given by the drain voltage of M9. (3) Rail-to-rail output amplification unit A common-source amplifier structure is formed by PMOS transistors M22 and M23. The sources of PMOS transistors M22 and M23 are connected to VDD and power ground, respectively. The drains of PMOS transistors M22 and M23 are shorted to serve as the output OUT of the entire circuit. The gates of PMOS transistors M22 and M23 are connected to the drains of PMOS transistor M12 and NMOS transistor M10, respectively. RC frequency compensation networks composed of capacitor C1 and resistor R5 and capacitor C2 and resistor R6 are connected between the gates and drains of PMOS transistors M22 and M23, respectively. (4) Static voltage bias circuit, connected between the gates of PMOS transistors M22 and M23, including PMOS pair transistors M18 and MM19. The source and drain of the pair transistors M18 and MM19 are connected to the gate of PMOS transistor M22. The drain and source of the pair transistors M18 and MM19 are connected to the gate of PMOS transistor M23. Current source I2 is connected to the drain and gate of NMOS transistor M20. The gate of NMOS transistor M20 is shorted to the gate of PMOS transistor M19. The source of NMOS transistor M20 is shorted to the gate and drain of NMOS transistor M21. The source of NMOS transistor M21 is grounded. Current source I1 is connected to the drain and gate of PMOS transistor M17. The gate of PMOS transistor M17 is shorted to the gate of PMOS transistor M18, and the source is shorted to the gate and drain of PMOS transistor M16. The source of PMOS transistor M16 is connected to VDD. (5) The drains of PMOS transistor M11 and NMOS transistor M9 are connected to the source and drain of PMOS transistor M15, respectively, and the gate of PMOS transistor M15 is connected to the drain of PMOS transistor M17. Beneficial effects

[0011] Compared with the prior art, the present invention has the following outstanding advantages: 1. Ultra-low input bias current at the fA level, significantly improving detection accuracy: This invention completely eliminates room-temperature PN junction reverse bias leakage, high-temperature parasitic NPN amplification leakage, and trap-assisted tunneling leakage in standard ESD devices through the OP1 negative feedback equipotential clamping mechanism. The room-temperature input bias current is less than 1fA, the maximum bias current is only 120fA under 85℃ medium-temperature conditions, and the maximum bias current is only 2.2pA under 120℃ high-temperature conditions. It stably achieves ultra-low bias current across the entire temperature range and common-mode range, completely solving the technical problem of high-temperature bias current surge in traditional operational amplifiers, and significantly improving the resolution of low-frequency capacitor detection and weak signal acquisition.

[0012] 2. Low noise voltage across the entire common-mode range, resulting in excellent signal amplification quality: Utilizing an enhanced PMOS + depletion-mode PMOS composite input architecture instead of the traditional NMOS / PMOS hybrid input architecture, it completely avoids the inherent 1 / f low-frequency noise defect of NMOS devices. Combined with transconductance noise reduction, current source size optimization, and other noise reduction designs, noise performance remains stable across the entire common-mode input voltage range. Low-frequency noise at 1kHz is consistently maintained at approximately 10nV / √Hz, without noise degradation issues in the high common-mode range, making it perfectly suited for high-precision amplification scenarios involving weak low-frequency signals.

[0013] 3. Strong process compatibility and excellent mass production capability: All core protection devices and circuit devices of this invention adopt the standardized units of the domestic general standard 5V process library, which do not require customized development or special process modification. The yield rate of tape-out is high, the batch consistency is good, and the mass production cost is controllable. It can be directly adapted to the mainstream domestic CMOS and BCD commercial process platforms, and is suitable for large-scale industrial mass production applications.

[0014] 4. Complete functions, high stability, and wide range of applications: This invention has multiple advantages such as full-dimensional ESD electrostatic protection, 0~VDD rail-to-rail input and output, ultra-low bias current, low noise across the entire range, and no high-frequency self-excitation. It has high circuit matching accuracy and strong working stability, and can be widely used in high-precision capacitor detection, weak bioelectric signal acquisition, industrial sensor signal conditioning, precision instrument amplification and other high-end analog circuit fields. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the overall circuit structure of the fA-level low input bias current low noise CMOS operational amplifier of the present invention. Figure 2 This is a simulation curve of the full-temperature input bias current under low common-mode conditions for the circuit of this invention. Figure 3 This is a simulation curve of the full-temperature input bias current under high common-mode conditions in the circuit of this invention; Figure 4 This is a simulation comparison diagram of the input noise voltage under high and low common-mode conditions of the circuit of this invention. Detailed Implementation

[0016] This invention proposes an fA-level low input bias current low noise operational amplifier. By clamping the voltage across the ESD diode and the voltage across the GGNMOS at the input of the operational amplifier through voltage negative feedback, an fA-level input bias current is achieved within the rail-to-rail input voltage range, and ESD protection is achieved for the input port. A low noise voltage within the rail-to-rail input voltage range is achieved by using a hybrid input structure of enhancement-mode PMOS and depletion-mode PMOS.

[0017] The present invention provides an fA-level low input bias current low noise CMOS operational amplifier circuit, as follows: Figure 1As shown, the circuit mainly consists of two parts: the input stage ESD protection circuit and the operational amplifier main circuit.

[0018] I. ESD Protection Circuit for Op-Amplifier Input Stage The input stage ESD protection circuit consists of a first ESD diode D1, a second ESD diode D2, a first GGNMOS transistor G1, a second GGNMOS transistor G2, a fourth GGNMOS transistor G4, a third GDPMOS transistor G3, a first current-limiting resistor R1, a second current-limiting resistor R2, a third current-limiting resistor R0, and a feedback clamping amplifier OP1. The positive terminal of the first ESD diode D1 and the negative terminal of the second ESD diode D2 are connected to the positive input terminal INP of the circuit. The negative terminal of the first ESD diode D1 and the positive terminal of the second ESD diode D2 are connected to the negative input terminal INN of the circuit. The negative terminals of the first ESD diode D1 and the second ESD diode D2 are connected to form a common point A. The gate and source terminals of the first GGNMOS transistor G1 and the second GGNMOS transistor G2 are connected to the substrate in parallel to the common point A. One end of the third current-limiting resistor R0 is connected to the common point A, and the other end is connected to the output terminal B of amplifier OP1; The drains of the third GDPMOS transistor G3 and the fourth GGNMOS transistor G4 are also connected at the common point A. The gate and source of the third GDPMOS transistor G3 are connected to VDD after being connected in parallel with the substrate, and the gate and source of the fourth GGNMOS transistor G4 are connected to ground after being connected in parallel with the substrate. One end of the first current-limiting resistor R1 is connected to the positive input terminal INP of the circuit, and the other end is connected to the positive input terminal OP1 of the amplifier. This end serves as an output terminal P1 of the ESD protection circuit. One end of the second current-limiting resistor R2 is connected to the negative input terminal INN of the circuit, and the other end serves as the other output terminal N1 of the ESD protection circuit.

[0019] In the circuit structure described above, diodes (D1, D2) and MOSFETs (G1, G2, G3 and G4) provide electrostatic protection for the input terminals INP and INN, while resistors (R0, R1, R2) limit the transient ESD current.

[0020] When a positive ESD pulse occurs from INP to ground, the ESD energy is discharged through the forward conduction of D1 and the amplification of the parasitic NPN current after avalanche breakdown of G4. When a negative ESD pulse occurs from INP to ground, the ESD energy is discharged through the forward conduction of the parasitic PN junction of G2 and the parasitic PN junction of G4. Similarly, the energy is discharged by positive and negative ESD pulses from INP to the power supply and by positive and negative ESD pulses from INN to the power supply / ground.

[0021] When a positive ESD pulse occurs from INP to INN, the ESD energy is discharged through the forward conduction of D1 and the parasitic PN junction of G1. When a negative ESD pulse occurs from INP to INN, the ESD energy is discharged through the forward conduction of the parasitic PN junction of G2 and the forward conduction of D2. Similarly, the energy of both positive and negative ESD pulses from INN to INP is discharged. The current-limiting resistors R0, R1, and R2 are polycrystalline resistors, which, compared to the injection resistors, have no reverse-biased leakage current in the PN junction.

[0022] When the operational amplifier operates in closed-loop mode, its virtual short characteristic makes the voltages INP and INN equal. Since OP1 is in unity-gain negative feedback, the voltages INP, B, and A are approximately equal, and all equal to the op-amp input voltages INP and INN. This makes the voltage difference across the ESD protection devices D1, D2, G1, and G2 at the op-amp input approximately zero. Therefore, the leakage current caused by the reverse bias voltage of the PN junction in the ESD protection transistors D1, D2, G1, and G2 is almost zero. This invention achieves a room-temperature leakage current in the fA range.

[0023] Since the gate, source, and drain voltages of the ESD protection devices G1 and G2 at the input are all the same, meaning the emitter and collector voltages of the parasitic NPN are the same at high temperatures, the high-temperature leakage current of the parasitic NPN is negligible. Simultaneously, there is no potential difference between the oxide layers of G1 and G2, so the trap energy levels cannot assist electrons in tunneling, and the trap-assisted tunneling current at high temperatures is also negligible. Therefore, this invention achieves extremely low leakage current at high temperatures.

[0024] Furthermore, in order to achieve extremely low input bias current within the rail-to-rail input range, the feedback clamp amplifier OP1 is required to have rail-to-rail input and rail-to-rail output capabilities, and its circuit structure can be the same as the main circuit structure of the operational amplifier.

[0025] II. Operational Amplifier Main Circuit The operational amplifier input amplification stage employs a hybrid input folded cascode structure of enhancement-mode PMOS and depletion-mode PMOS to achieve rail-to-rail voltage input and low input noise voltage. Specifically, it includes the following components: 1. Rail-to-rail voltage input amplifier stage A constant current source consisting of a common-source, common-gate structure, comprising a pair of enhancement-mode PMOS transistors M1 and M2 and a current source I0. The gate of PMOS transistor M1 is connected to P1, and its voltage is the same as the input voltage INP of the operational amplifier. The gate of PMOS transistor M2 is connected to vb1, which is the reference voltage generated internally by the operational amplifier. The PMOS type input differential pair transistors M3 and M4 have their sources connected in parallel and then connected to the drain of PMOS transistor M1. The PMOS type input differential pair transistors M5 and M6 have their sources connected in parallel and then connected to the drain of PMOS transistor M2. The drains of transistors M3 and M5 are connected in parallel as output point O1, and the drains of transistors M4 and M6 are connected in parallel as output point O2.

[0026] When the input common-mode voltage of the op-amp is much less than vb1, M1, M3, and M4 are turned on, and all the current from the current source I0 flows into M1, M3, and M4, so M2, M5, and M6 are turned off. The input differential pair transistors M5 and M6 are depletion-type PMOS. When the input common-mode voltage of the op-amp is much greater than vb1, M2, M5, and M6 are turned on, and all the current from the current source I0 flows into M2, M5, and M6, so M1, M3, and M4 are turned off. When the input common-mode voltage of the op-amp is near vb1, M1, M3, M4 and M2, M5, and M6 are turned on simultaneously.

[0027] In summary, the amplifier can operate within the common-mode input range of 0 to VDD, thus achieving rail-to-rail voltage input.

[0028] 2. Low input noise voltage amplification stage The common source transistor of the operational amplifier is composed of PMOS type input differential pair transistors M13 and M14. Their gates are shorted and connected to the reference voltage vb4 generated inside the operational amplifier. The sources of transistors M13 and M14 are connected to VDD. The PMOS type input differential pair transistors M11 and M12 form the common gate transistor of the operational amplifier. Their gates are shorted and connected to the reference voltage vb3 generated inside the operational amplifier. The sources of transistors M11 and M12 are connected to the drains of the upper-stage transistors M13 and M14, respectively. The NMOS type input differential pair transistors M9 and M10 form the common gate transistor of the op-amp. Their gates are shorted and connected to the reference voltage vb2 generated inside the op-amp. The sources of transistors M9 and M10 are connected to the drains of the next-stage NMOS type input differential pair transistors M7 and M8, respectively. The gates of NMOS type input differential pair transistors M7 and M8 are shorted, their drains are connected to the output terminals O1 and O2 of the rail-to-rail voltage input amplifier stage, and their sources are connected to one end of resistors R3 and R4, respectively. The other end of resistors R3 and R4 is grounded. The differential pair transistors M7 and M8, along with resistors R3 and R4, form the common source transistor of the operational amplifier. Its gate voltage is self-biased and is given by the drain voltage of M9.

[0029] The amplifier's input noise voltage mainly originates from M3, M4, M5, M6, M7, M8, M13, M14 and resistors R3 and R4 in the input folded common source common gate circuit.

[0030] This invention uses a depletion-type PMOS instead of a traditional enhancement-type NMOS to achieve a lower low-frequency noise voltage.

[0031] The source stages of M7 and M8 are connected in series with resistors R3 and R4, respectively, to reduce the effective transconductance of M7 and M8, thereby reducing the equivalent input noise voltage. M13 and M14 are PMOS current sources. In terms of size design, a small width-to-length ratio and a large width-to-length product are used to reduce the equivalent input noise voltage.

[0032] 3. Rail-to-rail voltage output unit A common-source amplifier structure is formed by PMOS transistors M22 and M23. The sources of PMOS transistors M22 and M23 are connected to VDD and power ground, respectively. The drains of PMOS transistors M22 and M23 are shorted to serve as the output OUT of the entire circuit. The gates of PMOS transistors M22 and M23 are connected to the drains of PMOS transistor M12 and NMOS transistor M10, respectively. RC frequency compensation networks composed of capacitor C1 and resistor R5 and capacitor C2 and resistor R6 are connected between the gates and drains of PMOS transistors M22 and M23, respectively. The output stage of the circuit consists of M22, M23, C1, C2, R5, and R6. The gate voltage bias circuits of M22 and M23 in the output stage are set by M16~M21 and current sources I1 and I2 in the figure. PMOS transistor M15 isolates the drain voltage of M9 and M11 to reduce voltage mismatch caused by channel modulation effect.

[0033] The common-source amplifier structure composed of output stages M22 and M23 has a high voltage gain. This invention uses frequency compensation to ensure that the operational amplifier can work stably without self-oscillation.

[0034] 4. Static voltage bias circuit, connected between the gates of PMOS transistors M22 and M23. This includes PMOS transistors M18 and MM19. The source and drain of transistors M18 and MM19 are connected to the gate of PMOS transistor M22. The drain and source of transistors M18 and MM19 are connected to the gate of PMOS transistor M23. Current source I2 is connected to the drain and gate of NMOS transistor M20. The gate of NMOS transistor M20 is shorted to the gate of PMOS transistor M19. The source of NMOS transistor M20 is shorted to the gate and drain of NMOS transistor M21. The source of NMOS transistor M21 is grounded. Current source I1 is connected to the drain and gate of PMOS transistor M17. The gate of PMOS transistor M17 is shorted to the gate of PMOS transistor M18, and the source is shorted to the gate and drain of PMOS transistor M16. The source of PMOS transistor M16 is connected to VDD. The drains of PMOS transistor M11 and NMOS transistor M9 are connected to the source and drain of PMOS transistor M15, respectively, and the gate of PMOS transistor M15 is connected to the drain of PMOS transistor M17. PMOS transistor M15 isolates the drain voltages of M9 and M11 to reduce voltage mismatch caused by channel modulation effect.

[0035] III. Simulation Verification of the Content of this Invention 1. The simulation results of the circuit of this invention under low common-mode conditions at full temperature (-40℃~120℃) are as follows: Figure 2 As shown, the input bias current at room temperature is less than 1fA, the input bias current at 85℃ is 120fA, and the input bias current at a high temperature of 120℃ is 2.2pA. 2. The simulation results of the circuit of this invention under high common-mode conditions at full temperature (-40℃~120℃) are as follows: Figure 3 As shown, the input bias current is less than 1fA at room temperature, 28fA at 85℃, and 568fA at a high temperature of 120℃. The leakage current suppression effect is even better under high common-mode input conditions, with no leakage current surge phenomenon across the entire range. 3. The circuit of this invention has an input noise voltage of 9.7nV / √Hz@1KHz under low common-mode conditions and 10.3nV / √Hz@1KHz under high common-mode conditions. Figure 4 As shown, the noise performance across the entire common-mode range is highly balanced and without degradation, and the low-frequency amplification performance is excellent.

Claims

1. An fA-level low input bias current low noise operational amplifier, comprising an input stage ESD protection circuit and the main operational amplifier circuit, characterized in that: The input stage ESD protection circuit consists of a first ESD diode D1, a second ESD diode D2, a first GGNMOS transistor G1, a second GGNMOS transistor G2, a fourth GGNMOS transistor G4, a third GDPMOS transistor G3, a first current-limiting resistor R1, a second current-limiting resistor R2, a third current-limiting resistor R0, and a feedback clamping amplifier OP1. The positive terminal of the first ESD diode D1 and the negative terminal of the second ESD diode D2 are connected to the positive input terminal INP of the circuit. The negative terminal of the first ESD diode D1 and the positive terminal of the second ESD diode D2 are connected to the negative input terminal INN of the circuit. The negative terminals of the first ESD diode D1 and the second ESD diode D2 are connected to form a common point A. The gate and source terminals of the first GGNMOS transistor G1 and the second GGNMOS transistor G2 are connected to the substrate in parallel to the common point A. One end of the third current-limiting resistor R0 is connected to the common point A, and the other end is connected to the output terminal B of amplifier OP1; The drains of the third GDPMOS transistor G3 and the fourth GGNMOS transistor G4 are also connected at the common point A. The gate and source of the third GDPMOS transistor G3 are connected to VDD after being connected in parallel with the substrate, and the gate and source of the fourth GGNMOS transistor G4 are connected to ground after being connected in parallel with the substrate. One end of the first current-limiting resistor R1 is connected to the positive input terminal INP of the circuit, and the other end is connected to the positive input terminal OP1 of the amplifier. This end serves as an output terminal P1 of the ESD protection circuit. One end of the second current-limiting resistor R2 is connected to the negative input terminal INN of the circuit, and the other end serves as the other output terminal N1 of the ESD protection circuit.

2. The fA-level low input bias low noise operational amplifier according to claim 1, characterized in that... The operational amplifier main circuit includes: (1) Rail-to-rail voltage input amplifier stage A constant current source consisting of a common-source, common-gate structure, comprising a pair of enhancement-mode PMOS transistors M1 and M2 and a current source I0. The gate of PMOS transistor M1 is connected to P1, and its voltage is the same as the input voltage INP of the operational amplifier. The gate of PMOS transistor M2 is connected to vb1, which is the reference voltage generated internally by the operational amplifier. The PMOS type input differential pair transistors M3 and M4 are connected in parallel to the drain of PMOS transistor M1. The PMOS type input differential pair transistors M5 and M6 are connected in parallel to the drain of PMOS transistor M2. The drains of PMOS transistors M3 and M5 are connected in parallel as output point O1, and the drains of PMOS transistors M4 and M6 are connected in parallel as output point O2. (2) Low input noise voltage amplification stage The common source transistor of the operational amplifier is composed of PMOS type input differential pair transistors M13 and M14. Their gates are shorted and connected to the reference voltage vb4 generated inside the operational amplifier. The sources of transistors M13 and M14 are connected to VDD. PMOS type input differential pair transistors M11 and M12 form the common gate transistor of the operational amplifier. Their gates are shorted and connected to the reference voltage vb3 generated inside the operational amplifier. The sources of transistors M11 and M12 are connected to the drains of the upper stage transistors M13 and M14, respectively. The NMOS type input differential pair transistors M9 and M10 form the common gate transistor of the operational amplifier. Their gates are shorted and connected to the reference voltage vb2 generated inside the operational amplifier. The sources of transistors M9 and M10 are connected to the drains of the next-stage NMOS type input differential pair transistors M7 and M8, respectively. The gates of NMOS type input differential pair transistors M7 and M8 are shorted, their drains are connected to the output terminals O1 and O2 of the rail-to-rail voltage input amplifier stage, and their sources are connected to one end of resistors R3 and R4, respectively. The other end of resistors R3 and R4 is grounded. The differential pair transistors M7 and M8, along with resistors R3 and R4, form the common source transistor of the operational amplifier. Its gate voltage is self-biased and is given by the drain voltage of M9. (3) Rail-to-rail output amplification unit A common-source amplifier structure is formed by PMOS transistors M22 and M23. The sources of PMOS transistors M22 and M23 are connected to VDD and power ground, respectively. The drains of PMOS transistors M22 and M23 are shorted to serve as the output OUT of the entire circuit. The gates of PMOS transistors M22 and M23 are connected to the drains of PMOS transistor M12 and NMOS transistor M10, respectively. RC frequency compensation networks composed of capacitor C1 and resistor R5 and capacitor C2 and resistor R6 are connected between the gates and drains of PMOS transistors M22 and M23, respectively. (4) Static voltage bias circuit, connected between the gates of PMOS transistors M22 and M23, including PMOS pair transistors M18 and M19. The source and drain of pair transistors M18 and M19 are connected to the gate of PMOS transistor M22. The drain and source of pair transistors M18 and M19 are connected to the gate of PMOS transistor M23. Current source I2 is connected to the drain and gate of NMOS transistor M20. The gate of NMOS transistor M20 is shorted to the gate of PMOS transistor M19. The source of NMOS transistor M20 is shorted to the gate and drain of NMOS transistor M21. The source of NMOS transistor M21 is grounded. Current source I1 is connected to the drain and gate of PMOS transistor M17. The gate of PMOS transistor M17 is shorted to the gate of PMOS transistor M18, and the source is shorted to the gate and drain of PMOS transistor M16. The source of PMOS transistor M16 is connected to VDD. (5) The drains of PMOS transistor M11 and NMOS transistor M9 are connected to the source and drain of PMOS transistor M15, respectively, and the gate of PMOS transistor M15 is connected to the drain of PMOS transistor M17.

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