Common mode filter integrated with electrostatic surge protection and manufacturing method thereof

Abstract

The application provides a common mode filter integrated with electrostatic surge protection and a manufacturing method. The common mode filter comprises an electrostatic surge protection semiconductor chip, a first layer RDL, a second layer RDL and a third layer RDL. A first sub-inductor is arranged on the first layer RDL, a second sub-inductor is arranged on the second layer RDL, the third layer RDL is provided with a metal circuit, the upper surface of the electrostatic surge protection semiconductor chip is provided with a first conductive part for electrically connecting with the first layer RDL, the lower surface of the electrostatic surge protection semiconductor chip is provided with a second conductive part for electrically connecting with the third layer RDL, the first layer RDL and the second layer RDL are respectively electrically connected with the metal circuit of the third layer RDL through a third conductive part, an external pin is arranged on the lower surface of the third layer RDL, and a plastic package is used for packaging the common mode filter to expose only the external pin. The application can improve the performance of the common mode filter and reduce the manufacturing cost.

Description

Technical Field

[0001] This invention relates to the field of common-mode filter technology, and more specifically to a common-mode filter with integrated electrostatic surge protection. Background Technology

[0002] Next-generation high-speed communication interfaces such as USB 4.0 and HDMI 2.1 generally employ differential signal architecture to achieve high-speed digital signal transmission, thereby ensuring signal transmission integrity and bandwidth. Due to process factors such as PCB wiring length deviations, trace asymmetry, and uneven dielectric constants, differential links are highly susceptible to generating common-mode noise. This noise radiates outwards, creating electromagnetic interference that interferes with the device's built-in wireless RF module, causing antenna sensitivity attenuation, wireless communication disconnection, and transmission errors. Therefore, a common-mode RF filter is typically connected in series in the differential signal path, relying on a magnetically coupled inductor structure to suppress common-mode interference and ensure high-speed differential signal transmission performance. Simultaneously, high-speed communication interfaces are often exposed within the device housing, making them susceptible to electrostatic discharge shocks caused by human friction and metal plugging / unplugging, as well as surge pulses from cable plugging / unplugging and power grid fluctuations. Instantaneous high-voltage energy can easily damage the semiconductor chips at the interface's backend, causing permanent interface circuit failure. To address this issue, independent ESD / TVS protection chips are typically connected in parallel to ground at the differential port, utilizing their transient energy dissipation characteristics to protect the port circuitry.

[0003] For high-speed interfaces, in order to simultaneously solve the above-mentioned ESD / TVS protection and common-mode noise filtering problems, engineering usually adopts two approaches: "discrete device solution" and "integrated solution".

[0004] For a single differential transmission line, the discrete component solution requires at least one RF common-mode filter and two ESD / TVS chips. This discrete component solution has the following significant drawbacks: On the one hand, multiple independent devices require multiple PCB pads and wiring space, significantly increasing the PCB area occupied by the interface area and restricting the design of thinner and smaller terminal devices. On the other hand, the interconnection between devices relies on PCB traces, which introduce additional parasitic resistance, parasitic inductance and parasitic capacitance, disrupting the impedance continuity of high-speed differential links, degrading the filtering effect and RF bandwidth, while extending the electrostatic discharge path, reducing the transient response speed of TVS devices, and weakening the overall interface protection reliability.

[0005] The integrated solution integrates ESD / TVS protection devices and common-mode inductors into the same package, simultaneously achieving common-mode filtering and electrostatic / surge protection functions. Currently, several integrated solutions exist. For example, the patent with publication number CN105321876A, entitled "A Technical Solution for a High-Frequency Common-Mode LC Filter Design Method with Integrated ESD Protection Function," uses wire bonding to achieve integrated integration. However, the bonding wires themselves introduce additional parasitic parameters, deteriorating the performance consistency of the common-mode filter. The patent with publication number CN108039347A, entitled "A Technical Solution for a Common-Mode Filter Device with Integrated Ultra-Low Capacitance and Large Quick-Return TVS," proposes an integrated approach based on wafer-level packaging. However, the large size of the spiral inductor results in a significant waste of silicon die area, greatly increasing manufacturing costs. The patent with publication number CN119891990A, entitled "A Technical Solution for a Heterogeneous Integrated Filter Structure with Transient Voltage Protection and its Manufacturing Method," proposes a heterogeneous integrated approach. However, it requires steps such as slotting the glass substrate, resulting in complex manufacturing processes and low yield. Summary of the Invention

[0006] To address the problems of parasitic bonding wires and wasted silicon die area faced by existing integrated packaging technologies, this invention provides a common-mode filter with integrated electrostatic surge protection, and also provides a method for manufacturing the common-mode filter with integrated electrostatic surge protection. Through innovative double-sided RDL molding technology, the common-mode inductor and the longitudinal ESD / TVS protection device are integrated into one.

[0007] This invention relates to a common-mode filter integrating electrostatic surge protection. The common-mode filter includes a first sub-inductor and a second sub-inductor coupled by a magnetic field, respectively disposed between a differential input port and a differential output port. The common-mode filter also includes a stacked electrostatic surge protection semiconductor chip, a first RDL layer, a second RDL layer, and a third RDL layer, where the RDL is a redistribution layer. The common-mode filter further includes external pins and a plastic package. The first sub-inductor is disposed on the first RDL layer, the second sub-inductor is disposed on the second RDL layer, the third RDL layer has metal lines, the electrostatic surge protection semiconductor chip is disposed between the first RDL layer and the third RDL layer, the second RDL layer is disposed above the first RDL layer, the upper surface of the electrostatic surge protection semiconductor chip has a first conductive element for electrical connection with the first RDL layer, the lower surface of the electrostatic surge protection semiconductor chip has a second conductive element for electrical connection with the third RDL layer, the first RDL layer and the second RDL layer are respectively electrically connected to the metal lines of the third RDL layer through the third conductive element, the external pins are disposed on the lower surface of the third RDL layer, the molding compound is used to encapsulate the external area of ​​the common-mode filter and fill the interlayer area between the second RDL layer and the first RDL layer, and between the first RDL layer and the electrostatic surge protection semiconductor chip and the third RDL layer, only exposing the external pins.

[0008] Furthermore, the differential input port includes a first differential input terminal and a second differential input terminal, and the differential output port includes a first differential output terminal and a second differential output terminal. The first differential input terminal and the first differential output terminal are disposed on the first layer RDL, and the second differential input terminal and the second differential output terminal are disposed on the second layer RDL. The external pins include a first pin, a second pin, a third pin, a fourth pin, and a fifth pin. The first pin is electrically connected to the first differential input terminal, the second pin is electrically connected to the first differential output terminal, the third pin is electrically connected to the second differential input terminal, the fourth pin is electrically connected to the second differential output terminal, and the fifth pin is a common ground terminal. The vertically arranged electrostatic surge protection semiconductor chips are arranged in a group of one or more, respectively disposed between the differential input port and the common ground terminal, and / or between the differential output port and the common ground terminal.

[0009] Furthermore, the number of the electrostatic surge protection semiconductor chip is one, and the electrostatic surge protection semiconductor chip is provided with multiple sets of physically isolated electrostatic surge protection elements, which are used to connect between the differential input port and the common ground terminal, and between the differential output port and the common ground terminal, respectively. or, The number of electrostatic surge protection semiconductor chips is two, and each electrostatic surge protection semiconductor chip is provided with one or more electrostatic surge protection elements, which are used to connect between the differential input port and the common ground terminal and between the differential output port and the common ground terminal, respectively. The two electrostatic surge protection semiconductor chips are arranged side by side and isolated above the third layer RDL.

[0010] Furthermore, the second sub-inductor of the second layer RDL is electrically connected to the metal lines of the first layer RDL and the third layer RDL, or the second sub-inductor of the second layer RDL is directly electrically connected to the metal lines of the third layer RDL.

[0011] Furthermore, the external pins are solder ball structures, and a ball-under metal layer is provided on the surface of the third RDL layer, on which solder balls are soldered as external pins.

[0012] Furthermore, the external pins are electroplated copper pillar pins, which are formed on the surface of the third RDL layer. The outer surface of the copper pillar pins is tin-plated, and the copper pillar pins are partially exposed outside the molding compound for soldering and conduction with the PCB board.

[0013] This invention also provides a method for manufacturing a common-mode filter with integrated electrostatic surge protection, used to manufacture the aforementioned common-mode filter with integrated electrostatic surge protection, the method comprising the following steps: A1. Processing electrostatic surge protection semiconductor chips: Conductive bumps are prepared on the front side of the semiconductor wafer as the first conductive element, and the semiconductor wafer is diced to obtain independent electrostatic surge protection semiconductor chips. A2. First molding: The back side of the electrostatic surge protection semiconductor chip is attached to a temporary carrier board, and the front side of the electrostatic surge protection semiconductor chip is first molded to form the first molding layer. Then, the conductive bumps are ground to expose them. A3. Fabrication of the first RDL layer: The first RDL layer is fabricated on top of the first molding layer using a combination of chemical plating and electroplating processes. A4. Second molding: The first layer RDL is molded and ground to form a second molding layer. Holes are drilled in the second molding layer to align with the pads on the upper surface of the first layer RDL to form a first through hole between the first layer RDL and the second layer RDL. A5. Fabrication of the second RDL: Fill the first through-hole to form a third conductive element, and form the second RDL on the upper surface of the second encapsulation layer; A6. Third molding: Molding the second layer RDL to form a third molding layer that protects the second layer RDL; A7. Fabrication of the third RDL: Peel off the temporary carrier board on the back of the electrostatic surge protection semiconductor chip, drill holes in the first molding layer aligned with the pads on the lower surface of the first RDL to form a second through hole, fill the second through hole to form a third conductive element between the first RDL and the third RDL, and form the third RDL on the first molding layer and the lower surface of the electrostatic surge protection semiconductor chip. A8. Fabrication of external pins and fourth molding: On the lower surface of the third RDL, external pins are fabricated according to the pin type, and the fourth molding is completed; A9. Cutting: The packaged board is cut according to the shape and size of the common-mode filter to form the final common-mode filter.

[0014] Furthermore, the external pins are solder ball structures, and the manufacturing method of step A8 is as follows: The third RDL is encapsulated, and slots are cut at the external pin locations to expose the third RDL pads. A ball under metal layer is prepared in the slots, and then solder balls are soldered on the ball under metal layer to form external pins. or, The external pins are electroplated copper pillar pins, and the manufacturing method of step A8 is as follows: Copper pillars are fabricated on the pads on the lower surface of the third RDL. Then, the third RDL is encapsulated to form a fourth encapsulation layer. The fourth encapsulation layer is then ground at the position corresponding to the copper pillar to expose the copper pillar. Finally, tin is plated on the surface of the copper pillar to form external leads.

[0015] Further, in step A7, a third through-hole is formed by drilling holes in the first molding compound layer aligned with the pads on the lower surface of the second RDL layer, and the third through-hole is filled to form a third conductive element that directly conducts electricity between the second RDL layer and the third RDL layer.

[0016] The present invention also provides another method for manufacturing a common-mode filter with integrated electrostatic surge protection, used to manufacture the aforementioned common-mode filter with integrated electrostatic surge protection, the method comprising the following steps: B1. Fabrication of the second RDL: The second RDL is prepared on a temporary carrier, and a first conductive bump is grown on the second RDL as a third conductive element. B2. First molding: The second layer RDL is molded and the first conductive bumps are ground to form the first molding layer; B3. Fabrication of the first RDL layer: A first RDL layer is prepared on the surface of the first molding layer, and then a second conductive bump is grown on the first RDL layer as a first conductive element. B4. Processing electrostatic surge protection semiconductor chip: The electrostatic surge protection semiconductor chip is flip-chip bonded to the first conductive component to realize the electrical connection between the electrostatic surge protection semiconductor chip and the first layer RDL; B5. Second molding: The first RDL layer of the bonded electrostatic surge protection semiconductor chip is molded to form a second molding layer, and then the surface of the second molding layer is ground to expose the second conductive element of the electrostatic surge protection semiconductor chip; B6. Fabrication of the third RDL: Drill holes on the surface of the second molding layer corresponding to the pads of the first RDL to form a second through hole. Then fill the second through hole to form a third conductive element between the first RDL and the third RDL, and form the third RDL on the surface of the second molding layer. B7. Third molding and fabrication of external leads: Copper pillar leads are fabricated on the surface of the third layer RDL and the third molding is completed; B8. Fourth molding: After peeling off the temporary carrier, a fourth molding is performed on the surface of the second layer RDL to protect the second layer RDL; B9. Cutting: The packaged board is cut according to the shape and size of the common-mode filter to form the final common-mode filter.

[0017] Compared with existing technologies, the beneficial effects of this invention are as follows: This invention innovatively adopts double-sided RDL molding technology to achieve integrated integration of common-mode inductors and vertical ESD / TVS protection devices. This invention uses RDL to generate circuitry, eliminating the need for bonding metal wires, effectively solving the parasitic bonding metal wire problem faced by existing common-mode filter integration packaging technologies. Furthermore, all circuitry is externally encapsulated in a molding compound, with only the electrostatic surge protection semiconductor chip using a semiconductor silicon chip, significantly reducing the area used for the semiconductor chip and effectively solving the problem of wasted silicon die area, thus reducing manufacturing costs. In addition, this invention features a simple process and high processing precision, effectively solving the problem of low yield caused by the complex manufacturing process of existing slotted TVS chips. This invention effectively improves the performance stability of common-mode filters, further reducing overall manufacturing costs. This invention is compatible with various high-speed differential communication interfaces such as USB 4.0 and HDMI 2.1, and its application scenarios cover multiple fields such as consumer electronics, automotive electronics, and industrial communication equipment. Attached Figure Description

[0018] To more clearly illustrate the solutions in this invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0019] Figure 1(a) is a schematic diagram of the common-mode filter structure according to the first embodiment of the present invention; Figure 1(b) is the equivalent circuit diagram of the common-mode filter of the first embodiment of the present invention; Figure 1(c) is a flowchart of the preparation method of the common-mode filter according to the first embodiment of the present invention; Figure 2 This is the equivalent circuit diagram of the common-mode filter according to the second embodiment of the present invention; Figure 3 This is a schematic diagram of the common-mode filter structure according to the third embodiment of the present invention; Figure 4 This is a schematic diagram of the common-mode filter structure according to the fourth embodiment of the present invention; Figure 5(a) is a flowchart of the preparation method of the common-mode filter according to the fifth embodiment of the present invention; Figure 5(b) is the equivalent circuit diagram of the common-mode filter of the fifth embodiment of the present invention. Detailed Implementation

[0020] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains; the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings are used to distinguish different objects, not to describe a particular order.

[0021] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment to other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this invention can be combined with other embodiments.

[0022] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0023] As shown in Figure 1(a) and Figure 1(b) Figures 2-4 As shown in Figure 5(a), the common-mode filter of the present invention integrates electrostatic surge protection. The common-mode filter includes a first sub-inductor and a second sub-inductor coupled by a magnetic field, which are respectively disposed between the differential input port and the differential output port. The common-mode filter also includes an electrostatic surge protection semiconductor chip, a first layer RDL, a second layer RDL, and a third layer RDL stacked together. The RDL is a redistribution layer. The common-mode filter also includes external pins and a plastic package.

[0024] The first sub-inductor is disposed on the first RDL layer, the second sub-inductor is disposed on the second RDL layer, the third RDL layer has metal lines, the electrostatic surge protection semiconductor chip is disposed between the first RDL layer and the third RDL layer, the second RDL layer is disposed above the first RDL layer, the upper surface of the electrostatic surge protection semiconductor chip has a first conductive element for electrical connection with the first RDL layer, the lower surface of the electrostatic surge protection semiconductor chip has a second conductive element for electrical connection with the third RDL layer, the first RDL layer and the second RDL layer are respectively electrically connected to the metal lines of the third RDL layer through the third conductive element, the external pins are disposed on the lower surface of the third RDL layer, the molding compound is used to encapsulate the external area of ​​the common-mode filter and fill the interlayer area between the second RDL layer and the first RDL layer, and between the first RDL layer and the electrostatic surge protection semiconductor chip and the third RDL layer, only exposing the external pins.

[0025] This invention innovatively employs double-sided RDL molding technology to achieve integrated common-mode inductance and vertical ESD / TVS protection devices. By using RDL to generate the circuitry, this invention eliminates the need for bonding metal wires, effectively solving the parasitic bonding wire problem faced by existing common-mode filter integration and packaging technologies. Furthermore, all circuitry is externally encapsulated in a molding compound, with only the electrostatic surge protection semiconductor chip using a silicon chip, significantly reducing the area used for the semiconductor chip and effectively solving the problem of wasted silicon die area, thus lowering manufacturing costs. In addition, this invention features a simple process and high processing precision, effectively addressing the low yield issues caused by the complex manufacturing process of existing slotted TVS chips. This invention effectively improves the performance stability of the common-mode filter and further reduces overall manufacturing costs.

[0026] The number of electrostatic surge protection semiconductor chips is one, and the electrostatic surge protection semiconductor chip is provided with two sets of physically isolated electrostatic surge protection elements, which are used to connect between the differential input port and the common ground terminal, and between the differential output port and the common ground terminal, respectively.

[0027] Of course, the number of electrostatic surge protection semiconductor chips (hereinafter referred to as semiconductor chips) in this example can also be set to two. Each electrostatic surge protection semiconductor chip is equipped with one or more sets of electrostatic surge protection elements (referred to as vertical ESD / TVS devices) for connecting the differential input port and the common ground terminal, and the differential output port and the common ground terminal respectively. The two electrostatic surge protection semiconductor chips are arranged side by side and isolated above the third layer RDL.

[0028] The electrostatic surge protection element of this invention can be a single device such as a common diode, Zener diode, Trench MOSFET (Trench Metal-Oxide-Semiconductor Field-Effect Transistor), SGTMOSFET (Shielded Gate Trench MOSFET), superjunction MOSFET, silicon controlled rectifier (SCR), or BJT (Bipolar Junction Transistor, including NPN and PNP types), or a series-parallel network of one or more devices. The second conductive element on the back side of the electrostatic surge protection semiconductor chip can be formed during semiconductor wafer manufacturing or by sputtering. In this example, the first conductive element is a conductive copper bump, and the second conductive element is the back gold covering the back side of the electrostatic surge protection semiconductor chip.

[0029] The following description is based on specific embodiments, and the various reference numerals in the embodiments are explained as follows: 100 and 200 represent the magnetic coupling coefficient between inductors; 101, 102, 201, and 202 represent sub-inductors; 110 and 210 represent the common ground (GND). 111, 112, 113, 114, 211, 212, 213, and 214 represent signal ports; 120, 121, 122, 221, 222, 223, 224, 320, 420, 521, and 521-1 represent vertical ESD / TVS devices; 130, 330, 430, 530, and 530-1 represent semiconductor chips; 131, 331, 431, 531, 531-1, 531-2, and 531-3 represent copper bumps; 132, 332, 432, 532, and 532-1 represent chip pads (PADs); 133, 333, 433, 533, and 533-1 represent gold on the reverse side; 134, 334, and 534 represent copper pillar pins; 135, 335, and 535 represent tin plating; 141, 341, 441, 542 represent the first layer RDL, 142, 342, 442, 541 represent the second layer RDL, and 143, 343, 443, 543 represent the third layer RDL. 151, 351, and 451 represent the first through-molding via (TMV-1); 152, 352, 452, and 552 represent the second through-molding via (TMV-2); and 353 represents the third through-molding via (TMV-3). 160, 360, 460, and 560 represent epoxy molding compound (EMC). 436 represents the Under Ball Metal (UBM). 470 represents the solder ball.

[0030] As shown in Figure 1(a), in one embodiment of the present invention, the common-mode inductor adopts double-sided RDL molding technology. On the front side of the semiconductor chip 130, there are two RDL metal layers (first layer RDL141 and second layer RDL142) for manufacturing the two sub-inductors 101 and 102 of the common-mode inductor; on the back side of the semiconductor chip 130, there is one RDL metal layer—the third layer RDL143—for leading the electrodes to external pins. Copper bumps 131 are used to connect the front pad PAD132 of the semiconductor chip with the first layer RDL141, the first through-hole via (TMV-1) 151 is used to connect the first layer RDL141 with the second layer RDL142, and the second through-hole via 152 is used to connect the first layer RDL141 with the third layer RDL143. The side cross-sectional view of the two through-holes can be trapezoidal, rectangular, funnel-shaped, etc., depending on the specific manufacturing process. Semiconductor chip 130 integrates multiple vertical TVS / ESD devices 120. A back gold layer 133 is present on the back of semiconductor chip 130, directly electrically connected to the third layer RDL 143. Copper pillar leads 134 are fabricated on the third layer RDL 143, with a tin-plated layer 135 on top, serving as the external leads of the entire common-mode filter. The remaining area is completely encapsulated; in this example, the material of the encapsulation body 160 can be epoxy molding compound (EMC), etc.

[0031] In this example, sub-inductors 101 and 102 can be implemented using a planar spiral inductor structure, with shapes that can be circular, elliptical, polygonal, rectangular, or other irregular closed shapes. Each of the two sub-inductors 101 and 102 is implemented using a redistribution layer (RDL) (in this example, the second RDL142 and the first RDL141). In vertical projection, the RDL layout of the two sub-inductors is flexible; they can overlap, partially overlap, or not overlap at all. However, sufficient magnetic field coupling between the two sub-inductors must be ensured to achieve good common-mode noise suppression and sufficient differential-mode bandwidth.

[0032] As shown in Figure 1(b), the equivalent circuit of this embodiment contains a common-mode inductor, which is formed by two sub-inductors 101 and 102 coupled by a magnetic field, with a magnetic coupling coefficient of 100. 110 is the common ground terminal, and 111-114 are the signal ports of the common-mode inductor, including differential input ports and differential output ports. The differential input ports include a first differential input terminal and a second differential input terminal, and the differential output ports include a first differential output terminal and a second differential output terminal. The first differential input terminal and the first differential output terminal are disposed on the first layer RDL, and the second differential input terminal and the second differential output terminal are disposed on the second layer RDL. Correspondingly, the external pins in this example include a first pin, a second pin, a third pin, a fourth pin, and a fifth pin. The first pin is electrically connected to the first differential input terminal, the second pin is electrically connected to the first differential output terminal, the third pin is electrically connected to the second differential input terminal, the fourth pin is electrically connected to the second differential output terminal, and the fifth pin is the common ground terminal.

[0033] In this example, a longitudinal ESD / TVS device 121 and 122 are connected between the first differential input terminal, the second differential input terminal, and the common ground terminal 110, respectively, to achieve electrostatic discharge and surge protection.

[0034] This invention integrates a common-mode inductor and a longitudinal ESD / TVS device, enabling a single device to simultaneously suppress common-mode noise and discharge static and surge energy.

[0035] As shown in Figure 1(c), the preparation method of this embodiment includes the following steps: A1. Processing electrostatic surge protection semiconductor chips: Conductive copper bumps are prepared on the front side of the semiconductor wafer, and the semiconductor wafer is diced to obtain independent electrostatic surge protection semiconductor chips. A2. First molding: The back side of the electrostatic surge protection semiconductor chip is attached to a temporary carrier board, and the front side of the electrostatic surge protection semiconductor chip is first molded to form the first molding layer. Then, the conductive copper bumps are ground to expose them. A3. Fabrication of the first RDL layer: The first RDL layer is fabricated on top of the first molding layer using a combination of chemical plating and electroplating processes. A4. Second molding: The first RDL layer is molded and ground to form a second molding layer. The second molding layer is aligned with the pads on the upper surface of the first RDL layer to form a first through-hole between the first RDL layer and the second RDL layer. In this example, the first through-hole can be prepared by photolithography or laser drilling. A5. Fabrication of the second RDL: Fill the first through-hole to form a third conductive element, and form the second RDL on the upper surface of the second encapsulation layer; A6. Third molding: Molding the second layer RDL to form a third molding layer that protects the second layer RDL; A7. Fabrication of the third RDL: Peel off the temporary carrier board on the back of the electrostatic surge protection semiconductor chip, drill holes in the first molding compound layer aligned with the pads on the lower surface of the first RDL to form a second through-hole, fill the second through-hole to form a third conductive element between the first RDL and the third RDL, and form the third RDL on the first molding compound layer and the lower surface of the electrostatic surge protection semiconductor chip. In this embodiment, a combination of chemical plating and electroplating is preferred. A8. Fabrication of external pins and fourth molding: On the lower surface of the third RDL, external pins are fabricated according to the pin type, and the fourth molding is completed; A9. Cutting: The packaged board is cut according to the shape and size of the common-mode filter to form the final common-mode filter. After cutting into individual common-mode filter units, electrical performance testing is performed.

[0036] In this embodiment, the external pins are electroplated copper pillar pins. The manufacturing method of step A8 is as follows: Copper pillar leads are fabricated on the pads on the lower surface of the third RDL layer. The third RDL layer is then encapsulated to form a fourth encapsulation layer. The fourth encapsulation layer is then ground at the corresponding positions of the copper pillars to expose them. Finally, tin plating is applied to the surface of the copper pillars to improve solderability and reliability, forming external leads. In this example, electroplating is preferably used for fabricating the copper pillar leads and applying tin, as it simplifies the process.

[0037] like Figure 2 As shown, as a second embodiment of the present invention, the equivalent circuit diagram of this embodiment is similar to that of the first embodiment, and also includes a common-mode inductor composed of two mutually coupled sub-inductors 201 and 202, with a magnetic coupling coefficient of 200. Furthermore, a vertical ESD / TVS device 221 and 222 are respectively connected between the first differential input terminal, the second differential input terminal, and the common ground terminal 210.

[0038] The difference between this embodiment and the first embodiment is that this embodiment additionally connects a vertical ESD / TVS device 223 and 224 between the first differential output terminal and the second differential output terminal of the common-mode inductor and the common ground terminal 210, respectively, to provide more robust electrostatic discharge (ESD) and surge protection. When an ESD or surge event occurs at any differential input terminal, the input-side ESD / TVS device 221 or 222, the sub-inductor 201 or 202, and the output-side ESD / TVS device 223 or 224, which are on the same signal link, together form a two-stage ESD / surge protection network, significantly improving the device's ESD and surge protection capabilities; the same applies when an ESD or surge event occurs at any differential output terminal.

[0039] like Figure 3 As shown, as the third embodiment of the present invention, this embodiment further optimizes the second through hole based on the first embodiment.

[0040] Similar to the first embodiment, the first through-hole 351 is used to connect the first layer RDL 341 and the second layer RDL 342. The second through-hole 352 is used to connect the first layer RDL 341 and the third layer RDL 343.

[0041] The difference between this embodiment and the first embodiment is that this embodiment considers the connectivity between the second layer RDL342 and the third layer RDL343. In the first embodiment, the second layer RDL342 must first reach the first layer RDL341 through the first through-hole 351, and then reach the third layer RDL343 through the second through-hole 352. The overall path is relatively long, which will bring more parasitic parameters. In this embodiment, by additionally setting the third through-hole 353, the second layer RDL342 and the third layer RDL343 can be directly connected, the package routing is more flexible, and the parasitic resistance and inductance on the signal path can be significantly reduced.

[0042] The manufacturing method of this embodiment differs from that of the first embodiment only in step A7. In step A7 of this example, a third through-hole 353 is formed by drilling a hole in the first molding compound layer aligned with the pad on the lower surface of the second layer RDL342. The third through-hole 353 is filled to form a third conductive element that directly conducts electricity between the second layer RDL and the third layer RDL.

[0043] Specifically, in this example, laser drilling is performed on the pads of the first layer RDL341 in the outer plastic encapsulation area of ​​the semiconductor chip 330, stopping at the first layer RDL341, to construct TMV-2 352.

[0044] In the plastic encapsulation area surrounding semiconductor chip 330 where there is no first layer RDL341, the pads of the second layer RDL342 are aligned, and laser drilling is performed until the second layer RDL342 is reached, for constructing TMV-3 353.

[0045] Then, the third layer RDL343 is fabricated in one piece and filled with TMV-2 352 and TMV-3 353, preferably using a combination of chemical plating and electroplating.

[0046] In this embodiment, the TMV-3 directly conducts between the second and third RDL layers, eliminating the need for conduction via the first RDL layer, thus shortening the conductive path length and reducing the overall parasitic resistance and inductance of the device.

[0047] like Figure 4 As shown, in the fourth embodiment of the present invention, the morphology of the external pins has been further optimized.

[0048] Unlike the first embodiment, in this embodiment, an Under Ball Metal (UBM) 436 is first fabricated on the third layer RDL443 and coated with flux. Then, solder balls 470 are placed on the UBM to form spherical leads. The solder balls are preferably made of SAC105 / 305 / 405 alloy. Compared to the flat leads of the first embodiment, the spherical leads in this embodiment help to further enhance the lead layout flexibility and solderability of the product.

[0049] In this example, solder ball 470 can be an external lead made of SAC series alloy solder ball, and the SAC alloy can be any one of SAC105, SAC305, or SAC405.

[0050] This embodiment uses external pins with a solder ball structure. The manufacturing method for step A8 is as follows: The third layer RDL is encapsulated, and slots are cut at the external pin positions. The process stops at the third layer RDL443, exposing the third layer RDL pads. A ball under metal layer is prepared in the slot, and then solder balls are placed on the ball under metal layer. Reflow soldering is performed to metallurgically bond the solder balls 470 to the third layer RDL443. The surface is then cleaned to form the external pins.

[0051] As shown in Figure 5(a), as the fifth embodiment of this patent, compared with the first embodiment, the number of electrostatic surge protection semiconductor chips in this embodiment is two. Each electrostatic surge protection semiconductor chip is provided with one or more vertical ESD / TVS devices 521, 521-1, which are used to connect between the differential input port and the common ground terminal and between the differential output port and the common ground terminal, respectively. The two semiconductor chips 530, 530-1 are arranged side by side and isolated above the third layer RDL.

[0052] As shown in Figure 5(b), this embodiment demonstrates another packaging process. In this case, two RDL layers are fabricated first, followed by chip placement. Specifically, the second RDL 541 and the first RDL 542 are fabricated sequentially, connected by first copper bumps 531 and 531-2. Then, multiple semiconductor chips 530 and 530-1 are flip-chip bonded. The pad 532 on the front side of semiconductor chip 530 is connected to the first RDL 542 via a second copper bump 531-1; the pad 532-1 on the front side of semiconductor chip 530-1 is connected to the first RDL 542 via a second copper bump 531-3. As shown in Figure 5(a), multiple independent semiconductor chips can be present and flip-chip mounted together. The advantage of this is that multiple vertical ESD / TVS devices can be placed in different semiconductor chips, completely isolated from each other, avoiding the introduction of additional parasitic problems and mitigating interference from additional parasitic parameters. Next, the third layer RDL543 and the second through-hole 552 are integrated into a single process, ultimately forming the external pins. Compared to the Chip-first process in the first embodiment, this embodiment uses the RDL-first process, which enables finer RDL metal wiring. This helps optimize the electrical characteristics of the common-mode inductor and improve the common-mode filtering effect. At the same time, it can also avoid unnecessary damage to the ESD / TVS silicon chip caused by the packaging process, optimize product yield and reliability, and ensure the stability of the electrostatic discharge and surge protection levels.

[0053] Specifically, the common-mode inductor manufacturing method in this example is as follows: B1. Fabrication of the second RDL: The second RDL is prepared on the temporary carrier, preferably by a combination of chemical plating and electroplating, and a first copper bump is grown on the second RDL as a third conductive element for electrical connection. The first copper bump is preferably generated by electroplating. B2. First molding: The second layer RDL541 is molded and the first copper bumps 531 and 531-2 are ground to expose them, forming the first molding layer. It is necessary to ensure that the top surface of the first copper bumps 531 and 531-2 is flush with the molding layer to provide a flat interface for the first layer RDL542. B3. Fabrication of the first RDL layer: The first RDL 542 is prepared on the surface of the first molding layer. Then, a second copper bump is grown on the first RDL 542 as the first conductive element. In this example, the second copper bumps 531-1 and 531-3 need to be compatible with the size and position of the pads 532 and 532-1 of the semiconductor chip to facilitate subsequent flip bonding. B4. Processing electrostatic surge protection semiconductor chip: The electrostatic surge protection semiconductor chip is flip-chip bonded to the first conductive component to realize the electrical connection between the electrostatic surge protection semiconductor chip and the first layer RDL. Specifically, in this example, the active surfaces of semiconductor chips 530 and 530-1 are facing down and are bonded to the first layer RDL 542 by hot pressing or reflow bonding through the second copper bump. B5. Second molding: The first RDL layer of the bonded electrostatic surge protection semiconductor chip is molded to form the second molding layer. Then, the surface of the second molding layer is ground to expose the back gold 533 and 533-1 of the semiconductor chip. B6. Fabrication of the third RDL layer: Laser drilling is performed on the surface of the second molding layer at the position corresponding to the pad of the first RDL layer, stopping at the first RDL 542, to construct the second through-hole 552. The alignment accuracy of the laser drilling is controlled within ±5μm to ensure that the second through-hole 552 falls completely on the pad of the first RDL 542. Then, the second through-hole 552 is filled to form the third conductive element between the first RDL 542 and the third RDL 543. The third RDL 543 is integrally fabricated on the surface of the second molding layer, preferably using a combination of chemical plating and electroplating. B7. Third molding and fabrication of external leads: Copper pillar leads 534 are fabricated on the surface of the third layer RDL543 and the third molding is completed to protect the copper pillar leads 534 and to use the rigidity of the temporary carrier board to suppress warping problems. B8. Fourth molding: Peel off the temporary carrier board to expose the bottom surface of the second layer RDL541, forming a double-sided wiring structure. Then, perform a fourth molding on the surface of the second layer RDL541 to protect the second layer RDL541. B9. Cutting: The packaged board is cut according to the shape and size of the common-mode filter to form the final common-mode filter.

[0054] In step B5, if semiconductor chips 530 and 530-1 do not have back gold, the grinding can be controlled to stop at a distance of ≥50μm from the active area on the front of the chip, and then the back gold can preferably be formed by sputtering.

[0055] In step B7, after the third molding process, a single-sided grinding is performed to expose the copper pillar leads 534. Then, tin plating is applied to form a tin plating layer 535 on the surface of the copper pillar leads 534, improving solderability and reliability. Electroplating is preferred. Alternatively, the single-sided grinding can be performed after the fourth molding process to fabricate the external leads.

[0056] In summary, this invention effectively solves the problems of parasitic bonding metal lines, wasted silicon die area, and low yield caused by complex manufacturing processes in the integrated packaging technology of existing common-mode filters through structural and manufacturing process improvements. It can be adapted to various high-speed differential communication interfaces such as USB4.0 and HDMI2.1, and its application scenarios cover multiple fields such as consumer electronics, automotive electronics, and industrial communication equipment.

[0057] The specific embodiments described above are preferred embodiments of the present invention and are not intended to limit the specific scope of the present invention. The scope of the present invention includes, but is not limited to, these specific embodiments. All equivalent changes made in accordance with the present invention are within the protection scope of the present invention.

Claims

1. A common-mode filter with integrated electrostatic surge protection, the common-mode filter comprising a first sub-inductor and a second sub-inductor coupled by a magnetic field, respectively disposed between a differential input port and a differential output port, characterized in that: The common-mode filter further includes a stacked electrostatic surge protection semiconductor chip, a first RDL layer, a second RDL layer, and a third RDL layer, where the RDL layer is a redistribution layer. The common-mode filter also includes external pins and a plastic package. The first sub-inductor is disposed on the first RDL layer, the second sub-inductor is disposed on the second RDL layer, the third RDL layer has metal lines, the electrostatic surge protection semiconductor chip is disposed between the first RDL layer and the third RDL layer, the second RDL layer is disposed above the first RDL layer, the upper surface of the electrostatic surge protection semiconductor chip has a first conductive element for electrical connection with the first RDL layer, the lower surface of the electrostatic surge protection semiconductor chip has a second conductive element for electrical connection with the third RDL layer, the first RDL layer and the second RDL layer are respectively electrically connected to the metal lines of the third RDL layer through the third conductive element, the external pins are disposed on the lower surface of the third RDL layer, the molding compound is used to encapsulate the external area of ​​the common-mode filter and fill the interlayer area between the second RDL layer and the first RDL layer, and between the first RDL layer and the electrostatic surge protection semiconductor chip and the third RDL layer, only exposing the external pins.

2. The common-mode filter with integrated electrostatic surge protection according to claim 1, characterized in that: The differential input port includes a first differential input terminal and a second differential input terminal, and the differential output port includes a first differential output terminal and a second differential output terminal. The first differential input terminal and the first differential output terminal are disposed on the first layer RDL, and the second differential input terminal and the second differential output terminal are disposed on the second layer RDL. The external pins include a first pin, a second pin, a third pin, a fourth pin, and a fifth pin. The first pin is electrically connected to the first differential input terminal, the second pin is electrically connected to the first differential output terminal, the third pin is electrically connected to the second differential input terminal, the fourth pin is electrically connected to the second differential output terminal, and the fifth pin is a common ground terminal. The vertically arranged electrostatic surge protection semiconductor chips are in groups of one or more, respectively located between the differential input port and the common ground terminal, and / or between the differential output port and the common ground terminal.

3. The common-mode filter with integrated electrostatic surge protection according to claim 2, characterized in that: The number of electrostatic surge protection semiconductor chips is one, and the electrostatic surge protection semiconductor chip is provided with multiple sets of physically isolated electrostatic surge protection elements, which are used to connect between the differential input port and the common ground terminal, and between the differential output port and the common ground terminal, respectively. or, The number of electrostatic surge protection semiconductor chips is two, and each electrostatic surge protection semiconductor chip is provided with one or more electrostatic surge protection elements, which are used to connect between the differential input port and the common ground terminal and between the differential output port and the common ground terminal, respectively. The two electrostatic surge protection semiconductor chips are arranged side by side and isolated above the third layer RDL.

4. The common-mode filter with integrated electrostatic surge protection according to claim 1, characterized in that: The second sub-inductor of the second layer RDL is electrically connected to the metal lines of the first layer RDL and the third layer RDL, or the second sub-inductor of the second layer RDL is directly electrically connected to the metal lines of the third layer RDL.

5. The common-mode filter with integrated electrostatic surge protection according to claim 1, characterized in that: The external pins are solder ball structures, and a ball-under metal layer is provided on the surface of the third RDL layer. Solder balls are soldered on the ball-under metal layer as external pins.

6. The common-mode filter with integrated electrostatic surge protection according to claim 1, characterized in that: The external pins are electroplated copper pillar pins, which are formed on the surface of the third RDL layer. The outer surface of the copper pillar pins is tin-plated, and the copper pillar pins are partially exposed outside the molding compound for soldering and connection with the PCB board.

7. A method for manufacturing a common-mode filter with integrated electrostatic surge protection, used to manufacture the common-mode filter with integrated electrostatic surge protection as described in any one of claims 1-6, characterized in that, The manufacturing method includes the following steps: A1. Processing electrostatic surge protection semiconductor chips: Conductive bumps are prepared on the front side of the semiconductor wafer as the first conductive element, and the semiconductor wafer is diced to obtain independent electrostatic surge protection semiconductor chips. A2. First molding: The back side of the electrostatic surge protection semiconductor chip is attached to a temporary carrier board, and the front side of the electrostatic surge protection semiconductor chip is first molded to form the first molding layer. Then, the conductive bumps are ground to expose them. A3. Fabrication of the first RDL layer: The first RDL layer is fabricated on top of the first molding layer using a combination of chemical plating and electroplating processes. A4. Second molding: The first layer RDL is molded and ground to form a second molding layer. Holes are drilled in the second molding layer to align with the pads on the upper surface of the first layer RDL to form a first through hole between the first layer RDL and the second layer RDL. A5. Fabrication of the second RDL: Fill the first through-hole to form a third conductive element, and form the second RDL on the upper surface of the second encapsulation layer; A6. Third molding: Molding the second layer RDL to form a third molding layer that protects the second layer RDL; A7. Fabrication of the third RDL: Peel off the temporary carrier board on the back of the electrostatic surge protection semiconductor chip, drill holes in the first molding layer aligned with the pads on the lower surface of the first RDL to form a second through hole, fill the second through hole to form a third conductive element between the first RDL and the third RDL, and form the third RDL on the first molding layer and the lower surface of the electrostatic surge protection semiconductor chip. A8. Fabrication of external pins and fourth molding: On the lower surface of the third RDL, external pins are fabricated according to the pin type, and the fourth molding is completed; A9. Cutting: The packaged board is cut according to the shape and size of the common-mode filter to form the final common-mode filter.

8. The manufacturing method according to claim 7, characterized in that: The external pins are solder ball structures, and the manufacturing method of step A8 is as follows: The third RDL is encapsulated, and slots are cut at the external pin locations to expose the third RDL pads. A ball under metal layer is prepared in the slots, and then solder balls are soldered on the ball under metal layer to form external pins. or, The external pins are electroplated copper pillar pins, and the manufacturing method of step A8 is as follows: Copper pillars are fabricated on the pads on the lower surface of the third RDL. Then, the third RDL is encapsulated to form a fourth encapsulation layer. The fourth encapsulation layer is then ground at the position corresponding to the copper pillar to expose the copper pillar. Finally, tin is plated on the surface of the copper pillar to form external leads.

9. The manufacturing method according to claim 7, characterized in that: In step A7, a third through-hole is formed by drilling holes in the first molding compound layer aligned with the pads on the lower surface of the second RDL layer, and the third through-hole is filled to form a third conductive element that directly conducts electricity between the second RDL layer and the third RDL layer.

10. A method for manufacturing a common-mode filter with integrated electrostatic surge protection, used to manufacture the common-mode filter with integrated electrostatic surge protection as described in any one of claims 1-6, characterized in that, The manufacturing method includes the following steps: B1. Fabrication of the second RDL: The second RDL is prepared on a temporary carrier, and a first conductive bump is grown on the second RDL as a third conductive element. B2. First molding: The second layer RDL is molded and the first conductive bumps are ground to form the first molding layer; B3. Fabrication of the first RDL layer: A first RDL layer is prepared on the surface of the first molding layer, and then a second conductive bump is grown on the first RDL layer as a first conductive element. B4. Processing electrostatic surge protection semiconductor chip: The electrostatic surge protection semiconductor chip is flip-chip bonded to the first conductive component to realize the electrical connection between the electrostatic surge protection semiconductor chip and the first layer RDL; B5. Second molding: The first RDL layer of the bonded electrostatic surge protection semiconductor chip is molded to form a second molding layer, and then the surface of the second molding layer is ground to expose the second conductive element of the electrostatic surge protection semiconductor chip; B6. Fabrication of the third RDL: Drill holes on the surface of the second molding layer corresponding to the pads of the first RDL to form a second through hole. Then fill the second through hole to form a third conductive element between the first RDL and the third RDL, and form the third RDL on the surface of the second molding layer. B7. Third molding and fabrication of external leads: Copper pillar leads are fabricated on the surface of the third layer RDL and the third molding is completed; B8. Fourth molding: After peeling off the temporary carrier, a fourth molding is performed on the surface of the second layer RDL to protect the second layer RDL; B9. Cutting: The packaged board is cut according to the shape and size of the common-mode filter to form the final common-mode filter.

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