A reconfigurable polyphase filter

Abstract

The application provides a reconfigurable polyphase filter, which comprises a differential hybrid input stage circuit, a first-stage polyphase filter circuit and a switch control terminal. The differential hybrid input stage circuit comprises an input stage I channel and an input stage Q channel, each channel generates a differential intermediate signal through a differential input coupling capacitor group, a common mode bias resistor group, a differential MOS conversion circuit and a cross-coupled output circuit. The first-stage polyphase filter circuit comprises a first-stage filter I channel, a first-stage filter Q channel and a feedforward capacitor circuit, and the switch control terminal controls the access or disconnection of the feedforward capacitor branch, so that the filter is switched between a polyphase filter state and a low-pass filter state. The filter channel is provided with a cross-coupled resistor and a PMOS equivalent capacitor unit to adjust the quality factor and compensate for the parasitic zero point; a voltage buffer circuit and a second-stage polyphase filter circuit can also be provided to improve the driving capability and expand the image rejection bandwidth. The application has the advantages of low power consumption, high linearity, low noise and reconfigurable filter state.

Description

Technical Field

[0001] This application relates to the field of radio frequency receiver technology, and more specifically, to a reconfigurable polyphase filter. Background Technology

[0002] With the development of wireless communication, the Internet of Things, cognitive radio, and dynamic spectrum access technologies, radio frequency receivers need to quickly identify target signals and suppress interference signals in complex spectrum environments. Especially in low-IF or quadrature downconversion receivers, the I / Q mixing process easily generates image signals. If these image signals cannot be effectively suppressed, it will reduce the receiver's output signal-to-noise ratio and signal selectivity. Existing active RC filters are easily limited by the operational amplifier gain bandwidth under high-frequency conditions, leading to increased power consumption. While Gm-C filters are suitable for high-frequency operation, their open-loop characteristics easily cause a decrease in linearity, making it difficult to simultaneously meet the requirements of low power consumption, high linearity, and image suppression.

[0003] To address the aforementioned issues, patent CN121308718A discloses a hybrid complex filter circuit with high linearity and high image rejection ratio based on a source follower. This circuit includes an AC coupling circuit, a multiphase filter circuit, and a feedforward capacitor. This solution improves linearity through the source follower structure, achieves a complex filtering effect through the AC coupling circuit and the multiphase filter, and enhances image rejection capability using the feedforward capacitor. To a certain extent, it improves upon the problems of high power consumption, insufficient linearity, and limited image rejection capability of traditional filters.

[0004] However, the feedforward capacitors in the above schemes mainly participate in filtering with a fixed connection, resulting in a relatively fixed circuit operating mode. When the spectrum environment of the receiver changes, the existing structure cannot flexibly switch between low-pass filtering and polyphase filtering states according to the strength of image interference or low-power operation requirements. Therefore, there is still room for improvement in further balancing power consumption, linearity, and image suppression performance. In addition, in broadband or high-frequency application scenarios, the passband flatness, stopband rejection capability, and parasitic effects on the frequency response of the filter will further limit the receiver performance.

[0005] Therefore, in view of the problem that the existing polyphase filters have relatively fixed operating modes and it is difficult to balance power consumption, linearity and image suppression performance, there is an urgent need for a polyphase filter that can flexibly adjust its operating state according to different receiving scenarios while maintaining low power consumption and high linearity, and improve image suppression performance. Summary of the Invention

[0006] The purpose of this application is to provide a reconfigurable polyphase filter to address the shortcomings of the prior art.

[0007] To achieve the above objectives, the technical solution adopted in this application is as follows: This application provides a reconfigurable multiphase filter, including a differential mixing input stage circuit, a first-stage multiphase filter circuit, and a switching control terminal; The differential mixed input stage circuit includes an input stage I path for processing I-channel differential input signals and an input stage Q path for processing Q-channel differential input signals. Both the input stage I path and the input stage Q path include a common-mode bias resistor group and a differential input coupling capacitor group, a differential MOS conversion circuit, and a cross-coupled output circuit connected in sequence. The common-mode bias resistor group is connected to the input terminals of the differential MOS conversion circuit and the cross-coupled output circuit, respectively, to provide common-mode bias to the differential MOS conversion circuit and the cross-coupled output circuit. The differential input signal of the path is coupled to the differential MOS conversion circuit through the differential input coupling capacitor group. The differential MOS conversion circuit converts the differential input signal under the common-mode bias provided by the common-mode bias resistor group. The cross-coupled output circuit generates the differential intermediate signal of the path according to the output signal of the differential MOS conversion circuit. The first-stage multiphase filter circuit includes a first-stage filter I path, a first-stage filter Q path, and a first-stage feedforward capacitor circuit. The input terminal of the first-stage filter I path is connected to the output terminal of the cross-coupled output circuit in the input stage I path, and the input terminal of the first-stage filter Q path is connected to the output terminal of the cross-coupled output circuit in the input stage Q path. The first-stage feedforward capacitor circuit includes at least a first set of feedforward capacitor branches and a second set of feedforward capacitor branches. Each feedforward capacitor branch includes a feedforward capacitor and a switching unit connected in series with the feedforward capacitor. The first set of feedforward capacitor branches is connected between the input terminal of the differential input coupling capacitor group in the input stage I path and the input terminal of the first-stage filter Q path. The second set of feedforward capacitor branches is connected between the input terminal of the differential input coupling capacitor group in the input stage Q path and the input terminal of the first-stage filter I path. When the switching unit is turned on, the first set of feedforward capacitor branches is used to feed forward the feedforward component of the I-path differential input signal to the input terminal of the first-stage filter Q path in a capacitive coupling manner. The second set of feedforward capacitor branches is used to feed forward the feedforward component of the Q-path differential input signal to the input terminal of the first-stage filter I path in a capacitive coupling manner, so as to form a cross-feedforward path between the first-stage filter I path and the first-stage filter Q path. The switch control terminal is connected to each switch unit and is used to control the feedforward capacitor branch to connect to or disconnect the corresponding cross feedforward path so that the reconfigurable multiphase filter can switch between multiphase filtering state and low-pass filtering state.

[0008] Furthermore, the input stage I-path has a third bias voltage input terminal VB3, an I-path positive input terminal IIP, an I-path negative input terminal IIN, an I-path first group of positive differential output nodes VOP_I, an I-path first group of negative differential output nodes VON_I, an I-path positive differential intermediate output terminal VSP_I, an I-path negative differential intermediate output terminal VSN_I, a first common-mode voltage input terminal VCM1, a second common-mode voltage input terminal VCM2, and a third common-mode voltage input terminal VCM3; the differential input coupling capacitor group of the input stage I-path includes a first capacitor C1 to a fourth capacitor C4, the differential MOS conversion circuit includes a zero bias transistor MVB0 and a first MOS transistor M1 to a fourth MOS transistor M4, the cross-coupled output circuit includes a fifth MOS transistor M5 to an eighth MOS transistor M8, a fifth capacitor C5, and a sixth capacitor C6, and the common-mode bias resistor group includes a first resistor R1 to a sixth resistor R6; The first capacitor C1 is connected between the negative input terminal IIN of the I-channel and the gate of the first MOSFET M1; the first resistor R1 is connected between the first common-mode voltage input terminal VCM1 and the gate of the first MOSFET M1; the second capacitor C2 is connected between the positive input terminal IIP of the I-channel and the gate of the second MOSFET M2; the second resistor R2 is connected between the first common-mode voltage input terminal VCM1 and the gate of the second MOSFET M2; the third capacitor C3 is connected between the positive input terminal IIP of the I-channel and the gate of the third MOSFET M3; the third resistor R3 is connected between the second common-mode voltage input terminal VCM2 and the gate of the third MOSFET M3; the fourth capacitor C4 is connected between the negative input terminal IIN of the I-channel and the gate of the fourth MOSFET M4; the fourth resistor R4 is connected between the second common-mode voltage input terminal VCM2 and the gate of the fourth MOSFET M4. The source of the zero-bias transistor MVB0 is connected to the power supply voltage VDD, the gate is connected to the third bias voltage input terminal VB3, and the drain is connected to the source of the first MOSFET M1 and the source of the second MOSFET M2. The drain of the first MOSFET M1 forms the first group of positive differential output nodes VOP_I, and the drain of the second MOSFET M2 forms the first group of negative differential output nodes VON_I. The source of the third MOSFET M3 is connected to the first group of positive differential output nodes VOP_I, and the drain of the third MOSFET M3 is connected to ground GND. The source of the fourth MOSFET M4 is connected to the first group of negative differential output nodes VON_I, and the drain of the fourth MOSFET M4 is connected to ground GND. The gate of the fifth MOSFET M5 is connected to the first negative differential output node VON_I of the I-channel, the source is connected to the power supply voltage VDD, and the drain is connected to the intermediate output terminal VSP_I of the I-channel. The gate of the sixth MOSFET M6 is connected to the first positive differential output node VOP_I of the I-channel, the source is connected to the power supply voltage VDD, and the drain is connected to the intermediate output terminal VSN_I of the I-channel. The fifth capacitor C5 is connected between the first positive differential output node VOP_I of the I-channel and the gate of the seventh MOSFET M7, and the fifth resistor R5 is connected to the third common-mode voltage input terminal VCM. 3 is connected between the gate of the seventh MOSFET M7 and the source of the seventh MOSFET M7 to the positive differential intermediate output terminal VSP_I of the I-path, and the drain of the seventh MOSFET M7 to ground GND; the sixth capacitor C6 is connected between the first negative differential output node VON_I of the I-path and the gate of the eighth MOSFET M8; the sixth resistor R6 is connected between the third common-mode voltage input terminal VCM3 and the gate of the eighth MOSFET M8; the source of the eighth MOSFET M8 is connected to the negative differential intermediate output terminal VSN_I of the I-path, and the drain of the eighth MOSFET M8 to ground GND; The resistance values ​​of the first resistor R1 to the sixth resistor R6 are equal, and the capacitance values ​​of the first capacitor C1 to the sixth capacitor C6 are equal.

[0009] Furthermore, the input stage Q path has a third bias voltage input terminal VB3, a Q-path positive input terminal IQP, a Q-path negative input terminal IQN, a Q-path first group of positive differential output nodes VOP_Q, a Q-path first group of negative differential output nodes VON_Q, a Q-path positive differential intermediate output terminal VSP_Q, a Q-path negative differential intermediate output terminal VSN_Q, a first common-mode voltage input terminal VCM1, a second common-mode voltage input terminal VCM2, and a third common-mode voltage input terminal VCM3; the differential input coupling capacitor group of the input stage Q path includes the seventh capacitor C7 to the tenth capacitor C10, the differential MOS conversion circuit includes the first bias transistor MVB1 and the ninth MOS transistor M9 to the twelfth MOS transistor M12, the cross-coupled output circuit includes the thirteenth MOS transistor M13 to the sixteenth MOS transistor M16, the eleventh capacitor C11 and the twelfth capacitor C12, and the common-mode bias resistor group includes the seventh resistor R7 to the twelfth resistor R12; The seventh capacitor C7 is connected between the negative input terminal IQN of the Q-path and the gate of the ninth MOSFET M9; the seventh resistor R7 is connected between the first common-mode voltage input terminal VCM1 and the gate of the ninth MOSFET M9; the eighth capacitor C8 is connected between the positive input terminal IQP of the Q-path and the gate of the tenth MOSFET M10; the eighth resistor R8 is connected between the first common-mode voltage input terminal VCM1 and the gate of the tenth MOSFET M10; the ninth capacitor C9 is connected between the positive input terminal IQP of the Q-path and the gate of the eleventh MOSFET M11; the ninth resistor R9 is connected between the second common-mode voltage input terminal VCM2 and the gate of the eleventh MOSFET M11; the tenth capacitor C10 is connected between the negative input terminal IQN of the Q-path and the gate of the twelfth MOSFET M12; the tenth resistor R10 is connected between the second common-mode voltage input terminal VCM2 and the gate of the twelfth MOSFET M12. The source of the first bias transistor MVB1 is connected to the power supply voltage VDD, the gate is connected to the third bias voltage input terminal VB3, and the drain is connected to the source of the ninth MOSFET M9 and the source of the tenth MOSFET M10, respectively. The drain of the ninth MOSFET M9 forms the first group of positive differential output nodes VOP_Q of the Q-path, and the drain of the tenth MOSFET M10 forms the first group of negative differential output nodes VON_Q of the Q-path. The source of the eleventh MOSFET M11 is connected to the first group of positive differential output nodes VOP_Q of the Q-path, and the drain of the eleventh MOSFET M11 is connected to ground GND. The source of the twelfth MOSFET M12 is connected to the first group of negative differential output nodes VON_Q of the Q-path, and the drain of the twelfth MOSFET M12 is connected to ground GND. The gate of the thirteenth MOSFET M13 is connected to the first negative differential output node VON_Q of the Q-path, the source is connected to the power supply voltage VDD, and the drain is connected to the positive differential intermediate output terminal VSP_Q of the Q-path. The gate of the fourteenth MOSFET M14 is connected to the first positive differential output node VOP_Q of the Q-path, the source is connected to the power supply voltage VDD, and the drain is connected to the negative differential intermediate output terminal VSN_Q of the Q-path. The eleventh capacitor C11 is connected between the first positive differential output node VOP_Q of the Q-path and the gate of the fifteenth MOSFET M15, and the eleventh resistor R11 is connected between the third common-mode voltage input terminal VCM3 and the tenth resistor. Between the gates of the five MOSFETs M15, the source of the fifteenth MOSFET M15 is connected to the positive differential intermediate output terminal VSP_Q of the Q-path, and the drain of the fifteenth MOSFET M15 is connected to ground GND; the twelfth capacitor C12 is connected between the first negative differential output node VON_Q of the Q-path and the gate of the sixteenth MOSFET M16; the twelfth resistor R12 is connected between the third common-mode voltage input terminal VCM3 and the gate of the sixteenth MOSFET M16; the source of the sixteenth MOSFET M16 is connected to the negative differential intermediate output terminal VSN_Q of the Q-path, and the drain of the sixteenth MOSFET M16 is connected to ground GND; The resistance values ​​of the seventh resistor R7 to the twelfth resistor R12 are equal, and the capacitance values ​​of the seventh capacitor C7 to the twelfth capacitor C12 are equal.

[0010] Furthermore, the first-stage filter I-path includes a first bias voltage input terminal VB1, a second bias voltage input terminal VB2, a first-stage I-path positive filter input terminal VSP_I, a first-stage I-path negative filter input terminal VSN_I, a first-stage I-path positive filter output terminal VOP_I1, a first-stage I-path negative filter output terminal VON_I1, second bias transistors MVB2 to fifth bias transistors MVB5, a seventeenth MOSFET M17, an eighteenth MOSFET M18, a first PMOS transistor MP1, a second PMOS transistor MP2, a thirteenth capacitor C13, a fourteenth capacitor C14, a thirteenth resistor R13, and a fourteenth resistor R14. The first-stage I-path positive filter input terminal and the I-path positive differential intermediate output terminal share the node VSP_I, and the first-stage I-path negative filter input terminal and the I-path negative differential intermediate output terminal share the node VSN_I. The sources of the second bias transistor MVB2 and the third bias transistor MVB3 are connected to the power supply voltage VDD. The gates of the second bias transistor MVB2 and the third bias transistor MVB3 are connected to the first bias voltage input terminal VB1. The drain of the second bias transistor MVB2 is connected to the first stage I-channel positive filter input terminal VSP_I. The drain of the third bias transistor MVB3 is connected to the first stage I-channel negative filter input terminal VSN_I. The thirteenth capacitor C13 is connected between the first stage I-channel positive filter input terminal VSP_I and the first stage I-channel negative filter input terminal VSN_I. The thirteenth resistor R13 is connected between the first stage I-channel positive filter input terminal VSP_I and the gate of the eighteenth MOS transistor M18. The fourteenth resistor R14 is connected between the first stage I-channel negative filter input terminal VSN_I and the gate of the seventeenth MOS transistor M17. The drain of the seventeenth MOSFET M17 is connected to the positive filter input VSP_I of the first stage I, and the source of the seventeenth MOSFET M17 is connected to the positive filter output VOP_I1 of the first stage I; the drain of the eighteenth MOSFET M18 is connected to the negative filter input VSN_I of the first stage I, and the source of the eighteenth MOSFET M18 is connected to the negative filter output VON_I1 of the first stage I; the source and drain of the first PMOS transistor MP1 are both connected to the positive filter input VSP_I of the first stage I, and the gate of the first PMOS transistor MP1 is connected to the gate of the eighteenth MOSFET M18; the source and drain of the second PMOS transistor MP2 are both connected to the negative filter input VSN_I of the first stage I, and the... The gate of the second PMOS transistor MP2 is connected to the gate of the seventeenth MOS transistor M17; the fourteenth capacitor C14 is connected between the positive filter output terminal VOP_I1 and the negative filter output terminal VON_I1 of the first stage I; the drain of the fourth bias transistor MVB4 is connected to the positive filter output terminal VOP_I1 of the first stage I, the gate of the fourth bias transistor MVB4 is connected to the second bias voltage input terminal VB2, and the source of the fourth bias transistor MVB4 is connected to ground GND; the drain of the fifth bias transistor MVB5 is connected to the negative filter output terminal VON_I1 of the first stage I, the gate of the fifth bias transistor MVB5 is connected to the second bias voltage input terminal VB2, and the source of the fifth bias transistor MVB5 is connected to ground GND. The first-stage filter Q-path includes a first bias voltage input terminal VB1, a second bias voltage input terminal VB2, a first-stage Q-path positive filter input terminal VSP_Q, a first-stage Q-path negative filter input terminal VSN_Q, a first-stage Q-path positive filter output terminal VOP_Q1, a first-stage Q-path negative filter output terminal VON_Q1, a sixth bias transistor MVB6 to a ninth bias transistor MVB9, a nineteenth MOS transistor M19, a twentieth MOS transistor M20, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifteenth capacitor C15, a sixteenth capacitor C16, a fifteenth resistor R15, and a sixteenth resistor R16. The first-stage Q-path positive filter input terminal and the Q-path positive differential intermediate output terminal share the same node VSP_Q, and the first-stage Q-path negative filter input terminal and the Q-path negative differential intermediate output terminal share the same node VSN_Q. The sources of the sixth bias transistor MVB6 and the seventh bias transistor MVB7 are connected to the power supply voltage VDD. The gates of the sixth bias transistor MVB6 and the seventh bias transistor MVB7 are connected to the first bias voltage input terminal VB1. The drain of the sixth bias transistor MVB6 is connected to the positive filter input terminal VSP_Q of the first stage Q-path. The drain of the seventh bias transistor MVB7 is connected to the negative filter input terminal VSN_Q of the first stage Q-path. The fifteenth capacitor C15 is connected between the positive filter input terminal VSP_Q of the first stage Q-path and the negative filter input terminal VSN_Q of the first stage Q-path. The fifteenth resistor R15 is connected between the positive filter input terminal VSP_Q of the first stage Q-path and the gate of the twentieth MOSFET M20. The sixteenth resistor R16 is connected between the negative filter input terminal VSN_Q of the first stage Q-path and the gate of the nineteenth MOSFET M19. The drain of the nineteenth MOSFET M19 is connected to the positive input terminal VSP_Q of the first-stage Q-channel filter, and the source of the nineteenth MOSFET M19 is connected to the positive output terminal VOP_Q1 of the first-stage Q-channel filter; the drain of the twentieth MOSFET M20 is connected to the negative input terminal VSN_Q of the first-stage Q-channel filter, and the source of the twentieth MOSFET M20 is connected to the negative output terminal VON_Q1 of the first-stage Q-channel filter; the source and drain of the third PMOS transistor MP3 are both connected to the positive input terminal VSP_Q of the first-stage Q-channel filter, and the gate of the third PMOS transistor MP3 is connected to the gate of the twentieth MOSFET M20; the source and drain of the fourth PMOS transistor MP4 are both connected to the negative input terminal VSN_Q of the first-stage Q-channel filter, and the... The gate of the four PMOS transistors MP4 is connected to the gate of the nineteenth PMOS transistor M19; the sixteenth capacitor C16 is connected between the positive filter output terminal VOP_Q1 and the negative filter output terminal VON_Q1 of the first stage Q-path; the drain of the eighth bias transistor MVB8 is connected to the positive filter output terminal VOP_Q1 of the first stage Q-path, the gate of the eighth bias transistor MVB8 is connected to the second bias voltage input terminal VB2, and the source of the eighth bias transistor MVB8 is connected to ground GND; the drain of the ninth bias transistor MVB9 is connected to the negative filter output terminal VON_Q1 of the first stage Q-path, the gate of the ninth bias transistor MVB9 is connected to the second bias voltage input terminal VB2, and the source of the ninth bias transistor MVB9 is connected to ground GND.

[0011] Furthermore, the first-stage feedforward capacitor circuit includes a first feedforward capacitor CH1 to a fourth feedforward capacitor CH4 and a first MOS switch MC1 to a fourth MOS switch MC4; the first feedforward capacitor CH1 and the first MOS switch MC1 are connected in series between the positive input terminal IIP of the I-channel and the positive filter input terminal VSP_Q of the first-stage Q-channel; the second feedforward capacitor CH2 and the second MOS switch MC2 are connected in series between the negative input terminal IIN of the I-channel and the negative filter input terminal VSN_Q of the first-stage Q-channel; the third feedforward capacitor CH3 and the third MOS switch MC3 are connected in series between the positive input terminal IQP of the Q-channel and the negative filter input terminal VSN_I of the first-stage I-channel; the fourth feedforward capacitor CH4 and the fourth MOS switch MC4 are connected in series between the negative input terminal IQN of the Q-channel and the positive filter input terminal VSP_I of the first-stage I-channel; the gates of the first MOS switches MC1 to the fourth MOS switches MC4 are all connected to the switch control terminal.

[0012] Furthermore, the switch control terminal is the switch voltage input terminal CTRL; when the switch voltage input terminal CTRL is in the first level state, the first MOS switch MC1 to the fourth MOS switch MC4 are turned on, and the first feedforward capacitor CH1 to the fourth feedforward capacitor CH4 are connected to the corresponding cross feedforward path, so that the reconfigurable multiphase filter is in the multiphase filtering state; when the switch voltage input terminal CTRL is in the second level state, the first MOS switch MC1 to the fourth MOS switch MC4 are turned off, and the first feedforward capacitor CH1 to the fourth feedforward capacitor CH4 are disconnected from the corresponding cross feedforward path, so that the reconfigurable multiphase filter is in the low-pass filtering state.

[0013] Furthermore, the thirteenth resistor R13 and the fourteenth resistor R14 in the first-stage filter I path, and the fifteenth resistor R15 and the sixteenth resistor R16 in the first-stage filter Q path, are used to form a cross-coupled feedback path to adjust the quality factor of the first-stage multiphase filter circuit. The first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are used as equivalent capacitor units with their source and drain shorted, respectively. They are used to form equivalent negative capacitors between the gates of the corresponding MOS transistors in the seventeenth MOS transistor M17, the eighteenth MOS transistor M18, the nineteenth MOS transistor M19, or the twentieth MOS transistor M20, in order to compensate for the high-frequency zeros introduced by parasitic parameters.

[0014] Furthermore, the reconfigurable multiphase filter also includes a voltage buffer circuit and a second-stage multiphase filter circuit. The voltage buffer circuit is connected between the first-stage multiphase filter circuit and the second-stage multiphase filter circuit. It is used to buffer the I-channel differential signal output from the first-stage I-channel positive filter output terminal VOP_I1 and the first-stage I-channel negative filter output terminal VON_I1, as well as the Q-channel differential signal output from the first-stage Q-channel positive filter output terminal VOP_Q1 and the first-stage Q-channel negative filter output terminal VON_Q1. The buffered I-channel differential signal and Q-channel differential signal are then output to the second-stage multiphase filter circuit.

[0015] Further, the voltage buffer circuit includes a second bias voltage input terminal VB2, a buffer I path, and a buffer Q path; the voltage buffer circuit has a second-stage I-path positive input terminal VIP_I, a second-stage I-path negative input terminal VIN_I, a second-stage Q-path positive input terminal VIP_Q, and a second-stage Q-path negative input terminal VIN_Q for output to the second-stage multiphase filter circuit; the buffer I path includes a first buffer MOSFET MB1 to a fourth buffer MOSFET MB4, the drain of the first buffer MOSFET MB1 is connected to the power supply voltage VDD, the gate of the first buffer MOSFET MB1 is connected to the first-stage I-path positive filter output terminal VOP_I1, and the source of the first buffer MOSFET MB1 is connected to the second-stage I-path positive input terminal VIP_I; the second buffer M... The drain of the OS transistor MB2 is connected to the positive input terminal VIP_I of the second stage I channel; the gate of the second buffer MOSFET MB2 is connected to the second bias voltage input terminal VB2; and the source of the second buffer MOSFET MB2 is connected to ground GND. The drain of the third buffer MOSFET MB3 is connected to the power supply voltage VDD; the gate of the third buffer MOSFET MB3 is connected to the negative filter output terminal VON_I1 of the first stage I channel; and the source of the third buffer MOSFET MB3 is connected to the negative input terminal VIN_I of the second stage I channel. The drain of the fourth buffer MOSFET MB4 is connected to the negative input terminal VIN_I of the second stage I channel; the gate of the fourth buffer MOSFET MB4 is connected to the second bias voltage input terminal VB2; and the source of the fourth buffer MOSFET MB4 is connected to ground GND. The buffer Q-path includes the fifth buffer MOSFET MB5 to the eighth buffer MOSFET MB8. The drain of the fifth buffer MOSFET MB5 is connected to the power supply voltage VDD, the gate of the fifth buffer MOSFET MB5 is connected to the positive filter output terminal VOP_Q1 of the first stage Q-path, and the source of the fifth buffer MOSFET MB5 is connected to the positive input terminal VIP_Q of the second stage Q-path. The drain of the sixth buffer MOSFET MB6 is connected to the positive input terminal VIP_Q of the second stage Q-path, the gate of the sixth buffer MOSFET MB6 is connected to the second bias voltage input terminal VB2, and the source of the sixth buffer MOSFET MB6 is connected to ground GND. The drain of the seventh buffer MOSFET MB7 is connected to the power supply voltage VDD, the gate of the seventh buffer MOSFET MB7 is connected to the negative filter output terminal VON_Q1 of the first stage Q-path, and the source of the seventh buffer MOSFET MB7 is connected to the negative input terminal VIN_Q of the second stage Q-path. The drain of the eighth buffer MOSFET MB8 is connected to the negative input terminal VIN_Q of the second stage Q-path, the gate of the eighth buffer MOSFET MB8 is connected to the second bias voltage input terminal VB2, and the source of the eighth buffer MOSFET MB8 is connected to ground GND.

[0016] Furthermore, the second-stage multiphase filter circuit includes a second-stage filter I-path, a second-stage filter Q-path, and a second-stage feedforward capacitor circuit. The second-stage filter I-path receives the I-path differential signals at the positive input terminal VIP_I and the negative input terminal VIN_I of the second-stage I-path. The second-stage filter Q-path receives the Q-path differential signals at the positive input terminal VIP_Q and the negative input terminal VIN_Q of the second-stage Q-path. The second-stage filter I-path has a second-stage I-path positive filter node VSP_I2, a second-stage I-path negative filter node VSN_I2, a second-stage I-path positive filter output terminal VOP_I2, and a second-stage I-path negative filter output terminal VON_I2. The second-stage filter Q-path has a second-stage Q-path positive filter node VSP_Q2, a second-stage Q-path negative filter node VSN_Q2, and a second-stage Q-path positive filter output terminal VON_I2. The second-stage Q-path negative filter output terminal is VOP_Q2; both the second-stage filter I-path and the second-stage filter Q-path include a second-stage input-side bridging capacitor, a second-stage output-side bridging capacitor, a second-stage cross-coupling resistor, a second-stage output MOS transistor pair, and a second-stage PMOS equivalent capacitor unit; the second-stage input-side bridging capacitor is connected between the positive and negative filter nodes of the corresponding path, the second-stage output-side bridging capacitor is connected between the positive and negative filter output terminals of the corresponding path, the second-stage cross-coupling resistor is connected between the filter node of the corresponding path and the gate of the inverting output MOS transistor, the second-stage output MOS transistor pair is connected between the positive and negative filter nodes of the corresponding path and the positive and negative filter output terminals, and the second-stage PMOS equivalent capacitor unit is connected between the filter node of the corresponding path and the gate of the inverting output MOS transistor; The second-stage feedforward capacitor circuit includes the fifth feedforward capacitor CH5 to the eighth feedforward capacitor CH8 and the fifth MOS switch MC5 to the eighth MOS switch MC8. The fifth feedforward capacitor CH5 and the fifth MOS switch MC5 are connected in series between the positive input terminal VIP_I of the second-stage I-channel and the positive filter node VSP_Q2 of the second-stage Q-channel. The sixth feedforward capacitor CH6 and the sixth MOS switch MC6 are connected in series between the negative input terminal VIN_I of the second-stage I-channel and the negative filter node VSN_Q2 of the second-stage Q-channel. The seventh feedforward capacitor CH7 and the seventh MOS switch MC7 are connected in series between the positive input terminal VIP_Q of the second-stage Q-channel and the negative filter node VSN_I2 of the second-stage I-channel. The eighth feedforward capacitor CH8 and the eighth MOS switch MC8 are connected in series between the negative input terminal VIN_Q of the second-stage Q-channel and the positive filter node VSP_I2 of the second-stage I-channel. The gates of the fifth MOS switches MC5 to the eighth MOS switches MC8 are all connected to the switch control terminal.

[0017] The beneficial effects of this application include: This application provides a reconfigurable multiphase filter that incorporates a differential hybrid input stage circuit on the input side. The differential input signals (I and Q channels) are processed through a differential input coupling capacitor bank, a common-mode bias resistor bank, a differential MOS converter circuit, and a cross-coupled output circuit. This structure isolates the DC operating point of the preceding stage, stabilizes the internal common-mode bias, and improves the effective transconductance and voltage gain of the input stage. This reduces the impact of noise from subsequent circuits referred to the input, thereby improving the overall noise performance of the filter.

[0018] In a differential hybrid input stage circuit, different MOS branches can generate nonlinear components with different polarities. By appropriately setting the size, transconductance, bias current, and overdrive voltage of each MOS transistor, the third-order nonlinear components can compensate for each other, reducing third-order intermodulation distortion and improving the circuit's linearity and input dynamic range. Simultaneously, the corresponding structures and parameter configurations of the input stage I-path and input stage Q-path help reduce amplitude and phase errors in both I and Q paths.

[0019] This application controls the connection or disconnection of the feedforward capacitor branch via a switch control terminal, enabling the same filter to switch between multiphase filtering and low-pass filtering states. When the feedforward capacitor branch is connected, a cross-feedforward path is formed between the I and Q paths, and the phase relationship of orthogonal signals is used to suppress image signals; when the feedforward capacitor branch is disconnected, the I and Q paths perform low-pass filtering along their respective main signal paths. Therefore, the filtering state can be flexibly selected according to different receiving scenarios, eliminating the need for separate multiphase filters and low-pass filters.

[0020] When image suppression is not required, disconnecting the feedforward capacitor branch can prevent the feedforward capacitor and related filter nodes from repeated charging and discharging, and reduce the additional capacitive load on the filter nodes, thereby reducing the dynamic power consumption generated by the cross feedforward path, which is beneficial to reducing the overall energy consumption of the circuit.

[0021] This application also forms a feedback path through cross-coupling resistors to adjust the quality factor of the filter and improve the passband flatness; and forms an equivalent capacitance unit through PMOS transistors with source-drain shorting to compensate for or move the high-frequency zeros introduced by the parasitic capacitance of the MOS transistors to the high-frequency direction, thereby reducing the impact of parasitic zeros on the operating frequency band and improving the high-frequency stopband rejection capability.

[0022] A voltage buffer circuit is placed between the first-stage and second-stage multiphase filter circuits to isolate the load influence between the preceding and following stages, thereby improving the driving capability of the second-stage circuit. The first-stage and second-stage feedforward capacitor circuits can respectively form complex notch points located at different frequency positions. After the two-stage filter responses are cascaded, a high image rejection ratio can be maintained over a wide frequency range, thus extending the image rejection bandwidth.

[0023] Therefore, this application can balance low power consumption, high linearity, low noise, good passband flatness and stopband rejection, and can flexibly switch the filtering state according to the receiving scenario, making it suitable for quadrature signal filtering and image rejection in broadband receivers. Attached Figure Description

[0024] Figure 1 A schematic diagram of a reconfigurable polyphase filter provided in this application; Figure 2 The simulation results of the frequency response of a reconfigurable polyphase filter provided in this application are shown in the figure. Figure 3 The simulation results of the linearity of a reconfigurable multiphase filter provided in this application are shown in the figure. Figure 4 The simulation results of the noise figure of a reconfigurable polyphase filter provided in this application are shown in the figure. Detailed Implementation

[0025] like Figure 1As shown, this embodiment provides a reconfigurable polyphase filter, belonging to the field of radio frequency receiver technology. It can be used in cognitive radio, dynamic spectrum access, and other receivers requiring frequency selection and image suppression of orthogonal signals. The reconfigurable polyphase filter is used to receive I-channel differential input signals and Q-channel differential input signals. The I-channel differential input signals and Q-channel differential input signals have orthogonal phase relationships, and each differential input signal includes a positive phase input signal and a negative phase input signal. By using differential form for signal transmission and processing, the effective differential components can be extracted by utilizing the relative changes between the positive and negative phase signals, and common-mode interference superimposed on both positive and negative phases can be suppressed.

[0026] The reconfigurable multiphase filter includes a differential hybrid input stage circuit, a first-stage multiphase filter circuit, and a switching control terminal. In a further embodiment, the reconfigurable multiphase filter also includes a voltage buffer circuit and a second-stage multiphase filter circuit. The differential hybrid input stage circuit is located on the signal input side of the first-stage multiphase filter circuit, and is used to receive I-channel differential input signals and Q-channel differential input signals respectively, and to perform capacitive coupling, common-mode biasing, differential conversion, and cross-coupling output processing on the two differential input signals to form I-channel differential intermediate signals and Q-channel differential intermediate signals. The first-stage multiphase filter circuit receives the above-mentioned differential intermediate signals and forms a multiphase filter response or a low-pass filter response according to the access state of the cross-feedforward path.

[0027] The differential mixed input stage circuit includes an input stage I path for processing I-channel differential input signals and an input stage Q path for processing Q-channel differential input signals. The input stage I path and the input stage Q path employ corresponding circuit hierarchies to ensure that the two paths have similar gains, common-mode operating points, propagation delays, and frequency responses, thereby reducing amplitude and phase mismatches between the I and Q paths.

[0028] The input stage I-path includes a differential input coupling capacitor bank, a differential MOS conversion circuit, a cross-coupled output circuit, and a common-mode bias resistor bank. It also has a third bias voltage input terminal VB3, an I-channel positive input terminal IIP, an I-channel negative input terminal IIN, an I-channel first group of positive differential output nodes VOP_I, an I-channel first group of negative differential output nodes VON_I, an I-channel positive differential intermediate output terminal VSP_I, an I-channel negative differential intermediate output terminal VSN_I, a first common-mode voltage input terminal VCM1, a second common-mode voltage input terminal VCM2, and a third common-mode voltage input terminal VCM3.

[0029] The differential input coupling capacitor bank in the input stage I path includes capacitors C1 to C4; the differential MOS conversion circuit includes the zero bias transistor MVB0 and MOS transistors M1 to M4; the cross-coupled output circuit includes MOS transistors M5 to M8, capacitor C5, and capacitor C6; the common mode bias resistor bank includes resistors R1 to R6.

[0030] The first capacitor C1 is connected between the negative input terminal IIN and the gate of the first MOSFET M1, and the first resistor R1 is connected between the first common-mode voltage input terminal VCM1 and the gate of the first MOSFET M1. The second capacitor C2 is connected between the positive input terminal IIP and the gate of the second MOSFET M2, and the second resistor R2 is connected between the first common-mode voltage input terminal VCM1 and the gate of the second MOSFET M2. The first capacitor C1 and the second capacitor C2 couple the negative input signal and the positive input signal to the gates of the first MOSFET M1 and the second MOSFET M2, respectively, and isolate the DC operating point of the preceding signal source. The first resistor R1 and the second resistor R2 apply the common-mode voltage provided by the first common-mode voltage input terminal VCM1 to the gates of the first MOSFET M1 and the second MOSFET M2, so that the coupled differential signal is superimposed on the preset common-mode potential.

[0031] The source of the zero-bias transistor MVB0 is connected to the power supply voltage VDD, and its gate is connected to the third bias voltage input terminal VB3. The drain of MVB0 is connected to the source of the first MOSFET M1 and the source of the second MOSFET M2. Under the control of the third bias voltage input terminal VB3, the zero-bias transistor MVB0 provides bias current to the first MOSFET M1 and the second MOSFET M2. The drain of the first MOSFET M1 forms the first group of positive differential output nodes VOP_I, and the drain of the second MOSFET M2 forms the first group of negative differential output nodes VON_I.

[0032] The third capacitor C3 is connected between the positive input terminal IIP of channel I and the gate of the third MOSFET M3, and the third resistor R3 is connected between the second common-mode voltage input terminal VCM2 and the gate of the third MOSFET M3. The fourth capacitor C4 is connected between the negative input terminal IIN of channel I and the gate of the fourth MOSFET M4, and the fourth resistor R4 is connected between the second common-mode voltage input terminal VCM2 and the gate of the fourth MOSFET M4. The source of the third MOSFET M3 is connected to the first group of positive differential output nodes VOP_I of channel I, and the drain of the third MOSFET M3 is connected to ground GND. The source of the fourth MOSFET M4 is connected to the first group of negative differential output nodes VON_I of channel I, and the drain of the fourth MOSFET M4 is connected to ground GND.

[0033] Therefore, the positive input signal at the positive input terminal IIP of channel I acts on the second MOSFET M2 through the second capacitor C2 and on the third MOSFET M3 through the third capacitor C3; the negative input signal at the negative input terminal IIN of channel I acts on the first MOSFET M1 through the first capacitor C1 and on the fourth MOSFET M4 through the fourth capacitor C4. The upper differential branch formed by the first MOSFET M1 and the second MOSFET M2, together with the lower differential branch formed by the third MOSFET M3 and the fourth MOSFET M4, acts on the first group of positive differential output nodes VOP_I and the first group of negative differential output nodes VON_I of channel I.

[0034] The gate of the fifth MOSFET M5 is connected to the first negative differential output node VON_I of channel I, the source of the fifth MOSFET M5 is connected to the power supply voltage VDD, and the drain of the fifth MOSFET M5 is connected to the positive differential intermediate output terminal VSP_I of channel I. The gate of the sixth MOSFET M6 is connected to the first positive differential output node VOP_I of channel I, the source of the sixth MOSFET M6 is connected to the power supply voltage VDD, and the drain of the sixth MOSFET M6 is connected to the negative differential intermediate output terminal VSN_I of channel I. The gates of the fifth MOSFET M5 and the sixth MOSFET M6 are connected to the first group of differential output nodes with opposite phases, thus forming a cross-control relationship between positive and negative phases.

[0035] The fifth capacitor C5 is connected between the first group of positive differential output nodes VOP_I and the gate of the seventh MOSFET M7. The fifth resistor R5 is connected between the third common-mode voltage input terminal VCM3 and the gate of the seventh MOSFET M7. The source of the seventh MOSFET M7 is connected to the positive differential intermediate output terminal VSP_I of the I-channel, and the drain of the seventh MOSFET M7 is connected to ground GND. The sixth capacitor C6 is connected between the first group of negative differential output nodes VON_I and the gate of the eighth MOSFET M8. The sixth resistor R6 is connected between the third common-mode voltage input terminal VCM3 and the gate of the eighth MOSFET M8. The source of the eighth MOSFET M8 is connected to the negative differential intermediate output terminal VSN_I of the I-channel, and the drain of the eighth MOSFET M8 is connected to ground GND.

[0036] The fifth capacitor C5 and the sixth capacitor C6 couple the signals at the positive and negative differential output nodes of the first group of I-channel to the gates of the seventh MOSFET M7 and the eighth MOSFET M8, respectively; the fifth resistor R5 and the sixth resistor R6 provide the third common-mode voltage to the gates of the seventh MOSFET M7 and the eighth MOSFET M8, respectively. The fifth MOSFET M5 and the seventh MOSFET M7 work together to act on the positive differential intermediate output terminal VSP_I of I-channel, and the sixth MOSFET M6 and the eighth MOSFET M8 work together to act on the negative differential intermediate output terminal VSN_I of I-channel, so that the signals on the first group of differential output nodes form the I-channel differential intermediate signal after cross-control and capacitive coupling.

[0037] The resistance values ​​of the first resistor R1 to the sixth resistor R6 are equal, and the capacitance values ​​of the first capacitor C1 to the sixth capacitor C6 are equal.

[0038] The above parameter matching relationship helps to ensure that the positive and negative phase branches have consistent bias and capacitive coupling characteristics, and reduces the gain error and phase error between the positive and negative phases.

[0039] The input stage Q-path includes a differential input coupling capacitor bank, a differential MOS conversion circuit, a cross-coupled output circuit, and a common-mode bias resistor bank. It also has a third bias voltage input terminal VB3, a Q-path positive input terminal IQP, a Q-path negative input terminal IQN, a Q-path first group of positive differential output nodes VOP_Q, a Q-path first group of negative differential output nodes VON_Q, a Q-path positive differential intermediate output terminal VSP_Q, a Q-path negative differential intermediate output terminal VSN_Q, a first common-mode voltage input terminal VCM1, a second common-mode voltage input terminal VCM2, and a third common-mode voltage input terminal VCM3.

[0040] The differential input coupling capacitor bank in the input stage Q path includes capacitors C7 to C10 (seventh capacitor); the differential MOS conversion circuit includes transistor MVB1 (first bias transistor) and transistors M9 to M12 (ninth MOS transistor); the cross-coupled output circuit includes transistors M13 to M16 (thirteenth MOS transistor), capacitor C11 (eleventh capacitor), and capacitor C12 (twelfth capacitor); the common-mode bias resistor bank includes resistors R7 to R12 (seventh resistor).

[0041] The seventh capacitor C7 is connected between the negative input terminal IQN of the Q-path and the gate of the ninth MOSFET M9, and the seventh resistor R7 is connected between the first common-mode voltage input terminal VCM1 and the gate of the ninth MOSFET M9; the eighth capacitor C8 is connected between the positive input terminal IQP of the Q-path and the gate of the tenth MOSFET M10, and the eighth resistor R8 is connected between the first common-mode voltage input terminal VCM1 and the gate of the tenth MOSFET M10; the ninth capacitor C9 is connected between the positive input terminal IQP of the Q-path and the gate of the eleventh MOSFET M11, and the ninth resistor R9 is connected between the second common-mode voltage input terminal VCM2 and the gate of the eleventh MOSFET M11; the tenth capacitor C10 is connected between the negative input terminal IQN of the Q-path and the gate of the twelfth MOSFET M12, and the tenth resistor R10 is connected between the second common-mode voltage input terminal VCM2 and the gate of the twelfth MOSFET M12.

[0042] The source of the first bias transistor MVB1 is connected to the power supply voltage VDD, the gate of the first bias transistor MVB1 is connected to the third bias voltage input terminal VB3, and the drain of the first bias transistor MVB1 is connected to the source of the ninth MOSFET M9 and the source of the tenth MOSFET M10.

[0043] The drain of the ninth MOSFET M9 forms the first positive differential output node VOP_Q of the Q-path, and the drain of the tenth MOSFET M10 forms the first negative differential output node VON_Q of the Q-path; the source of the eleventh MOSFET M11 is connected to the first positive differential output node VOP_Q of the Q-path, and the drain of the eleventh MOSFET M11 is connected to ground GND; the source of the twelfth MOSFET M12 is connected to the first negative differential output node VON_Q of the Q-path, and the drain of the twelfth MOSFET M12 is connected to ground GND.

[0044] The gate of the thirteenth MOSFET M13 is connected to the first negative differential output node VON_Q of the Q-path; the source of the thirteenth MOSFET M13 is connected to the power supply voltage VDD; and the drain of the thirteenth MOSFET M13 is connected to the positive differential intermediate output terminal VSP_Q of the Q-path. The gate of the fourteenth MOSFET M14 is connected to the first positive differential output node VOP_Q of the Q-path; the source of the fourteenth MOSFET M14 is connected to the power supply voltage VDD; and the drain of the fourteenth MOSFET M14 is connected to the negative differential intermediate output terminal VSN_Q of the Q-path.

[0045] The eleventh capacitor C11 is connected between the first group of positive differential output nodes VOP_Q of the Q-path and the gate of the fifteenth MOSFET M15. The eleventh resistor R11 is connected between the third common-mode voltage input terminal VCM3 and the gate of the fifteenth MOSFET M15. The source of the fifteenth MOSFET M15 is connected to the positive differential intermediate output terminal VSP_Q of the Q-path, and the drain of the fifteenth MOSFET M15 is connected to ground GND. The twelfth capacitor C12 is connected between the first group of negative differential output nodes VON_Q of the Q-path and the gate of the sixteenth MOSFET M16. The twelfth resistor R12 is connected between the third common-mode voltage input terminal VCM3 and the gate of the sixteenth MOSFET M16. The source of the sixteenth MOSFET M16 is connected to the negative differential intermediate output terminal VSN_Q of the Q-path, and the drain of the sixteenth MOSFET M16 is connected to ground GND.

[0046] The resistance values ​​of the seventh resistor R7 to the twelfth resistor R12 are equal, and the capacitance values ​​of the seventh capacitor C7 to the twelfth capacitor C12 are equal. By employing corresponding device numbers, connection levels, and parameter matching relationships between the input stage Q path and the input stage I path, the I-path differential intermediate signal and the Q-path differential intermediate signal can have similar gains, common-mode voltages, and transmission phases.

[0047] For the above differential hybrid input stage circuit, its small-signal voltage gain can be approximated as:

[0048] In the formula, g m1 The transconductance values ​​are those of the third MOSFET M3 and the fourth MOSFET M4. g m2Here are the transconductance values ​​of the first MOSFET M1 and the second MOSFET M2. g ds1 The output conductance values ​​of the third MOSFET M3 and the fourth MOSFET M4 are... g ds2 The output conductance values ​​of the first MOSFET M1 and the second MOSFET M2; g m3 The transconductance values ​​are those of the seventh MOSFET M7 and the eighth MOSFET M8. g m4 The transconductance values ​​are those of the fifth MOSFET M5 and the sixth MOSFET M6. g ds3 The output conductance values ​​of the seventh MOSFET M7 and the eighth MOSFET M8 are... g ds4 The output conductance values ​​of the fifth MOSFET M5 and the sixth MOSFET M6; R NB1 and R NB2 These are the small-signal equivalent impedances of the corresponding differential hybrid nodes.

[0049] As can be seen from the above gain relationship, the differential hybrid input stage circuit utilizes the hybrid differential branching of the preceding and following stages to achieve a signal amplification capability greater than unity gain. With the increased input stage voltage gain, the noise generated by the subsequent filter and buffer circuits, when referred to the input terminal, contributes less to the overall equivalent input noise of the system, thus improving overall noise performance.

[0050] The third-order nonlinear term of the small-signal current at the output of the differential mixed-input stage circuit can be expressed as:

[0051] In the formula, V ov1 The overdrive voltages of the third MOSFET M3 and the fourth MOSFET M4 are... V ov2 The overdrive voltages of the first MOSFET M1 and the second MOSFET M2 are... V in The input differential voltage is used. The inverted signal generated by the branch containing the third MOSFET M3 and the fourth MOSFET M4 is superimposed on the in-phase signal generated by the branch containing the first MOSFET M1 and the second MOSFET M2. Since the third-order nonlinear coefficients of the two types of transistor configurations have opposite polarities, the two terms in the parentheses of the above formula can be made to cancel each other out or approach mutual cancellation by selecting the corresponding transistor size, bias current, transconductance, and overdrive voltage. Furthermore, by reducing the transconductance ratio... g m2 / g m1This allows the third derivative of the total output current to approach zero over a wider input dynamic range, thereby suppressing third-order intermodulation distortion and improving linearity.

[0052] The first-stage multiphase filter circuit includes a first-stage filter I-path, a first-stage filter Q-path, and a first-stage feedforward capacitor circuit. The first-stage I-path positive filter input and the I-path positive differential intermediate output share node VSP_I, and the first-stage I-path negative filter input and the I-path negative differential intermediate output share node VSN_I. The first-stage Q-path positive filter input and the Q-path positive differential intermediate output share node VSP_Q, and the first-stage Q-path negative filter input and the Q-path negative differential intermediate output share node VSN_Q.

[0053] The first-stage filter I-path includes the first bias voltage input terminal VB1, the second bias voltage input terminal VB2, the first-stage I-path positive filter input terminal VSP_I, the first-stage I-path negative filter input terminal VSN_I, the first-stage I-path positive filter output terminal VOP_I1, the first-stage I-path negative filter output terminal VON_I1, the second bias transistors MVB2 to MVB5, the seventeenth MOSFET M17, the eighteenth MOSFET M18, the first PMOS transistor MP1, the second PMOS transistor MP2, the thirteenth capacitor C13, the fourteenth capacitor C14, the thirteenth resistor R13, and the fourteenth resistor R14.

[0054] The sources of the second bias transistor MVB2 and the third bias transistor MVB3 are connected to the power supply voltage VDD, and their gates are connected to the first bias voltage input terminal VB1. The drain of the second bias transistor MVB2 is connected to the positive filter input terminal VSP_I of the first stage I, and the drain of the third bias transistor MVB3 is connected to the negative filter input terminal VSN_I of the first stage I. The second bias transistor MVB2 and the third bias transistor MVB3 provide upper bias current to the positive and negative filter input nodes, respectively.

[0055] The thirteenth capacitor C13 is connected between the positive filter input terminal VSP_I and the negative filter input terminal VSN_I of the first stage I channel to establish a differential energy storage path between the positive and negative filter input nodes. The thirteenth resistor R13 is connected between the positive filter input terminal VSP_I of the first stage I channel and the gate of the eighteenth MOSFET M18, and the fourteenth resistor R14 is connected between the negative filter input terminal VSN_I of the first stage I channel and the gate of the seventeenth MOSFET M17, thereby forming a cross-coupled feedback path.

[0056] The drain of the seventeenth MOSFET M17 is connected to the positive input terminal VSP_I of the first stage I-channel filter, and the source of the seventeenth MOSFET M17 is connected to the positive output terminal VOP_I1 of the first stage I-channel filter; the drain of the eighteenth MOSFET M18 is connected to the negative input terminal VSN_I of the first stage I-channel filter, and the source of the eighteenth MOSFET M18 is connected to the negative output terminal VON_I1 of the first stage I-channel filter.

[0057] The source and drain of the first PMOS transistor MP1 are both connected to the positive filter input terminal VSP_I of the first stage I, and the gate of the first PMOS transistor MP1 is connected to the gate of the eighteenth MOS transistor M18. The source and drain of the second PMOS transistor MP2 are both connected to the negative filter input terminal VSN_I of the first stage I, and the gate of the second PMOS transistor MP2 is connected to the gate of the seventeenth MOS transistor M17. The first PMOS transistor MP1 and the second PMOS transistor MP2 are connected with their source and drain shorted, so that they mainly exhibit the capacitance characteristics between the gate and the source-drain shorted terminal, and form an equivalent negative capacitance between the corresponding filter input node and the gate of the inverting output MOS transistor.

[0058] The fourteenth capacitor C14 is connected across the positive filter output terminal VOP_I1 and the negative filter output terminal VON_I1 of the first stage I-channel to establish a differential energy storage path between the positive and negative filter output terminals. The drain of the fourth bias transistor MVB4 is connected to the positive filter output terminal VOP_I1 of the first stage I-channel, the gate of the fourth bias transistor MVB4 is connected to the second bias voltage input terminal VB2, and the source of the fourth bias transistor MVB4 is connected to ground GND. The drain of the fifth bias transistor MVB5 is connected to the negative filter output terminal VON_I1 of the first stage I-channel, the gate of the fifth bias transistor MVB5 is connected to the second bias voltage input terminal VB2, and the source of the fifth bias transistor MVB5 is connected to ground GND.

[0059] The first-stage filter Q-path and the first-stage filter I-path adopt a corresponding structure. The first-stage filter Q-path includes the first bias voltage input terminal VB1, the second bias voltage input terminal VB2, the first-stage Q-path positive filter input terminal VSP_Q, the first-stage Q-path negative filter input terminal VSN_Q, the first-stage Q-path positive filter output terminal VOP_Q1, the first-stage Q-path negative filter output terminal VON_Q1, the sixth bias transistor MVB6 to the ninth bias transistor MVB9, the nineteenth MOSFET M19, the twentieth MOSFET M20, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifteenth capacitor C15, the sixteenth capacitor C16, the fifteenth resistor R15, and the sixteenth resistor R16.

[0060] The sources of the sixth bias transistor MVB6 and the seventh bias transistor MVB7 are connected to the power supply voltage VDD, and their gates are connected to the first bias voltage input terminal VB1. The drain of the sixth bias transistor MVB6 is connected to the positive Q-channel filter input terminal VSP_Q of the first stage, and the drain of the seventh bias transistor MVB7 is connected to the negative Q-channel filter input terminal VSN_Q of the first stage. The fifteenth capacitor C15 is connected between the positive Q-channel filter input terminal VSP_Q and the negative Q-channel filter input terminal VSN_Q of the first stage.

[0061] The fifteenth resistor R15 is connected between the positive input terminal VSP_Q of the first-stage Q-channel filter and the gate of the twentieth MOSFET M20. The sixteenth resistor R16 is connected between the negative input terminal VSN_Q of the first-stage Q-channel filter and the gate of the nineteenth MOSFET M19. The drain of the nineteenth MOSFET M19 is connected to the positive input terminal VSP_Q of the first-stage Q-channel filter, and the source of the nineteenth MOSFET M19 is connected to the positive output terminal VOP_Q1 of the first-stage Q-channel filter. The drain of the twentieth MOSFET M20 is connected to the negative input terminal VSN_Q of the first-stage Q-channel filter, and the source of the twentieth MOSFET M20 is connected to the negative output terminal VON_Q1 of the first-stage Q-channel filter.

[0062] The source and drain of the third PMOS transistor MP3 are both connected to the positive input terminal VSP_Q of the first-stage Q-channel filter, and the gate of the third PMOS transistor MP3 is connected to the gate of the twentieth MOS transistor M20. The source and drain of the fourth PMOS transistor MP4 are both connected to the negative input terminal VSN_Q of the first-stage Q-channel filter, and the gate of the fourth PMOS transistor MP4 is connected to the gate of the nineteenth MOS transistor M19. The sixteenth capacitor C16 is connected between the positive output terminal VOP_Q1 of the first-stage Q-channel filter and the negative output terminal VON_Q1 of the first-stage Q-channel filter.

[0063] The drain of the eighth bias transistor MVB8 is connected to the positive filter output terminal VOP_Q1 of the first stage Q-channel, the gate of the eighth bias transistor MVB8 is connected to the second bias voltage input terminal VB2, and the source of the eighth bias transistor MVB8 is connected to ground GND; the drain of the ninth bias transistor MVB9 is connected to the negative filter output terminal VON_Q1 of the first stage Q-channel, the gate of the ninth bias transistor MVB9 is connected to the second bias voltage input terminal VB2, and the source of the ninth bias transistor MVB9 is connected to ground GND.

[0064] Resistors R13 (13th) and R14 (14th) form a cross-coupled feedback path for the first-stage filter I path, and resistors R15 (15th) and R16 (16th) form a cross-coupled feedback path for the first-stage filter Q path. By selecting the values ​​of these cross-coupled resistors, the amplitude of the feedback signal and the quality factor of the first-stage multiphase filter circuit can be adjusted. PMOS transistors MP1 through MP4 form an equivalent capacitance unit to compensate for the high-frequency zeros introduced by the parasitic capacitances of PMOS transistors M17 through M20, thereby improving the stopband attenuation characteristics.

[0065] The first-stage feedforward capacitor circuit includes first feedforward capacitor CH1 to fourth feedforward capacitor CH4 and first MOS switch MC1 to fourth MOS switch MC4.

[0066] One end of the first feedforward capacitor CH1 is connected to the positive input terminal IIP of the I-channel, and the other end is connected to the drain of the first MOS switch MC1. The source of the first MOS switch MC1 is connected to the positive input terminal VSP_Q of the first stage Q-channel, and the gate of the first MOS switch MC1 is connected to the switching voltage input terminal CTRL. One end of the second feedforward capacitor CH2 is connected to the negative input terminal IIN of the I-channel, and the other end is connected to the drain of the second MOS switch MC2. The source of the second MOS switch MC2 is connected to the negative input terminal VSN_Q of the first stage Q-channel, and the gate of the second MOS switch MC2 is connected to the switching voltage input terminal CTRL.

[0067] One end of the third feedforward capacitor CH3 is connected to the positive input terminal IQP of the Q-channel, and the other end is connected to the source of the third MOS switch MC3. The drain of the third MOS switch MC3 is connected to the negative filter input terminal VSN_I of the first stage I-channel, and the gate of the third MOS switch MC3 is connected to the switch voltage input terminal CTRL.

[0068] One end of the fourth feedforward capacitor CH4 is connected to the negative input terminal IQN of the Q-channel, and the other end is connected to the source of the fourth MOS switch MC4. The drain of the fourth MOS switch MC4 is connected to the positive input terminal VSP_I of the first stage I-channel filter, and the gate of the fourth MOS switch MC4 is connected to the switching voltage input terminal CTRL.

[0069] When the switching voltage input terminal CTRL is in the first level state, the first MOS switch MC1 to the fourth MOS switch MC4 are turned on, and the first feedforward capacitor CH1 to the fourth feedforward capacitor CH4 are connected to the corresponding cross feedforward paths. The feedforward components of the I-channel differential input signal enter the first-stage filter Q-path respectively, and the feedforward components of the Q-channel differential input signal enter the first-stage filter I-path according to the cross phase relationship, so that the first-stage filter I-path and the first-stage filter Q-path form a multiphase filter response.

[0070] When the switching voltage input terminal CTRL is in the second level state, the first MOS switch MC1 to the fourth MOS switch MC4 are turned off, the first feedforward capacitor CH1 to the fourth feedforward capacitor CH4 are disconnected from the corresponding cross feedforward path, and the first-stage filter I path and the first-stage filter Q path are low-pass filtered along their respective main signal paths, so that the reconfigurable multiphase filter is in the low-pass filtering state.

[0071] By controlling the CTRL switch voltage input terminal, the first-stage and second-stage feedforward capacitor circuits can be selectively connected or disconnected according to the actual receiving scenario. When there is strong image interference in the received signal or when image suppression performance is required to be high, the CTRL switch voltage input terminal controls the MOS switches to turn on, so that the corresponding feedforward capacitors are connected to the cross-feedforward path between the I and Q paths. The reconfigurable multiphase filter operates in multiphase filtering mode to improve image suppression capability by utilizing the phase relationship between orthogonal signals. When the image interference is weak or there is no need to form a complex notch response, the CTRL switch voltage input terminal controls the MOS switches to turn off, so that the feedforward capacitors are disconnected from the corresponding cross-feedforward paths. The reconfigurable multiphase filter operates in low-pass filtering mode. At this time, the I and Q signals are filtered along their respective main signal paths. The feedforward capacitors no longer charge and discharge repeatedly with changes in the input signal. The corresponding filtering nodes do not need to drive the additional capacitive load formed by the cross-feedforward branches, thereby reducing the charging and discharging current in the feedforward branches and the dynamic power consumption generated by the periodic charging and discharging of the feedforward capacitors and related filtering nodes, and helping to reduce the overall power consumption of the reconfigurable multiphase filter.

[0072] Specifically, in integrated circuits, the dynamic power consumption of capacitive nodes is typically related to the node's equivalent capacitance, signal swing, and operating frequency. When a feedforward capacitor branch is connected, the input signal needs to periodically charge and discharge the feedforward capacitor and the filter node connected to it, thus generating additional dynamic current. When the feedforward capacitor branch is disconnected, this part of the capacitor no longer participates in the signal transmission between the I and Q paths, the equivalent load of the filter node decreases, and the charging and discharging current required by the main signal path decreases accordingly. Therefore, switching to low-pass filtering in operating scenarios where image rejection is not required can avoid the additional dynamic power consumption generated by continuously maintaining the cross-feedforward response.

[0073] By introducing the first feedforward capacitor CH1 to the fourth feedforward capacitor CH4, the first-stage multiphase filter circuit forms the first-stage complex notch point. The equivalent capacitance of each feedforward capacitor is... C H At that time, the equivalent transconductance value of the first-stage feedforward path is g mf1 The first-order complex notch point satisfies:

[0074] By changing the capacitance values ​​of the first feedforward capacitor CH1 to the fourth feedforward capacitor CH4 C H The first-level complex notch point can be adjusted independently. ω p1 Furthermore, it does not change the main low-pass pole structure, and has little impact on the passband gain and cutoff frequency.

[0075] The following example illustrates the frequency characteristics of the first-stage filter I path, using the transmission relationship from the input terminal VSP_I of the first-stage I-path positive filter to the output terminal VOP_I1 of the first-stage I-path positive filter.

[0076] The transfer function of the first-stage filter I path can be expressed as:

[0077] In the formula, g m5 The transconductance values ​​are those of the seventeenth MOSFET M17 and the eighteenth MOSFET M18. C gs1 These are the gate-source parasitic capacitance values ​​for the seventeenth MOSFET M17 and the eighteenth MOSFET M18. C gd1 These are the gate-drain parasitic capacitance values ​​for the seventeenth MOSFET M17 and the eighteenth MOSFET M18. C 14 This refers to the capacitance value of the fourteenth capacitor, C14. r 1 represents the resistance values ​​of the thirteenth resistor R13 and the fourteenth resistor R14. C 01 This is the equivalent capacitance value formed by the first PMOS transistor MP1 and the second PMOS transistor MP2.

[0078] Based on the transfer function described above, the first-stage filter I path generates one left-half-plane zero and one right-half-plane zero, and their relationship can be expressed as:

[0079]

[0080] Zero point of left half plane z 0 increases the gain slope of the amplitude-frequency response by 20 dB / dec. Right half-plane zero. z 1. This also increases the gain slope of the amplitude-frequency response by 20 dB / dec. C 01 Less than C gd1 Under these conditions, with the equivalent capacitance value C 01 Increase, difference C gd1 - C01 Decrease, zero point of the right half-plane z 1. Moving it towards higher frequencies (pushing it to the right) can reduce the impact of this zero point on the operating frequency band and adjacent stopbands, thereby enhancing the high-frequency stopband suppression capability.

[0081] The low-pass cutoff angular frequency of the dual second-order filter formed by the first-stage filter I path. ω 0 and quality factor Q 0 can be approximated as:

[0082] Low-pass cutoff angular frequency ω 0 is used to characterize the bandwidth range of the first-stage bisecond-order filter; quality factor. Q 0 is used to characterize the peak response and selectivity near the cutoff frequency. With other parameters fixed, the values ​​of the thirteenth resistor R13 and the fourteenth resistor R14 are varied. r 1. Adjustable quality factor Q 0, thereby improving the passband flatness. The first-stage filter Q-path adopts the corresponding structure and has the corresponding transfer relationship.

[0083] To reduce the interstage load effect caused by the first-stage multiphase filter circuit directly driving the second-stage multiphase filter circuit, a voltage buffer circuit is set between the first-stage and second-stage multiphase filter circuits. The voltage buffer circuit receives the I-channel differential signals output from the first-stage I-channel positive filter output terminal VOP_I1 and the first-stage I-channel negative filter output terminal VON_I1, as well as the Q-channel differential signals output from the first-stage Q-channel positive filter output terminal VOP_Q1 and the first-stage Q-channel negative filter output terminal VON_Q1, and outputs the buffered signals to the second-stage multiphase filter circuit.

[0084] The voltage buffer circuit includes a buffer I path and a buffer Q path, and has a second-stage I positive input terminal VIP_I, a second-stage I negative input terminal VIN_I, a second-stage Q positive input terminal VIP_Q, and a second-stage Q negative input terminal VIN_Q.

[0085] The buffer I-path includes first buffer MOSFETs MB1 to fourth buffer MOSFETs MB4. The drain of the first buffer MOSFET MB1 is connected to the power supply voltage VDD, the gate is connected to the positive filter output terminal VOP_I1 of the first stage I-path, and the source is connected to the positive input terminal VIP_I of the second stage I-path. The drain of the second buffer MOSFET MB2 is connected to the positive input terminal VIP_I of the second stage I-path, the gate is connected to the second bias voltage input terminal VB2, and the source is connected to ground GND. The drain of the third buffer MOSFET MB3 is connected to the power supply voltage VDD, the gate is connected to the negative filter output terminal VON_I1 of the first stage I-path, and the source is connected to the negative input terminal VIN_I of the second stage I-path. The drain of the fourth buffer MOSFET MB4 is connected to the negative input terminal VIN_I of the second stage I-path, the gate is connected to the second bias voltage input terminal VB2, and the source is connected to ground GND.

[0086] The buffer Q path includes the fifth buffer MOSFET MB5 to the eighth buffer MOSFET MB8. The drain of the fifth buffer MOSFET MB5 is connected to the power supply voltage VDD, the gate of the fifth buffer MOSFET MB5 is connected to the positive filter output terminal VOP_Q1 of the first stage Q path, and the source of the fifth buffer MOSFET MB5 is connected to the positive input terminal VIP_Q of the second stage Q path.

[0087] The drain of the sixth buffer MOSFET MB6 is connected to the positive input terminal VIP_Q of the second stage Q-channel, the gate of the sixth buffer MOSFET MB6 is connected to the second bias voltage input terminal VB2, and the source of the sixth buffer MOSFET MB6 is connected to ground GND; the drain of the seventh buffer MOSFET MB7 is connected to the power supply voltage VDD, the gate of the seventh buffer MOSFET MB7 is connected to the negative filter output terminal VON_Q1 of the first stage Q-channel, and the source of the seventh buffer MOSFET MB7 is connected to the negative input terminal VIN_Q of the second stage Q-channel; the drain of the eighth buffer MOSFET MB8 is connected to the negative input terminal VIN_Q of the second stage Q-channel, the gate of the eighth buffer MOSFET MB8 is connected to the second bias voltage input terminal VB2, and the source of the eighth buffer MOSFET MB8 is connected to ground GND.

[0088] The first buffer MOSFET MB1, the third buffer MOSFET MB3, the fifth buffer MOSFET MB5, and the seventh buffer MOSFET MB7 receive the positive and negative differential signals output from the first-stage multiphase filter circuit in source-follower mode, respectively. The second buffer MOSFET MB2, the fourth buffer MOSFET MB4, the sixth buffer MOSFET MB6, and the eighth buffer MOSFET MB8 provide bias current under the control of the second bias voltage input terminal VB2. The voltage buffer circuit has a high input impedance, which reduces the signal current drawn from the output terminal of the first-stage filter; at the same time, it has a low output impedance, which improves the driving capability of the second-stage multiphase filter circuit. The voltage gain of the voltage buffer circuit is close to 1, which can reduce the influence of the second-stage load on the pole location and quality factor of the first stage while basically maintaining the signal amplitude.

[0089] The second-stage multiphase filter circuit includes a second-stage filter I-path, a second-stage filter Q-path, and a second-stage feedforward capacitor circuit. The second-stage filter I-path receives the I-path differential signals from the positive input terminal VIP_I and the negative input terminal VIN_I of the second-stage I-path, and has a second-stage positive filter node VSP_I2, a second-stage negative filter node VSN_I2, a second-stage positive filter output terminal VOP_I2, and a second-stage negative filter output terminal VON_I2. The second-stage filter Q-path receives the Q-path differential signals from the positive input terminal VIP_Q and the negative input terminal VIN_Q of the second-stage Q-path, and has a second-stage positive filter node VSP_Q2, a second-stage negative filter node VSN_Q2, a second-stage positive filter output terminal VOP_Q2, and a second-stage negative filter output terminal VON_Q2.

[0090] The second-stage filter I path includes the twenty-first MOSFET M21 to the twenty-fourth MOSFET M24, the tenth bias transistor MVB10 to the fifteenth bias transistor MVB15, the fifth PMOS transistor MP5, the sixth PMOS transistor MP6, the seventeenth capacitor C17, the eighteenth capacitor C18, the seventeenth resistor R17, and the eighteenth resistor R18.

[0091] The gate of the 21st MOSFET M21 is connected to the positive input terminal VIP_I of the second stage I channel, the drain of the 21st MOSFET M21 is connected to ground GND, and the source of the 21st MOSFET M21 is connected to the positive filter node VSP_I2 of the second stage I channel; the gate of the 22nd MOSFET M22 is connected to the negative input terminal VIN_I of the second stage I channel, the drain of the 22nd MOSFET M22 is connected to ground GND, and the source of the 22nd MOSFET M22 is connected to the negative filter node VSN_I2 of the second stage I channel.

[0092] The sources of the tenth bias transistor MVB10 and the twelfth bias transistor MVB12 are connected to the power supply voltage VDD, their gates are connected to the first bias voltage input terminal VB1, and their drains are connected to the second-stage I-path positive filter node VSP_I2. The sources of the eleventh bias transistor MVB11 and the thirteenth bias transistor MVB13 are connected to the power supply voltage VDD, their gates are connected to the first bias voltage input terminal VB1, and their drains are connected to the second-stage I-path negative filter node VSN_I2. These bias transistors, together with the twenty-first MOSFET M21 and the twenty-second MOSFET M22, establish the DC operating points of the second-stage I-path positive and negative filter nodes.

[0093] The seventeenth capacitor, C17, is connected between the second-stage I-path positive filter node VSP_I2 and the second-stage I-path negative filter node VSN_I2. The seventeenth resistor, R17, is connected between the second-stage I-path positive filter node VSP_I2 and the gate of the twenty-fourth MOSFET, M24. The eighteenth resistor, R18, is connected between the second-stage I-path negative filter node VSN_I2 and the gate of the twenty-third MOSFET, M23. The source and drain of the fifth PMOS transistor, MP5, are both connected to the second-stage I-path positive filter node VSP_I2, and its gate is connected to the gate of the twenty-fourth MOSFET, M24. The source and drain of the sixth PMOS transistor, MP6, are both connected to the second-stage I-path negative filter node VSN_I2, and its gate is connected to the gate of the twenty-third MOSFET, M23.

[0094] The drain of the 23rd MOSFET M23 is connected to the positive filter node VSP_I2 of the second-stage I-path, and the source of the 23rd MOSFET M23 is connected to the positive filter output terminal VOP_I2 of the second-stage I-path. The drain of the 24th MOSFET M24 is connected to the negative filter node VSN_I2 of the second-stage I-path, and the source of the 24th MOSFET M24 is connected to the negative filter output terminal VON_I2 of the second-stage I-path. The 18th capacitor C18 is connected between the positive filter output terminal VOP_I2 and the negative filter output terminal VON_I2 of the second-stage I-path.

[0095] The drain of the fourteenth bias transistor MVB14 is connected to the positive filter output terminal VOP_I2 of the second stage I, the gate of the fourteenth bias transistor MVB14 is connected to the second bias voltage input terminal VB2, and the source of the fourteenth bias transistor MVB14 is connected to ground GND; the drain of the fifteenth bias transistor MVB15 is connected to the negative filter output terminal VON_I2 of the second stage I, the gate of the fifteenth bias transistor MVB15 is connected to the second bias voltage input terminal VB2, and the source of the fifteenth bias transistor MVB15 is connected to ground GND.

[0096] The second-stage filter Q-path includes the twenty-fifth MOSFET M25 to the twenty-eighth MOSFET M28, the sixteenth bias transistor MVB16 to the twenty-first bias transistor MVB21, the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, the nineteenth capacitor C19, the twentieth capacitor C20, the nineteenth resistor R19, and the twentieth resistor R20.

[0097] The gate of the 25th MOSFET M25 is connected to the positive input terminal VIP_Q of the second-stage Q-path, the drain of the 25th MOSFET M25 is connected to ground GND, and the source of the 25th MOSFET M25 is connected to the positive filter node VSP_Q2 of the second-stage Q-path; the gate of the 26th MOSFET M26 is connected to the negative input terminal VIN_Q of the second-stage Q-path, the drain of the 26th MOSFET M26 is connected to ground GND, and the source of the 26th MOSFET M26 is connected to the negative filter node VSN_Q2 of the second-stage Q-path.

[0098] The sources of the sixteenth bias transistor MVB16 and the eighteenth bias transistor MVB18 are connected to the power supply voltage VDD, their gates are connected to the first bias voltage input terminal VB1, and their drains are connected to the second-stage Q-path positive filter node VSP_Q2. The sources of the seventeenth bias transistor MVB17 and the nineteenth bias transistor MVB19 are connected to the power supply voltage VDD, their gates are connected to the first bias voltage input terminal VB1, and their drains are connected to the second-stage Q-path negative filter node VSN_Q2. The nineteenth capacitor C19 is connected across the second-stage Q-path positive filter node VSP_Q2 and the second-stage Q-path negative filter node VSN_Q2.

[0099] The nineteenth resistor R19 is connected between the positive filter node VSP_Q2 of the second-stage Q-path and the gate of the twenty-eighth MOSFET M28. The twentieth resistor R20 is connected between the negative filter node VSN_Q2 of the second-stage Q-path and the gate of the twenty-seventh MOSFET M27. The source and drain of the seventh PMOS transistor MP7 are both connected to the positive filter node VSP_Q2 of the second-stage Q-path, and the gate of the seventh PMOS transistor MP7 is connected to the gate of the twenty-eighth MOSFET M28. The source and drain of the eighth PMOS transistor MP8 are both connected to the negative filter node VSN_Q2 of the second-stage Q-path, and the gate of the eighth PMOS transistor MP8 is connected to the gate of the twenty-seventh MOSFET M27.

[0100] The drain of the 27th MOSFET M27 is connected to the positive filter node VSP_Q2 of the second-stage Q-path, and the source of the 27th MOSFET M27 is connected to the output terminal VOP_Q2 of the second-stage Q-path positive filter. The drain of the 28th MOSFET M28 is connected to the negative filter node VSN_Q2 of the second-stage Q-path, and the source of the 28th MOSFET M28 is connected to the output terminal VON_Q2 of the second-stage Q-path negative filter. The 20th capacitor C20 is connected across the output terminals VOP_Q2 and VON_Q2 of the second-stage Q-path positive filter.

[0101] The drain of the 20th bias transistor MVB20 is connected to the positive output terminal VOP_Q2 of the second stage Q-channel, the gate of the 20th bias transistor MVB20 is connected to the second bias voltage input terminal VB2, and the source of the 20th bias transistor MVB20 is connected to ground GND; the drain of the 21st bias transistor MVB21 is connected to the negative output terminal VON_Q2 of the second stage Q-channel, the gate of the 21st bias transistor MVB21 is connected to the second bias voltage input terminal VB2, and the source of the 21st bias transistor MVB21 is connected to ground GND.

[0102] The second-stage feedforward capacitor circuit includes the fifth feedforward capacitor CH5 to the eighth feedforward capacitor CH8, and the fifth MOS switch MC5 to the eighth MOS switch MC8.

[0103] One end of the fifth feedforward capacitor CH5 is connected to the positive input terminal VIP_I of the second stage I-channel, and the other end is connected to the drain of the fifth MOS switch MC5. The source of the fifth MOS switch MC5 is connected to the positive filter node VSP_Q2 of the second stage Q-channel, and the gate of the fifth MOS switch MC5 is connected to the switch voltage input terminal CTRL. One end of the sixth feedforward capacitor CH6 is connected to the negative input terminal VIN_I of the second stage I-channel, and the other end is connected to the drain of the sixth MOS switch MC6. The source of the sixth MOS switch MC6 is connected to the negative filter node VSN_Q2 of the second stage Q-channel, and the gate of the sixth MOS switch MC6 is connected to the switch voltage input terminal CTRL.

[0104] One end of the seventh feedforward capacitor CH7 is connected to the positive input terminal VIP_Q of the second stage Q-channel, and the other end is connected to the source of the seventh MOS switch MC7. The drain of the seventh MOS switch MC7 is connected to the negative filter node VSN_I2 of the second stage I-channel, and the gate of the seventh MOS switch MC7 is connected to the switch voltage input terminal CTRL. One end of the eighth feedforward capacitor CH8 is connected to the negative input terminal VIN_Q of the second stage Q-channel, and the other end is connected to the source of the eighth MOS switch MC8. The drain of the eighth MOS switch MC8 is connected to the positive filter node VSP_I2 of the second stage I-channel, and the gate of the eighth MOS switch MC8 is connected to the switch voltage input terminal CTRL.

[0105] When the fifth MOS switch MC5 to the eighth MOS switch MC8 are turned on, the fifth feedforward capacitor CH5 to the eighth feedforward capacitor CH8 are connected to the second-stage cross feedforward path, so that the buffered I-channel differential signal and Q-channel differential signal provide feedforward components to the second-stage filter node of the other positive cross path respectively.

[0106] The equivalent capacitance values ​​of the fifth feedforward capacitor CH5 to the eighth feedforward capacitor CH8 are... C H2 The equivalent transconductance value of the second-stage feedforward path is g mf2 At that time, the second-order complex notch point satisfies:

[0107] By changing the capacitance values ​​of the fifth feedforward capacitor CH5 to the eighth feedforward capacitor CH8 C H2 The second-level complex notch point can be adjusted independently. ω p2 Furthermore, it has little impact on the main low-pass poles, passband gain, or other indicators.

[0108] By selecting the capacitance values ​​of the first-stage and second-stage feedforward capacitors respectively, the complex notch points of the first and second stages can be located at different frequency positions. After the two-stage filter response is cascaded, the combined effect of multiple notches and filter poles can maintain a high image rejection ratio over a wide frequency range, thereby extending the image rejection bandwidth.

[0109] The following example illustrates the frequency characteristics of the second-stage filter I path, using the transmission relationship between the second-stage I-path positive filter node VSP_I2 and the second-stage I-path positive filter output terminal VOP_I2 as an example.

[0110] The transfer function of the second-stage filter I path can be expressed as:

[0111] In the formula, g m7 The transconductance values ​​are those of the twenty-third MOSFET M23 and the twenty-fourth MOSFET M24. C gs2 The gate-source parasitic capacitance values ​​are those of the twenty-third MOSFET M23 and the twenty-fourth MOSFET M24. C gd2 These are the gate-drain parasitic capacitance values ​​for the twenty-third MOSFET M23 and the twenty-fourth MOSFET M24. C 18 This refers to the capacitance value of the eighteenth capacitor, C18. r 2 represents the resistance values ​​of the seventeenth resistor R17 and the eighteenth resistor R18. C 02 This is the equivalent capacitance value formed by the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6.

[0112] Based on the transfer function described above, the second-stage filter I path generates one left-half-plane zero and one right-half-plane zero, and their relationship can be expressed as:

[0113]

[0114] Zero point of left half plane z 2. Increases the gain slope of the amplitude-frequency response by 20 dB / dec. C02 Less than C gd2 Under these conditions, with the equivalent capacitance value C 02 Increase, zero point of the right half-plane z 3. Moving towards higher frequencies (pushing to the right) can reduce the impact of high-frequency parasitic nulls on the target stopband.

[0115] The low-pass cutoff angular frequency of the dual second-order filter formed by the second-stage filter I path. ω 1 and quality factor Q 1 can be approximated as:

[0116] Low-pass cutoff angular frequency ω 1 is used to characterize the bandwidth range and quality factor of the second-order bisecond-stage filter. Q 1. Used to characterize the peak response near the cutoff frequency. With other parameters fixed, the values ​​of the seventeenth resistor R17 and the eighteenth resistor R18 are varied. r 2. Adjustable quality factor Q 1. To improve the passband flatness of the second-stage filtering path. The second-stage filtering Q-path adopts a corresponding structure and has a corresponding transfer relationship.

[0117] In actual operation, the I-channel differential input signal and the Q-channel differential input signal first enter the differential mixed input stage circuit. The differential input coupling capacitor bank isolates the DC potential of the preceding stage, and the common-mode bias resistor bank establishes the DC operating point required by the differential MOS conversion circuit and the cross-coupled output circuit. The differential MOS conversion circuit and the cross-coupled output circuit together improve the input stage gain and suppress the third-order nonlinear component.

[0118] When the switching voltage input terminal CTRL is at the level that turns on all MOS switches, the first-stage feedforward capacitor circuit and the second-stage feedforward capacitor circuit simultaneously establish a cross-feedforward path between the I and Q paths. The first-stage multiphase filter circuit first performs low-pass filtering and image suppression on the differential input signal, the voltage buffer circuit isolates and drives the first-stage output signal, and the second-stage multiphase filter circuit further performs low-pass filtering and image suppression. The first-stage complex notch point and the second-stage complex notch point together constitute a broadband image suppression response.

[0119] When the switching voltage input terminal CTRL is at the level that turns off all MOS switches, the first-stage feedforward capacitor circuit and the second-stage feedforward capacitor circuit disconnect the corresponding cross feedforward paths. Each I-path filter path and Q-path filter path performs low-pass filtering along the main signal path, so that the reconfigurable multiphase filter switches to the low-pass filtering state.

[0120] like Figure 2 As shown, Figure 2 The simulation results of the frequency response of the reconfigurable polyphase filter in this embodiment are shown, where the simulation curves represent the response of the useful signal and the response of the image signal, respectively. The circuit simulation is based on a 180-nm CMOS process model. This embodiment uses a standard power supply voltage of 1.8 V, and the input is an ideal quadrature differential signal with a frequency of 10 MHz and a signal strength of -30 dBm. The voltage values ​​at the first common-mode voltage input terminal VCM1 are 0.95 V, the second common-mode voltage input terminal VCM2 are 0.33 V, and the third common-mode voltage input terminal VCM3 are 0.5 V. The simulation shows that the passband gain of the reconfigurable polyphase filter is 11.7 dB, the image rejection bandwidth is 3 MHz to 6 MHz, and the image rejection ratio (IRR) reaches 35.1 dB. Therefore, this reconfigurable polyphase filter can perform frequency-selective filtering of the useful signal while significantly attenuating the signal on the image frequency side, thereby improving the amplitude difference between the useful signal and the image signal.

[0121] It should be noted that the image rejection bandwidth refers to the frequency range within which the image rejection ratio continuously meets the predetermined suppression requirement, and is not equivalent to the frequency position of a single complex notch point. The first-stage and second-stage feedforward capacitor circuits introduce complex notch points on one side of the image frequency, resulting in strong suppression of the image signal near the corresponding notch point. Simultaneously, the filter poles, quality factors, and frequency distribution between the two complex notch points in the first and second-stage multiphase filter circuits collectively determine the overall shape of the image signal response curve. Therefore, by appropriately setting the capacitance values ​​of the first-stage and second-stage feedforward capacitors, the two complex notch points can be located at different frequency positions, and the cascading effect of the two-stage filter responses can be used to expand the continuous frequency range that meets the predetermined image rejection ratio, thereby extending the image rejection bandwidth.

[0122] like Figure 3 As shown, Figure 3 The simulation results of the linearity of the reconfigurable polyphase filter in this embodiment are shown. The simulation results show that the input third-order intermodulation point (IIP3) of the reconfigurable polyphase filter is 9.9 dBm, and the output third-order intermodulation point (OIP3) is 21.6 dBm, which improves the linearity by about 25% compared with the traditional filter. The input and output third-order intermodulation points are used to characterize the circuit's ability to suppress third-order intermodulation distortion. The higher the value, the more linear the signal transmission characteristics can be maintained over a wider dynamic range when the input signal amplitude increases.

[0123] The improved linearity is primarily due to the synergistic effect of multiple branches in the differential hybrid input stage circuit. Different MOS branches in the differential MOS converter circuit respond to the same differential input signal and are superimposed at the differential output node. Since the third-order nonlinear components generated by MOS branches with different connection configurations have different phases or polarities, by appropriately setting the size, transconductance, bias current, and overdrive voltage of each MOS transistor, the third-order nonlinear components generated by each branch can compensate for each other, thereby reducing third-order intermodulation distortion. The cross-coupled output circuit further converts and outputs the differential signal, which helps improve the linear response under large-signal input conditions while maintaining differential gain, thus increasing the input dynamic range of the reconfigurable multiphase filter.

[0124] like Figure 4 As shown, Figure 4 The simulation results of the noise figure of the reconfigurable multiphase filter in this embodiment are shown. Under the simulation conditions corresponding to this embodiment, the noise figure of the reconfigurable multiphase filter within the image rejection bandwidth is less than 41 dB. The differential hybrid input stage circuit performs front-end processing on the I-channel differential input signal and the Q-channel differential input signal through differential input coupling capacitor banks, differential MOS conversion circuits, cross-coupled output circuits, and common-mode bias resistor banks. This not only suppresses common-mode interference but also achieves an input stage voltage gain greater than unity gain. With the improved input stage gain, the noise generated by the subsequent multiphase filter circuit and voltage buffer circuit, when referred to the entire filter input, has a correspondingly reduced equivalent noise contribution, thereby improving the overall noise performance of the reconfigurable multiphase filter.

[0125] Under the power supply, bias, and simulation conditions of this embodiment, the overall power consumption of the reconfigurable multiphase filter is 3.9 mW. The CTRL switch can control the connection or disconnection of the first-stage and second-stage feedforward capacitor circuits to the corresponding cross-feedforward paths. When there is strong image interference in the received signal or when image suppression performance is required to be high, all MOS switches are turned on, and the reconfigurable multiphase filter operates in multiphase filtering state to form an image suppression response by utilizing the orthogonal phase relationship between the I-channel and Q-channel signals. When the image interference is weak or there is no need to form a complex notch response, all MOS switches are turned off, and the reconfigurable multiphase filter switches to low-pass filtering state. At this time, the feedforward capacitors no longer periodically charge and discharge with changes in the input signal, and the first-stage and second-stage filter nodes do not need to drive the additional capacitive load formed by the cross-feedforward branches, thereby reducing the charging and discharging current and additional dynamic power consumption in the cross-feedforward path and helping to reduce the overall power consumption of the circuit.

[0126] In summary, this embodiment improves the input stage gain and compensates for third-order nonlinear components through a differential hybrid input stage circuit, achieves broadband image rejection response through two-stage multiphase filter circuits and two-stage feedforward capacitor circuits, improves passband flatness and high-frequency stopband rejection capability through cross-coupled feedback paths and PMOS equivalent capacitor units, and reduces load coupling between the preceding and following stages through a voltage buffer circuit. Therefore, this reconfigurable multiphase filter can balance passband gain, image rejection capability, linearity, noise performance, and filter state reconfigurability under low power consumption conditions.

[0127] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A reconfigurable polyphase filter, characterized in that, It includes a differential mixed input stage circuit, a first-stage multiphase filter circuit, and a switching control terminal; The differential mixed input stage circuit includes an input stage I path for processing I-channel differential input signals and an input stage Q path for processing Q-channel differential input signals. Both the input stage I path and the input stage Q path include a common-mode bias resistor group and a differential input coupling capacitor group, a differential MOS conversion circuit, and a cross-coupled output circuit connected in sequence. The common-mode bias resistor group is connected to the input terminals of the differential MOS conversion circuit and the cross-coupled output circuit, respectively, to provide common-mode bias to the differential MOS conversion circuit and the cross-coupled output circuit. The differential input signal of the path is coupled to the differential MOS conversion circuit through the differential input coupling capacitor group. The differential MOS conversion circuit converts the differential input signal under the common-mode bias provided by the common-mode bias resistor group. The cross-coupled output circuit generates the differential intermediate signal of the path according to the output signal of the differential MOS conversion circuit. The first-stage multiphase filter circuit includes a first-stage filter I path, a first-stage filter Q path, and a first-stage feedforward capacitor circuit. The input terminal of the first-stage filter I path is connected to the output terminal of the cross-coupled output circuit in the input stage I path, and the input terminal of the first-stage filter Q path is connected to the output terminal of the cross-coupled output circuit in the input stage Q path. The first-stage feedforward capacitor circuit includes at least a first set of feedforward capacitor branches and a second set of feedforward capacitor branches. Each feedforward capacitor branch includes a feedforward capacitor and a switching unit connected in series with the feedforward capacitor. The first set of feedforward capacitor branches is connected between the input terminal of the differential input coupling capacitor group in the input stage I path and the input terminal of the first-stage filter Q path. The second set of feedforward capacitor branches is connected between the input terminal of the differential input coupling capacitor group in the input stage Q path and the input terminal of the first-stage filter I path. When the switching unit is turned on, the first set of feedforward capacitor branches is used to feed forward the feedforward component of the I-path differential input signal to the input terminal of the first-stage filter Q path in a capacitive coupling manner. The second set of feedforward capacitor branches is used to feed forward the feedforward component of the Q-path differential input signal to the input terminal of the first-stage filter I path in a capacitive coupling manner, so as to form a cross-feedforward path between the first-stage filter I path and the first-stage filter Q path. The switch control terminal is connected to each switch unit and is used to control the feedforward capacitor branch to connect to or disconnect the corresponding cross feedforward path so that the reconfigurable multiphase filter can switch between multiphase filtering state and low-pass filtering state.

2. The reconfigurable polyphase filter according to claim 1, characterized in that, The input stage I-path has a third bias voltage input terminal VB3, an I-path positive input terminal IIP, an I-path negative input terminal IIN, an I-path first group of positive differential output nodes VOP_I, an I-path first group of negative differential output nodes VON_I, an I-path positive differential intermediate output terminal VSP_I, an I-path negative differential intermediate output terminal VSN_I, a first common-mode voltage input terminal VCM1, a second common-mode voltage input terminal VCM2, and a third common-mode voltage input terminal VCM3; the differential input coupling capacitor group of the input stage I-path includes the first capacitor C1 to the fourth capacitor C4, the differential MOS conversion circuit includes the zero bias transistor MVB0 and the first MOS transistor M1 to the fourth MOS transistor M4, the cross-coupled output circuit includes the fifth MOS transistor M5 to the eighth MOS transistor M8, the fifth capacitor C5 and the sixth capacitor C6, and the common-mode bias resistor group includes the first resistor R1 to the sixth resistor R6; The first capacitor C1 is connected between the negative input terminal IIN of the I-channel and the gate of the first MOSFET M1; the first resistor R1 is connected between the first common-mode voltage input terminal VCM1 and the gate of the first MOSFET M1; the second capacitor C2 is connected between the positive input terminal IIP of the I-channel and the gate of the second MOSFET M2; the second resistor R2 is connected between the first common-mode voltage input terminal VCM1 and the gate of the second MOSFET M2; the third capacitor C3 is connected between the positive input terminal IIP of the I-channel and the gate of the third MOSFET M3; the third resistor R3 is connected between the second common-mode voltage input terminal VCM2 and the gate of the third MOSFET M3; the fourth capacitor C4 is connected between the negative input terminal IIN of the I-channel and the gate of the fourth MOSFET M4; the fourth resistor R4 is connected between the second common-mode voltage input terminal VCM2 and the gate of the fourth MOSFET M4. The source of the zero-bias transistor MVB0 is connected to the power supply voltage VDD, the gate is connected to the third bias voltage input terminal VB3, and the drain is connected to the source of the first MOSFET M1 and the source of the second MOSFET M2. The drain of the first MOSFET M1 forms the first group of positive differential output nodes VOP_I, and the drain of the second MOSFET M2 forms the first group of negative differential output nodes VON_I. The source of the third MOSFET M3 is connected to the first group of positive differential output nodes VOP_I, and the drain of the third MOSFET M3 is connected to ground GND. The source of the fourth MOSFET M4 is connected to the first group of negative differential output nodes VON_I, and the drain of the fourth MOSFET M4 is connected to ground GND. The gate of the fifth MOSFET M5 is connected to the first group of negative differential output node VON_I, the source is connected to the power supply voltage VDD, and the drain is connected to the middle output terminal VSP_I of the first group of positive differential output. The gate of the sixth MOSFET M6 is connected to the first group of positive differential output node VOP_I, the source is connected to the power supply voltage VDD, and the drain is connected to the middle output terminal VSN_I of the first group of negative differential output. The fifth capacitor C5 is connected between the first group of positive differential output node VOP_I and the gate of the seventh MOSFET M7. The fifth resistor R5 is connected between the third common-mode voltage input terminal VCM3 and the gate of the seventh MOSFET M7. The source of the seventh MOSFET M7 is connected to the middle output terminal VSP_I of the first group of positive differential output, and the drain of the seventh MOSFET M7 is connected to ground GND. The sixth capacitor C6 is connected between the first negative differential output node VON_I of the I-channel and the gate of the eighth MOSFET M8. The sixth resistor R6 is connected between the third common-mode voltage input terminal VCM3 and the gate of the eighth MOSFET M8. The source of the eighth MOSFET M8 is connected to the intermediate negative differential output terminal VSN_I of the I-channel, and the drain of the eighth MOSFET M8 is connected to ground GND. The resistance values ​​of the first resistor R1 to the sixth resistor R6 are equal, and the capacitance values ​​of the first capacitor C1 to the sixth capacitor C6 are equal.

3. The reconfigurable polyphase filter according to claim 2, characterized in that, The input stage Q path has a third bias voltage input terminal VB3, a positive Q-path input terminal IQP, a negative Q-path input terminal IQN, a first group of positive differential output nodes VOP_Q, a first group of negative differential output nodes VON_Q, a positive differential intermediate output terminal VSP_Q, a negative differential intermediate output terminal VSN_Q, a first common-mode voltage input terminal VCM1, a second common-mode voltage input terminal VCM2, and a third common-mode voltage input terminal VCM3. The differential input coupling capacitor group of the input stage Q path includes the seventh capacitor C7 to the tenth capacitor C10, the differential MOS conversion circuit includes the first bias transistor MVB1 and the ninth MOS transistor M9 to the twelfth MOS transistor M12, the cross-coupled output circuit includes the thirteenth MOS transistor M13 to the sixteenth MOS transistor M16, the eleventh capacitor C11 and the twelfth capacitor C12, and the common-mode bias resistor group includes the seventh resistor R7 to the twelfth resistor R12. The seventh capacitor C7 is connected between the negative input terminal IQN of the Q-path and the gate of the ninth MOSFET M9; the seventh resistor R7 is connected between the first common-mode voltage input terminal VCM1 and the gate of the ninth MOSFET M9; the eighth capacitor C8 is connected between the positive input terminal IQP of the Q-path and the gate of the tenth MOSFET M10; the eighth resistor R8 is connected between the first common-mode voltage input terminal VCM1 and the gate of the tenth MOSFET M10; the ninth capacitor C9 is connected between the positive input terminal IQP of the Q-path and the gate of the eleventh MOSFET M11; the ninth resistor R9 is connected between the second common-mode voltage input terminal VCM2 and the gate of the eleventh MOSFET M11; the tenth capacitor C10 is connected between the negative input terminal IQN of the Q-path and the gate of the twelfth MOSFET M12; the tenth resistor R10 is connected between the second common-mode voltage input terminal VCM2 and the gate of the twelfth MOSFET M12. The source of the first bias transistor MVB1 is connected to the power supply voltage VDD, the gate is connected to the third bias voltage input terminal VB3, and the drain is connected to the source of the ninth MOSFET M9 and the source of the tenth MOSFET M10, respectively. The drain of the ninth MOSFET M9 forms the first positive differential output node VOP_Q of the Q-path; the drain of the tenth MOSFET M10 forms the first negative differential output node VON_Q of the Q-path; the source of the eleventh MOSFET M11 is connected to the first positive differential output node VOP_Q of the Q-path, and the drain of the eleventh MOSFET M11 is connected to ground GND; the source of the twelfth MOSFET M12 is connected to the first negative differential output node VON_Q of the Q-path, and the drain of the twelfth MOSFET M12 is connected to ground GND. The gate of the thirteenth MOSFET M13 is connected to the first negative differential output node VON_Q of the Q-path, the source is connected to the power supply voltage VDD, and the drain is connected to the positive differential intermediate output terminal VSP_Q of the Q-path. The gate of the fourteenth MOSFET M14 is connected to the first positive differential output node VOP_Q of the Q-path, the source is connected to the power supply voltage VDD, and the drain is connected to the negative differential intermediate output terminal VSN_Q of the Q-path. The eleventh capacitor C11 is connected between the first positive differential output node VOP_Q of the Q-path and the gate of the fifteenth MOSFET M15, and the eleventh resistor R11 is connected between the third common-mode voltage input terminal VCM3 and the tenth resistor. Between the gates of the five MOSFETs M15, the source of the fifteenth MOSFET M15 is connected to the positive differential intermediate output terminal VSP_Q of the Q-path, and the drain of the fifteenth MOSFET M15 is connected to ground GND; the twelfth capacitor C12 is connected between the first negative differential output node VON_Q of the Q-path and the gate of the sixteenth MOSFET M16; the twelfth resistor R12 is connected between the third common-mode voltage input terminal VCM3 and the gate of the sixteenth MOSFET M16; the source of the sixteenth MOSFET M16 is connected to the negative differential intermediate output terminal VSN_Q of the Q-path, and the drain of the sixteenth MOSFET M16 is connected to ground GND; The resistance values ​​of the seventh resistor R7 to the twelfth resistor R12 are equal, and the capacitance values ​​of the seventh capacitor C7 to the twelfth capacitor C12 are equal.

4. The reconfigurable polyphase filter according to claim 3, characterized in that, The first-stage filter I-path includes the first bias voltage input terminal VB1, the second bias voltage input terminal VB2, the first-stage I-path positive filter input terminal VSP_I, the first-stage I-path negative filter input terminal VSN_I, the first-stage I-path positive filter output terminal VOP_I1, the first-stage I-path negative filter output terminal VON_I1, the second bias transistors MVB2 to MVB5, the seventeenth MOSFET M17, the eighteenth MOSFET M18, the first PMOS transistor MP1, the second PMOS transistor MP2, the thirteenth capacitor C13, the fourteenth capacitor C14, the thirteenth resistor R13, and the fourteenth resistor R14. The first-stage I-path positive filter input terminal and the I-path positive differential intermediate output terminal share the node VSP_I, and the first-stage I-path negative filter input terminal and the I-path negative differential intermediate output terminal share the node VSN_I. The sources of the second bias transistor MVB2 and the third bias transistor MVB3 are connected to the power supply voltage VDD. The gates of the second bias transistor MVB2 and the third bias transistor MVB3 are connected to the first bias voltage input terminal VB1. The drain of the second bias transistor MVB2 is connected to the first stage I-channel positive filter input terminal VSP_I. The drain of the third bias transistor MVB3 is connected to the first stage I-channel negative filter input terminal VSN_I. The thirteenth capacitor C13 is connected between the first stage I-channel positive filter input terminal VSP_I and the first stage I-channel negative filter input terminal VSN_I. The thirteenth resistor R13 is connected between the first stage I-channel positive filter input terminal VSP_I and the gate of the eighteenth MOS transistor M18. The fourteenth resistor R14 is connected between the first stage I-channel negative filter input terminal VSN_I and the gate of the seventeenth MOS transistor M17. The drain of the seventeenth MOSFET M17 is connected to the positive input terminal VSP_I of the first-stage I-channel filter, and the source of the seventeenth MOSFET M17 is connected to the positive output terminal VOP_I1 of the first-stage I-channel filter. The drain of the eighteenth MOSFET M18 is connected to the negative input terminal VSN_I of the first-stage I-channel filter, and the source of the eighteenth MOSFET M18 is connected to the negative output terminal VON_I1 of the first-stage I-channel filter. The source and drain of the first PMOS transistor MP1 are both connected to the positive input terminal VSP_I of the first-stage I-channel filter, and the gate of the first PMOS transistor MP1 is connected to the gate of the eighteenth MOSFET M18. The source and drain of the second PMOS transistor MP2 are both connected to the first stage I-path negative filter input terminal VSN_I, and the gate of the second PMOS transistor MP2 is connected to the gate of the seventeenth MOS transistor M17; the fourteenth capacitor C14 is connected between the first stage I-path positive filter output terminal VOP_I1 and the first stage I-path negative filter output terminal VON_I1; the drain of the fourth bias transistor MVB4 is connected to the first stage I-path positive filter output terminal VOP_I1, the gate of the fourth bias transistor MVB4 is connected to the second bias voltage input terminal VB2, and the source of the fourth bias transistor MVB4 is connected to ground GND; The drain of the fifth bias transistor MVB5 is connected to the output terminal VON_I1 of the first stage I-channel negative filter, the gate of the fifth bias transistor MVB5 is connected to the second bias voltage input terminal VB2, and the source of the fifth bias transistor MVB5 is connected to ground GND. The first-stage filter Q-path includes a first bias voltage input terminal VB1, a second bias voltage input terminal VB2, a first-stage Q-path positive filter input terminal VSP_Q, a first-stage Q-path negative filter input terminal VSN_Q, a first-stage Q-path positive filter output terminal VOP_Q1, a first-stage Q-path negative filter output terminal VON_Q1, a sixth bias transistor MVB6 to a ninth bias transistor MVB9, a nineteenth MOS transistor M19, a twentieth MOS transistor M20, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifteenth capacitor C15, a sixteenth capacitor C16, a fifteenth resistor R15, and a sixteenth resistor R16. The first-stage Q-path positive filter input terminal and the Q-path positive differential intermediate output terminal share the same node VSP_Q, and the first-stage Q-path negative filter input terminal and the Q-path negative differential intermediate output terminal share the same node VSN_Q. The sources of the sixth bias transistor MVB6 and the seventh bias transistor MVB7 are connected to the power supply voltage VDD. The gates of the sixth bias transistor MVB6 and the seventh bias transistor MVB7 are connected to the first bias voltage input terminal VB1. The drain of the sixth bias transistor MVB6 is connected to the positive filter input terminal VSP_Q of the first stage Q-path. The drain of the seventh bias transistor MVB7 is connected to the negative filter input terminal VSN_Q of the first stage Q-path. The fifteenth capacitor C15 is connected between the positive filter input terminal VSP_Q of the first stage Q-path and the negative filter input terminal VSN_Q of the first stage Q-path. The fifteenth resistor R15 is connected between the positive filter input terminal VSP_Q of the first stage Q-path and the gate of the twentieth MOSFET M20. The sixteenth resistor R16 is connected between the negative filter input terminal VSN_Q of the first stage Q-path and the gate of the nineteenth MOSFET M19. The drain of the nineteenth MOSFET M19 is connected to the positive input terminal VSP_Q of the first-stage Q-channel filter, and the source of the nineteenth MOSFET M19 is connected to the positive output terminal VOP_Q1 of the first-stage Q-channel filter; the drain of the twentieth MOSFET M20 is connected to the negative input terminal VSN_Q of the first-stage Q-channel filter, and the source of the twentieth MOSFET M20 is connected to the negative output terminal VON_Q1 of the first-stage Q-channel filter; the source and drain of the third PMOS transistor MP3 are both connected to the positive input terminal VSP_Q of the first-stage Q-channel filter, and the gate of the third PMOS transistor MP3 is connected to the gate of the twentieth MOSFET M20; the source and drain of the fourth PMOS transistor MP4 are both connected to the negative input terminal VSN_Q of the first-stage Q-channel filter, and the... The gate of the four PMOS transistors MP4 is connected to the gate of the nineteenth PMOS transistor M19; the sixteenth capacitor C16 is connected between the positive filter output terminal VOP_Q1 and the negative filter output terminal VON_Q1 of the first stage Q-path; the drain of the eighth bias transistor MVB8 is connected to the positive filter output terminal VOP_Q1 of the first stage Q-path, the gate of the eighth bias transistor MVB8 is connected to the second bias voltage input terminal VB2, and the source of the eighth bias transistor MVB8 is connected to ground GND; the drain of the ninth bias transistor MVB9 is connected to the negative filter output terminal VON_Q1 of the first stage Q-path, the gate of the ninth bias transistor MVB9 is connected to the second bias voltage input terminal VB2, and the source of the ninth bias transistor MVB9 is connected to ground GND.

5. The reconfigurable polyphase filter according to claim 4, characterized in that, The first-stage feedforward capacitor circuit includes first feedforward capacitors CH1 to CH4 and first MOS switches MC1 to MC4. The first feedforward capacitor CH1 and the first MOS switch MC1 are connected in series between the positive input terminal IIP of the I-channel and the positive filter input terminal VSP_Q of the first-stage Q-channel. The second feedforward capacitor CH2 and the second MOS switch MC2 are connected in series between the negative input terminal IIN of the I-channel and the negative filter input terminal VSN_Q of the first-stage Q-channel. The third feedforward capacitor CH3 and the third MOS switch MC3 are connected in series between the positive input terminal IQP of the Q-channel and the negative filter input terminal VSN_I of the first-stage I-channel. The fourth feedforward capacitor CH4 and the fourth MOS switch MC4 are connected in series between the negative input terminal IQN of the Q-channel and the positive filter input terminal VSP_I of the first-stage I-channel. The gates of the first MOS switches MC1 to the fourth MOS switches MC4 are all connected to the switch control terminal.

6. The reconfigurable polyphase filter according to claim 5, characterized in that, The switch control terminal is the switch voltage input terminal CTRL. When the switch voltage input terminal CTRL is in the first level state, the first MOS switch MC1 to the fourth MOS switch MC4 are turned on, and the first feedforward capacitor CH1 to the fourth feedforward capacitor CH4 are connected to the corresponding cross feedforward path, so that the reconfigurable multiphase filter is in the multiphase filtering state. When the switch voltage input terminal CTRL is in the second level state, the first MOS switch MC1 to the fourth MOS switch MC4 are turned off, and the first feedforward capacitor CH1 to the fourth feedforward capacitor CH4 are disconnected from the corresponding cross feedforward path, so that the reconfigurable multiphase filter is in the low-pass filtering state.

7. The reconfigurable polyphase filter according to claim 4, characterized in that, The thirteenth resistor R13 and the fourteenth resistor R14 in the first-stage filter I path, and the fifteenth resistor R15 and the sixteenth resistor R16 in the first-stage filter Q path, are used to form a cross-coupled feedback path to adjust the quality factor of the first-stage multiphase filter circuit. The first PMOS transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, and the fourth PMOS transistor MP4 are used as equivalent capacitor units with their source and drain shorted, respectively. They are used to form equivalent negative capacitors between the gates of the corresponding MOS transistors in the seventeenth MOS transistor M17, the eighteenth MOS transistor M18, the nineteenth MOS transistor M19, or the twentieth MOS transistor M20, in order to compensate for the high-frequency zeros introduced by parasitic parameters.

8. The reconfigurable polyphase filter according to claim 4, characterized in that, The reconfigurable multiphase filter also includes a voltage buffer circuit and a second-stage multiphase filter circuit. The voltage buffer circuit is connected between the first-stage multiphase filter circuit and the second-stage multiphase filter circuit. It is used to buffer the I-channel differential signal output from the first-stage I-channel positive filter output terminal VOP_I1 and the first-stage I-channel negative filter output terminal VON_I1, as well as the Q-channel differential signal output from the first-stage Q-channel positive filter output terminal VOP_Q1 and the first-stage Q-channel negative filter output terminal VON_Q1. The buffered I-channel differential signal and Q-channel differential signal are then output to the second-stage multiphase filter circuit.

9. The reconfigurable polyphase filter according to claim 8, characterized in that, The voltage buffer circuit includes a second bias voltage input terminal VB2, a buffer I path, and a buffer Q path; the voltage buffer circuit has a second-stage I positive input terminal VIP_I, a second-stage I negative input terminal VIN_I, a second-stage Q positive input terminal VIP_Q, and a second-stage Q negative input terminal VIN_Q for output to the second-stage multiphase filter circuit; The buffer I path includes the first buffer MOSFET MB1 to the fourth buffer MOSFET MB4. The drain of the first buffer MOSFET MB1 is connected to the power supply voltage VDD, the gate of the first buffer MOSFET MB1 is connected to the positive filter output terminal VOP_I1 of the first stage I path, and the source of the first buffer MOSFET MB1 is connected to the positive input terminal VIP_I of the second stage I path. The drain of the second buffer MOSFET MB2 is connected to the positive input terminal VIP_I of the second stage I-channel, the gate of the second buffer MOSFET MB2 is connected to the second bias voltage input terminal VB2, and the source of the second buffer MOSFET MB2 is connected to ground GND; the drain of the third buffer MOSFET MB3 is connected to the power supply voltage VDD, the gate of the third buffer MOSFET MB3 is connected to the negative filter output terminal VON_I1 of the first stage I-channel, and the source of the third buffer MOSFET MB3 is connected to the negative input terminal VIN_I of the second stage I-channel; the drain of the fourth buffer MOSFET MB4 is connected to the negative input terminal VIN_I of the second stage I-channel, the gate of the fourth buffer MOSFET MB4 is connected to the second bias voltage input terminal VB2, and the source of the fourth buffer MOSFET MB4 is connected to ground GND; The buffer Q-path includes the fifth buffer MOSFET MB5 to the eighth buffer MOSFET MB8. The drain of the fifth buffer MOSFET MB5 is connected to the power supply voltage VDD, the gate of the fifth buffer MOSFET MB5 is connected to the positive filter output terminal VOP_Q1 of the first stage Q-path, and the source of the fifth buffer MOSFET MB5 is connected to the positive input terminal VIP_Q of the second stage Q-path. The drain of the sixth buffer MOSFET MB6 is connected to the positive input terminal VIP_Q of the second stage Q-path, the gate of the sixth buffer MOSFET MB6 is connected to the second bias voltage input terminal VB2, and the source of the sixth buffer MOSFET MB6 is connected to ground GND. The drain of the seventh buffer MOSFET MB7 is connected to the power supply voltage VDD, the gate of the seventh buffer MOSFET MB7 is connected to the negative filter output terminal VON_Q1 of the first stage Q-path, and the source of the seventh buffer MOSFET MB7 is connected to the negative input terminal VIN_Q of the second stage Q-path. The drain of the eighth buffer MOSFET MB8 is connected to the negative input terminal VIN_Q of the second stage Q-path, the gate of the eighth buffer MOSFET MB8 is connected to the second bias voltage input terminal VB2, and the source of the eighth buffer MOSFET MB8 is connected to ground GND.

10. The reconfigurable polyphase filter according to claim 9, characterized in that, The second-stage multiphase filter circuit includes a second-stage filter I path, a second-stage filter Q path, and a second-stage feedforward capacitor circuit. The second-stage filter I path is used to receive the I-channel differential signal at the positive input terminal VIP_I and the negative input terminal VIN_I of the second-stage I path, and the second-stage filter Q path is used to receive the Q-channel differential signal at the positive input terminal VIP_Q and the negative input terminal VIN_Q of the second-stage Q path. The second-stage filter I path has a second-stage I-path positive filter node VSP_I2, a second-stage I-path negative filter node VSN_I2, a second-stage I-path positive filter output terminal VOP_I2, and a second-stage I-path negative filter output terminal VON_I2. The second-stage filter Q path has a second-stage Q-path positive filter node VSP_Q2, a second-stage Q-path negative filter node VSN_Q2, a second-stage Q-path positive filter output terminal VOP_Q2, and a second-stage Q-path negative filter output terminal VON_Q2. Both the second-stage filter I path and the second-stage filter Q path include a second-stage input-side bridging capacitor, a second-stage output-side bridging capacitor, and a second-stage AC... The system includes a cross-coupling resistor, a pair of second-stage output MOSFETs, and a second-stage PMOS equivalent capacitor unit. A second-stage input-side bridging capacitor is connected between the positive and negative filter nodes of the corresponding path. A second-stage output-side bridging capacitor is connected between the positive and negative filter output terminals of the corresponding path. A second-stage cross-coupling resistor is connected between the filter node of the corresponding path and the gate of the inverting output MOSFET. The second-stage output MOSFET pair is connected between the positive and negative filter nodes of the corresponding path and the positive and negative filter output terminals, respectively. A second-stage PMOS equivalent capacitor unit is connected between the filter node of the corresponding path and the gate of the inverting output MOSFET. The second-stage feedforward capacitor circuit includes the fifth feedforward capacitor CH5 to the eighth feedforward capacitor CH8 and the fifth MOS switch MC5 to the eighth MOS switch MC8. The fifth feedforward capacitor CH5 and the fifth MOS switch MC5 are connected in series between the positive input terminal VIP_I of the second-stage I-channel and the positive filter node VSP_Q2 of the second-stage Q-channel. The sixth feedforward capacitor CH6 and the sixth MOS switch MC6 are connected in series between the negative input terminal VIN_I of the second-stage I-channel and the negative filter node VSN_Q2 of the second-stage Q-channel. The seventh feedforward capacitor CH7 and the seventh MOS switch MC7 are connected in series between the positive input terminal VIP_Q of the second-stage Q-channel and the negative filter node VSN_I2 of the second-stage I-channel. The eighth feedforward capacitor CH8 and the eighth MOS switch MC8 are connected in series between the negative input terminal VIN_Q of the second-stage Q-channel and the positive filter node VSP_I2 of the second-stage I-channel. The gates of the fifth MOS switches MC5 to the eighth MOS switches MC8 are all connected to the switch control terminal.

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